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==== Watchdog Timer (WDT)

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| Hardware source file(s): | neorv32_wdt.vhd |

| Software driver file(s): | neorv32_wdt.c |

|                          | neorv32_wdt.h |

| Top entity port:         | none |

| Configuration generics:  | _IO_WDT_EN_ | implement GPIO port when _true_

| CPU interrupts:          | fast IRQ channel 0 | watchdog timer overflow (see <<_processor_interrupts>>)

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**Theory of Operation**

The watchdog (WDT) provides a last resort for safety-critical applications. The WDT has an internal 20-bit

wide counter that needs to be reset every now and then by the user program. If the counter overflows, either

a system reset or an interrupt is generated (depending on the configured operation mode).

Configuration of the watchdog is done by a single control register _WDT_CT_. The watchdog is enabled by

setting the _WDT_CT_EN_ bit. The clock used to increment the internal counter is selected via the 3-bit

_WDT_CT_CLK_SELx_ prescaler:

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| **`WDT_CT_CLK_SELx`** | Main clock prescaler | Timeout period in clock cycles

| `0b000` | 2 | 2 097 152

| `0b001` | 4 | 4 194 304

| `0b010` | 8 | 8 388 608

| `0b011` | 64 | 67 108 864

| `0b100` | 128 | 134 217 728

| `0b101` | 1024 | 1 073 741 824

| `0b110` | 2048 | 2 147 483 648

| `0b111` | 4096 | 4 294 967 296

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Whenever the internal timer overflows the watchdog executes one of two possible actions: Either a hard

processor reset is triggered or an interrupt is requested at CPU's fast interrupt channel #0. The

WDT_CT_MODE bit defines the action to be taken on an overflow: When cleared, the Watchdog will trigger an

IRQ, when set the WDT will cause a system reset. The configured actions can also be triggered manually at

any time by setting the _WDT_CT_FORCE_ bit. The watchdog is reset by setting the _WDT_CT_RESET_ bit.

The cause of the last action of the watchdog can be determined via the _WDT_CT_RCAUSE_ flag. If this flag is

zero, the processor has been reset via the external reset signal. If this flag is set the last system reset was

initiated by the watchdog.

The Watchdog control register can be locked in order to protect the current configuration. The lock is

activated by setting bit _WDT_CT_LOCK_. In the locked state any write access to the configuration flags is

ignored (see table below, "accessible if locked"). Read accesses to the control register are not effected. The

lock can only be removed by a system reset (via external reset signal or via a watchdog reset action).

.WDT register map

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| Address | Name [C] | Bit(s), Name [C] | R/W | Writable if locked | Function

.9+<| `0xffffffbc` .9+<| _WDT_CT_ <|`0` _WDT_CT_EN_       ^| r/w ^| no  <| watchdog enable

                                  <|`1` _WDT_CT_CLK_SEL0_ ^| r/w ^| no  .3+<| 3-bit clock prescaler select

                                  <|`2` _WDT_CT_CLK_SEL1_ ^| r/w ^| no

                                  <|`3` _WDT_CT_CLK_SEL2_ ^| r/w ^| no

                                  <|`4` _WDT_CT_MODE_     ^| r/w ^| no  <| overflow action: `1`=reset, `0`=IRQ

                                  <|`5` _WDT_CT_RCAUSE_   ^| r/- ^| -   <| cause of last system reset: `0`=caused by external reset signal, `1`=caused by watchdog

                                  <|`6` _WDT_CT_RESET_    ^| -/w ^| yes <| watchdog reset when set, auto-clears

                                  <|`7` _WDT_CT_FORCE_    ^| -/w ^| yes <| force configured watchdog action when set, auto-clears

                                  <|`8` _WDT_CT_LOCK_     ^| r/w ^| no  <| lock access to configuration when set, clears only on system reset (via external reset signal OR watchdog reset action = reset)

|=======================