OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [docs/] [datasheet/] [soc_wishbone.adoc] - Blame information for rev 62

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 60 zero_gravi
<<<
2
:sectnums:
3
==== Processor-External Memory Interface (WISHBONE) (AXI4-Lite)
4
 
5
[cols="<3,<3,<4"]
6
[frame="topbot",grid="none"]
7
|=======================
8 61 zero_gravi
| Hardware source file(s): | neorv32_wishbone.vhd |
9 60 zero_gravi
| Software driver file(s): | none             | _implicitly used_
10
| Top entity port:         | `wb_tag_o`  | request tag output (3-bit)
11
|                          | `wb_adr_o`  | address output (32-bit)
12
|                          | `wb_dat_i`  | data input (32-bit)
13
|                          | `wb_dat_o`  | data output (32-bit)
14
|                          | `wb_we_o`   | write enable (1-bit)
15
|                          | `wb_sel_o`  | byte enable (4-bit)
16
|                          | `wb_stb_o`  | strobe (1-bit)
17
|                          | `wb_cyc_o`  | valid cycle (1-bit)
18
|                          | `wb_lock_o` | exclusive access request (1-bit)
19
|                          | `wb_ack_i`  | acknowledge (1-bit)
20
|                          | `wb_err_i`  | bus error (1-bit)
21
|                          | `fence_o`   | an executed `fence` instruction
22
|                          | `fencei_o`  | an executed `fence.i` instruction
23 62 zero_gravi
| Configuration generics:  | _MEM_EXT_EN_         | enable external memory interface when _true_
24
|                          | _MEM_EXT_TIMEOUT_    | number of clock cycles after which an unacknowledged external bus access will auto-terminate (0 = disabled)
25
|                          | _MEM_EXT_PIPE_MODE_  | when _false_ (default): classic/standard Wishbone protocol; when _true_: pipelined Wishbone protocol
26
|                          | _MEM_EXT_BIG_ENDIAN_ | byte-order (Endianness) of external memory interface; true=BIG, false=little (default)
27
|                          | _MEM_EXT_ASYNC_RX_   | use registered RX path when _false_ (default); use async/direct RX path when _true_
28
| CPU interrupts:          | none |
29 60 zero_gravi
|=======================
30
 
31
The external memory interface uses the Wishbone interface protocol. The external interface port is available
32
when the _MEM_EXT_EN_ generic is _true_. This interface can be used to attach external memories, custom
33
hardware accelerators additional IO devices or all other kinds of IP blocks. All memory accesses from the
34
CPU, that do not target the internal bootloader ROM, the internal IO region or the internal data/instruction
35
memories (if implemented at all) are forwarded to the Wishbone gateway and thus to the external memory
36
interface.
37
 
38
[TIP]
39
When using the default processor setup, all access addresses between 0x00000000 and
40
0xffff0000 (= beginning of processor-internal BOOT ROM) are delegated to the external memory
41
/ bus interface if they are not targeting the (actually enabled/implemented) processor-internal
42
instruction memory (IMEM) or the (actually enabled/implemented) processor-internal data memory
43
(DMEM). See section <<_address_space>> for more information.
44
 
45
**Wishbone Bus Protocol**
46
 
47
The external memory interface either uses **standard** ("classic") Wishbone transactions (default) or
48 62 zero_gravi
**pipelined** Wishbone transactions. The transaction protocol is configured via the _MEM_EXT_PIPE_MODE_ generic:
49 60 zero_gravi
 
50 62 zero_gravi
When _MEM_EXT_PIPE_MODE_ is _false_, all bus control signals including _STB_ are active (and stable) until the
51
transfer is acknowledged/terminated. If _MEM_EXT_PIPE_MODE_ is _true_, all bus control except _STB_ are active
52 60 zero_gravi
(and stable) until the transfer is acknowledged/terminated. In this case, _STB_ is active only during the very
53
first bus clock cycle.
54
 
55
.Exemplary Wishbone bus accesses using "classic" and "pipelined" protocol
56
[cols="^2,^2"]
57
[grid="none"]
58
|=======================
59
a| image::wishbone_classic_read.png[700,300]
60
a| image::wishbone_pipelined_write.png[700,300]
61
| **Classic** Wishbone read access | **Pipelined** Wishbone write access
62
|=======================
63
 
64
 
65
[TOP]
66
A detailed description of the implemented Wishbone bus protocol and the according interface signals
67
can be found in the data sheet "Wishbone B4 – WISHBONE System-on-Chip (SoC) Interconnection
68
Architecture for Portable IP Cores". A copy of this document can be found in the docs folder of this
69
project.
70
 
71
**Interface Latency**
72
 
73 61 zero_gravi
By default, the Wishbone gateway introduces two additional latency cycles: processor-outgoing ("TX") and
74
processor-incoming ("RX") signals are fully registered. Thus, any access from the CPU to a processor-external devices
75
via Wishbone requires 2 additional clock cycles (at least; depending on device's latency).
76 60 zero_gravi
 
77 61 zero_gravi
If the attached Wishbone network / peripheral already provides output registers or if the Wishbone network is not relevant
78 62 zero_gravi
for timing closure, the default buffering of incoming ("RX") data within the gateway can be disabled by implementing an
79
"asynchronous" RX path. The configuration is done via the _MEM_EXT_ASYNC_RX_ generic.
80 61 zero_gravi
 
81 60 zero_gravi
**Bus Access Timeout**
82
 
83
The Wishbone bus interface provides an option to configure a bus access timeout counter. The _MEM_EXT_TIMEOUT_
84
top generic is used to specify the _maximum_ time (in clock cycles) a bus access can be pending before it is automatically
85
terminated. If _MEM_EXT_TIMEOUT_ is set to zero, the timeout disabled an a bus access can take an arbitrary number of cycles to complete.
86
 
87
When _MEM_EXT_TIMEOUT_ is greater than zero, the WIshbone adapter starts an internal countdown whenever the CPU
88
accesses a memory address via the external memory interface. If the accessed memory / device does not acknowledge (via `wb_ack_i`)
89
or terminate (via `wb_err_i`) the transfer within _MEM_EXT_TIMEOUT_ clock cycles, the bus access is automatically canceled
90
(setting `wb_cyc_o` low again) and a load/store/instruction fetch bus access fault exception is raised.
91
 
92
[TIP]
93
This feature can be used as **safety guard** if the external memory system does not check for "address space holes". That means that addresses, which
94
do not belong to a certain memory or device, do not permanently stall the processor due to an unacknowledged/unterminated bus access. If the external
95
memory system can guarantee to access **any** bus access (even it targets an unimplemented address) the timeout feature should be disabled
96
(_MEM_EXT_TIMEOUT_ = 0).
97
 
98
**Wishbone Tag**
99
 
100
The 3-bit wishbone `wb_tag_o` signal provides additional information regarding the access type. This signal
101
is compatible to the AXI4 _AxPROT_ signal.
102
 
103
* `wb_tag_o(0)` 1: privileged access (CPU is in machine mode); 0: unprivileged access
104
* `wb_tag_o(1)` always zero (indicating "secure access")
105
* `wb_tag_o(2)` 1: instruction fetch access, 0: data access
106
 
107
**Exclusive / Atomic Bus Access**
108
 
109
If the atomic memory access CPU extension (via _CPU_EXTENSION_RISCV_A_) is enabled, the CPU can
110
request an atomic/exclusive bus access via the external memory interface.
111
 
112
The load-reservate instruction (`lr.w`) will set the `wb_lock_o` signal telling the bus interconnect to establish a
113
reservation for the current accessed address (start of an exclusive access). This signal will stay asserted until
114
another memory access instruction is executed (for example a `sc.w`).
115
 
116
The memory system has to make sure that no other entity can access the reservated address until `wb_lock_o`
117
is released again. If this attempt fails, the memory system has to assert `wb_err_i` in order to indicate that the
118
reservation was broken.
119
 
120
[TIP]
121
See section <<_bus_interface>> for the CPU bus interface protocol.
122
 
123
**Endianness**
124
 
125
The NEORV32 CPU and the Processor setup are *little-endian* architectures. To allow direct connection
126
to a big-endian memory system the external bus interface provides an _Endianness configuration_. The
127 62 zero_gravi
Endianness (of the external memory interface) can be configured via the _MEM_EXT_BIG_ENDIAN_ generic.
128
By default, the external memory interface uses little-endian byte-order (like the rest of the processor / CPU).
129 60 zero_gravi
 
130
Application software can check the Endianness configuration of the external bus interface via the
131
_SYSINFO_FEATURES_MEM_EXT_ENDIAN_ flag in the processor's SYSINFO module (see section
132
<<_system_configuration_information_memory_sysinfo>> for more information).
133
 
134
**AXI4-Lite Connectivity**
135
 
136 61 zero_gravi
The AXI4-Lite wrapper (`rtl/templates/system/neorv32_SystemTop_axi4lite.vhd`) provides a Wishbone-to-
137 60 zero_gravi
AXI4-Lite bridge, compatible with Xilinx Vivado (IP packager and block design editor). All entity signals of
138
this wrapper are of type _std_logic_ or _std_logic_vector_, respectively.
139
 
140
The AXI Interface has been verified using Xilinx Vivado IP Packager and Block Designer. The AXI
141
interface port signals are automatically detected when packaging the core.
142
 
143
.Example AXI SoC using Xilinx Vivado
144
image::neorv32_axi_soc.png[]
145
 
146
[WARNING]
147
Using the auto-termination timeout feature (_MEM_EXT_TIMEOUT_ greater than zero) is **not AXI4 compliant** as the AXI protocol does not support canceling of
148 61 zero_gravi
bus transactions. Therefore, the NEORV32 top wrapper with AXI4-Lite interface (`rtl/templates/system/neorv32_SystemTop_axi4lite`) configures _MEM_EXT_TIMEOUT_ = 0 by default.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.