Subversion Repositories neorv32

Let's Get It Started!

This user guide uses the NEORV32 project _as is_ from the official `neorv32` repository.

To make your first NEORV32 project run, follow the guides from the upcoming sections. It is recommended to

follow these guides step by step and eventually in the presented order.

[TIP]

This guide uses the minimalistic and platform/toolchain agnostic SoC test setups from

`rtl/test_setups` for illustration. You can use one of the provided test setups for

your first FPGA tests. Alternatively, have a look at the `setups` folder,

which provides more sophisticated example setups for various FPGAs/FPGA boards and toolchains.

:sectnums:

== Software Toolchain Setup

To compile (and debug) executables for the NEORV32 a RISC-V toolchain is required.

There are two possibilities to get this:

1. Download and _build_ the official RISC-V GNU toolchain yourself.

2. Download and install a prebuilt version of the toolchain; this might also done via the package manager / app store of your OS

[NOTE]

The default toolchain prefix (`RISCV_PREFIX` variable) for this project is **`riscv32-unknown-elf-`**. Of course you can use any other RISC-V

toolchain (like `riscv64-unknown-elf-`) that is capable to emit code for a `rv32` architecture. Just change `RISCV_PREFIX`

according to your needs.

:sectnums:

=== Building the Toolchain from Scratch

To build the toolchain by yourself you can follow the guide from the official https://github.com/riscv-collab/riscv-gnu-toolchain GitHub page.

You need to make sure the generated toolchain fits the architecture of the NEORV32 core. To get a toolchain that even supports minimal

ISA extension configurations, it is recommend to compile for `rv32i` only. Please note that this minimal ISA also provides further ISA

extensions like `m` or `c`. Of course you can use a _multilib_ approach to generate toolchains for several target ISAs at once.

.Configuring GCC build for `rv32i` (minimal ISA)

[source,bash]

----

riscv-gnu-toolchain$ ./configure --prefix=/opt/riscv --with-arch=rv32i --with-abi=ilp32

riscv-gnu-toolchain$ make

----

[IMPORTANT]

Keep in mind that - for instance - a toolchain build with `--with-arch=rv32imc` only provides library code compiled with

compressed (`C`) and `mul`/`div` instructions (`M`)! Hence, this code cannot be executed (without

emulation) on an architecture without these extensions!

:sectnums:

=== Downloading and Installing a Prebuilt Toolchain

Alternatively, you can download a prebuilt toolchain.

:sectnums:

==== Use The Toolchain I have Build

I have compiled a GCC toolchain on a 64-bit x86 Ubuntu (Ubuntu on Windows, actually) and uploaded it to

GitHub. You can directly download the according toolchain archive as single _zip-file_ within a packed

release from https://github.com/stnolting/riscv-gcc-prebuilt.

Unpack the downloaded toolchain archive and copy the content to a location in your file system (e.g.

`/opt/riscv`). More information about downloading and installing my prebuilt toolchains can be found in

the repository's README.

:sectnums:

==== Use a Third Party Toolchain

Of course you can also use any other prebuilt version of the toolchain. There are a lot  RISC-V GCC packages out there -

even for Windows. On Linux system you might even be able to fetch a toolchain via your distribution's package manager.

[IMPORTANT]

Make sure the toolchain can (also) emit code for a `rv32i` architecture, uses the `ilp32` or `ilp32e` ABI and **was not build** using

CPU extensions that are not supported by the NEORV32 (like `D`).

:sectnums:

=== Installation

Now you have the toolchain binaries. The last step is to add them to your `PATH` environment variable (if you have not

already done so): make sure to add the _binaries_ folder (`bin`) of your toolchain.

[source,bash]

----

$ export PATH:$PATH:/opt/riscv/bin

----

You should add this command to your `.bashrc` (if you are using bash) to automatically add the RISC-V

toolchain at every console start.

:sectnums:

=== Testing the Installation

To make sure everything works fine, navigate to an example project in the NEORV32 example folder and

execute the following command:

[source,bash]

----

neorv32/sw/example/blink_led$ make check

----

This will test all the tools required for generating NEORV32 executables.

Everything is working fine if `Toolchain check OK` appears at the end.

<<<

// ####################################################################################################################

:sectnums:

== General Hardware Setup

This guide shows the basics of setting up a NEORV32 project for FPGA implementation (or simulation only)

_from scratch_. It uses a _simplified_ test "SoC" setup of the processor to keeps things simple at the beginning.

This simple setup is intended for evaluation or as "hello world" project to check out the NEORV32

on _your_ FPGA board.

[TIP]

If you want to use a more sophisticated pre-defined setup to start with, check out the

`setups` folder, which provides example setups for various FPGA, boards and toolchains.

The NEORV32 project features two minimalistic pre-configured test setups in

https://github.com/stnolting/neorv32/blob/master/rtl/test_setups[`rtl/test_setups`].

Both test setups only implement very basic processor and CPU features.

The main difference between the two setups is the processor boot concept - so how to get a software executable

_into_ the processor:

* **`rtl/test_setups/neorv32_testsetup_approm.vhd`**: this setup does not require a connection via UART. The

software executable is "installed" into the bitstream to initialize a read-only memory. Use this setup

if your FPGA board does _not_ provide a UART interface.

* **`rtl/test_setups/neorv32_testsetup_bootloader.vhd`**: this setups uses the UART and the default NEORV32

bootloader to upload new software executables. Use this setup if your board _does_ provide a UART interface.

.NEORV32 "hello world" test setup (`rtl/test_setups/neorv32_testsetup_bootloader.vhd`)

image::neorv32_test_setup.png[align=center]

.External Clock Source

[NOTE]

These test setups are intended to be directly used as **design top entity**. Of course you can also instantiate them

into another design unit. If your FPGA board only provides _very fast_ external clock sources (like on the FOMU board)

you might need to add clock management components (PLLs, DCMs, MMCMs, ...) to the test setup or to the according top entity

if you instantiate one of the test setups.

[start=1]

. Create a new project with your FPGA EDA tool of choice.

. Add all VHDL files from the project's `rtl/core` folder to your project.

.Internal Memories

[IMPORTANT]

For a _general_ first setup (technology-independent) use the _default_ memory architectures for the internal memories

(IMEM and DMEM). These are located in `rtl/core/mem`, so **make sure to add the files from `rtl/core/mem` to your project, too**. +

 +

If synthesis cannot efficiently map those default memory descriptions to the available memory resources, you can later replace the

default memory architectures by optimized platform-specific memory architectures. **Example:** The `setups/radiant/UPduino_v3`

example setup uses optimized memory primitives. Hence, it does not include the default memory architectures from

`rtl/core/mem` as these are replaced by device-specific implementations. However, it still has to include the entity

definitions from `rtl/core`.

[start=3]

. Make sure to add all the rtl files to a new library called `neorv32`. If your FPGA tools does not

provide a field to enter the library name, check out the "properties" menu of the added rtl files.

.Compile order

[NOTE]

Some tools (like Lattice Radiant) might require a _manual compile order_ of the VHDL source files to identify the dependencies.

The package file `neorv32_package.vhd` should be analyzed first followed by the memory image files (`neorv32_application_imagevhd`

and `neorv32_bootloader_image.vhd`) and the entity-only files (`neorv32_*mem.entity.vhd`).

[start=4]

. The `rtl/core/neorv32_top.vhd` VHDL file is the top entity of the NEORV32 processor, which can be

instantiated into the "real" project. However, in this tutorial we will use one of the pre-defined

test setups from `rtl/test_setups` (see above).

[IMPORTANT]

Make sure to include the `neorv32` package into your design when instantiating the processor: add

`library neorv32;` and `use neorv32.neorv32_package.all;` to your design unit.

[start=5]

. Add the pre-defined test setup of choice to the project, too, and select it as _top entity_.

. The entity of both test setups

provide a minimal set of configuration generics, that might have to be adapted to match your FPGA and board:

.Test setup entity - configuration generics

[source,vhdl]

----

  generic (

    -- adapt these for your setup --

    CLOCK_FREQUENCY   : natural := 100000000; <1>

    MEM_INT_IMEM_SIZE : natural := 16*1024;   <2>

    MEM_INT_DMEM_SIZE : natural := 8*1024     <3>

  );

----

<1> Clock frequency of `clk_i` signal in Hertz

<2> Default size of internal instruction memory: 16kB

<3> Default size of internal data memory: 8kB

[start=7]

. If you feel like it - or if your FPGA does not provide sufficient resources - you can modify the

_memory sizes_ (`MEM_INT_IMEM_SIZE` and `MEM_INT_DMEM_SIZE` - marked with notes "2" and "3"). But as mentioned

above, let's keep things simple at first and use the standard configuration for now.

. There is one generic that _has to be set according to your FPGA board_ setup: the actual clock frequency

of the top's clock input signal (`clk_i`). Use the `CLOCK_FREQUENCY` generic to specify your clock source's

frequency in Hertz (Hz).

[NOTE]

If you have changed the default memory configuration (`MEM_INT_IMEM_SIZE` and `MEM_INT_DMEM_SIZE` generics)

keep those new sizes in mind - these values are required for setting

up the software framework in the next section <<_general_software_framework_setup>>.

[start=9]

. Depending on your FPGA tool of choice, it is time to assign the signals of the test setup top entity to

the according pins of your FPGA board. All the signals can be found in the entity declaration of the

corresponding test setup:

.Entity signals of `neorv32_testsetup_approm.vhd`

[source,vhdl]

----

  port (

    -- Global control --

    clk_i       : in  std_ulogic; -- global clock, rising edge

    rstn_i      : in  std_ulogic; -- global reset, low-active, async

    -- GPIO --

    gpio_o      : out std_ulogic_vector(7 downto 0) -- parallel output

  );

----

.Entity signals of `neorv32_testsetup_bootloader.vhd`

[source,vhdl]

----

  port (

    -- Global control --

    clk_i       : in  std_ulogic; -- global clock, rising edge

    rstn_i      : in  std_ulogic; -- global reset, low-active, async

    -- GPIO --

    gpio_o      : out std_ulogic_vector(7 downto 0); -- parallel output

    -- UART0 --

    uart0_txd_o : out std_ulogic; -- UART0 send data

    uart0_rxd_i : in  std_ulogic  -- UART0 receive data

  );

----

.Signal Polarity

[NOTE]

If your FPGA board has inverse polarity for certain input/output you can add `not` gates. Example: The reset signal

`rstn_i` is low-active by default; the LEDs connected to `gpio_o` high-active by default.

You can do this in your board top if you instantiate the test setup,

or _inside_ the test setup if this is your top entity (low-active LEDs example: `gpio_o <= NOT con_gpio_o(7 downto 0);`).

[start=10]

. Attach the clock input `clk_i` to your clock source and connect the reset line `rstn_i` to a button of

your FPGA board. Check whether it is low-active or high-active - the reset signal of the processor is

**low-active**, so maybe you need to invert the input signal.

. If possible, connected _at least_ bit `0` of the GPIO output port `gpio_o` to a LED (see "Signal Polarity" note above).

. Finally, if your are using the UART-based test setup (`neorv32_testsetup_bootloader.vhd`)

connect the UART communication signals `uart0_txd_o` and `uart0_rxd_i` to the host interface (e.g. USB-UART converter).

. Perform the project HDL compilation (synthesis, mapping, bitstream generation).

. Program the generated bitstream into your FPGA and press the button connected to the reset signal.

. Done! The LED at `gpio_o(0)` should be flashing now.

[TIP]

After the GCC toolchain for compiling RISC-V source code is ready (chapter <<_general_software_framework_setup>>),

you can advance to one of these chapters to learn how to get a software executable into your processor setup:

* If you are using the `neorv32_testsetup_approm.vhd` setup: See section <<_installing_an_executable_directly_into_memory>>.

* If you are using the `neorv32_testsetup_bootloader.vhd` setup: See section <<_uploading_and_starting_of_a_binary_executable_image_via_uart>>.

<<<

// ####################################################################################################################

:sectnums:

== General Software Framework Setup

To allow executables to be _actually executed_ on the NEORV32 Processor the configuration of the software framework

has to be aware to the hardware configuration. This guide focuses on the memory configuration. To enabled

certain CPU ISA features refer to the <<_enabling_risc_v_cpu_extensions>> section.

[TIP]

If you have **not** changed the _default_ memory configuration in section <<_general_hardware_setup>>

you are already done and you can skip the rest of this guide.

[start=1]

. Open the NEORV32 linker script `sw/common/neorv32.ld` with a text editor. Right at the

beginning of this script you will find the `MEMORY` configuration listing the different memory section:

.Cut-out of the linker script `neorv32.ld`: `ram` memory section configuration

[source,c]

----

MEMORY

{

  ram  (rwx) : ORIGIN = 0x80000000, LENGTH = DEFINED(make_bootloader) ? 512 : 8*1024 <1>

...

----

<1> Size of the data memory address space (right-most value) (internal/external DMEM); here 8kB

[start=2]

. We only need to change the `ram` section, which presents the available data address space.

If you have changed the DMEM (_MEM_INT_DMEM_SIZE_ generic) size adapt the `LENGTH` parameter of the `ram`

section (here: `8*1024`) so it is equal to your DMEM hardware configuration.

[IMPORTANT]

Make sure you only modify the _right-most_ value (here: 8*1024)! +

The "`512`" are not relevant for the application.

[start=3]

. Done! Save your changes and close the linker script.

.Advanced: Section base address and size

[IMPORTANT]

More information can be found in the datasheet section https://stnolting.github.io/neorv32/#_address_space[Address Space].

<<<

// ####################################################################################################################

:sectnums:

== Application Program Compilation

This guide shows how to compile an example C-code application into a NEORV32 executable that

can be uploaded via the bootloader or the on-chip debugger.

[IMPORTANT]

If your FPGA board does not provide such an interface - don't worry!

Section <<_installing_an_executable_directly_into_memory>> shows how to

run custom programs on your FPGA setup without having a UART.

[start=1]

. Open a terminal console and navigate to one of the project's example programs. For instance, navigate to the

simple `sw/example_blink_led` example program. This program uses the NEORV32 GPIO module to display

an 8-bit counter on the lowest eight bit of the `gpio_o` output port.

. To compile the project and generate an executable simply execute:

[source,bash]

----

neorv32/sw/example/blink_led$ make clean_all exe

----

[start=3]

. We are using the `clean_all` target to make sure everything is re-build.

. This will compile and link the application sources together with all the included libraries. At the end,

your application is transformed into an ELF file (`main.elf`). The _NEORV32 image generator_ (in `sw/image_gen`)

takes this file and creates a final executable. The makefile will show the resulting memory utilization and

the executable size:

[source,bash]

----

neorv32/sw/example/blink_led$ make clean_all exe

Memory utilization:

   text    data     bss     dec     hex filename

   3176       0     120    3296     ce0 main.elf

Compiling ../../../sw/image_gen/image_gen

Executable (neorv32_exe.bin) size in bytes:

3188

----

[start=5]

. That's it. The `exe` target has created the actual executable `neorv32_exe.bin` in the current folder

that is ready to be uploaded to the processor.

[TIP]

The compilation process will also create a `main.asm` assembly listing file in the current folder, which

shows the actual assembly code of the application.

<<<

// ####################################################################################################################

:sectnums:

== Uploading and Starting of a Binary Executable Image via UART

Follow this guide to use the bootloader to upload an executable via UART.

[NOTE]

This concept uses the default "Indirect Boot" scenario that uses the bootloader to upload new executables.

See datasheet section https://stnolting.github.io/neorv32/#_indirect_boot[Indirect Boot] for more information.

[IMPORTANT]

If your FPGA board does not provide such an interface - don't worry!

Section <<_installing_an_executable_directly_into_memory>> shows how to

run custom programs on your FPGA setup without having a UART.

[start=1]

. Connect the primary UART (UART0) interface of your FPGA board to a serial port of your host computer.

. Start a terminal program. In this tutorial, I am using TeraTerm for Windows. You can download it fore free

from https://ttssh2.osdn.jp/index.html.en

[NOTE]

_Any_ terminal program that can connect to a serial port should work. However, make sure the program

can transfer data in _raw_ byte mode without any protocol overhead around it.

[start=3]

. Open a connection to the the serial port your UART is connected to. Configure the terminal setting according to the

following parameters:

* 19200 Baud

* 8 data bits

* 1 stop bit

* no parity bits

* _no_ transmission/flow control protocol

* receiver (host computer) newline on `\r\n` (carriage return & newline)

[start=4]

. Also make sure that single chars are send from your computer _without_ any consecutive "new line" or "carriage

return" commands (this is highly dependent on your terminal application of choice, TeraTerm only

sends the raw chars by default).

. Press the NEORV32 reset button to restart the bootloader. The status LED starts blinking and the

bootloader intro screen appears in your console. Hurry up and press any key (hit space!) to abort the

automatic boot sequence and to start the actual bootloader user interface console.

.Bootloader console; aborted auto-boot sequence

[source,bash]

----

<< NEORV32 Bootloader >>

BLDV: Mar 23 2021

HWV:  0x01050208

CLK:  0x05F5E100

MISA: 0x40901105

ZEXT: 0x00000023

PROC: 0x0EFF0037

IMEM: 0x00004000 bytes @ 0x00000000

DMEM: 0x00002000 bytes @ 0x80000000

Autoboot in 8s. Press key to abort.

Aborted.

Available commands:

h: Help

r: Restart

u: Upload

s: Store to flash

l: Load from flash

e: Execute

CMD:>

----

[start=6]

. Execute the "Upload" command by typing `u`. Now the bootloader is waiting for a binary executable to be send.

[source,bash]

----

CMD:> u

Awaiting neorv32_exe.bin...

----

[start=7]

. Use the "send file" option of your terminal program to send a NEORV32 executable (`neorv32_exe.bin`).

. Again, make sure to transmit the executable in raw binary mode (no transfer protocol).

When using TeraTerm, select the "binary" option in the send file dialog.

. If everything went fine, OK will appear in your terminal:

[source,bash]

----

CMD:> u

Awaiting neorv32_exe.bin... OK

----

[start=10]

. The executable is now in the instruction memory of the processor. To execute the program right

now run the "Execute" command by typing `e`:

[source,bash]

----

CMD:> u

Awaiting neorv32_exe.bin... OK

CMD:> e

Booting...

Blinking LED demo program

----

[start=11]

. If everything went fine, you should see the LEDs blinking.

[NOTE]

The bootloader will print error codes if something went wrong.

See section https://stnolting.github.io/neorv32/#_bootloader[Bootloader] of the NEORV32 datasheet for more information.

[TIP]

See section <<_programming_an_external_spi_flash_via_the_bootloader>> to learn how to use an external SPI

flash for nonvolatile program storage.

[TIP]

Executables can also be uploaded via the **on-chip debugger**.

See section <<_debugging_with_gdb>> for more information.

<<<

// ####################################################################################################################

:sectnums:

== Installing an Executable Directly Into Memory

If you do not want to use the bootloader (or the on-chip debugger) for executable upload or if your setup does not provide

a serial interface for that, you can also directly install an application into embedded memory.

This concept uses the "Direct Boot" scenario that implements the processor-internal IMEM as ROM, which is

pre-initialized with the application's executable during synthesis. Hence, it provides _non-volatile_ storage of the

executable inside the processor. This storage cannot be altered during runtime and any source code modification of

the application requires to re-program the FPGA via the bitstream.

[TIP]

See datasheet section https://stnolting.github.io/neorv32/#_direct_boot[Direct Boot] for more information.

Using the IMEM as ROM:

* for this boot concept the bootloader is no longer required

* this concept only works for the internal IMEM (but can be extended to work with external memories coupled via the processor's bus interface)

* make sure that the memory components (like block RAM) the IMEM is mapped to support an initialization via the bitstream

[start=1]

. At first, make sure your processor setup actually implements the internal IMEM: the `MEM_INT_IMEM_EN` generics has to be set to `true`:

.Processor top entity configuration - enable internal IMEM

[source,vhdl]

----

  -- Internal Instruction memory --

  MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory

----

[start=2]

. For this setup we do not want the bootloader to be implemented at all. Disable implementation of the bootloader by setting the

`INT_BOOTLOADER_EN` generic to `false`. This will also modify the processor-internal IMEM so it is initialized with the executable during synthesis.

.Processor top entity configuration - disable internal bootloader

[source,vhdl]

----

  -- General --

  INT_BOOTLOADER_EN => false, -- boot configuration: false = boot from int/ext (I)MEM

----

[start=3]

. To generate an "initialization image" for the IMEM that contains the actual application, run the `install` target when compiling your application:

[source,bash]

----

neorv32/sw/example/blink_led$ make clean_all install

Memory utilization:

   text    data     bss     dec     hex filename

   3176       0     120    3296     ce0 main.elf

Compiling ../../../sw/image_gen/image_gen

Installing application image to ../../../rtl/core/neorv32_application_image.vhd

----

[start=4]

. The `install` target has compiled all the application sources but instead of creating an executable (`neorv32_exe.bit`) that can be uploaded via the

bootloader, it has created a VHDL memory initialization image `core/neorv32_application_image.vhd`.

. This VHDL file is automatically copied to the core's rtl folder (`rtl/core`) so it will be included for the next synthesis.

. Perform a new synthesis. The IMEM will be build as pre-initialized ROM (inferring embedded memories if possible).

. Upload your bitstream. Your application code now resides unchangeable in the processor's IMEM and is directly executed after reset.

The synthesis tool / simulator will print asserts to inform about the (IMEM) memory / boot configuration:

[source]

----

NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Direct boot from memory (processor-internal IMEM).

NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal IMEM as ROM (3176 bytes), pre-initialized with application.

----

<<<

// ####################################################################################################################

:sectnums:

== Setup of a New Application Program Project

[start=1]

. The easiest way of creating a _new_ software application project is to copy an _existing_ one. This will keep all

file dependencies. For example you can copy `sw/example/blink_led` to `sw/example/flux_capacitor`.

. If you want to place you application somewhere outside `sw/example` you need to adapt the application's makefile.

In the makefile you will find a variable that keeps the relative or absolute path to the NEORV32 repository home

folder. Just modify this variable according to your new project's home location:

[source,makefile]

----

# Relative or absolute path to the NEORV32 home folder (use default if not set by user)

NEORV32_HOME ?= ../../..

----

[start=3]

. If your project contains additional source files outside of the project folder, you can add them to

the `APP_SRC` variable:

[source,makefile]

----

# User's application sources (add additional files here)

APP_SRC = $(wildcard *.c) ../somewhere/some_file.c

----

[start=4]

. You also can add a folder containing your application's include files to the

`APP_INC` variable (do not forget the `-I` prefix):

[source,makefile]

----

# User's application include folders (don't forget the '-I' before each entry)

APP_INC = -I . -I ../somewhere/include_stuff_folder

----

<<<

// ####################################################################################################################

:sectnums:

== Enabling RISC-V CPU Extensions

Whenever you enable/disable a RISC-V CPU extensions via the according `CPU_EXTENSION_RISCV_x` generic, you need to

adapt the toolchain configuration so the compiler can actually generate according code for it.

To do so, open the makefile of your project (for example `sw/example/blink_led/makefile`) and scroll to the

"USER CONFIGURATION" section right at the beginning of the file. You need to modify the `MARCH` variable and eventually

the `MABI` variable according to your CPU hardware configuration.

[source,makefile]

----

# CPU architecture and ABI

MARCH ?= rv32i <1>

MABI  ?= ilp32 <2>

----

<1> MARCH = Machine architecture ("ISA string")

<2> MABI = Machine binary interface

For example, if you enable the RISC-V `C` extension (16-bit compressed instructions) via the `CPU_EXTENSION_RISCV_C`

generic (set `true`) you need to add the `c` extension also to the `MARCH` ISA string in order to make the compiler

emit compressed instructions.

.Privileged Architecture Extensions

[IMPORTANT]

Privileged architecture extensions like `Zicsr` or `Zifencei` are "used" _implicitly_ by the compiler. Hence, according

instruction will only be generated when "encoded" via inline assembly or when linking according libraries. In this case,

these instruction will _always_ be emitted (even if the according extension is not specified in `MARCH`). +

**I recommend to _not_ specify any privileged architecture extensions in `MARCH`.**

[WARNING]

ISA extension enabled in hardware can be a superset of the extensions enabled in software, but not the other way

around. For example generating compressed instructions for a CPU configuration that has the `c` extension disabled

will cause _illegal instruction exceptions_ at runtime.

You can also override the default `MARCH` and `MABI` configurations from the makefile when invoking the makefile:

[source,bash]

----

$ make MARCH=rv32ic clean_all all

----

[NOTE]

The RISC-V ISA string for `MARCH` follows a certain _canonical_ structure:

`rev32[i/e][m][a][f][d][g][q][c][b][v][n]...` For example `rv32imac` is valid while `rv32icma` is not.

<<<

// ####################################################################################################################

:sectnums:

== Application-Specific Processor Configuration

Due to the processor's configuration options, which are mainly defined via the top entity VHDL generics, the SoC

can be tailored to the application-specific requirements. Note that this chapter does not focus on optional

_SoC features_ like IO/peripheral modules. It rather gives ideas on how to optimize for _overall goals_

like performance and area.

[NOTE]

Please keep in mind that optimizing the design in one direction (like performance) will also effect other potential

optimization goals (like area and energy).

=== Optimize for Performance

The following points show some concepts to optimize the processor for performance regardless of the costs

(i.e. increasing area and energy requirements):

* Enable all performance-related RISC-V CPU extensions that implement dedicated hardware accelerators instead

of emulating operations entirely in software:  `M`, `C`, `Zfinx`

* Enable mapping of compleX CPU operations to dedicated hardware: `FAST_MUL_EN => true` to use DSP slices for

multiplications, `FAST_SHIFT_EN => true` use a fast barrel shifter for shift operations.

* Implement the instruction cache: `ICACHE_EN => true`

* Use as many _internal_ memory as possible to reduce memory access latency: `MEM_INT_IMEM_EN => true` and

`MEM_INT_DMEM_EN => true`, maximize `MEM_INT_IMEM_SIZE` and `MEM_INT_DMEM_SIZE`

* Increase the CPU's instruction prefetch buffer size: `CPU_IPB_ENTRIES`

* _To be continued..._

=== Optimize for Size

The NEORV32 is a size-optimized processor system that is intended to fit into tiny niches within large SoC

designs or to be used a customized microcontroller in really tiny / low-power FPGAs (like Lattice iCE40).

Here are some ideas how to make the processor even smaller while maintaining it's _general purpose system_

concept and maximum RISC-V compatibility.

**SoC**

* This is obvious, but exclude all unused optional IO/peripheral modules from synthesis via the processor

configuration generics.

* If an IO module provides an option to configure the number of "channels", constrain this number to the

actually required value (e.g. the PWM module `IO_PWM_NUM_CH` or the external interrupt controller `XIRQ_NUM_CH`).

* Reduce the FIFO sizes of implemented modules (e.g. `SLINK_TX_FIFO`).

* Disable the instruction cache (`ICACHE_EN => false`) if the design only uses processor-internal IMEM

and DMEM memories.

* _To be continued..._

**CPU**

* Use the _embedded_ RISC-V CPU architecture extension (`CPU_EXTENSION_RISCV_E`) to reduce block RAM utilization.

* The compressed instructions extension (`CPU_EXTENSION_RISCV_C`) requires additional logic for the decoder but

also reduces program code size by approximately 30%.

* If not explicitly used/required, constrain the CPU's counter sizes: `CPU_CNT_WIDTH` for `[m]instret[h]`

(number of instruction) and `[m]cycle[h]` (number of cycles) counters. You can even remove these counters

by setting `CPU_CNT_WIDTH => 0` if they are not used at all (note, this is not RISC-V compliant).

* Reduce the CPU's prefetch buffer size (`CPU_IPB_ENTRIES`).

* Map CPU shift operations to a small and iterative shifter unit (`FAST_SHIFT_EN => false`).

* If you have unused DSP block available, you can map multiplication operations to those slices instead of

using LUTs to implement the multiplier (`FAST_MUL_EN => true`).

* If there is no need to execute division in hardware, use the `Zmmul` extension instead of the full-scale

`M` extension.

* Disable CPU extension that are not explicitly used (`A`, `U`, `Zfinx`).

* _To be continued..._

=== Optimize for Clock Speed

The NEORV32 Processor and CPU are designed to provide minimal logic between register stages to keep the

critical path as short as possible. When enabling additional extension or modules the impact on the existing

logic is also kept at a minimum to prevent timing degrading. If there is a major impact on existing

logic (example: many physical memory protection address configuration registers) the VHDL code automatically

adds additional register stages to maintain critical path length. Obviously, this increases operation latency.

In order to optimize for a minimal critical path (= maximum clock speed) the following points should be considered:

* Complex CPU extensions (in terms of hardware requirements) should be avoided (examples: floating-point unit, physical memory protection).

* Large carry chains (>32-bit) should be avoided (constrain CPU counter sizes: e.g. `CPU_CNT_WIDTH => 32` and `HPM_NUM_CNTS => 32`).

* If the target FPGA provides sufficient DSP resources, CPU multiplication operations can be mapped to DSP slices (`FAST_MUL_EN => true`)

reducing LUT usage and critical path impact while also increasing overall performance.

* Use the synchronous (registered) RX path configuration of the external memory interface (`MEM_EXT_ASYNC_RX => false`).

* _To be continued..._

[NOTE]

The short and fixed-length critical path allows to integrate the core into existing clock domains.

So no clock domain-crossing and no sub-clock generation is required. However, for very high clock

frequencies (this is technology / platform dependent) clock domain crossing becomes crucial for chip-internal

connections.

=== Optimize for Energy

There are no _dedicated_ configuration options to optimize the processor for energy (minimal consumption;

energy/instruction ratio) yet. However, a reduced processor area (<<_optimize_for_size>>) will also reduce

static energy consumption.

To optimize your setup for low-power applications, you can make use of the CPU sleep mode (`wfi` instruction).

Put the CPU to sleep mode whenever possible. Disable all processor modules that are not actually used (exclude them

from synthesis if the will be _never_ used; disable the module via it's control register if the module is not

_currently_ used). When is sleep mode, you can keep a timer module running (MTIME or the watch dog) to wake up

the CPU again. Since the wake up is triggered by _any_ interrupt, the external interrupt controller can also

be used to wake up the CPU again. By this, all timers (and all other modules) can be deactivated as well.

.Processor-internal clock generator shutdown

[TIP]

If _no_ IO/peripheral module is currently enabled, the processor's internal clock generator circuit will be

shut down reducing switching activity and thus, dynamic energy consumption.

<<<

// ####################################################################################################################

:sectnums:

== Adding Custom Hardware Modules

In resemblance to the RISC-V ISA, the NEORV32 processor was designed to ease customization and _extensibility_.

The processor provides several predefined options to add application-specific custom hardware modules and accelerators.

=== Standard (_External_) Interfaces

The processor already provides a set of standard interfaces that are intended to connect _chip-external_ devices.

However, these interfaces can also be used chip-internally. The most suitable interfaces are

https://stnolting.github.io/neorv32/#_general_purpose_input_and_output_port_gpio[GPIO],

https://stnolting.github.io/neorv32/#_primary_universal_asynchronous_receiver_and_transmitter_uart0[UART],

https://stnolting.github.io/neorv32/#_serial_peripheral_interface_controller_spi[SPI] and

https://stnolting.github.io/neorv32/#_two_wire_serial_interface_controller_twi[TWI].

The SPI and (especially) the GPIO interfaces might be the most straightforward approaches since they

have a minimal  protocol overhead. Device-specific interrupt capabilities can be added using the

https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq[External Interrupt Controller (XIRQ)].

Beyond simplicity, these interface only provide a very limited bandwidth and require more sophisticated

software handling ("bit-banging" for the GPIO).

=== External Bus Interface

The https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite[External Bus Interface]

provides the classic approach to connect to custom IP. By default, the bus interface implements the widely adopted

Wishbone interface standard. However, this project also includes wrappers to bridge to other protocol standards like ARM's

AXI4-Lite or Intel's Avalon. By using a full-featured bus protocol, complex SoC structures can be implemented (including

several modules and even multi-core architectures). Many FPGA EDA tools provide graphical editors to build and customize

whole SoC architectures and even include pre-defined IP libraries.

.Example AXI SoC using Xilinx Vivado

image::neorv32_axi_soc.png[]

The bus interface uses a memory-mapped approach. All data transfers are handled by simple load/store operations since the

external bus interface is mapped into the processor's https://stnolting.github.io/neorv32/#_address_space[address space].

This allows a very simple still high-bandwidth communications.

=== Stream Link Interface

The NEORV32 https://stnolting.github.io/neorv32/#_stream_link_interface_slink[Stream Link Interface] provides

point-to-point, unidirectional and parallel data channels that can be used to transfer streaming data. In

contrast to the external bus interface, the streaming data does not provide any kind of "direction" control,

so it can be seen as "constant address bursts". The stream link interface provides less protocol overhead

and less latency than the bus interface. Furthermore, FIFOs can be be configured to each direction (RX/TX) to

allow more CPU-independent operation.

=== Custom Functions Subsystem

The NEORV32 https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs[Custom Functions Subsystem] is

an "empty" template for a processor-internal module. It provides 32 32-bit memory-mapped interface

registers that can be used to communicate with any arbitrary custom design logic. The intentions of this

subsystem is to provide a simple base, where the user can concentrate on implementing the actual design logic

rather than taking care of the communication between the CPU/software and the design logic. The interface

registers are already allocated within the processor's address space and are supported by the software framework

via low-level hardware access mechanisms. Additionally, the CFS provides a direct pre-defined interrupt channel to

the CPU, which is also supported by the NEORV32 runtime environment.

<<<

// ####################################################################################################################

:sectnums:

== Customizing the Internal Bootloader

The NEORV32 bootloader provides several options to configure and customize it for a certain application setup.

This configuration is done by passing _defines_ when compiling the bootloader. Of course you can also

modify to bootloader source code to provide a setup that perfectly fits your needs.

[IMPORTANT]

Each time the bootloader sources are modified, the bootloader has to be re-compiled (and re-installed to the

bootloader ROM) and the processor has to be re-synthesized.

[NOTE]

Keep in mind that the maximum size for the bootloader is limited to 32kB and should be compiled using the

base ISA `rv32i` only to ensure it can work independently of the actual CPU configuration.

.Bootloader configuration parameters

[cols="<2,^1,^2,<6"]

[options="header", grid="rows"]

|=======================

| Parameter | Default | Legal values | Description

4+^| Serial console interface

| `UART_EN`   | `1` | `0`, `1` | Set to `0` to disable UART0 (no serial console at all)

| `UART_BAUD` | `19200` | _any_ | Baud rate of UART0

4+^| Status LED

| `STATUS_LED_EN`  | `1` | `0`, `1` | Enable bootloader status led ("heart beat") at `GPIO` output port pin #`STATUS_LED_PIN` when `1`

| `STATUS_LED_PIN` | `0` | `0` ... `31` | `GPIO` output pin used for the high-active status LED

4+^| Boot configuration

| `AUTO_BOOT_SPI_EN`  | `0` | `0`, `1` | Set `1` to enable immediate boot from external SPI flash

| `AUTO_BOOT_OCD_EN`  | `0` | `0`, `1` | Set `1` to enable boot via on-chip debugger (OCD)

| `AUTO_BOOT_TIMEOUT` | `8` | _any_ | Time in seconds after the auto-boot sequence starts (if there is no UART input by user); set to 0 to disabled auto-boot sequence

4+^| SPI configuration

| `SPI_EN`                | `1` | `0`, `1` | Set `1` to enable the usage of the SPI module (including load/store executables from/to SPI flash options)

| `SPI_FLASH_CS`          | `0` | `0` ... `7` | SPI chip select output (`spi_csn_o`) for selecting flash

| `SPI_FLASH_SECTOR_SIZE` | `65536` | _any_ | SPI flash sector size in bytes

| `SPI_FLASH_CLK_PRSC`    | `CLK_PRSC_8`  | `CLK_PRSC_2` `CLK_PRSC_4` `CLK_PRSC_8` `CLK_PRSC_64` `CLK_PRSC_128` `CLK_PRSC_1024` `CLK_PRSC_2024` `CLK_PRSC_4096` | SPI clock pre-scaler (dividing main processor clock)

| `SPI_BOOT_BASE_ADDR`    | `0x08000000` | _any_ 32-bit value | Defines the _base_ address of the executable in external flash

|=======================

Each configuration parameter is implemented as C-language `define` that can be manually overridden (_redefined_) when

invoking the bootloader's makefile. The according parameter and its new value has to be _appended_

(using `+=`) to the makefile `USER_FLAGS` variable. Make sure to use the `-D` prefix here.

For example, to configure a UART Baud rate of 57600 and redirecting the status LED to output pin 20

use the following command (_in_ the bootloader's source folder `sw/bootloader`):

.Example: customizing, re-compiling and re-installing the bootloader

[source,console]

----

$ make USER_FLAGS+=-DUART_BAUD=57600 USER_FLAGS+=-DSTATUS_LED_PIN=20 clean_all bootloader

----

[NOTE]

The `clean_all` target ensure that all libraries are re-compiled. The `bootloader` target will automatically

compile and install the bootloader to the HDL boot ROM (updating `rtl/core/neorv32_bootloader_image.vhd`).

:sectnums:

=== Bootloader Boot Configuration

The bootloader provides several _boot configurations_ that define where the actual application's executable

shall be fetched from. Note that the non-default boot configurations provide a smaller memory footprint

reducing boot ROM implementation costs.

:sectnums!:

==== Default Boot Configuration

The _default_ bootloader configuration provides a UART-based user interface that allows to upload new executables

at any time. Optionally, the executable can also be programmed to an external SPI flash by the bootloader (see

section <<_programming_an_external_spi_flash_via_the_bootloader>>).

This configuration also provides an _automatic boot sequence_ (auto-boot) which will start fetching an executable

from external SPI flash using the default SPI configuration. By this, the default bootloader configuration

provides a "non volatile program storage" mechanism that automatically boot from external SPI flash

(after `AUTO_BOOT_TIMEOUT`) while still providing the option to re-program SPI flash at any time

via the UART interface.

:sectnums!: