OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_boot_rom.vhd] - Blame information for rev 62

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - Processor-internal bootloader ROM (BOOTROM) >>                                   #
3
-- # ********************************************************************************************* #
4
-- # BSD 3-Clause License                                                                          #
5
-- #                                                                                               #
6
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
7
-- #                                                                                               #
8
-- # Redistribution and use in source and binary forms, with or without modification, are          #
9
-- # permitted provided that the following conditions are met:                                     #
10
-- #                                                                                               #
11
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
12
-- #    conditions and the following disclaimer.                                                   #
13
-- #                                                                                               #
14
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
15
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
16
-- #    provided with the distribution.                                                            #
17
-- #                                                                                               #
18
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
19
-- #    endorse or promote products derived from this software without specific prior written      #
20
-- #    permission.                                                                                #
21
-- #                                                                                               #
22
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
23
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
24
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
25
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
26
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
27
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
28
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
29
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
30
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
31
-- # ********************************************************************************************* #
32
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
33
-- #################################################################################################
34
 
35
library ieee;
36
use ieee.std_logic_1164.all;
37
use ieee.numeric_std.all;
38
 
39
library neorv32;
40
use neorv32.neorv32_package.all;
41
use neorv32.neorv32_bootloader_image.all; -- this file is generated by the image generator
42
 
43
entity neorv32_boot_rom is
44 23 zero_gravi
  generic (
45 62 zero_gravi
    BOOTROM_BASE : std_ulogic_vector(31 downto 0) -- boot ROM base address
46 23 zero_gravi
  );
47 2 zero_gravi
  port (
48
    clk_i  : in  std_ulogic; -- global clock line
49
    rden_i : in  std_ulogic; -- read enable
50
    addr_i : in  std_ulogic_vector(31 downto 0); -- address
51
    data_o : out std_ulogic_vector(31 downto 0); -- data out
52
    ack_o  : out std_ulogic -- transfer acknowledge
53
  );
54
end neorv32_boot_rom;
55
 
56
architecture neorv32_boot_rom_rtl of neorv32_boot_rom is
57
 
58 61 zero_gravi
  -- determine required ROM size in bytes (expand to next power of two) --
59
  constant boot_rom_size_index_c : natural := index_size_f((bootloader_init_image'length)); -- address with (32-bit entries)
60
  constant boot_rom_size_c       : natural := (2**boot_rom_size_index_c)*4; -- size in bytes
61 2 zero_gravi
 
62 61 zero_gravi
  -- IO space: module base address --
63
  constant hi_abb_c : natural := 31; -- high address boundary bit
64
  constant lo_abb_c : natural := index_size_f(boot_rom_max_size_c); -- low address boundary bit
65 2 zero_gravi
 
66
  -- local signals --
67
  signal acc_en : std_ulogic;
68
  signal rden   : std_ulogic;
69
  signal rdata  : std_ulogic_vector(31 downto 0);
70 61 zero_gravi
  signal addr   : std_ulogic_vector(boot_rom_size_index_c-1 downto 0);
71 2 zero_gravi
 
72 61 zero_gravi
  -- ROM - initialized with executable code --
73
  constant mem_rom : mem32_t(0 to boot_rom_size_c/4-1) := mem32_init_f(bootloader_init_image, boot_rom_size_c/4);
74 2 zero_gravi
 
75
begin
76
 
77 61 zero_gravi
  -- Sanity Checks --------------------------------------------------------------------------
78
  -- -------------------------------------------------------------------------------------------
79
  assert false report "NEORV32 PROCESSOR CONFIG NOTE: Implementing internal bootloader ROM (" & natural'image(boot_rom_size_c) & " bytes)." severity note;
80
  assert not (boot_rom_size_c > boot_rom_max_size_c) report "NEORV32 PROCESSOR CONFIG ERROR! Boot ROM size out of range! Max "& natural'image(boot_rom_max_size_c) & " bytes." severity error;
81
 
82
 
83 2 zero_gravi
  -- Access Control -------------------------------------------------------------------------
84
  -- -------------------------------------------------------------------------------------------
85 61 zero_gravi
  acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = BOOTROM_BASE(hi_abb_c downto lo_abb_c)) else '0';
86
  addr   <= addr_i(boot_rom_size_index_c+1 downto 2); -- word aligned
87 2 zero_gravi
 
88
 
89
  -- Memory Access --------------------------------------------------------------------------
90
  -- -------------------------------------------------------------------------------------------
91
  mem_file_access: process(clk_i)
92
  begin
93
    if rising_edge(clk_i) then
94
      rden <= rden_i and acc_en;
95
      if (acc_en = '1') then -- reduce switching activity when not accessed
96 61 zero_gravi
        rdata <= mem_rom(to_integer(unsigned(addr)));
97 2 zero_gravi
      end if;
98
    end if;
99
  end process mem_file_access;
100
 
101
  -- output gate --
102
  data_o <= rdata when (rden = '1') else (others => '0');
103
  ack_o  <= rden;
104
 
105
 
106
end neorv32_boot_rom_rtl;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.