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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_busswitch.vhd] - Blame information for rev 57

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1 12 zero_gravi
-- #################################################################################################
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-- # << NEORV32 - Bus Switch >>                                                                    #
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-- # ********************************************************************************************* #
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-- # Allows to access a single peripheral bus ("p_bus") by two controller busses. Controller port  #
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-- # A ("ca_bus") has priority over controller port B ("cb_bus").                                  #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
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-- #                                                                                               #
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-- # Redistribution and use in source and binary forms, with or without modification, are          #
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-- # permitted provided that the following conditions are met:                                     #
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-- #                                                                                               #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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-- #    conditions and the following disclaimer.                                                   #
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-- #                                                                                               #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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-- #    conditions and the following disclaimer in the documentation and/or other materials        #
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-- #    provided with the distribution.                                                            #
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-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
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-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_busswitch is
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  generic (
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    PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only
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    PORT_CB_READ_ONLY : boolean := false  -- set if controller port B is read-only
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  );
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  port (
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    -- global control --
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    clk_i           : in  std_ulogic; -- global clock, rising edge
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    rstn_i          : in  std_ulogic; -- global reset, low-active, async
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    -- controller interface a --
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    ca_bus_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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    ca_bus_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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    ca_bus_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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    ca_bus_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
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    ca_bus_we_i     : in  std_ulogic; -- write enable
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    ca_bus_re_i     : in  std_ulogic; -- read enable
61 57 zero_gravi
    ca_bus_lock_i   : in  std_ulogic; -- exclusive access request
62 12 zero_gravi
    ca_bus_ack_o    : out std_ulogic; -- bus transfer acknowledge
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    ca_bus_err_o    : out std_ulogic; -- bus transfer error
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    -- controller interface b --
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    cb_bus_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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    cb_bus_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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    cb_bus_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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    cb_bus_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
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    cb_bus_we_i     : in  std_ulogic; -- write enable
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    cb_bus_re_i     : in  std_ulogic; -- read enable
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    cb_bus_lock_i   : in  std_ulogic; -- exclusive access request
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    cb_bus_ack_o    : out std_ulogic; -- bus transfer acknowledge
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    cb_bus_err_o    : out std_ulogic; -- bus transfer error
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    -- peripheral bus --
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    p_bus_src_o     : out std_ulogic; -- access source: 0 = A, 1 = B
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    p_bus_addr_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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    p_bus_rdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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    p_bus_wdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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    p_bus_ben_o     : out std_ulogic_vector(03 downto 0); -- byte enable
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    p_bus_we_o      : out std_ulogic; -- write enable
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    p_bus_re_o      : out std_ulogic; -- read enable
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    p_bus_lock_o    : out std_ulogic; -- exclusive access request
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    p_bus_ack_i     : in  std_ulogic; -- bus transfer acknowledge
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    p_bus_err_i     : in  std_ulogic  -- bus transfer error
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  );
86
end neorv32_busswitch;
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architecture neorv32_busswitch_rtl of neorv32_busswitch is
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90
  -- access requests --
91 42 zero_gravi
  signal ca_rd_req_buf,  ca_wr_req_buf   : std_ulogic;
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  signal cb_rd_req_buf,  cb_wr_req_buf   : std_ulogic;
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  signal ca_req_current, ca_req_buffered : std_ulogic;
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  signal cb_req_current, cb_req_buffered : std_ulogic;
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96
  -- internal bus lines --
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  signal ca_bus_ack, cb_bus_ack : std_ulogic;
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  signal ca_bus_err, cb_bus_err : std_ulogic;
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  signal p_bus_we,   p_bus_re   : std_ulogic;
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101
  -- access arbiter --
102
  type arbiter_state_t is (IDLE, BUSY, RETIRE, BUSY_SWITCHED, RETIRE_SWITCHED);
103
  type arbiter_t is record
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    state     : arbiter_state_t;
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    state_nxt : arbiter_state_t;
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    bus_sel   : std_ulogic;
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    re_trig   : std_ulogic;
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    we_trig   : std_ulogic;
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  end record;
110
  signal arbiter : arbiter_t;
111
 
112
begin
113
 
114
  -- Access Buffer --------------------------------------------------------------------------
115
  -- -------------------------------------------------------------------------------------------
116
  access_buffer: process(rstn_i, clk_i)
117
  begin
118
    if (rstn_i = '0') then
119
      ca_rd_req_buf <= '0';
120
      ca_wr_req_buf <= '0';
121
      cb_rd_req_buf <= '0';
122
      cb_wr_req_buf <= '0';
123
    elsif rising_edge(clk_i) then
124
 
125
      -- controller A requests --
126
      if (ca_rd_req_buf = '0') and (ca_wr_req_buf = '0') then -- idle
127
        ca_rd_req_buf <= ca_bus_re_i;
128
        ca_wr_req_buf <= ca_bus_we_i;
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      elsif (ca_bus_err = '1') or -- error termination
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            (ca_bus_ack = '1') then -- normal termination
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        ca_rd_req_buf <= '0';
132
        ca_wr_req_buf <= '0';
133
      end if;
134
 
135
      -- controller B requests --
136
      if (cb_rd_req_buf = '0') and (cb_wr_req_buf = '0') then
137
        cb_rd_req_buf <= cb_bus_re_i;
138
        cb_wr_req_buf <= cb_bus_we_i;
139 57 zero_gravi
      elsif (cb_bus_err = '1') or -- error termination
140 12 zero_gravi
            (cb_bus_ack = '1') then -- normal termination
141
        cb_rd_req_buf <= '0';
142
        cb_wr_req_buf <= '0';
143
      end if;
144
 
145
    end if;
146
  end process access_buffer;
147
 
148
  -- any current requests? --
149
  ca_req_current <= (ca_bus_re_i or ca_bus_we_i) when (PORT_CA_READ_ONLY = false) else ca_bus_re_i;
150
  cb_req_current <= (cb_bus_re_i or cb_bus_we_i) when (PORT_CB_READ_ONLY = false) else cb_bus_re_i;
151
 
152
  -- any buffered requests? --
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  ca_req_buffered <= (ca_rd_req_buf or ca_wr_req_buf) when (PORT_CA_READ_ONLY = false) else ca_rd_req_buf;
154
  cb_req_buffered <= (cb_rd_req_buf or cb_wr_req_buf) when (PORT_CB_READ_ONLY = false) else cb_rd_req_buf;
155
 
156
 
157
  -- Access Arbiter Sync --------------------------------------------------------------------
158
  -- -------------------------------------------------------------------------------------------
159
  -- for registers that require a specific reset state --
160
  arbiter_sync: process(rstn_i, clk_i)
161
  begin
162
    if (rstn_i = '0') then
163
      arbiter.state <= IDLE;
164
    elsif rising_edge(clk_i) then
165
      arbiter.state <= arbiter.state_nxt;
166
    end if;
167
  end process arbiter_sync;
168
 
169
 
170
  -- Peripheral Bus Arbiter -----------------------------------------------------------------
171
  -- -------------------------------------------------------------------------------------------
172
  arbiter_comb: process(arbiter, ca_req_current, cb_req_current, ca_req_buffered, cb_req_buffered,
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                        ca_rd_req_buf, ca_wr_req_buf, cb_rd_req_buf, cb_wr_req_buf, p_bus_ack_i, p_bus_err_i)
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  begin
175
    -- arbiter defaults --
176
    arbiter.state_nxt <= arbiter.state;
177
    arbiter.bus_sel   <= '0';
178
    arbiter.we_trig   <= '0';
179
    arbiter.re_trig   <= '0';
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    --
181
    p_bus_src_o <= '0';
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183
    -- state machine --
184
    case arbiter.state is
185
 
186
      when IDLE => -- Controller a has full bus access
187
      -- ------------------------------------------------------------
188 36 zero_gravi
        p_bus_src_o <= '0'; -- access from port A
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        if (ca_req_current = '1') then -- current request?
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          arbiter.bus_sel   <= '0';
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          arbiter.state_nxt <= BUSY;
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        elsif (ca_req_buffered = '1') then -- buffered request?
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          arbiter.bus_sel   <= '0';
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          arbiter.state_nxt <= RETIRE;
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        elsif (cb_req_current = '1') then -- current request from controller b?
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          arbiter.bus_sel   <= '1';
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          arbiter.state_nxt <= BUSY_SWITCHED;
198
        elsif (cb_req_buffered = '1') then -- buffered request from controller b?
199
          arbiter.bus_sel   <= '1';
200
          arbiter.state_nxt <= RETIRE_SWITCHED;
201
        end if;
202
 
203
      when BUSY => -- transaction in progress
204
      -- ------------------------------------------------------------
205 36 zero_gravi
        p_bus_src_o     <= '0'; -- access from port A
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        arbiter.bus_sel <= '0';
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        if (p_bus_err_i = '1') or -- error termination
208 12 zero_gravi
           (p_bus_ack_i = '1') then -- normal termination
209
          arbiter.state_nxt <= IDLE;
210
        end if;
211
 
212
      when RETIRE => -- retire pending access
213
      -- ------------------------------------------------------------
214 36 zero_gravi
        p_bus_src_o     <= '0'; -- access from port A
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        arbiter.bus_sel <= '0';
216
        if (PORT_CA_READ_ONLY = false) then
217
          arbiter.we_trig <= ca_wr_req_buf;
218
        end if;
219
        arbiter.re_trig   <= ca_rd_req_buf;
220
        arbiter.state_nxt <= BUSY;
221
 
222
      when BUSY_SWITCHED => -- switched transaction in progress
223
      -- ------------------------------------------------------------
224 36 zero_gravi
        p_bus_src_o     <= '1'; -- access from port B
225 12 zero_gravi
        arbiter.bus_sel <= '1';
226 57 zero_gravi
        if (p_bus_err_i = '1') or -- error termination
227 12 zero_gravi
           (p_bus_ack_i = '1') then -- normal termination
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          if (ca_req_buffered = '1') or (ca_req_current = '1') then -- any request from A?
229
            arbiter.state_nxt <= RETIRE;
230
          else
231
            arbiter.state_nxt <= IDLE;
232
          end if;
233 12 zero_gravi
        end if;
234
 
235
      when RETIRE_SWITCHED => -- retire pending switched access
236
      -- ------------------------------------------------------------
237 36 zero_gravi
        p_bus_src_o     <= '1'; -- access from port B
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        arbiter.bus_sel <= '1';
239
        if (PORT_CB_READ_ONLY = false) then
240
          arbiter.we_trig <= cb_wr_req_buf;
241
        end if;
242
        arbiter.re_trig   <= cb_rd_req_buf;
243
        arbiter.state_nxt <= BUSY_SWITCHED;
244
 
245
    end case;
246
  end process arbiter_comb;
247
 
248
 
249
  -- Peripheral Bus Switch ------------------------------------------------------------------
250
  -- -------------------------------------------------------------------------------------------
251 36 zero_gravi
  p_bus_addr_o   <= ca_bus_addr_i   when (arbiter.bus_sel = '0')    else cb_bus_addr_i;
252
  p_bus_wdata_o  <= cb_bus_wdata_i  when (PORT_CA_READ_ONLY = true) else ca_bus_wdata_i when (PORT_CB_READ_ONLY = true) else
253
                    ca_bus_wdata_i  when (arbiter.bus_sel = '0')    else cb_bus_wdata_i;
254
  p_bus_ben_o    <= cb_bus_ben_i    when (PORT_CA_READ_ONLY = true) else ca_bus_ben_i   when (PORT_CB_READ_ONLY = true) else
255
                    ca_bus_ben_i    when (arbiter.bus_sel = '0')    else cb_bus_ben_i;
256
  p_bus_we       <= ca_bus_we_i     when (arbiter.bus_sel = '0')    else cb_bus_we_i;
257
  p_bus_re       <= ca_bus_re_i     when (arbiter.bus_sel = '0')    else cb_bus_re_i;
258 12 zero_gravi
  p_bus_we_o     <= (p_bus_we or arbiter.we_trig);
259
  p_bus_re_o     <= (p_bus_re or arbiter.re_trig);
260 57 zero_gravi
  p_bus_lock_o   <= ca_bus_lock_i or cb_bus_lock_i;
261 12 zero_gravi
 
262
  ca_bus_rdata_o <= p_bus_rdata_i;
263
  cb_bus_rdata_o <= p_bus_rdata_i;
264
 
265
  ca_bus_ack     <= p_bus_ack_i and (not arbiter.bus_sel);
266
  cb_bus_ack     <= p_bus_ack_i and (    arbiter.bus_sel);
267
  ca_bus_ack_o   <= ca_bus_ack;
268
  cb_bus_ack_o   <= cb_bus_ack;
269
 
270
  ca_bus_err     <= p_bus_err_i and (not arbiter.bus_sel);
271
  cb_bus_err     <= p_bus_err_i and (    arbiter.bus_sel);
272
  ca_bus_err_o   <= ca_bus_err;
273
  cb_bus_err_o   <= cb_bus_err;
274
 
275
 
276
end neorv32_busswitch_rtl;

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