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-- #################################################################################################
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-- # << NEORV32 - Custom Functions Subsystem (CFS) >>                                              #
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-- # ********************************************************************************************* #
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-- # For tightly-coupled custom co-processors. Provides 32x32-bit memory-mapped registers.         #
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-- # This is just an "example/illustrating template". Modify this file to implement your custom    #
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-- # design logic.                                                                                 #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
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-- #                                                                                               #
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-- # Redistribution and use in source and binary forms, with or without modification, are          #
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-- # permitted provided that the following conditions are met:                                     #
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-- #                                                                                               #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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-- #    conditions and the following disclaimer.                                                   #
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-- #                                                                                               #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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-- #    conditions and the following disclaimer in the documentation and/or other materials        #
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-- #    provided with the distribution.                                                            #
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-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
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-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_cfs is
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  generic (
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    CFS_CONFIG : std_ulogic_vector(31 downto 0) := (others => '0') -- custom CFS configuration conduit generic
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  );
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  port (
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    -- host access --
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    clk_i       : in  std_ulogic; -- global clock line
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    rstn_i      : in  std_ulogic; -- global reset line, low-active, use as async
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    addr_i      : in  std_ulogic_vector(31 downto 0); -- address
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    rden_i      : in  std_ulogic; -- read enable
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    wren_i      : in  std_ulogic; -- word write enable
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    data_i      : in  std_ulogic_vector(31 downto 0); -- data in
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    data_o      : out std_ulogic_vector(31 downto 0); -- data out
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    ack_o       : out std_ulogic; -- transfer acknowledge
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    err_o       : out std_ulogic; -- transfer error
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    -- clock generator --
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    clkgen_en_o : out std_ulogic; -- enable clock generator
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    clkgen_i    : in  std_ulogic_vector(07 downto 0); -- "clock" inputs
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    -- CPU state --
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    sleep_i     : in  std_ulogic; -- set if cpu is in sleep mode
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    -- interrupt --
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    irq_o       : out std_ulogic; -- interrupt request
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    irq_ack_i   : in  std_ulogic; -- interrupt acknowledge
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    -- custom io (conduits) --
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    cfs_in_i    : in  std_ulogic_vector(31 downto 0); -- custom inputs
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    cfs_out_o   : out std_ulogic_vector(31 downto 0)  -- custom outputs
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  );
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end neorv32_cfs;
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architecture neorv32_cfs_rtl of neorv32_cfs is
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  -- IO space: module base address (DO NOT MODIFY!) --
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  constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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  constant lo_abb_c : natural := index_size_f(cfs_size_c); -- low address boundary bit
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  -- access control --
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  signal acc_en : std_ulogic; -- module access enable
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  signal addr   : std_ulogic_vector(31 downto 0); -- access address
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  signal wren   : std_ulogic; -- word write enable
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  signal rden   : std_ulogic; -- read enable
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  -- default CFS interface registers --
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  type cfs_regs_t is array (0 to 3) of std_ulogic_vector(31 downto 0); -- just implement 4 registers for this example
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  signal cfs_reg_wr : cfs_regs_t; -- interface registers for WRITE accesses
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  signal cfs_reg_rd : cfs_regs_t; -- interface registers for READ accesses
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begin
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  -- Access Control -------------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  -- These assignments are required to check if the CFS is accessed at all.
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  -- DO NOT MODIFY this unless you really know what you are doing.
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  acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = cfs_base_c(hi_abb_c downto lo_abb_c)) else '0';
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  addr   <= cfs_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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  wren   <= acc_en and wren_i; -- full 32-bit word write enable
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  rden   <= acc_en and rden_i; -- the read access is always a full 32-bit word wide; if required, the byte/half-word select/masking is done in the CPU
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  -- CFS Generic ----------------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  -- In its default version, the CFS provides a single generic: CFS_CONFIG. This generic can be set using the processor top's IO_CFS_CONFIG generic.
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  -- It is intended as a "conduit" to propagate custom implementation option from the top down to this entiy.
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  -- CFS IOs --------------------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  -- By default, the CFS provides two IO signals (cfs_in_i and cfs_out_o) that are available at the processor top entity.
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  -- These are intended as "conduits" to propagate custom signals this entity <=> processor top entity.
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  cfs_out_o <= (others => '0'); -- not used for this minimal example
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  -- Reset System ---------------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  -- The CFS can be reset using the global rstn_i signal. This signal should be used as asynchronous reset and is active-low.
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  -- Note that rstn_i can be asserted by an external reset and also by a watchdog-cause reset.
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  --
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  -- Most default peripheral devices of the NEORV32 do NOT use a dedicated reset at all. Instead, these units are reset by writing ZERO
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  -- to a specific "control register" located right at the beginning of the devices's address space (so this register is cleared at first).
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  -- The crt0 start-up code write ZERO to every single address in the processor's IO space - including the CFS.
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  -- Make sure that this clearing does not cause any unintended actions in the CFS.
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128
 
129
  -- Clock System ---------------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  -- The processor top unit implements a clock generator providing 8 "derived clocks"
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  -- Actually, these signals should not be used as direct clock signals, but as *clock enable* signals.
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  -- clkgen_i is always synchronous to the main system clock (clk_i).
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  --
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  -- The following clock divider rates are available:
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  -- clkgen_i(clk_div2_c)    -> MAIN_CLK/2
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  -- clkgen_i(clk_div4_c)    -> MAIN_CLK/4
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  -- clkgen_i(clk_div8_c)    -> MAIN_CLK/8
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  -- clkgen_i(clk_div64_c)   -> MAIN_CLK/64
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  -- clkgen_i(clk_div128_c)  -> MAIN_CLK/128
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  -- clkgen_i(clk_div1024_c) -> MAIN_CLK/1024
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  -- clkgen_i(clk_div2048_c) -> MAIN_CLK/2048
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  -- clkgen_i(clk_div4096_c) -> MAIN_CLK/4096
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  --
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  -- For instance, if you want to drive a clock process at MAIN_CLK/8 clock speed you can use the following construct:
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  --
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  --   if (rstn_i = '0') then -- async and low-active reset (if required at all)
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  --   ...
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  --   elsif rising_edge(clk_i) then -- always use the main clock for all clock processes!
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  --     if (clkgen_i(clk_div8_c) = '1') then -- the div8 "clock" is actually a clock enable
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  --       ...
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  --     end if;
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  --   end if;
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  --
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  -- The clkgen_i input clocks are available when at least one IO/peripheral device (for example the UART) requires the clocks generated by the
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  -- clock generator. The CFS can enable the clock generator by itself by setting the clkgen_en_o signal high.
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  -- The CFS cannot ensure to deactive the clock generator by setting the clkgen_en_o signal low as other peripherals might still keep the generator activated.
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  -- Make sure to deactivate the CFS's clkgen_en_o if no clocks are required in here to reduce dynamic power consumption.
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  clkgen_en_o <= '0'; -- not used for this minimal example
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  -- Further Power Optimization -------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  -- The CFS can decide to go into low-power mode (by disabling all switching activity) when the CPU enters sleep mode.
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  -- The sleep_i signal is high when the CPU is in sleep mode. Any interrupt including the CFS's irq_o interrupt request signal
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  -- will wake up the CPU again.
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  -- Interrupt ------------------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  -- The CFS features a single interrupt signal. This interrupt is connected to the CPU's "fast interrupt" channel 1.
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  -- Note that this fast interrupt channel is shared with the GPIO pin-change interrupt. Make sure to disable the GPIO's pin-change interrupt
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  -- via the according control register if you want to use this interrupt exclusively for the CFS.
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  --
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  -- The interrupt is single-shot. Setting the irq_o signal high for one cycle will generate an interrupt request.
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  -- The interrupt is acknowledged by the CPU via the one-shot irq_ack_i signal indicating that the according interrupt handler is starting.
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  irq_o <= '0'; -- not used for this minimal example
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  -- Read/Write Access ----------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  -- Here we are reading/writing from/to the interface registers of the module. Please note that the peripheral/IO
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  -- modules of the NEORV32 can only be written in full word mode (32-bit). Any other write access (half-word or byte)
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  -- will trigger a store bus access fault exception.
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  --
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  -- The CFS provides up to 32 memory-mapped 32-bit interface register. For instance, these could be used to provide
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  -- a <control register> for global control of the unit, a <data register> for reading/writing from/to a data FIFO, a <command register>
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  -- for issueing commands and a <status register> for status information.
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  --
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  -- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o signal.
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  -- If no ACK is generated, the bus access will time out and cause a store bus access fault exception. This exception can also be immediatly
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  -- triggered by setting err_o high for one cycle (only during a valid bus access).
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  err_o <= '0'; -- not used for this minimal example
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  -- Host access: Read and write access to the interface registers + bus transfer acknowledge.
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  -- This example only implements four physical r/w register (the four lowest CF register). The remaining addresses of the CFS are not
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  -- associated with any writable or readable register - an access to those is simply ignored but still acknowledged.
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  host_access: process(clk_i)
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  begin
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    if rising_edge(clk_i) then -- synchronous interface for reads and writes
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      -- transfer/access acknowledge --
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      ack_o <= rden or wren; -- default: required for the CPU to check the CFS is answering a bus read OR write request; all r/w accesses (to any cfs_reg) will succeed
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--    ack_o <= rden; -- use this construct if your CFS is read-only
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--    ack_o <= wren; -- use this construct if your CFS is write-only
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--    ack_o <= ... -- or define the ACK by yourself (example: some registers are read-only, some others can only be written, ...)
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      -- write access --
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      for i in 0 to 3 loop -- iterate over all 4 bytes in a word
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        if (wren = '1') then -- word-wide write-access only!
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          case addr is -- make sure to use the internal 'addr' signal for the read/write interface
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            when cfs_reg0_addr_c => cfs_reg_wr(0) <= data_i; -- for example: control register
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            when cfs_reg1_addr_c => cfs_reg_wr(1) <= data_i; -- for example: data in/out fifo
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            when cfs_reg2_addr_c => cfs_reg_wr(2) <= data_i; -- for example: command fifo
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            when cfs_reg3_addr_c => cfs_reg_wr(3) <= data_i; -- for example: status register
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            when others          => NULL;
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          end case;
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        end if;
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      end loop; -- i
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      -- read access --
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      data_o <= (others => '0'); -- the output has to be zero if there is no actual read access
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      if (rden = '1') then -- the read access is always a full 32-bit word wide; if required, the byte/half-word select/masking is done in the CPU
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        case addr is -- make sure to use the internal 'addr' signal for the read/write interface
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          when cfs_reg0_addr_c => data_o <= cfs_reg_rd(0);
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          when cfs_reg1_addr_c => data_o <= cfs_reg_rd(1);
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          when cfs_reg2_addr_c => data_o <= cfs_reg_rd(2);
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          when cfs_reg3_addr_c => data_o <= cfs_reg_rd(3);
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          when others          => data_o <= (others => '0'); -- the remaining registers are not implemented and will read as zero
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        end case;
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      end if;
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    end if;
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  end process host_access;
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  -- CFS Function Core ----------------------------------------------------------------------
240
  -- -------------------------------------------------------------------------------------------
241
  -- This is where the actual functionality can be implemented.
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  -- In this example we are just implementing four r/w registers that invert any value written to them.
243
 
244
  cfs_core: process(cfs_reg_wr)
245
  begin
246
    cfs_reg_rd(0) <= not cfs_reg_wr(0); -- just invert the written value
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    cfs_reg_rd(1) <= not cfs_reg_wr(1);
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    cfs_reg_rd(2) <= not cfs_reg_wr(2);
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    cfs_reg_rd(3) <= not cfs_reg_wr(3);
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  end process cfs_core;
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end neorv32_cfs_rtl;

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