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zero_gravi |
-- #################################################################################################
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-- # << NEORV32 - CPU Top Entity >> #
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-- # ********************************************************************************************* #
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zero_gravi |
-- # NEORV32 CPU: #
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5 |
13 |
zero_gravi |
-- # * neorv32_cpu.vhd : CPU top entity #
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-- # * neorv32_cpu_alu.vhd : Arithmetic/logic unit #
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-- # * neorv32_cpu_bus.vhd : Instruction and data bus interface unit #
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8 |
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-- # * neorv32_cpu_cp_muldiv.vhd : MULDIV co-processor #
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-- # * neorv32_cpu_ctrl.vhd : CPU control and CSR system #
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-- # * neorv32_cpu_decompressor.vhd : Compressed instructions decoder #
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11 |
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-- # * neorv32_cpu_regfile.vhd : Data register file #
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12 |
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zero_gravi |
-- # #
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-- # Check the processor's documentary for more information: docs/NEORV32.pdf #
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zero_gravi |
-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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44 |
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-- #################################################################################################
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45 |
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library ieee;
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47 |
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use ieee.std_logic_1164.all;
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48 |
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use ieee.numeric_std.all;
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49 |
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library neorv32;
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51 |
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use neorv32.neorv32_package.all;
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52 |
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53 |
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entity neorv32_cpu is
|
54 |
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generic (
|
55 |
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-- General --
|
56 |
14 |
zero_gravi |
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
|
57 |
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
|
58 |
2 |
zero_gravi |
-- RISC-V CPU Extensions --
|
59 |
12 |
zero_gravi |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
60 |
|
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
61 |
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
62 |
15 |
zero_gravi |
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
63 |
12 |
zero_gravi |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
64 |
|
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
65 |
19 |
zero_gravi |
-- Extension Options --
|
66 |
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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67 |
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FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
68 |
15 |
zero_gravi |
-- Physical Memory Protection (PMP) --
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69 |
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PMP_USE : boolean := false; -- implement PMP?
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70 |
16 |
zero_gravi |
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
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71 |
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PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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72 |
14 |
zero_gravi |
-- Bus Interface --
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73 |
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BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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74 |
2 |
zero_gravi |
);
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75 |
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port (
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76 |
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-- global control --
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77 |
14 |
zero_gravi |
clk_i : in std_ulogic := '0'; -- global clock, rising edge
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78 |
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
79 |
12 |
zero_gravi |
-- instruction bus interface --
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80 |
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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81 |
14 |
zero_gravi |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
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82 |
12 |
zero_gravi |
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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83 |
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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84 |
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i_bus_we_o : out std_ulogic; -- write enable
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85 |
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i_bus_re_o : out std_ulogic; -- read enable
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86 |
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i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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87 |
14 |
zero_gravi |
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
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88 |
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i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
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89 |
12 |
zero_gravi |
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
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90 |
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-- data bus interface --
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91 |
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d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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92 |
14 |
zero_gravi |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
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93 |
12 |
zero_gravi |
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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94 |
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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95 |
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d_bus_we_o : out std_ulogic; -- write enable
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96 |
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d_bus_re_o : out std_ulogic; -- read enable
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97 |
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d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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98 |
14 |
zero_gravi |
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
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99 |
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d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
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100 |
12 |
zero_gravi |
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
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101 |
11 |
zero_gravi |
-- system time input from MTIME --
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102 |
14 |
zero_gravi |
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
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103 |
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-- interrupts (risc-v compliant) --
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104 |
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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105 |
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mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
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106 |
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mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
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107 |
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-- fast interrupts (custom) --
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108 |
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firq_i : in std_ulogic_vector(3 downto 0) := (others => '0')
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109 |
2 |
zero_gravi |
);
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110 |
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end neorv32_cpu;
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111 |
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112 |
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architecture neorv32_cpu_rtl of neorv32_cpu is
|
113 |
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114 |
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-- local signals --
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115 |
12 |
zero_gravi |
signal ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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116 |
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signal alu_cmp : std_ulogic_vector(1 downto 0); -- alu comparator result
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117 |
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signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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118 |
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signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
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119 |
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signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
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120 |
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signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
|
121 |
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signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu adder result
|
122 |
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signal rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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123 |
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signal alu_wait : std_ulogic; -- alu is busy due to iterative unit
|
124 |
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signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch
|
125 |
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signal bus_d_wait : std_ulogic; -- wait for current bus data access
|
126 |
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signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
127 |
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signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
|
128 |
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signal ma_instr : std_ulogic; -- misaligned instruction address
|
129 |
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signal ma_load : std_ulogic; -- misaligned load data address
|
130 |
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signal ma_store : std_ulogic; -- misaligned store data address
|
131 |
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signal be_instr : std_ulogic; -- bus error on instruction access
|
132 |
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signal be_load : std_ulogic; -- bus error on load data access
|
133 |
|
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signal be_store : std_ulogic; -- bus error on store data access
|
134 |
|
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signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
|
135 |
|
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signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
|
136 |
|
|
signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for current executed instruction)
|
137 |
2 |
zero_gravi |
|
138 |
|
|
-- co-processor interface --
|
139 |
|
|
signal cp0_data, cp1_data : std_ulogic_vector(data_width_c-1 downto 0);
|
140 |
|
|
signal cp0_valid, cp1_valid : std_ulogic;
|
141 |
19 |
zero_gravi |
signal cp0_start, cp1_start : std_ulogic;
|
142 |
2 |
zero_gravi |
|
143 |
15 |
zero_gravi |
-- pmp interface --
|
144 |
|
|
signal pmp_addr : pmp_addr_if_t;
|
145 |
|
|
signal pmp_ctrl : pmp_ctrl_if_t;
|
146 |
|
|
signal priv_mode : std_ulogic_vector(1 downto 0); -- current CPU privilege level
|
147 |
|
|
|
148 |
2 |
zero_gravi |
begin
|
149 |
|
|
|
150 |
15 |
zero_gravi |
-- Sanity Checks --------------------------------------------------------------------------
|
151 |
|
|
-- -------------------------------------------------------------------------------------------
|
152 |
|
|
sanity_check: process(clk_i)
|
153 |
|
|
begin
|
154 |
|
|
if rising_edge(clk_i) then
|
155 |
|
|
-- CSR system --
|
156 |
|
|
if (CPU_EXTENSION_RISCV_Zicsr = false) then
|
157 |
18 |
zero_gravi |
assert false report "NEORV32 CPU CONFIG WARNING! No exception/interrupt/machine features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning;
|
158 |
15 |
zero_gravi |
end if;
|
159 |
|
|
-- U-extension requires Zicsr extension --
|
160 |
|
|
if (CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_U = true) then
|
161 |
18 |
zero_gravi |
assert false report "NEORV32 CPU CONFIG ERROR! User mode requires CPU_EXTENSION_RISCV_Zicsr extension." severity error;
|
162 |
15 |
zero_gravi |
end if;
|
163 |
|
|
-- PMP requires Zicsr extension --
|
164 |
|
|
if (CPU_EXTENSION_RISCV_Zicsr = false) and (PMP_USE = true) then
|
165 |
18 |
zero_gravi |
assert false report "NEORV32 CPU CONFIG ERROR! Physical memory protection (PMP) requires CPU_EXTENSION_RISCV_Zicsr extension." severity error;
|
166 |
15 |
zero_gravi |
end if;
|
167 |
16 |
zero_gravi |
-- performance counters require Zicsr extension --
|
168 |
15 |
zero_gravi |
if (CPU_EXTENSION_RISCV_Zicsr = false) and (CSR_COUNTERS_USE = true) then
|
169 |
18 |
zero_gravi |
assert false report "NEORV32 CPU CONFIG ERROR! Performance counter CSRs require CPU_EXTENSION_RISCV_Zicsr extension." severity error;
|
170 |
15 |
zero_gravi |
end if;
|
171 |
|
|
-- PMP regions --
|
172 |
|
|
if (PMP_NUM_REGIONS > pmp_max_r_c) and (PMP_USE = true) then
|
173 |
18 |
zero_gravi |
assert false report "NEORV32 CPU CONFIG ERROR! Number of PMP regions out of valid range." severity error;
|
174 |
15 |
zero_gravi |
end if;
|
175 |
|
|
-- PMP granulartiy --
|
176 |
16 |
zero_gravi |
if ((PMP_GRANULARITY < 1) or (PMP_GRANULARITY > 32)) and (PMP_USE = true) then
|
177 |
18 |
zero_gravi |
assert false report "NEORV32 CPU CONFIG ERROR! Invalid PMP granulartiy (0 < G < 33)." severity error;
|
178 |
15 |
zero_gravi |
end if;
|
179 |
18 |
zero_gravi |
-- Bus timeout --
|
180 |
|
|
if (BUS_TIMEOUT < 1) then
|
181 |
|
|
assert false report "NEORV32 CPU CONFIG ERROR! Invalid bus timeout - must be at least 1 cycle." severity error;
|
182 |
|
|
end if;
|
183 |
15 |
zero_gravi |
end if;
|
184 |
|
|
end process sanity_check;
|
185 |
|
|
|
186 |
2 |
zero_gravi |
-- Control Unit ---------------------------------------------------------------------------
|
187 |
|
|
-- -------------------------------------------------------------------------------------------
|
188 |
|
|
neorv32_cpu_control_inst: neorv32_cpu_control
|
189 |
|
|
generic map (
|
190 |
|
|
-- General --
|
191 |
8 |
zero_gravi |
CSR_COUNTERS_USE => CSR_COUNTERS_USE, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
192 |
12 |
zero_gravi |
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id
|
193 |
|
|
CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
|
194 |
2 |
zero_gravi |
-- RISC-V CPU Extensions --
|
195 |
15 |
zero_gravi |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
196 |
|
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
|
197 |
|
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
198 |
|
|
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
|
199 |
|
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
200 |
|
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
201 |
|
|
-- Physical memory protection (PMP) --
|
202 |
|
|
PMP_USE => PMP_USE, -- implement physical memory protection?
|
203 |
|
|
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (1..4)
|
204 |
|
|
PMP_GRANULARITY => PMP_GRANULARITY -- granularity (0=none, 1=8B, 2=16B, 3=32B, ...)
|
205 |
2 |
zero_gravi |
)
|
206 |
|
|
port map (
|
207 |
|
|
-- global control --
|
208 |
|
|
clk_i => clk_i, -- global clock, rising edge
|
209 |
|
|
rstn_i => rstn_i, -- global reset, low-active, async
|
210 |
|
|
ctrl_o => ctrl, -- main control bus
|
211 |
|
|
-- status input --
|
212 |
|
|
alu_wait_i => alu_wait, -- wait for ALU
|
213 |
12 |
zero_gravi |
bus_i_wait_i => bus_i_wait, -- wait for bus
|
214 |
|
|
bus_d_wait_i => bus_d_wait, -- wait for bus
|
215 |
2 |
zero_gravi |
-- data input --
|
216 |
|
|
instr_i => instr, -- instruction
|
217 |
|
|
cmp_i => alu_cmp, -- comparator status
|
218 |
|
|
alu_add_i => alu_add, -- ALU.add result
|
219 |
|
|
-- data output --
|
220 |
|
|
imm_o => imm, -- immediate
|
221 |
6 |
zero_gravi |
fetch_pc_o => fetch_pc, -- PC for instruction fetch
|
222 |
|
|
curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
|
223 |
|
|
next_pc_o => next_pc, -- next PC (corresponding to current instruction)
|
224 |
2 |
zero_gravi |
-- csr interface --
|
225 |
|
|
csr_wdata_i => alu_res, -- CSR write data
|
226 |
|
|
csr_rdata_o => csr_rdata, -- CSR read data
|
227 |
14 |
zero_gravi |
-- interrupts (risc-v compliant) --
|
228 |
|
|
msw_irq_i => msw_irq_i, -- machine software interrupt
|
229 |
|
|
mext_irq_i => mext_irq_i, -- machine external interrupt
|
230 |
2 |
zero_gravi |
mtime_irq_i => mtime_irq_i, -- machine timer interrupt
|
231 |
14 |
zero_gravi |
-- fast interrupts (custom) --
|
232 |
|
|
firq_i => firq_i,
|
233 |
11 |
zero_gravi |
-- system time input from MTIME --
|
234 |
|
|
time_i => time_i, -- current system time
|
235 |
15 |
zero_gravi |
-- physical memory protection --
|
236 |
|
|
pmp_addr_o => pmp_addr, -- addresses
|
237 |
|
|
pmp_ctrl_o => pmp_ctrl, -- configs
|
238 |
|
|
priv_mode_o => priv_mode, -- current CPU privilege level
|
239 |
2 |
zero_gravi |
-- bus access exceptions --
|
240 |
|
|
mar_i => mar, -- memory address register
|
241 |
|
|
ma_instr_i => ma_instr, -- misaligned instruction address
|
242 |
|
|
ma_load_i => ma_load, -- misaligned load data address
|
243 |
|
|
ma_store_i => ma_store, -- misaligned store data address
|
244 |
|
|
be_instr_i => be_instr, -- bus error on instruction access
|
245 |
|
|
be_load_i => be_load, -- bus error on load data access
|
246 |
12 |
zero_gravi |
be_store_i => be_store -- bus error on store data access
|
247 |
2 |
zero_gravi |
);
|
248 |
|
|
|
249 |
|
|
|
250 |
|
|
-- Register File --------------------------------------------------------------------------
|
251 |
|
|
-- -------------------------------------------------------------------------------------------
|
252 |
|
|
neorv32_regfile_inst: neorv32_cpu_regfile
|
253 |
|
|
generic map (
|
254 |
|
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E -- implement embedded RF extension?
|
255 |
|
|
)
|
256 |
|
|
port map (
|
257 |
|
|
-- global control --
|
258 |
|
|
clk_i => clk_i, -- global clock, rising edge
|
259 |
|
|
ctrl_i => ctrl, -- main control bus
|
260 |
|
|
-- data input --
|
261 |
|
|
mem_i => rdata, -- memory read data
|
262 |
|
|
alu_i => alu_res, -- ALU result
|
263 |
|
|
csr_i => csr_rdata, -- CSR read data
|
264 |
13 |
zero_gravi |
pc_i => next_pc, -- next pc (for linking)
|
265 |
2 |
zero_gravi |
-- data output --
|
266 |
|
|
rs1_o => rs1, -- operand 1
|
267 |
|
|
rs2_o => rs2 -- operand 2
|
268 |
|
|
);
|
269 |
|
|
|
270 |
|
|
|
271 |
|
|
-- ALU ------------------------------------------------------------------------------------
|
272 |
|
|
-- -------------------------------------------------------------------------------------------
|
273 |
|
|
neorv32_cpu_alu_inst: neorv32_cpu_alu
|
274 |
11 |
zero_gravi |
generic map (
|
275 |
|
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M -- implement muld/div extension?
|
276 |
|
|
)
|
277 |
2 |
zero_gravi |
port map (
|
278 |
|
|
-- global control --
|
279 |
|
|
clk_i => clk_i, -- global clock, rising edge
|
280 |
|
|
rstn_i => rstn_i, -- global reset, low-active, async
|
281 |
|
|
ctrl_i => ctrl, -- main control bus
|
282 |
|
|
-- data input --
|
283 |
|
|
rs1_i => rs1, -- rf source 1
|
284 |
|
|
rs2_i => rs2, -- rf source 2
|
285 |
6 |
zero_gravi |
pc2_i => curr_pc, -- delayed PC
|
286 |
2 |
zero_gravi |
imm_i => imm, -- immediate
|
287 |
|
|
csr_i => csr_rdata, -- csr read data
|
288 |
|
|
-- data output --
|
289 |
|
|
cmp_o => alu_cmp, -- comparator status
|
290 |
|
|
add_o => alu_add, -- OPA + OPB
|
291 |
|
|
res_o => alu_res, -- ALU result
|
292 |
|
|
-- co-processor interface --
|
293 |
19 |
zero_gravi |
cp0_start_o => cp0_start, -- trigger co-processor 0
|
294 |
2 |
zero_gravi |
cp0_data_i => cp0_data, -- co-processor 0 result
|
295 |
|
|
cp0_valid_i => cp0_valid, -- co-processor 0 result valid
|
296 |
19 |
zero_gravi |
cp1_start_o => cp1_start, -- trigger co-processor 1
|
297 |
2 |
zero_gravi |
cp1_data_i => cp1_data, -- co-processor 1 result
|
298 |
|
|
cp1_valid_i => cp1_valid, -- co-processor 1 result valid
|
299 |
|
|
-- status --
|
300 |
|
|
wait_o => alu_wait -- busy due to iterative processing units
|
301 |
|
|
);
|
302 |
|
|
|
303 |
|
|
|
304 |
|
|
-- Co-Processor 0: MULDIV Unit ------------------------------------------------------------
|
305 |
|
|
-- -------------------------------------------------------------------------------------------
|
306 |
|
|
neorv32_cpu_cp_muldiv_inst_true:
|
307 |
|
|
if (CPU_EXTENSION_RISCV_M = true) generate
|
308 |
|
|
neorv32_cpu_cp_muldiv_inst: neorv32_cpu_cp_muldiv
|
309 |
19 |
zero_gravi |
generic map (
|
310 |
|
|
FAST_MUL_EN => FAST_MUL_EN -- use DSPs for faster multiplication
|
311 |
|
|
)
|
312 |
2 |
zero_gravi |
port map (
|
313 |
|
|
-- global control --
|
314 |
|
|
clk_i => clk_i, -- global clock, rising edge
|
315 |
|
|
rstn_i => rstn_i, -- global reset, low-active, async
|
316 |
|
|
ctrl_i => ctrl, -- main control bus
|
317 |
|
|
-- data input --
|
318 |
19 |
zero_gravi |
start_i => cp0_start, -- trigger operation
|
319 |
2 |
zero_gravi |
rs1_i => rs1, -- rf source 1
|
320 |
|
|
rs2_i => rs2, -- rf source 2
|
321 |
|
|
-- result and status --
|
322 |
|
|
res_o => cp0_data, -- operation result
|
323 |
|
|
valid_o => cp0_valid -- data output valid
|
324 |
|
|
);
|
325 |
|
|
end generate;
|
326 |
|
|
|
327 |
|
|
neorv32_cpu_cp_muldiv_inst_false:
|
328 |
|
|
if (CPU_EXTENSION_RISCV_M = false) generate
|
329 |
|
|
cp0_data <= (others => '0');
|
330 |
|
|
cp0_valid <= '0';
|
331 |
|
|
end generate;
|
332 |
|
|
|
333 |
|
|
|
334 |
|
|
-- Co-Processor 1: Not Implemented Yet ----------------------------------------------------
|
335 |
|
|
-- -------------------------------------------------------------------------------------------
|
336 |
|
|
cp1_data <= (others => '0');
|
337 |
|
|
cp1_valid <= '0';
|
338 |
|
|
|
339 |
|
|
|
340 |
12 |
zero_gravi |
-- Bus Interface Unit ---------------------------------------------------------------------
|
341 |
2 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
342 |
|
|
neorv32_cpu_bus_inst: neorv32_cpu_bus
|
343 |
|
|
generic map (
|
344 |
11 |
zero_gravi |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
345 |
15 |
zero_gravi |
BUS_TIMEOUT => BUS_TIMEOUT, -- cycles after which a valid bus access will timeout
|
346 |
|
|
-- Physical memory protection (PMP) --
|
347 |
|
|
PMP_USE => PMP_USE, -- implement physical memory protection?
|
348 |
|
|
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (1..4)
|
349 |
|
|
PMP_GRANULARITY => PMP_GRANULARITY -- granularity (0=none, 1=8B, 2=16B, 3=32B, ...)
|
350 |
2 |
zero_gravi |
)
|
351 |
|
|
port map (
|
352 |
|
|
-- global control --
|
353 |
12 |
zero_gravi |
clk_i => clk_i, -- global clock, rising edge
|
354 |
|
|
rstn_i => rstn_i, -- global reset, low-active, async
|
355 |
|
|
ctrl_i => ctrl, -- main control bus
|
356 |
|
|
-- cpu instruction fetch interface --
|
357 |
|
|
fetch_pc_i => fetch_pc, -- PC for instruction fetch
|
358 |
|
|
instr_o => instr, -- instruction
|
359 |
|
|
i_wait_o => bus_i_wait, -- wait for fetch to complete
|
360 |
|
|
--
|
361 |
|
|
ma_instr_o => ma_instr, -- misaligned instruction address
|
362 |
|
|
be_instr_o => be_instr, -- bus error on instruction access
|
363 |
|
|
-- cpu data access interface --
|
364 |
|
|
addr_i => alu_add, -- ALU.add result -> access address
|
365 |
|
|
wdata_i => rs2, -- write data
|
366 |
|
|
rdata_o => rdata, -- read data
|
367 |
|
|
mar_o => mar, -- current memory address register
|
368 |
|
|
d_wait_o => bus_d_wait, -- wait for access to complete
|
369 |
|
|
--
|
370 |
|
|
ma_load_o => ma_load, -- misaligned load data address
|
371 |
|
|
ma_store_o => ma_store, -- misaligned store data address
|
372 |
|
|
be_load_o => be_load, -- bus error on load data access
|
373 |
|
|
be_store_o => be_store, -- bus error on store data access
|
374 |
15 |
zero_gravi |
-- physical memory protection --
|
375 |
|
|
pmp_addr_i => pmp_addr, -- addresses
|
376 |
|
|
pmp_ctrl_i => pmp_ctrl, -- configs
|
377 |
|
|
priv_mode_i => priv_mode, -- current CPU privilege level
|
378 |
12 |
zero_gravi |
-- instruction bus --
|
379 |
|
|
i_bus_addr_o => i_bus_addr_o, -- bus access address
|
380 |
|
|
i_bus_rdata_i => i_bus_rdata_i, -- bus read data
|
381 |
|
|
i_bus_wdata_o => i_bus_wdata_o, -- bus write data
|
382 |
|
|
i_bus_ben_o => i_bus_ben_o, -- byte enable
|
383 |
|
|
i_bus_we_o => i_bus_we_o, -- write enable
|
384 |
|
|
i_bus_re_o => i_bus_re_o, -- read enable
|
385 |
|
|
i_bus_cancel_o => i_bus_cancel_o, -- cancel current bus transaction
|
386 |
|
|
i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge
|
387 |
|
|
i_bus_err_i => i_bus_err_i, -- bus transfer error
|
388 |
|
|
i_bus_fence_o => i_bus_fence_o, -- fence operation
|
389 |
|
|
-- data bus --
|
390 |
|
|
d_bus_addr_o => d_bus_addr_o, -- bus access address
|
391 |
|
|
d_bus_rdata_i => d_bus_rdata_i, -- bus read data
|
392 |
|
|
d_bus_wdata_o => d_bus_wdata_o, -- bus write data
|
393 |
|
|
d_bus_ben_o => d_bus_ben_o, -- byte enable
|
394 |
|
|
d_bus_we_o => d_bus_we_o, -- write enable
|
395 |
|
|
d_bus_re_o => d_bus_re_o, -- read enable
|
396 |
|
|
d_bus_cancel_o => d_bus_cancel_o, -- cancel current bus transaction
|
397 |
|
|
d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge
|
398 |
|
|
d_bus_err_i => d_bus_err_i, -- bus transfer error
|
399 |
|
|
d_bus_fence_o => d_bus_fence_o -- fence operation
|
400 |
2 |
zero_gravi |
);
|
401 |
|
|
|
402 |
|
|
|
403 |
|
|
end neorv32_cpu_rtl;
|