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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu.vhd] - Blame information for rev 2

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-- #################################################################################################
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-- # << NEORV32 - CPU Top Entity >>                                                                #
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-- # ********************************************************************************************* #
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-- # Top NEORV32 CPU:                                                                              #
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-- # * neorv32_cpu_alu: Arithemtical/logical unit                                                  #
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-- # * neorv32_cpu_ctrl: CPU control and CSR system                                                #
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-- #   * neorv32_cpu_decompressor: Compressed instructions decoder                                 #
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-- # * neorv32_cpu_bus: Memory/IO bus interface unit                                               #
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-- # * neorv32_cpu_cp_muldiv: MULDIV co-processor                                                  #
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-- # * neorv32_cpu_regfile: Data register file                                                     #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
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-- #                                                                                               #
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-- # Redistribution and use in source and binary forms, with or without modification, are          #
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-- # permitted provided that the following conditions are met:                                     #
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-- #                                                                                               #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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-- #    conditions and the following disclaimer.                                                   #
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-- #                                                                                               #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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-- #    conditions and the following disclaimer in the documentation and/or other materials        #
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-- #    provided with the distribution.                                                            #
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-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
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-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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-- #################################################################################################
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43
library ieee;
44
use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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47
library neorv32;
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use neorv32.neorv32_package.all;
49
 
50
entity neorv32_cpu is
51
  generic (
52
    -- General --
53
    CLOCK_FREQUENCY           : natural := 0; -- clock frequency of clk_i in Hz
54
    HART_ID                   : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
55
    BOOTLOADER_USE            : boolean := true;   -- implement processor-internal bootloader?
56
    -- RISC-V CPU Extensions --
57
    CPU_EXTENSION_RISCV_C     : boolean := false;  -- implement compressed extension?
58
    CPU_EXTENSION_RISCV_E     : boolean := false;  -- implement embedded RF extension?
59
    CPU_EXTENSION_RISCV_M     : boolean := false;  -- implement muld/div extension?
60
    CPU_EXTENSION_RISCV_Zicsr : boolean := true;   -- implement CSR system?
61
    -- Memory configuration: Instruction memory --
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    MEM_ISPACE_BASE           : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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    MEM_ISPACE_SIZE           : natural := 8*1024; -- total size of instruction memory space in byte
64
    MEM_INT_IMEM_USE          : boolean := true;   -- implement processor-internal instruction memory
65
    MEM_INT_IMEM_SIZE         : natural := 8*1024; -- size of processor-internal instruction memory in bytes
66
    MEM_INT_IMEM_ROM          : boolean := false;  -- implement processor-internal instruction memory as ROM
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    -- Memory configuration: Data memory --
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    MEM_DSPACE_BASE           : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
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    MEM_DSPACE_SIZE           : natural := 4*1024; -- total size of data memory space in byte
70
    MEM_INT_DMEM_USE          : boolean := true;   -- implement processor-internal data memory
71
    MEM_INT_DMEM_SIZE         : natural := 4*1024; -- size of processor-internal data memory in bytes
72
    -- Memory configuration: External memory interface --
73
    MEM_EXT_USE               : boolean := false;  -- implement external memory bus interface?
74
    MEM_EXT_TIMEOUT           : natural := 15;     -- cycles after which a valid bus access will timeout
75
    -- Processor peripherals --
76
    IO_GPIO_USE               : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
77
    IO_MTIME_USE              : boolean := true;   -- implement machine system timer (MTIME)?
78
    IO_UART_USE               : boolean := true;   -- implement universal asynchronous receiver/transmitter (UART)?
79
    IO_SPI_USE                : boolean := true;   -- implement serial peripheral interface (SPI)?
80
    IO_TWI_USE                : boolean := true;   -- implement two-wire interface (TWI)?
81
    IO_PWM_USE                : boolean := true;   -- implement pulse-width modulation unit (PWM)?
82
    IO_WDT_USE                : boolean := true;   -- implement watch dog timer (WDT)?
83
    IO_CLIC_USE               : boolean := true;   -- implement core local interrupt controller (CLIC)?
84
    IO_TRNG_USE               : boolean := true    -- implement true random number generator (TRNG)?
85
  );
86
  port (
87
    -- global control --
88
    clk_i       : in  std_ulogic; -- global clock, rising edge
89
    rstn_i      : in  std_ulogic; -- global reset, low-active, async
90
    -- bus interface --
91
    bus_addr_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
92
    bus_rdata_i : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
93
    bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
94
    bus_ben_o   : out std_ulogic_vector(03 downto 0); -- byte enable
95
    bus_we_o    : out std_ulogic; -- write enable
96
    bus_re_o    : out std_ulogic; -- read enable
97
    bus_ack_i   : in  std_ulogic; -- bus transfer acknowledge
98
    bus_err_i   : in  std_ulogic; -- bus transfer error
99
    -- external interrupts --
100
    clic_irq_i  : in  std_ulogic; -- CLIC interrupt request
101
    mtime_irq_i : in  std_ulogic  -- machine timer interrupt
102
  );
103
end neorv32_cpu;
104
 
105
architecture neorv32_cpu_rtl of neorv32_cpu is
106
 
107
  -- local signals --
108
  signal ctrl        : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
109
  signal alu_cmp     : std_ulogic_vector(1 downto 0); -- alu comparator result
110
  signal imm         : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
111
  signal pc          : std_ulogic_vector(data_width_c-1 downto 0); -- current program counter
112
  signal pc_delayed  : std_ulogic_vector(data_width_c-1 downto 0); -- delayed program counter
113
  signal instr       : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
114
  signal rs1, rs2    : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
115
  signal alu_res     : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
116
  signal alu_add     : std_ulogic_vector(data_width_c-1 downto 0); -- alu adder result
117
  signal rdata       : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
118
  signal alu_wait    : std_ulogic; -- alu is busy due to iterative unit
119
  signal bus_wait    : std_ulogic; -- wait for bus to finish operation
120
  signal csr_rdata   : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
121
  signal mar         : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
122
  signal ma_instr    : std_ulogic; -- misaligned instruction address
123
  signal ma_load     : std_ulogic; -- misaligned load data address
124
  signal ma_store    : std_ulogic; -- misaligned store data address
125
  signal be_instr    : std_ulogic; -- bus error on instruction access
126
  signal be_load     : std_ulogic; -- bus error on load data access
127
  signal be_store    : std_ulogic; -- bus error on store data access
128
  signal bus_exc_ack : std_ulogic; -- bus exception error acknowledge
129
 
130
  -- co-processor interface --
131
  signal cp0_data,  cp1_data  : std_ulogic_vector(data_width_c-1 downto 0);
132
  signal cp0_valid, cp1_valid : std_ulogic;
133
 
134
begin
135
 
136
  -- Control Unit ---------------------------------------------------------------------------
137
  -- -------------------------------------------------------------------------------------------
138
  neorv32_cpu_control_inst: neorv32_cpu_control
139
  generic map (
140
    -- General --
141
    CLOCK_FREQUENCY           => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
142
    HART_ID                   => HART_ID,         -- custom hardware thread ID
143
    BOOTLOADER_USE            => BOOTLOADER_USE,  -- implement processor-internal bootloader?
144
    -- RISC-V CPU Extensions --
145
    CPU_EXTENSION_RISCV_C     => CPU_EXTENSION_RISCV_C,     -- implement compressed extension?
146
    CPU_EXTENSION_RISCV_E     => CPU_EXTENSION_RISCV_E,     -- implement embedded RF extension?
147
    CPU_EXTENSION_RISCV_M     => CPU_EXTENSION_RISCV_M,     -- implement muld/div extension?
148
    CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
149
    -- Memory configuration: Instruction memory --
150
    MEM_ISPACE_BASE           => MEM_ISPACE_BASE,   -- base address of instruction memory space
151
    MEM_ISPACE_SIZE           => MEM_ISPACE_SIZE,   -- total size of instruction memory space in byte
152
    MEM_INT_IMEM_USE          => MEM_INT_IMEM_USE,  -- implement processor-internal instruction memory
153
    MEM_INT_IMEM_SIZE         => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
154
    MEM_INT_IMEM_ROM          => MEM_INT_IMEM_ROM,  -- implement processor-internal instruction memory as ROM
155
    -- Memory configuration: Data memory --
156
    MEM_DSPACE_BASE           => MEM_DSPACE_BASE,   -- base address of data memory space
157
    MEM_DSPACE_SIZE           => MEM_DSPACE_SIZE,   -- total size of data memory space in byte
158
    MEM_INT_DMEM_USE          => MEM_INT_DMEM_USE,  -- implement processor-internal data memory
159
    MEM_INT_DMEM_SIZE         => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
160
    -- Memory configuration: External memory interface --
161
    MEM_EXT_USE               => MEM_EXT_USE,       -- implement external memory bus interface?
162
    -- Processor peripherals --
163
    IO_GPIO_USE               => IO_GPIO_USE,       -- implement general purpose input/output port unit (GPIO)?
164
    IO_MTIME_USE              => IO_MTIME_USE,      -- implement machine system timer (MTIME)?
165
    IO_UART_USE               => IO_UART_USE,       -- implement universal asynchronous receiver/transmitter (UART)?
166
    IO_SPI_USE                => IO_SPI_USE,        -- implement serial peripheral interface (SPI)?
167
    IO_TWI_USE                => IO_TWI_USE,        -- implement two-wire interface (TWI)?
168
    IO_PWM_USE                => IO_PWM_USE,        -- implement pulse-width modulation unit (PWM)?
169
    IO_WDT_USE                => IO_WDT_USE,        -- implement watch dog timer (WDT)?
170
    IO_CLIC_USE               => IO_CLIC_USE,       -- implement core local interrupt controller (CLIC)?
171
    IO_TRNG_USE               => IO_TRNG_USE        -- implement true random number generator (TRNG)?
172
  )
173
  port map (
174
    -- global control --
175
    clk_i         => clk_i,       -- global clock, rising edge
176
    rstn_i        => rstn_i,      -- global reset, low-active, async
177
    ctrl_o        => ctrl,        -- main control bus
178
    -- status input --
179
    alu_wait_i    => alu_wait,    -- wait for ALU
180
    bus_wait_i    => bus_wait,    -- wait for bus
181
    -- data input --
182
    instr_i       => instr,       -- instruction
183
    cmp_i         => alu_cmp,     -- comparator status
184
    alu_add_i     => alu_add,     -- ALU.add result
185
    -- data output --
186
    imm_o         => imm,         -- immediate
187
    pc_o          => pc,          -- current PC
188
    alu_pc_o      => pc_delayed,  -- delayed PC for ALU
189
    -- csr interface --
190
    csr_wdata_i   => alu_res,     -- CSR write data
191
    csr_rdata_o   => csr_rdata,   -- CSR read data
192
    -- external interrupt --
193
    clic_irq_i    => clic_irq_i,  -- CLIC interrupt request
194
    mtime_irq_i   => mtime_irq_i, -- machine timer interrupt
195
    -- bus access exceptions --
196
    mar_i         => mar,         -- memory address register
197
    ma_instr_i    => ma_instr,    -- misaligned instruction address
198
    ma_load_i     => ma_load,     -- misaligned load data address
199
    ma_store_i    => ma_store,    -- misaligned store data address
200
    be_instr_i    => be_instr,    -- bus error on instruction access
201
    be_load_i     => be_load,     -- bus error on load data access
202
    be_store_i    => be_store,    -- bus error on store data access
203
    bus_exc_ack_o => bus_exc_ack  -- bus exception error acknowledge
204
  );
205
 
206
 
207
  -- Register File --------------------------------------------------------------------------
208
  -- -------------------------------------------------------------------------------------------
209
  neorv32_regfile_inst: neorv32_cpu_regfile
210
  generic map (
211
    CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E -- implement embedded RF extension?
212
  )
213
  port map (
214
    -- global control --
215
    clk_i  => clk_i,              -- global clock, rising edge
216
    ctrl_i => ctrl,               -- main control bus
217
    -- data input --
218
    mem_i  => rdata,              -- memory read data
219
    alu_i  => alu_res,            -- ALU result
220
    csr_i  => csr_rdata,          -- CSR read data
221
    pc_i   => pc,                 -- current pc
222
    -- data output --
223
    rs1_o  => rs1,                -- operand 1
224
    rs2_o  => rs2                 -- operand 2
225
  );
226
 
227
 
228
  -- ALU ------------------------------------------------------------------------------------
229
  -- -------------------------------------------------------------------------------------------
230
  neorv32_cpu_alu_inst: neorv32_cpu_alu
231
  generic map (
232
    CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
233
    CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M  -- implement mul/div extension?
234
  )
235
  port map (
236
    -- global control --
237
    clk_i       => clk_i,         -- global clock, rising edge
238
    rstn_i      => rstn_i,        -- global reset, low-active, async
239
    ctrl_i      => ctrl,          -- main control bus
240
    -- data input --
241
    rs1_i       => rs1,           -- rf source 1
242
    rs2_i       => rs2,           -- rf source 2
243
    pc_i        => pc,            -- current PC
244
    pc2_i       => pc_delayed,    -- delayed PC
245
    imm_i       => imm,           -- immediate
246
    csr_i       => csr_rdata,     -- csr read data
247
    -- data output --
248
    cmp_o       => alu_cmp,       -- comparator status
249
    add_o       => alu_add,       -- OPA + OPB
250
    res_o       => alu_res,       -- ALU result
251
    -- co-processor interface --
252
    cp0_data_i  => cp0_data,      -- co-processor 0 result
253
    cp0_valid_i => cp0_valid,     -- co-processor 0 result valid
254
    cp1_data_i  => cp1_data,      -- co-processor 1 result
255
    cp1_valid_i => cp1_valid,     -- co-processor 1 result valid
256
    -- status --
257
    wait_o      => alu_wait       -- busy due to iterative processing units
258
  );
259
 
260
 
261
  -- Co-Processor 0: MULDIV Unit ------------------------------------------------------------
262
  -- -------------------------------------------------------------------------------------------
263
  neorv32_cpu_cp_muldiv_inst_true:
264
  if (CPU_EXTENSION_RISCV_M = true) generate
265
    neorv32_cpu_cp_muldiv_inst: neorv32_cpu_cp_muldiv
266
    port map (
267
      -- global control --
268
      clk_i   => clk_i,           -- global clock, rising edge
269
      rstn_i  => rstn_i,          -- global reset, low-active, async
270
      ctrl_i  => ctrl,            -- main control bus
271
      -- data input --
272
      rs1_i   => rs1,             -- rf source 1
273
      rs2_i   => rs2,             -- rf source 2
274
      -- result and status --
275
      res_o   => cp0_data,        -- operation result
276
      valid_o => cp0_valid        -- data output valid
277
    );
278
  end generate;
279
 
280
  neorv32_cpu_cp_muldiv_inst_false:
281
  if (CPU_EXTENSION_RISCV_M = false) generate
282
    cp0_data  <= (others => '0');
283
    cp0_valid <= '0';
284
  end generate;
285
 
286
 
287
  -- Co-Processor 1: Not Implemented Yet ----------------------------------------------------
288
  -- -------------------------------------------------------------------------------------------
289
  cp1_data  <= (others => '0');
290
  cp1_valid <= '0';
291
 
292
 
293
  -- Bus Unit -------------------------------------------------------------------------------
294
  -- -------------------------------------------------------------------------------------------
295
  neorv32_cpu_bus_inst: neorv32_cpu_bus
296
  generic map (
297
    CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
298
    MEM_EXT_TIMEOUT       => MEM_EXT_TIMEOUT        -- cycles after which a valid bus access will timeout
299
  )
300
  port map (
301
    -- global control --
302
    clk_i       => clk_i,         -- global clock, rising edge
303
    rstn_i      => rstn_i,        -- global reset, low-active, async
304
    ctrl_i      => ctrl,          -- main control bus
305
    -- data input --
306
    wdata_i     => rs2,           -- write data
307
    pc_i        => pc,            -- current PC
308
    alu_i       => alu_res,       -- ALU result
309
    -- data output --
310
    instr_o     => instr,         -- instruction
311
    rdata_o     => rdata,         -- read data
312
    -- status --
313
    mar_o       => mar,           -- current memory address register
314
    ma_instr_o  => ma_instr,      -- misaligned instruction address
315
    ma_load_o   => ma_load,       -- misaligned load data address
316
    ma_store_o  => ma_store,      -- misaligned store data address
317
    be_instr_o  => be_instr,      -- bus error on instruction access
318
    be_load_o   => be_load,       -- bus error on load data access
319
    be_store_o  => be_store,      -- bus error on store data access
320
    bus_wait_o  => bus_wait,      -- wait for bus operation to finish
321
    exc_ack_i   => bus_exc_ack,   -- exception controller ACK
322
    -- bus system --
323
    bus_addr_o  => bus_addr_o,    -- bus access address
324
    bus_rdata_i => bus_rdata_i,   -- bus read data
325
    bus_wdata_o => bus_wdata_o,   -- bus write data
326
    bus_ben_o   => bus_ben_o,     -- byte enable
327
    bus_we_o    => bus_we_o,      -- write enable
328
    bus_re_o    => bus_re_o,      -- read enable
329
    bus_ack_i   => bus_ack_i,     -- bus transfer acknowledge
330
    bus_err_i   => bus_err_i      -- bus transfer error
331
  );
332
 
333
 
334
end neorv32_cpu_rtl;

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