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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu.vhd] - Blame information for rev 29

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1 2 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - CPU Top Entity >>                                                                #
3
-- # ********************************************************************************************* #
4 18 zero_gravi
-- # NEORV32 CPU:                                                                                  #
5 13 zero_gravi
-- # * neorv32_cpu.vhd                  : CPU top entity                                           #
6
-- #   * neorv32_cpu_alu.vhd            : Arithmetic/logic unit                                    #
7
-- #   * neorv32_cpu_bus.vhd            : Instruction and data bus interface unit                  #
8
-- #   * neorv32_cpu_cp_muldiv.vhd      : MULDIV co-processor                                      #
9
-- #   * neorv32_cpu_ctrl.vhd           : CPU control and CSR system                               #
10
-- #     * neorv32_cpu_decompressor.vhd : Compressed instructions decoder                          #
11
-- #   * neorv32_cpu_regfile.vhd        : Data register file                                       #
12 18 zero_gravi
-- #                                                                                               #
13 29 zero_gravi
-- # Check out the processor's data sheet for more information: docs/NEORV32.pdf                   #
14 2 zero_gravi
-- # ********************************************************************************************* #
15
-- # BSD 3-Clause License                                                                          #
16
-- #                                                                                               #
17
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
18
-- #                                                                                               #
19
-- # Redistribution and use in source and binary forms, with or without modification, are          #
20
-- # permitted provided that the following conditions are met:                                     #
21
-- #                                                                                               #
22
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
23
-- #    conditions and the following disclaimer.                                                   #
24
-- #                                                                                               #
25
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
26
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
27
-- #    provided with the distribution.                                                            #
28
-- #                                                                                               #
29
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
30
-- #    endorse or promote products derived from this software without specific prior written      #
31
-- #    permission.                                                                                #
32
-- #                                                                                               #
33
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
34
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
35
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
36
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
37
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
38
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
39
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
40
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
41
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
42
-- # ********************************************************************************************* #
43
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
44
-- #################################################################################################
45
 
46
library ieee;
47
use ieee.std_logic_1164.all;
48
use ieee.numeric_std.all;
49
 
50
library neorv32;
51
use neorv32.neorv32_package.all;
52
 
53
entity neorv32_cpu is
54
  generic (
55
    -- General --
56 14 zero_gravi
    HW_THREAD_ID                 : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
57
    CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
58 2 zero_gravi
    -- RISC-V CPU Extensions --
59 12 zero_gravi
    CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
60
    CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
61
    CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
62 15 zero_gravi
    CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
63 12 zero_gravi
    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
64
    CPU_EXTENSION_RISCV_Zifencei : boolean := true;  -- implement instruction stream sync.?
65 19 zero_gravi
    -- Extension Options --
66
    FAST_MUL_EN                  : boolean := false; -- use DSPs for M extension's multiplier
67 15 zero_gravi
    -- Physical Memory Protection (PMP) --
68
    PMP_USE                      : boolean := false; -- implement PMP?
69 16 zero_gravi
    PMP_NUM_REGIONS              : natural := 4;     -- number of regions (max 8)
70
    PMP_GRANULARITY              : natural := 14;    -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
71 14 zero_gravi
    -- Bus Interface --
72
    BUS_TIMEOUT                  : natural := 15     -- cycles after which a valid bus access will timeout
73 2 zero_gravi
  );
74
  port (
75
    -- global control --
76 14 zero_gravi
    clk_i          : in  std_ulogic := '0'; -- global clock, rising edge
77
    rstn_i         : in  std_ulogic := '0'; -- global reset, low-active, async
78 12 zero_gravi
    -- instruction bus interface --
79
    i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
80 14 zero_gravi
    i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
81 12 zero_gravi
    i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
82
    i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
83
    i_bus_we_o     : out std_ulogic; -- write enable
84
    i_bus_re_o     : out std_ulogic; -- read enable
85
    i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
86 14 zero_gravi
    i_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
87
    i_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
88 12 zero_gravi
    i_bus_fence_o  : out std_ulogic; -- executed FENCEI operation
89
    -- data bus interface --
90
    d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
91 14 zero_gravi
    d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
92 12 zero_gravi
    d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
93
    d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
94
    d_bus_we_o     : out std_ulogic; -- write enable
95
    d_bus_re_o     : out std_ulogic; -- read enable
96
    d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
97 14 zero_gravi
    d_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
98
    d_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
99 12 zero_gravi
    d_bus_fence_o  : out std_ulogic; -- executed FENCE operation
100 11 zero_gravi
    -- system time input from MTIME --
101 14 zero_gravi
    time_i         : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
102
    -- interrupts (risc-v compliant) --
103
    msw_irq_i      : in  std_ulogic := '0'; -- machine software interrupt
104
    mext_irq_i     : in  std_ulogic := '0'; -- machine external interrupt
105
    mtime_irq_i    : in  std_ulogic := '0'; -- machine timer interrupt
106
    -- fast interrupts (custom) --
107
    firq_i         : in  std_ulogic_vector(3 downto 0) := (others => '0')
108 2 zero_gravi
  );
109
end neorv32_cpu;
110
 
111
architecture neorv32_cpu_rtl of neorv32_cpu is
112
 
113
  -- local signals --
114 12 zero_gravi
  signal ctrl       : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
115
  signal alu_cmp    : std_ulogic_vector(1 downto 0); -- alu comparator result
116
  signal imm        : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
117
  signal instr      : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
118
  signal rs1, rs2   : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
119
  signal alu_res    : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
120
  signal rdata      : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
121
  signal alu_wait   : std_ulogic; -- alu is busy due to iterative unit
122
  signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch
123
  signal bus_d_wait : std_ulogic; -- wait for current bus data access
124
  signal csr_rdata  : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
125
  signal mar        : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
126
  signal ma_instr   : std_ulogic; -- misaligned instruction address
127
  signal ma_load    : std_ulogic; -- misaligned load data address
128
  signal ma_store   : std_ulogic; -- misaligned store data address
129
  signal be_instr   : std_ulogic; -- bus error on instruction access
130
  signal be_load    : std_ulogic; -- bus error on load data access
131
  signal be_store   : std_ulogic; -- bus error on store data access
132
  signal fetch_pc   : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
133
  signal curr_pc    : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
134 27 zero_gravi
  signal next_pc    : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for next to-be-executed instruction)
135 2 zero_gravi
 
136
  -- co-processor interface --
137
  signal cp0_data,  cp1_data  : std_ulogic_vector(data_width_c-1 downto 0);
138
  signal cp0_valid, cp1_valid : std_ulogic;
139 19 zero_gravi
  signal cp0_start, cp1_start : std_ulogic;
140 2 zero_gravi
 
141 15 zero_gravi
  -- pmp interface --
142
  signal pmp_addr  : pmp_addr_if_t;
143
  signal pmp_ctrl  : pmp_ctrl_if_t;
144
  signal priv_mode : std_ulogic_vector(1 downto 0); -- current CPU privilege level
145
 
146 2 zero_gravi
begin
147
 
148 15 zero_gravi
  -- Sanity Checks --------------------------------------------------------------------------
149
  -- -------------------------------------------------------------------------------------------
150 23 zero_gravi
  -- CSR system --
151
  assert not (CPU_EXTENSION_RISCV_Zicsr = false) report "NEORV32 CPU CONFIG WARNING! No exception/interrupt/machine features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning;
152
  -- U-extension requires Zicsr extension --
153
  assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_U = true)) report "NEORV32 CPU CONFIG ERROR! User mode requires CPU_EXTENSION_RISCV_Zicsr extension." severity error;
154
  -- PMP requires Zicsr extension --
155
  assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Physical memory protection (PMP) requires CPU_EXTENSION_RISCV_Zicsr extension." severity error;
156
  -- PMP regions --
157
  assert not ((PMP_NUM_REGIONS > pmp_max_r_c) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions out of valid range." severity error;
158
  -- PMP granulartiy --
159
  assert not (((PMP_GRANULARITY < 1) or (PMP_GRANULARITY > 32)) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Invalid PMP granulartiy (0 < G < 33)." severity error;
160
  -- Bus timeout --
161
  assert not (BUS_TIMEOUT < 1) report "NEORV32 CPU CONFIG ERROR! Invalid bus timeout - must be at least 1 cycle." severity error;
162 15 zero_gravi
 
163 23 zero_gravi
 
164 2 zero_gravi
  -- Control Unit ---------------------------------------------------------------------------
165
  -- -------------------------------------------------------------------------------------------
166
  neorv32_cpu_control_inst: neorv32_cpu_control
167
  generic map (
168
    -- General --
169 27 zero_gravi
    HW_THREAD_ID                 => HW_THREAD_ID,    -- hardware thread id
170
    CPU_BOOT_ADDR                => CPU_BOOT_ADDR,   -- cpu boot address
171 2 zero_gravi
    -- RISC-V CPU Extensions --
172 15 zero_gravi
    CPU_EXTENSION_RISCV_C        => CPU_EXTENSION_RISCV_C,        -- implement compressed extension?
173
    CPU_EXTENSION_RISCV_E        => CPU_EXTENSION_RISCV_E,        -- implement embedded RF extension?
174
    CPU_EXTENSION_RISCV_M        => CPU_EXTENSION_RISCV_M,        -- implement muld/div extension?
175
    CPU_EXTENSION_RISCV_U        => CPU_EXTENSION_RISCV_U,        -- implement user mode extension?
176
    CPU_EXTENSION_RISCV_Zicsr    => CPU_EXTENSION_RISCV_Zicsr,    -- implement CSR system?
177
    CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
178
    -- Physical memory protection (PMP) --
179
    PMP_USE                      => PMP_USE,         -- implement physical memory protection?
180
    PMP_NUM_REGIONS              => PMP_NUM_REGIONS, -- number of regions (1..4)
181
    PMP_GRANULARITY              => PMP_GRANULARITY  -- granularity (0=none, 1=8B, 2=16B, 3=32B, ...)
182 2 zero_gravi
  )
183
  port map (
184
    -- global control --
185
    clk_i         => clk_i,       -- global clock, rising edge
186
    rstn_i        => rstn_i,      -- global reset, low-active, async
187
    ctrl_o        => ctrl,        -- main control bus
188
    -- status input --
189
    alu_wait_i    => alu_wait,    -- wait for ALU
190 12 zero_gravi
    bus_i_wait_i  => bus_i_wait,  -- wait for bus
191
    bus_d_wait_i  => bus_d_wait,  -- wait for bus
192 2 zero_gravi
    -- data input --
193
    instr_i       => instr,       -- instruction
194
    cmp_i         => alu_cmp,     -- comparator status
195 27 zero_gravi
    alu_res_i     => alu_res,     -- ALU processing result
196 2 zero_gravi
    -- data output --
197
    imm_o         => imm,         -- immediate
198 6 zero_gravi
    fetch_pc_o    => fetch_pc,    -- PC for instruction fetch
199
    curr_pc_o     => curr_pc,     -- current PC (corresponding to current instruction)
200 27 zero_gravi
    next_pc_o     => next_pc,     -- next PC (corresponding to current instruction
201 2 zero_gravi
    csr_rdata_o   => csr_rdata,   -- CSR read data
202 14 zero_gravi
    -- interrupts (risc-v compliant) --
203
    msw_irq_i     => msw_irq_i,   -- machine software interrupt
204
    mext_irq_i    => mext_irq_i,  -- machine external interrupt
205 2 zero_gravi
    mtime_irq_i   => mtime_irq_i, -- machine timer interrupt
206 14 zero_gravi
    -- fast interrupts (custom) --
207
    firq_i        => firq_i,
208 11 zero_gravi
    -- system time input from MTIME --
209
    time_i        => time_i,      -- current system time
210 15 zero_gravi
    -- physical memory protection --
211
    pmp_addr_o    => pmp_addr,    -- addresses
212
    pmp_ctrl_o    => pmp_ctrl,    -- configs
213
    priv_mode_o   => priv_mode,   -- current CPU privilege level
214 2 zero_gravi
    -- bus access exceptions --
215
    mar_i         => mar,         -- memory address register
216
    ma_instr_i    => ma_instr,    -- misaligned instruction address
217
    ma_load_i     => ma_load,     -- misaligned load data address
218
    ma_store_i    => ma_store,    -- misaligned store data address
219
    be_instr_i    => be_instr,    -- bus error on instruction access
220
    be_load_i     => be_load,     -- bus error on load data access
221 12 zero_gravi
    be_store_i    => be_store     -- bus error on store data access
222 2 zero_gravi
  );
223
 
224
 
225
  -- Register File --------------------------------------------------------------------------
226
  -- -------------------------------------------------------------------------------------------
227
  neorv32_regfile_inst: neorv32_cpu_regfile
228
  generic map (
229
    CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E -- implement embedded RF extension?
230
  )
231
  port map (
232
    -- global control --
233
    clk_i  => clk_i,              -- global clock, rising edge
234
    ctrl_i => ctrl,               -- main control bus
235
    -- data input --
236
    mem_i  => rdata,              -- memory read data
237
    alu_i  => alu_res,            -- ALU result
238
    csr_i  => csr_rdata,          -- CSR read data
239 13 zero_gravi
    pc_i   => next_pc,            -- next pc (for linking)
240 2 zero_gravi
    -- data output --
241
    rs1_o  => rs1,                -- operand 1
242
    rs2_o  => rs2                 -- operand 2
243
  );
244
 
245
 
246
  -- ALU ------------------------------------------------------------------------------------
247
  -- -------------------------------------------------------------------------------------------
248
  neorv32_cpu_alu_inst: neorv32_cpu_alu
249 11 zero_gravi
  generic map (
250
    CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M -- implement muld/div extension?
251
  )
252 2 zero_gravi
  port map (
253
    -- global control --
254
    clk_i       => clk_i,         -- global clock, rising edge
255
    rstn_i      => rstn_i,        -- global reset, low-active, async
256
    ctrl_i      => ctrl,          -- main control bus
257
    -- data input --
258
    rs1_i       => rs1,           -- rf source 1
259
    rs2_i       => rs2,           -- rf source 2
260 6 zero_gravi
    pc2_i       => curr_pc,       -- delayed PC
261 2 zero_gravi
    imm_i       => imm,           -- immediate
262
    -- data output --
263
    cmp_o       => alu_cmp,       -- comparator status
264
    res_o       => alu_res,       -- ALU result
265
    -- co-processor interface --
266 19 zero_gravi
    cp0_start_o => cp0_start,     -- trigger co-processor 0
267 2 zero_gravi
    cp0_data_i  => cp0_data,      -- co-processor 0 result
268
    cp0_valid_i => cp0_valid,     -- co-processor 0 result valid
269 19 zero_gravi
    cp1_start_o => cp1_start,     -- trigger co-processor 1
270 2 zero_gravi
    cp1_data_i  => cp1_data,      -- co-processor 1 result
271
    cp1_valid_i => cp1_valid,     -- co-processor 1 result valid
272
    -- status --
273
    wait_o      => alu_wait       -- busy due to iterative processing units
274
  );
275
 
276
 
277
  -- Co-Processor 0: MULDIV Unit ------------------------------------------------------------
278
  -- -------------------------------------------------------------------------------------------
279
  neorv32_cpu_cp_muldiv_inst_true:
280
  if (CPU_EXTENSION_RISCV_M = true) generate
281
    neorv32_cpu_cp_muldiv_inst: neorv32_cpu_cp_muldiv
282 19 zero_gravi
    generic map (
283
      FAST_MUL_EN => FAST_MUL_EN -- use DSPs for faster multiplication
284
    )
285 2 zero_gravi
    port map (
286
      -- global control --
287
      clk_i   => clk_i,           -- global clock, rising edge
288
      rstn_i  => rstn_i,          -- global reset, low-active, async
289
      ctrl_i  => ctrl,            -- main control bus
290
      -- data input --
291 19 zero_gravi
      start_i => cp0_start,       -- trigger operation
292 27 zero_gravi
      rs1_i   => rs1,             -- rf source 1
293
      rs2_i   => rs2,             -- rf source 2
294 2 zero_gravi
      -- result and status --
295
      res_o   => cp0_data,        -- operation result
296
      valid_o => cp0_valid        -- data output valid
297
    );
298
  end generate;
299
 
300
  neorv32_cpu_cp_muldiv_inst_false:
301
  if (CPU_EXTENSION_RISCV_M = false) generate
302
    cp0_data  <= (others => '0');
303
    cp0_valid <= '0';
304
  end generate;
305
 
306
 
307
  -- Co-Processor 1: Not Implemented Yet ----------------------------------------------------
308
  -- -------------------------------------------------------------------------------------------
309
  cp1_data  <= (others => '0');
310
  cp1_valid <= '0';
311
 
312
 
313 12 zero_gravi
  -- Bus Interface Unit ---------------------------------------------------------------------
314 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
315
  neorv32_cpu_bus_inst: neorv32_cpu_bus
316
  generic map (
317 11 zero_gravi
    CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
318 15 zero_gravi
    BUS_TIMEOUT           => BUS_TIMEOUT,           -- cycles after which a valid bus access will timeout
319
    -- Physical memory protection (PMP) --
320 27 zero_gravi
    PMP_USE               => PMP_USE,               -- implement physical memory protection?
321
    PMP_NUM_REGIONS       => PMP_NUM_REGIONS,       -- number of regions (1..4)
322
    PMP_GRANULARITY       => PMP_GRANULARITY        -- granularity (0=none, 1=8B, 2=16B, 3=32B, ...)
323 2 zero_gravi
  )
324
  port map (
325
    -- global control --
326 12 zero_gravi
    clk_i          => clk_i,          -- global clock, rising edge
327
    rstn_i         => rstn_i,         -- global reset, low-active, async
328
    ctrl_i         => ctrl,           -- main control bus
329
    -- cpu instruction fetch interface --
330
    fetch_pc_i     => fetch_pc,       -- PC for instruction fetch
331
    instr_o        => instr,          -- instruction
332
    i_wait_o       => bus_i_wait,     -- wait for fetch to complete
333
    --
334
    ma_instr_o     => ma_instr,       -- misaligned instruction address
335
    be_instr_o     => be_instr,       -- bus error on instruction access
336
    -- cpu data access interface --
337 29 zero_gravi
    addr_i         => alu_res,       -- ALU result -> access address
338 12 zero_gravi
    wdata_i        => rs2,            -- write data
339
    rdata_o        => rdata,          -- read data
340
    mar_o          => mar,            -- current memory address register
341
    d_wait_o       => bus_d_wait,     -- wait for access to complete
342
    --
343
    ma_load_o      => ma_load,        -- misaligned load data address
344
    ma_store_o     => ma_store,       -- misaligned store data address
345
    be_load_o      => be_load,        -- bus error on load data access
346
    be_store_o     => be_store,       -- bus error on store data access
347 15 zero_gravi
    -- physical memory protection --
348
    pmp_addr_i     => pmp_addr,       -- addresses
349
    pmp_ctrl_i     => pmp_ctrl,       -- configs
350
    priv_mode_i    => priv_mode,      -- current CPU privilege level
351 12 zero_gravi
    -- instruction bus --
352
    i_bus_addr_o   => i_bus_addr_o,   -- bus access address
353
    i_bus_rdata_i  => i_bus_rdata_i,  -- bus read data
354
    i_bus_wdata_o  => i_bus_wdata_o,  -- bus write data
355
    i_bus_ben_o    => i_bus_ben_o,    -- byte enable
356
    i_bus_we_o     => i_bus_we_o,     -- write enable
357
    i_bus_re_o     => i_bus_re_o,     -- read enable
358
    i_bus_cancel_o => i_bus_cancel_o, -- cancel current bus transaction
359
    i_bus_ack_i    => i_bus_ack_i,    -- bus transfer acknowledge
360
    i_bus_err_i    => i_bus_err_i,    -- bus transfer error
361
    i_bus_fence_o  => i_bus_fence_o,  -- fence operation
362
    -- data bus --
363
    d_bus_addr_o   => d_bus_addr_o,   -- bus access address
364
    d_bus_rdata_i  => d_bus_rdata_i,  -- bus read data
365
    d_bus_wdata_o  => d_bus_wdata_o,  -- bus write data
366
    d_bus_ben_o    => d_bus_ben_o,    -- byte enable
367
    d_bus_we_o     => d_bus_we_o,     -- write enable
368
    d_bus_re_o     => d_bus_re_o,     -- read enable
369
    d_bus_cancel_o => d_bus_cancel_o, -- cancel current bus transaction
370
    d_bus_ack_i    => d_bus_ack_i,    -- bus transfer acknowledge
371
    d_bus_err_i    => d_bus_err_i,    -- bus transfer error
372
    d_bus_fence_o  => d_bus_fence_o   -- fence operation
373 2 zero_gravi
  );
374
 
375
 
376
end neorv32_cpu_rtl;

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