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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu.vhd] - Blame information for rev 8

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1 2 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - CPU Top Entity >>                                                                #
3
-- # ********************************************************************************************* #
4
-- # Top NEORV32 CPU:                                                                              #
5
-- # * neorv32_cpu_alu: Arithemtical/logical unit                                                  #
6
-- # * neorv32_cpu_ctrl: CPU control and CSR system                                                #
7
-- #   * neorv32_cpu_decompressor: Compressed instructions decoder                                 #
8
-- # * neorv32_cpu_bus: Memory/IO bus interface unit                                               #
9
-- # * neorv32_cpu_cp_muldiv: MULDIV co-processor                                                  #
10
-- # * neorv32_cpu_regfile: Data register file                                                     #
11
-- # ********************************************************************************************* #
12
-- # BSD 3-Clause License                                                                          #
13
-- #                                                                                               #
14
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
15
-- #                                                                                               #
16
-- # Redistribution and use in source and binary forms, with or without modification, are          #
17
-- # permitted provided that the following conditions are met:                                     #
18
-- #                                                                                               #
19
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
20
-- #    conditions and the following disclaimer.                                                   #
21
-- #                                                                                               #
22
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
23
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
24
-- #    provided with the distribution.                                                            #
25
-- #                                                                                               #
26
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
27
-- #    endorse or promote products derived from this software without specific prior written      #
28
-- #    permission.                                                                                #
29
-- #                                                                                               #
30
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
31
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
32
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
33
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
34
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
35
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
36
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
37
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
38
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
39
-- # ********************************************************************************************* #
40
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
41
-- #################################################################################################
42
 
43
library ieee;
44
use ieee.std_logic_1164.all;
45
use ieee.numeric_std.all;
46
 
47
library neorv32;
48
use neorv32.neorv32_package.all;
49
 
50
entity neorv32_cpu is
51
  generic (
52
    -- General --
53 8 zero_gravi
    CLOCK_FREQUENCY              : natural := 0; -- clock frequency of clk_i in Hz
54
    HART_ID                      : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
55
    BOOTLOADER_USE               : boolean := true;   -- implement processor-internal bootloader?
56
    CSR_COUNTERS_USE             : boolean := true;   -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
57 2 zero_gravi
    -- RISC-V CPU Extensions --
58 8 zero_gravi
    CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?
59
    CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
60
    CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement muld/div extension?
61
    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?
62
    CPU_EXTENSION_RISCV_Zifencei : boolean := true;   -- implement instruction stream sync.?
63 2 zero_gravi
    -- Memory configuration: Instruction memory --
64 8 zero_gravi
    MEM_ISPACE_BASE              : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
65
    MEM_ISPACE_SIZE              : natural := 8*1024; -- total size of instruction memory space in byte
66
    MEM_INT_IMEM_USE             : boolean := true;   -- implement processor-internal instruction memory
67
    MEM_INT_IMEM_SIZE            : natural := 8*1024; -- size of processor-internal instruction memory in bytes
68
    MEM_INT_IMEM_ROM             : boolean := false;  -- implement processor-internal instruction memory as ROM
69 2 zero_gravi
    -- Memory configuration: Data memory --
70 8 zero_gravi
    MEM_DSPACE_BASE              : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
71
    MEM_DSPACE_SIZE              : natural := 4*1024; -- total size of data memory space in byte
72
    MEM_INT_DMEM_USE             : boolean := true;   -- implement processor-internal data memory
73
    MEM_INT_DMEM_SIZE            : natural := 4*1024; -- size of processor-internal data memory in bytes
74 2 zero_gravi
    -- Memory configuration: External memory interface --
75 8 zero_gravi
    MEM_EXT_USE                  : boolean := false;  -- implement external memory bus interface?
76
    MEM_EXT_TIMEOUT              : natural := 15;     -- cycles after which a valid bus access will timeout
77 2 zero_gravi
    -- Processor peripherals --
78 8 zero_gravi
    IO_GPIO_USE                  : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
79
    IO_MTIME_USE                 : boolean := true;   -- implement machine system timer (MTIME)?
80
    IO_UART_USE                  : boolean := true;   -- implement universal asynchronous receiver/transmitter (UART)?
81
    IO_SPI_USE                   : boolean := true;   -- implement serial peripheral interface (SPI)?
82
    IO_TWI_USE                   : boolean := true;   -- implement two-wire interface (TWI)?
83
    IO_PWM_USE                   : boolean := true;   -- implement pulse-width modulation unit (PWM)?
84
    IO_WDT_USE                   : boolean := true;   -- implement watch dog timer (WDT)?
85
    IO_CLIC_USE                  : boolean := true;   -- implement core local interrupt controller (CLIC)?
86
    IO_TRNG_USE                  : boolean := true;   -- implement true random number generator (TRNG)?
87
    IO_DEVNULL_USE               : boolean := true    -- implement dummy device (DEVNULL)?
88 2 zero_gravi
  );
89
  port (
90
    -- global control --
91
    clk_i       : in  std_ulogic; -- global clock, rising edge
92
    rstn_i      : in  std_ulogic; -- global reset, low-active, async
93
    -- bus interface --
94
    bus_addr_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
95
    bus_rdata_i : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
96
    bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
97
    bus_ben_o   : out std_ulogic_vector(03 downto 0); -- byte enable
98
    bus_we_o    : out std_ulogic; -- write enable
99
    bus_re_o    : out std_ulogic; -- read enable
100
    bus_ack_i   : in  std_ulogic; -- bus transfer acknowledge
101
    bus_err_i   : in  std_ulogic; -- bus transfer error
102
    -- external interrupts --
103
    clic_irq_i  : in  std_ulogic; -- CLIC interrupt request
104
    mtime_irq_i : in  std_ulogic  -- machine timer interrupt
105
  );
106
end neorv32_cpu;
107
 
108
architecture neorv32_cpu_rtl of neorv32_cpu is
109
 
110
  -- local signals --
111
  signal ctrl        : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
112
  signal alu_cmp     : std_ulogic_vector(1 downto 0); -- alu comparator result
113
  signal imm         : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
114
  signal instr       : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
115
  signal rs1, rs2    : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
116
  signal alu_res     : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
117
  signal alu_add     : std_ulogic_vector(data_width_c-1 downto 0); -- alu adder result
118
  signal rdata       : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
119
  signal alu_wait    : std_ulogic; -- alu is busy due to iterative unit
120
  signal bus_wait    : std_ulogic; -- wait for bus to finish operation
121
  signal csr_rdata   : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
122
  signal mar         : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
123
  signal ma_instr    : std_ulogic; -- misaligned instruction address
124
  signal ma_load     : std_ulogic; -- misaligned load data address
125
  signal ma_store    : std_ulogic; -- misaligned store data address
126
  signal be_instr    : std_ulogic; -- bus error on instruction access
127
  signal be_load     : std_ulogic; -- bus error on load data access
128
  signal be_store    : std_ulogic; -- bus error on store data access
129
  signal bus_exc_ack : std_ulogic; -- bus exception error acknowledge
130 6 zero_gravi
  signal bus_busy    : std_ulogic; -- bus unit is busy
131
  signal fetch_pc    : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
132
  signal curr_pc     : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
133
  signal next_pc     : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for current executed instruction)
134 2 zero_gravi
 
135
  -- co-processor interface --
136
  signal cp0_data,  cp1_data  : std_ulogic_vector(data_width_c-1 downto 0);
137
  signal cp0_valid, cp1_valid : std_ulogic;
138
 
139
begin
140
 
141
  -- Control Unit ---------------------------------------------------------------------------
142
  -- -------------------------------------------------------------------------------------------
143
  neorv32_cpu_control_inst: neorv32_cpu_control
144
  generic map (
145
    -- General --
146 8 zero_gravi
    CLOCK_FREQUENCY              => CLOCK_FREQUENCY,  -- clock frequency of clk_i in Hz
147
    HART_ID                      => HART_ID,          -- custom hardware thread ID
148
    BOOTLOADER_USE               => BOOTLOADER_USE,   -- implement processor-internal bootloader?
149
    CSR_COUNTERS_USE             => CSR_COUNTERS_USE, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
150 2 zero_gravi
    -- RISC-V CPU Extensions --
151 8 zero_gravi
    CPU_EXTENSION_RISCV_C        => CPU_EXTENSION_RISCV_C,     -- implement compressed extension?
152
    CPU_EXTENSION_RISCV_E        => CPU_EXTENSION_RISCV_E,     -- implement embedded RF extension?
153
    CPU_EXTENSION_RISCV_M        => CPU_EXTENSION_RISCV_M,     -- implement muld/div extension?
154
    CPU_EXTENSION_RISCV_Zicsr    => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
155
    CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
156 2 zero_gravi
    -- Memory configuration: Instruction memory --
157 8 zero_gravi
    MEM_ISPACE_BASE              => MEM_ISPACE_BASE,   -- base address of instruction memory space
158
    MEM_ISPACE_SIZE              => MEM_ISPACE_SIZE,   -- total size of instruction memory space in byte
159
    MEM_INT_IMEM_USE             => MEM_INT_IMEM_USE,  -- implement processor-internal instruction memory
160
    MEM_INT_IMEM_SIZE            => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
161
    MEM_INT_IMEM_ROM             => MEM_INT_IMEM_ROM,  -- implement processor-internal instruction memory as ROM
162 2 zero_gravi
    -- Memory configuration: Data memory --
163 8 zero_gravi
    MEM_DSPACE_BASE              => MEM_DSPACE_BASE,   -- base address of data memory space
164
    MEM_DSPACE_SIZE              => MEM_DSPACE_SIZE,   -- total size of data memory space in byte
165
    MEM_INT_DMEM_USE             => MEM_INT_DMEM_USE,  -- implement processor-internal data memory
166
    MEM_INT_DMEM_SIZE            => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
167 2 zero_gravi
    -- Memory configuration: External memory interface --
168 8 zero_gravi
    MEM_EXT_USE                  => MEM_EXT_USE,       -- implement external memory bus interface?
169 2 zero_gravi
    -- Processor peripherals --
170 8 zero_gravi
    IO_GPIO_USE                  => IO_GPIO_USE,       -- implement general purpose input/output port unit (GPIO)?
171
    IO_MTIME_USE                 => IO_MTIME_USE,      -- implement machine system timer (MTIME)?
172
    IO_UART_USE                  => IO_UART_USE,       -- implement universal asynchronous receiver/transmitter (UART)?
173
    IO_SPI_USE                   => IO_SPI_USE,        -- implement serial peripheral interface (SPI)?
174
    IO_TWI_USE                   => IO_TWI_USE,        -- implement two-wire interface (TWI)?
175
    IO_PWM_USE                   => IO_PWM_USE,        -- implement pulse-width modulation unit (PWM)?
176
    IO_WDT_USE                   => IO_WDT_USE,        -- implement watch dog timer (WDT)?
177
    IO_CLIC_USE                  => IO_CLIC_USE,       -- implement core local interrupt controller (CLIC)?
178
    IO_TRNG_USE                  => IO_TRNG_USE,       -- implement true random number generator (TRNG)?
179
    IO_DEVNULL_USE               => IO_DEVNULL_USE     -- implement dummy device (DEVNULL)?
180 2 zero_gravi
  )
181
  port map (
182
    -- global control --
183
    clk_i         => clk_i,       -- global clock, rising edge
184
    rstn_i        => rstn_i,      -- global reset, low-active, async
185
    ctrl_o        => ctrl,        -- main control bus
186
    -- status input --
187
    alu_wait_i    => alu_wait,    -- wait for ALU
188
    bus_wait_i    => bus_wait,    -- wait for bus
189
    -- data input --
190
    instr_i       => instr,       -- instruction
191
    cmp_i         => alu_cmp,     -- comparator status
192
    alu_add_i     => alu_add,     -- ALU.add result
193
    -- data output --
194
    imm_o         => imm,         -- immediate
195 6 zero_gravi
    fetch_pc_o    => fetch_pc,    -- PC for instruction fetch
196
    curr_pc_o     => curr_pc,     -- current PC (corresponding to current instruction)
197
    next_pc_o     => next_pc,     -- next PC (corresponding to current instruction)
198 2 zero_gravi
    -- csr interface --
199
    csr_wdata_i   => alu_res,     -- CSR write data
200
    csr_rdata_o   => csr_rdata,   -- CSR read data
201
    -- external interrupt --
202
    clic_irq_i    => clic_irq_i,  -- CLIC interrupt request
203
    mtime_irq_i   => mtime_irq_i, -- machine timer interrupt
204
    -- bus access exceptions --
205
    mar_i         => mar,         -- memory address register
206
    ma_instr_i    => ma_instr,    -- misaligned instruction address
207
    ma_load_i     => ma_load,     -- misaligned load data address
208
    ma_store_i    => ma_store,    -- misaligned store data address
209
    be_instr_i    => be_instr,    -- bus error on instruction access
210
    be_load_i     => be_load,     -- bus error on load data access
211
    be_store_i    => be_store,    -- bus error on store data access
212 6 zero_gravi
    bus_exc_ack_o => bus_exc_ack, -- bus exception error acknowledge
213
    bus_busy_i    => bus_busy     -- bus unit is busy
214 2 zero_gravi
  );
215
 
216
 
217
  -- Register File --------------------------------------------------------------------------
218
  -- -------------------------------------------------------------------------------------------
219
  neorv32_regfile_inst: neorv32_cpu_regfile
220
  generic map (
221
    CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E -- implement embedded RF extension?
222
  )
223
  port map (
224
    -- global control --
225
    clk_i  => clk_i,              -- global clock, rising edge
226
    ctrl_i => ctrl,               -- main control bus
227
    -- data input --
228
    mem_i  => rdata,              -- memory read data
229
    alu_i  => alu_res,            -- ALU result
230
    csr_i  => csr_rdata,          -- CSR read data
231 6 zero_gravi
    pc_i   => next_pc,            -- next pc
232 2 zero_gravi
    -- data output --
233
    rs1_o  => rs1,                -- operand 1
234
    rs2_o  => rs2                 -- operand 2
235
  );
236
 
237
 
238
  -- ALU ------------------------------------------------------------------------------------
239
  -- -------------------------------------------------------------------------------------------
240
  neorv32_cpu_alu_inst: neorv32_cpu_alu
241
  port map (
242
    -- global control --
243
    clk_i       => clk_i,         -- global clock, rising edge
244
    rstn_i      => rstn_i,        -- global reset, low-active, async
245
    ctrl_i      => ctrl,          -- main control bus
246
    -- data input --
247
    rs1_i       => rs1,           -- rf source 1
248
    rs2_i       => rs2,           -- rf source 2
249 6 zero_gravi
    pc2_i       => curr_pc,       -- delayed PC
250 2 zero_gravi
    imm_i       => imm,           -- immediate
251
    csr_i       => csr_rdata,     -- csr read data
252
    -- data output --
253
    cmp_o       => alu_cmp,       -- comparator status
254
    add_o       => alu_add,       -- OPA + OPB
255
    res_o       => alu_res,       -- ALU result
256
    -- co-processor interface --
257
    cp0_data_i  => cp0_data,      -- co-processor 0 result
258
    cp0_valid_i => cp0_valid,     -- co-processor 0 result valid
259
    cp1_data_i  => cp1_data,      -- co-processor 1 result
260
    cp1_valid_i => cp1_valid,     -- co-processor 1 result valid
261
    -- status --
262
    wait_o      => alu_wait       -- busy due to iterative processing units
263
  );
264
 
265
 
266
  -- Co-Processor 0: MULDIV Unit ------------------------------------------------------------
267
  -- -------------------------------------------------------------------------------------------
268
  neorv32_cpu_cp_muldiv_inst_true:
269
  if (CPU_EXTENSION_RISCV_M = true) generate
270
    neorv32_cpu_cp_muldiv_inst: neorv32_cpu_cp_muldiv
271
    port map (
272
      -- global control --
273
      clk_i   => clk_i,           -- global clock, rising edge
274
      rstn_i  => rstn_i,          -- global reset, low-active, async
275
      ctrl_i  => ctrl,            -- main control bus
276
      -- data input --
277
      rs1_i   => rs1,             -- rf source 1
278
      rs2_i   => rs2,             -- rf source 2
279
      -- result and status --
280
      res_o   => cp0_data,        -- operation result
281
      valid_o => cp0_valid        -- data output valid
282
    );
283
  end generate;
284
 
285
  neorv32_cpu_cp_muldiv_inst_false:
286
  if (CPU_EXTENSION_RISCV_M = false) generate
287
    cp0_data  <= (others => '0');
288
    cp0_valid <= '0';
289
  end generate;
290
 
291
 
292
  -- Co-Processor 1: Not Implemented Yet ----------------------------------------------------
293
  -- -------------------------------------------------------------------------------------------
294
  cp1_data  <= (others => '0');
295
  cp1_valid <= '0';
296
 
297
 
298
  -- Bus Unit -------------------------------------------------------------------------------
299
  -- -------------------------------------------------------------------------------------------
300
  neorv32_cpu_bus_inst: neorv32_cpu_bus
301
  generic map (
302 6 zero_gravi
    MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
303 2 zero_gravi
  )
304
  port map (
305
    -- global control --
306
    clk_i       => clk_i,         -- global clock, rising edge
307
    rstn_i      => rstn_i,        -- global reset, low-active, async
308
    ctrl_i      => ctrl,          -- main control bus
309
    -- data input --
310
    wdata_i     => rs2,           -- write data
311 6 zero_gravi
    pc_i        => fetch_pc,      -- current PC for instruction fetch
312 2 zero_gravi
    alu_i       => alu_res,       -- ALU result
313
    -- data output --
314
    instr_o     => instr,         -- instruction
315
    rdata_o     => rdata,         -- read data
316
    -- status --
317
    mar_o       => mar,           -- current memory address register
318
    ma_instr_o  => ma_instr,      -- misaligned instruction address
319
    ma_load_o   => ma_load,       -- misaligned load data address
320
    ma_store_o  => ma_store,      -- misaligned store data address
321
    be_instr_o  => be_instr,      -- bus error on instruction access
322
    be_load_o   => be_load,       -- bus error on load data access
323
    be_store_o  => be_store,      -- bus error on store data access
324
    bus_wait_o  => bus_wait,      -- wait for bus operation to finish
325 6 zero_gravi
    bus_busy_o  => bus_busy,      -- bus unit is busy
326 2 zero_gravi
    exc_ack_i   => bus_exc_ack,   -- exception controller ACK
327
    -- bus system --
328
    bus_addr_o  => bus_addr_o,    -- bus access address
329
    bus_rdata_i => bus_rdata_i,   -- bus read data
330
    bus_wdata_o => bus_wdata_o,   -- bus write data
331
    bus_ben_o   => bus_ben_o,     -- byte enable
332
    bus_we_o    => bus_we_o,      -- write enable
333
    bus_re_o    => bus_re_o,      -- read enable
334
    bus_ack_i   => bus_ack_i,     -- bus transfer acknowledge
335
    bus_err_i   => bus_err_i      -- bus transfer error
336
  );
337
 
338
 
339
end neorv32_cpu_rtl;

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