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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_alu.vhd] - Blame information for rev 23

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1 2 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - Arithmetical/Logical Unit >>                                                     #
3
-- # ********************************************************************************************* #
4 20 zero_gravi
-- # Main data and address ALU. Includes comparator unit and co-processor interface/arbiter.       #
5
-- # The shifter sub-unit uses an iterative approach.                                              #
6 2 zero_gravi
-- # ********************************************************************************************* #
7
-- # BSD 3-Clause License                                                                          #
8
-- #                                                                                               #
9
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
10
-- #                                                                                               #
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-- # Redistribution and use in source and binary forms, with or without modification, are          #
12
-- # permitted provided that the following conditions are met:                                     #
13
-- #                                                                                               #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
15
-- #    conditions and the following disclaimer.                                                   #
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-- #                                                                                               #
17
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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-- #    conditions and the following disclaimer in the documentation and/or other materials        #
19
-- #    provided with the distribution.                                                            #
20
-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
23
-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
36
-- #################################################################################################
37
 
38
library ieee;
39
use ieee.std_logic_1164.all;
40
use ieee.numeric_std.all;
41
 
42
library neorv32;
43
use neorv32.neorv32_package.all;
44
 
45
entity neorv32_cpu_alu is
46 11 zero_gravi
  generic (
47
    CPU_EXTENSION_RISCV_M : boolean := true -- implement muld/div extension?
48
  );
49 2 zero_gravi
  port (
50
    -- global control --
51
    clk_i       : in  std_ulogic; -- global clock, rising edge
52
    rstn_i      : in  std_ulogic; -- global reset, low-active, async
53
    ctrl_i      : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
54
    -- data input --
55
    rs1_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
56
    rs2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
57
    pc2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
58
    imm_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- immediate
59
    csr_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
60
    -- data output --
61
    cmp_o       : out std_ulogic_vector(1 downto 0); -- comparator status
62
    add_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- OPA + OPB
63
    res_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
64
    -- co-processor interface --
65 19 zero_gravi
    cp0_start_o : out std_ulogic; -- trigger co-processor 0
66 2 zero_gravi
    cp0_data_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
67
    cp0_valid_i : in  std_ulogic; -- co-processor 0 result valid
68 19 zero_gravi
    cp1_start_o : out std_ulogic; -- trigger co-processor 1
69 2 zero_gravi
    cp1_data_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result
70
    cp1_valid_i : in  std_ulogic; -- co-processor 1 result valid
71
    -- status --
72
    wait_o      : out std_ulogic -- busy due to iterative processing units
73
  );
74
end neorv32_cpu_alu;
75
 
76
architecture neorv32_cpu_cpu_rtl of neorv32_cpu_alu is
77
 
78
  -- operands --
79 6 zero_gravi
  signal opa, opb, opc : std_ulogic_vector(data_width_c-1 downto 0);
80 2 zero_gravi
 
81
  -- results --
82
  signal add_res : std_ulogic_vector(data_width_c-1 downto 0);
83
  signal alu_res : std_ulogic_vector(data_width_c-1 downto 0);
84
 
85
  -- comparator --
86
  signal cmp_opx   : std_ulogic_vector(data_width_c downto 0);
87
  signal cmp_opy   : std_ulogic_vector(data_width_c downto 0);
88
  signal cmp_sub   : std_ulogic_vector(data_width_c downto 0);
89
  signal sub_res   : std_ulogic_vector(data_width_c-1 downto 0);
90
  signal cmp_equal : std_ulogic;
91
  signal cmp_less  : std_ulogic;
92
 
93
  -- shifter --
94 12 zero_gravi
  type shifter_t is record
95
    cmd    : std_ulogic;
96
    cmd_ff : std_ulogic;
97
    start  : std_ulogic;
98
    run    : std_ulogic;
99 19 zero_gravi
    halt   : std_ulogic;
100 12 zero_gravi
    cnt    : std_ulogic_vector(4 downto 0);
101
    sreg   : std_ulogic_vector(data_width_c-1 downto 0);
102
  end record;
103
  signal shifter : shifter_t;
104 2 zero_gravi
 
105 19 zero_gravi
  -- co-processor arbiter and interface --
106
  type cp_ctrl_t is record
107
    cmd_ff : std_ulogic;
108
    busy   : std_ulogic;
109
    start  : std_ulogic;
110
    halt   : std_ulogic;
111
    rb_ff0 : std_ulogic;
112
    rb_ff1 : std_ulogic;
113
  end record;
114
  signal cp_ctrl : cp_ctrl_t;
115 2 zero_gravi
 
116 23 zero_gravi
  -- bit manipulation --
117
  signal bitm_res : std_ulogic_vector(31 downto 0);
118
 
119 2 zero_gravi
begin
120
 
121
  -- Operand Mux ----------------------------------------------------------------------------
122
  -- -------------------------------------------------------------------------------------------
123 6 zero_gravi
  input_op_mux: process(ctrl_i, csr_i, pc2_i, rs1_i, rs2_i, imm_i)
124 2 zero_gravi
  begin
125
    -- opa (first ALU input operand) --
126 12 zero_gravi
    case ctrl_i(ctrl_alu_opa_mux_msb_c downto ctrl_alu_opa_mux_lsb_c) is
127
      when "00"   => opa <= rs1_i;
128
      when "01"   => opa <= pc2_i;
129
      when others => opa <= csr_i;
130
    end case;
131 2 zero_gravi
    -- opb (second ALU input operand) --
132 12 zero_gravi
    case ctrl_i(ctrl_alu_opb_mux_msb_c downto ctrl_alu_opb_mux_lsb_c) is
133
      when "00"   => opb <= rs2_i;
134
      when "01"   => opb <= imm_i;
135
      when others => opb <= rs1_i;
136
    end case;
137 19 zero_gravi
    -- opc (second operand for comparison and SUB) --
138 2 zero_gravi
    if (ctrl_i(ctrl_alu_opc_mux_c) = '0') then
139
      opc <= imm_i;
140
    else
141
      opc <= rs2_i;
142
    end if;
143
  end process input_op_mux;
144
 
145
 
146
  -- Comparator Unit ------------------------------------------------------------------------
147
  -- -------------------------------------------------------------------------------------------
148
  -- less than (x < y) --
149
  cmp_opx  <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i;
150
  cmp_opy  <= (opc(opc'left)     and (not ctrl_i(ctrl_alu_unsigned_c))) & opc;
151
  cmp_sub  <= std_ulogic_vector(signed(cmp_opx) - signed(cmp_opy));
152 9 zero_gravi
  cmp_less <= cmp_sub(cmp_sub'left); -- carry (borrow) indicates a "less"
153 2 zero_gravi
  sub_res  <= cmp_sub(data_width_c-1 downto 0); -- use the less-comparator also for SUB operations
154
 
155
  -- equal (x = y) --
156
  cmp_equal <= '1' when (rs1_i = opc) else '0';
157
 
158
  -- output for branch condition evaluation -
159
  cmp_o(alu_cmp_equal_c) <= cmp_equal;
160
  cmp_o(alu_cmp_less_c)  <= cmp_less;
161
 
162
 
163
  -- Binary Adder ---------------------------------------------------------------------------
164
  -- -------------------------------------------------------------------------------------------
165
  add_res <= std_ulogic_vector(unsigned(opa) + unsigned(opb));
166
  add_o   <= add_res; -- direct output
167
 
168
 
169 23 zero_gravi
  -- Bit Manipulation Unit ------------------------------------------------------------------
170
  -- -------------------------------------------------------------------------------------------
171
 
172
  -- ------------------ --
173
  -- UNDER CONSTRUCTION --
174
  -- ------------------ --
175
 
176
--bitm_minmax <= rs1_i when ((cmp_less xor ???) = '1') else rs2_i; -- min[u] / max[u]
177
 
178
  -- result of bit manipulation operation --
179
  bitm_res <= opa and (not opb); -- ANDN
180
 
181
 
182 2 zero_gravi
  -- Iterative Shifter Unit -----------------------------------------------------------------
183
  -- -------------------------------------------------------------------------------------------
184
  shifter_unit: process(rstn_i, clk_i)
185
  begin
186
    if (rstn_i = '0') then
187 12 zero_gravi
      shifter.sreg   <= (others => '0');
188
      shifter.cnt    <= (others => '0');
189
      shifter.cmd_ff <= '0';
190 2 zero_gravi
    elsif rising_edge(clk_i) then
191 12 zero_gravi
      shifter.cmd_ff <= shifter.cmd;
192
      if (shifter.start = '1') then -- trigger new shift
193
        shifter.sreg <= opa; -- shift operand
194
        shifter.cnt  <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
195
      elsif (shifter.run = '1') then -- running shift
196 23 zero_gravi
        -- coarse shift: multiples of 4 --
197 12 zero_gravi
        if (or_all_f(shifter.cnt(shifter.cnt'left downto 2)) = '1') then -- shift amount >= 4
198
          shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 4);
199
          if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
200
            shifter.sreg <= shifter.sreg(shifter.sreg'left-4 downto 0) & "0000";
201
          else -- SRL: shift right logical / SRA: shift right arithmetical
202
            shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
203
                            (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
204
                            (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
205
                            (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 4);
206
          end if;
207 23 zero_gravi
        -- fine shift: single shifts, 0..3 times --
208 12 zero_gravi
        else
209
          shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 1);
210
          if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
211
            shifter.sreg <= shifter.sreg(shifter.sreg'left-1 downto 0) & '0';
212
          else -- SRL: shift right logical / SRA: shift right arithmetical
213
            shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 1);
214
          end if;
215 2 zero_gravi
        end if;
216
      end if;
217
    end if;
218
  end process shifter_unit;
219
 
220
  -- is shift operation? --
221 19 zero_gravi
  shifter.cmd   <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_shift_c) and (ctrl_i(ctrl_cp_use_c) = '0') else '0';
222 12 zero_gravi
  shifter.start <= '1' when (shifter.cmd = '1') and (shifter.cmd_ff = '0') else '0';
223 2 zero_gravi
 
224
  -- shift operation running? --
225 19 zero_gravi
  shifter.run  <= '1' when (or_all_f(shifter.cnt) = '1') or (shifter.start = '1') else '0';
226
  shifter.halt <= '1' when (or_all_f(shifter.cnt(shifter.cnt'left downto 1)) = '1') or (shifter.start = '1') else '0';
227 2 zero_gravi
 
228
 
229 19 zero_gravi
  -- Coprocessor Arbiter --------------------------------------------------------------------
230 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
231 19 zero_gravi
  cp_arbiter: process(rstn_i, clk_i)
232 2 zero_gravi
  begin
233
    if (rstn_i = '0') then
234 19 zero_gravi
      cp_ctrl.cmd_ff <= '0';
235
      cp_ctrl.busy   <= '0';
236
      cp_ctrl.rb_ff0 <= '0';
237
      cp_ctrl.rb_ff1 <= '0';
238 2 zero_gravi
    elsif rising_edge(clk_i) then
239 19 zero_gravi
      if (CPU_EXTENSION_RISCV_M = true) then
240
        cp_ctrl.cmd_ff <= ctrl_i(ctrl_cp_use_c);
241
        cp_ctrl.rb_ff0 <= '0';
242
        cp_ctrl.rb_ff1 <= cp_ctrl.rb_ff0;
243
        if (cp_ctrl.start = '1') then
244
          cp_ctrl.busy <= '1';
245
        elsif ((cp0_valid_i or cp1_valid_i) = '1') then -- cp computation done?
246
          cp_ctrl.busy   <= '0';
247
          cp_ctrl.rb_ff0 <= '1';
248 2 zero_gravi
        end if;
249 23 zero_gravi
      else -- no co-processor(s) implemented
250 19 zero_gravi
        cp_ctrl.cmd_ff <= '0';
251
        cp_ctrl.busy   <= '0';
252
        cp_ctrl.rb_ff0 <= '0';
253
        cp_ctrl.rb_ff1 <= '0';
254 2 zero_gravi
      end if;
255
    end if;
256 19 zero_gravi
  end process cp_arbiter;
257 2 zero_gravi
 
258
  -- is co-processor operation? --
259 19 zero_gravi
  cp_ctrl.start <= '1' when (ctrl_i(ctrl_cp_use_c) = '1') and (cp_ctrl.cmd_ff = '0') else '0';
260 23 zero_gravi
  cp0_start_o   <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = cp_sel_muldiv_c) else '0'; -- MULDIV CP
261
  cp1_start_o   <= '0'; -- not yet implemented
262 2 zero_gravi
 
263
  -- co-processor operation running? --
264 19 zero_gravi
  cp_ctrl.halt <= cp_ctrl.busy or cp_ctrl.start;
265 2 zero_gravi
 
266
 
267
  -- ALU Function Select --------------------------------------------------------------------
268
  -- -------------------------------------------------------------------------------------------
269 23 zero_gravi
  alu_function_mux: process(ctrl_i, opa, opb, add_res, sub_res, cmp_less, shifter, bitm_res)
270 2 zero_gravi
  begin
271
    case ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) is
272 23 zero_gravi
      when alu_cmd_bitm_c  => alu_res <= bitm_res;
273 2 zero_gravi
      when alu_cmd_xor_c   => alu_res <= opa xor opb;
274 23 zero_gravi
      when alu_cmd_or_c    => alu_res <= opa or  opb;
275 2 zero_gravi
      when alu_cmd_and_c   => alu_res <= opa and opb;
276 9 zero_gravi
      when alu_cmd_sub_c   => alu_res <= sub_res;
277
      when alu_cmd_add_c   => alu_res <= add_res;
278 12 zero_gravi
      when alu_cmd_shift_c => alu_res <= shifter.sreg;
279 2 zero_gravi
      when alu_cmd_slt_c   => alu_res <= (others => '0'); alu_res(0) <= cmp_less;
280 3 zero_gravi
      when others          => alu_res <= (others => '0'); -- undefined
281 2 zero_gravi
    end case;
282
  end process alu_function_mux;
283
 
284
 
285
  -- ALU Result -----------------------------------------------------------------------------
286
  -- -------------------------------------------------------------------------------------------
287 19 zero_gravi
  wait_o <= shifter.halt or cp_ctrl.halt; -- wait until iterative units have completed
288
  res_o  <= (cp0_data_i or cp1_data_i) when (cp_ctrl.rb_ff1 = '1') else alu_res; -- FIXME
289 2 zero_gravi
 
290
 
291
end neorv32_cpu_cpu_rtl;

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