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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_alu.vhd] - Blame information for rev 44

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1 2 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - Arithmetical/Logical Unit >>                                                     #
3
-- # ********************************************************************************************* #
4 20 zero_gravi
-- # Main data and address ALU. Includes comparator unit and co-processor interface/arbiter.       #
5 2 zero_gravi
-- # ********************************************************************************************* #
6
-- # BSD 3-Clause License                                                                          #
7
-- #                                                                                               #
8 44 zero_gravi
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
9 2 zero_gravi
-- #                                                                                               #
10
-- # Redistribution and use in source and binary forms, with or without modification, are          #
11
-- # permitted provided that the following conditions are met:                                     #
12
-- #                                                                                               #
13
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
14
-- #    conditions and the following disclaimer.                                                   #
15
-- #                                                                                               #
16
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
17
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
18
-- #    provided with the distribution.                                                            #
19
-- #                                                                                               #
20
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
21
-- #    endorse or promote products derived from this software without specific prior written      #
22
-- #    permission.                                                                                #
23
-- #                                                                                               #
24
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
25
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
26
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
27
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
28
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
29
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
30
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
31
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
32
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
33
-- # ********************************************************************************************* #
34
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
35
-- #################################################################################################
36
 
37
library ieee;
38
use ieee.std_logic_1164.all;
39
use ieee.numeric_std.all;
40
 
41
library neorv32;
42
use neorv32.neorv32_package.all;
43
 
44
entity neorv32_cpu_alu is
45 11 zero_gravi
  generic (
46 34 zero_gravi
    CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
47
    FAST_SHIFT_EN         : boolean := false -- use barrel shifter for shift operations
48 11 zero_gravi
  );
49 2 zero_gravi
  port (
50
    -- global control --
51
    clk_i       : in  std_ulogic; -- global clock, rising edge
52
    rstn_i      : in  std_ulogic; -- global reset, low-active, async
53
    ctrl_i      : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
54
    -- data input --
55
    rs1_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
56
    rs2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
57
    pc2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
58
    imm_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- immediate
59
    -- data output --
60
    cmp_o       : out std_ulogic_vector(1 downto 0); -- comparator status
61
    res_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
62 36 zero_gravi
    add_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
63 2 zero_gravi
    -- co-processor interface --
64 19 zero_gravi
    cp0_start_o : out std_ulogic; -- trigger co-processor 0
65 2 zero_gravi
    cp0_data_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
66
    cp0_valid_i : in  std_ulogic; -- co-processor 0 result valid
67 19 zero_gravi
    cp1_start_o : out std_ulogic; -- trigger co-processor 1
68 2 zero_gravi
    cp1_data_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result
69
    cp1_valid_i : in  std_ulogic; -- co-processor 1 result valid
70 36 zero_gravi
    cp2_start_o : out std_ulogic; -- trigger co-processor 2
71
    cp2_data_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 2 result
72
    cp2_valid_i : in  std_ulogic; -- co-processor 2 result valid
73
    cp3_start_o : out std_ulogic; -- trigger co-processor 3
74
    cp3_data_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 3 result
75
    cp3_valid_i : in  std_ulogic; -- co-processor 3 result valid
76 2 zero_gravi
    -- status --
77
    wait_o      : out std_ulogic -- busy due to iterative processing units
78
  );
79
end neorv32_cpu_alu;
80
 
81
architecture neorv32_cpu_cpu_rtl of neorv32_cpu_alu is
82
 
83
  -- operands --
84 29 zero_gravi
  signal opa, opb : std_ulogic_vector(data_width_c-1 downto 0);
85 2 zero_gravi
 
86
  -- results --
87 36 zero_gravi
  signal addsub_res : std_ulogic_vector(data_width_c downto 0);
88 39 zero_gravi
  --
89 29 zero_gravi
  signal cp_res     : std_ulogic_vector(data_width_c-1 downto 0);
90 39 zero_gravi
  signal arith_res  : std_ulogic_vector(data_width_c-1 downto 0);
91
  signal logic_res  : std_ulogic_vector(data_width_c-1 downto 0);
92 2 zero_gravi
 
93
  -- comparator --
94 36 zero_gravi
  signal cmp_opx : std_ulogic_vector(data_width_c downto 0);
95
  signal cmp_opy : std_ulogic_vector(data_width_c downto 0);
96
  signal cmp_sub : std_ulogic_vector(data_width_c downto 0);
97 2 zero_gravi
 
98
  -- shifter --
99 12 zero_gravi
  type shifter_t is record
100 34 zero_gravi
    cmd     : std_ulogic;
101
    cmd_ff  : std_ulogic;
102
    start   : std_ulogic;
103
    run     : std_ulogic;
104
    halt    : std_ulogic;
105
    cnt     : std_ulogic_vector(4 downto 0);
106
    sreg    : std_ulogic_vector(data_width_c-1 downto 0);
107
    -- for barrel shifter only --
108
    bs_a_in : std_ulogic_vector(4 downto 0);
109
    bs_d_in : std_ulogic_vector(data_width_c-1 downto 0);
110 12 zero_gravi
  end record;
111
  signal shifter : shifter_t;
112 2 zero_gravi
 
113 19 zero_gravi
  -- co-processor arbiter and interface --
114
  type cp_ctrl_t is record
115 29 zero_gravi
    cmd    : std_ulogic;
116 19 zero_gravi
    cmd_ff : std_ulogic;
117
    busy   : std_ulogic;
118
    start  : std_ulogic;
119
    halt   : std_ulogic;
120
  end record;
121
  signal cp_ctrl : cp_ctrl_t;
122 2 zero_gravi
 
123
begin
124
 
125
  -- Operand Mux ----------------------------------------------------------------------------
126
  -- -------------------------------------------------------------------------------------------
127 36 zero_gravi
  opa <= pc2_i when (ctrl_i(ctrl_alu_opa_mux_c) = '1') else rs1_i; -- operand a (first ALU input operand), only required for arithmetic ops
128 29 zero_gravi
  opb <= imm_i when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else rs2_i; -- operand b (second ALU input operand)
129 2 zero_gravi
 
130
 
131
  -- Comparator Unit ------------------------------------------------------------------------
132
  -- -------------------------------------------------------------------------------------------
133
  cmp_opx  <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i;
134 29 zero_gravi
  cmp_opy  <= (rs2_i(rs2_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs2_i;
135
  cmp_sub  <= std_ulogic_vector(signed(cmp_opx) - signed(cmp_opy)); -- less than (x < y)
136 2 zero_gravi
 
137 29 zero_gravi
  cmp_o(alu_cmp_equal_c) <= '1' when (rs1_i = rs2_i) else '0';
138
  cmp_o(alu_cmp_less_c)  <= cmp_sub(cmp_sub'left); -- less = carry (borrow)
139 2 zero_gravi
 
140
 
141 29 zero_gravi
  -- Binary Adder/Subtractor ----------------------------------------------------------------
142 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
143 29 zero_gravi
  binary_arithmetic_core: process(ctrl_i, opa, opb)
144
    variable cin_v  : std_ulogic_vector(0 downto 0);
145
    variable op_a_v : std_ulogic_vector(data_width_c downto 0);
146
    variable op_b_v : std_ulogic_vector(data_width_c downto 0);
147
    variable op_y_v : std_ulogic_vector(data_width_c downto 0);
148
    variable res_v  : std_ulogic_vector(data_width_c downto 0);
149
  begin
150
    -- operand sign-extension --
151
    op_a_v := (opa(opa'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opa;
152
    op_b_v := (opb(opb'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opb;
153 2 zero_gravi
 
154 29 zero_gravi
    -- add/sub(slt) select --
155
    if (ctrl_i(ctrl_alu_addsub_c) = '1') then -- subtraction
156
      op_y_v   := not op_b_v;
157
      cin_v(0) := '1';
158 36 zero_gravi
    else -- addition
159 29 zero_gravi
      op_y_v   := op_b_v;
160
      cin_v(0) := '0';
161
    end if;
162 2 zero_gravi
 
163 36 zero_gravi
    -- adder core (result + carry/borrow) --
164
    addsub_res <= std_ulogic_vector(unsigned(op_a_v) + unsigned(op_y_v) + unsigned(cin_v(0 downto 0)));
165 29 zero_gravi
  end process binary_arithmetic_core;
166
 
167 36 zero_gravi
  -- direct output of address result --
168
  add_o <= addsub_res(data_width_c-1 downto 0);
169 29 zero_gravi
 
170 39 zero_gravi
  -- ALU arithmetic logic core --
171
  arithmetic_core: process(ctrl_i, addsub_res)
172
  begin
173
    if (ctrl_i(ctrl_alu_arith_c) = alu_arith_cmd_addsub_c) then -- ADD/SUB
174
      arith_res <= addsub_res(data_width_c-1 downto 0);
175
    else -- SLT
176
      arith_res <= (others => '0');
177
      arith_res(0) <= addsub_res(addsub_res'left); -- => carry/borrow
178
    end if;
179
  end process arithmetic_core;
180 36 zero_gravi
 
181 39 zero_gravi
 
182 34 zero_gravi
  -- Shifter Unit ---------------------------------------------------------------------------
183 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
184 36 zero_gravi
  shifter_unit: process(clk_i)
185 34 zero_gravi
    variable bs_input_v   : std_ulogic_vector(data_width_c-1 downto 0);
186
    variable bs_level_4_v : std_ulogic_vector(data_width_c-1 downto 0);
187
    variable bs_level_3_v : std_ulogic_vector(data_width_c-1 downto 0);
188
    variable bs_level_2_v : std_ulogic_vector(data_width_c-1 downto 0);
189
    variable bs_level_1_v : std_ulogic_vector(data_width_c-1 downto 0);
190
    variable bs_level_0_v : std_ulogic_vector(data_width_c-1 downto 0);
191 2 zero_gravi
  begin
192 36 zero_gravi
    if rising_edge(clk_i) then
193 12 zero_gravi
      shifter.cmd_ff <= shifter.cmd;
194 34 zero_gravi
 
195
      -- --------------------------------------------------------------------------------
196
      -- Iterative shifter (small but slow) (default)
197
      -- --------------------------------------------------------------------------------
198
      if (FAST_SHIFT_EN = false) then
199
 
200
        if (shifter.start = '1') then -- trigger new shift
201 36 zero_gravi
          shifter.sreg <= rs1_i; -- shift operand (can only be rs1; opa would also contain pc)
202 34 zero_gravi
          shifter.cnt  <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
203
        elsif (shifter.run = '1') then -- running shift
204
          -- coarse shift: multiples of 4 --
205
          if (or_all_f(shifter.cnt(shifter.cnt'left downto 2)) = '1') then -- shift amount >= 4
206
            shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 4);
207
            if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
208
              shifter.sreg <= shifter.sreg(shifter.sreg'left-4 downto 0) & "0000";
209
            else -- SRL: shift right logical / SRA: shift right arithmetical
210
              shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
211
                              (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
212
                              (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
213
                              (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 4);
214
            end if;
215
          -- fine shift: single shifts, 0..3 times --
216
          else
217
            shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 1);
218
            if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
219
              shifter.sreg <= shifter.sreg(shifter.sreg'left-1 downto 0) & '0';
220
            else -- SRL: shift right logical / SRA: shift right arithmetical
221
              shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 1);
222
            end if;
223 12 zero_gravi
          end if;
224 34 zero_gravi
        end if;
225
 
226
      -- --------------------------------------------------------------------------------
227
      -- Barrel shifter (huge but fast)
228
      -- --------------------------------------------------------------------------------
229
      else
230
 
231
        -- operands and cycle control --
232
        if (shifter.start = '1') then -- trigger new shift
233 36 zero_gravi
          shifter.bs_d_in <= rs1_i; -- shift operand (can only be rs1; opa would also contain pc)
234 34 zero_gravi
          shifter.bs_a_in <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
235
          shifter.cnt     <= (others => '0');
236
        end if;
237
 
238
        -- convert left shifts to right shifts --
239
        if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- is left shift?
240
          bs_input_v := bit_rev_f(shifter.bs_d_in); -- reverse bit order of input operand
241 12 zero_gravi
        else
242 34 zero_gravi
          bs_input_v := shifter.bs_d_in;
243 2 zero_gravi
        end if;
244 34 zero_gravi
        -- shift >> 16 --
245
        if (shifter.bs_a_in(4) = '1') then
246
          bs_level_4_v(31 downto 16) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
247
          bs_level_4_v(15 downto 00) := (bs_input_v(31 downto 16));
248
        else
249
          bs_level_4_v := bs_input_v;
250
        end if;
251
        -- shift >> 8 --
252
        if (shifter.bs_a_in(3) = '1') then
253
          bs_level_3_v(31 downto 24) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
254
          bs_level_3_v(23 downto 00) := (bs_level_4_v(31 downto 8));
255
        else
256
          bs_level_3_v := bs_level_4_v;
257
        end if;
258
        -- shift >> 4 --
259
        if (shifter.bs_a_in(2) = '1') then
260
          bs_level_2_v(31 downto 28) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
261
          bs_level_2_v(27 downto 00) := (bs_level_3_v(31 downto 4));
262
        else
263
          bs_level_2_v := bs_level_3_v;
264
        end if;
265
        -- shift >> 2 --
266
        if (shifter.bs_a_in(1) = '1') then
267
          bs_level_1_v(31 downto 30) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
268
          bs_level_1_v(29 downto 00) := (bs_level_2_v(31 downto 2));
269
        else
270
          bs_level_1_v := bs_level_2_v;
271
        end if;
272
        -- shift >> 1 --
273
        if (shifter.bs_a_in(0) = '1') then
274
          bs_level_0_v(31 downto 31) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
275
          bs_level_0_v(30 downto 00) := (bs_level_1_v(31 downto 1));
276
        else
277
          bs_level_0_v := bs_level_1_v;
278
        end if;
279
        -- re-convert original left shifts --
280
        if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then
281
          shifter.sreg <= bit_rev_f(bs_level_0_v);
282
        else
283
          shifter.sreg <= bs_level_0_v;
284
        end if;
285 2 zero_gravi
      end if;
286
    end if;
287
  end process shifter_unit;
288
 
289
  -- is shift operation? --
290 39 zero_gravi
  shifter.cmd   <= '1' when (ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) = alu_func_cmd_shift_c) else '0';
291 12 zero_gravi
  shifter.start <= '1' when (shifter.cmd = '1') and (shifter.cmd_ff = '0') else '0';
292 2 zero_gravi
 
293
  -- shift operation running? --
294 19 zero_gravi
  shifter.run  <= '1' when (or_all_f(shifter.cnt) = '1') or (shifter.start = '1') else '0';
295
  shifter.halt <= '1' when (or_all_f(shifter.cnt(shifter.cnt'left downto 1)) = '1') or (shifter.start = '1') else '0';
296 2 zero_gravi
 
297
 
298 19 zero_gravi
  -- Coprocessor Arbiter --------------------------------------------------------------------
299 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
300 19 zero_gravi
  cp_arbiter: process(rstn_i, clk_i)
301 2 zero_gravi
  begin
302
    if (rstn_i = '0') then
303 19 zero_gravi
      cp_ctrl.cmd_ff <= '0';
304
      cp_ctrl.busy   <= '0';
305 2 zero_gravi
    elsif rising_edge(clk_i) then
306 40 zero_gravi
      cp_ctrl.cmd_ff <= cp_ctrl.cmd;
307
      if ((cp0_valid_i or cp1_valid_i or cp2_valid_i or cp3_valid_i) = '1') then -- cp computation done?
308
        cp_ctrl.busy <= '0';
309
      elsif (cp_ctrl.start = '1') then
310
        cp_ctrl.busy <= '1';
311 2 zero_gravi
      end if;
312
    end if;
313 19 zero_gravi
  end process cp_arbiter;
314 2 zero_gravi
 
315
  -- is co-processor operation? --
316 39 zero_gravi
  cp_ctrl.cmd   <= '1' when (ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) = alu_func_cmd_copro_c) else '0';
317 29 zero_gravi
  cp_ctrl.start <= '1' when (cp_ctrl.cmd = '1') and (cp_ctrl.cmd_ff = '0') else '0';
318 2 zero_gravi
 
319 39 zero_gravi
  -- co-processor select --
320
  cp0_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "00") else '0';
321
  cp1_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "01") else '0';
322
  cp2_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "10") else '0';
323
  cp3_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "11") else '0';
324 2 zero_gravi
 
325 39 zero_gravi
  -- co-processor operation (still) running? --
326
  cp_ctrl.halt <= (cp_ctrl.busy and (not (cp0_valid_i or cp1_valid_i or cp2_valid_i or cp3_valid_i))) or cp_ctrl.start;
327
 
328 24 zero_gravi
  -- co-processor result --
329 39 zero_gravi
  cp_read_back: process(clk_i)
330
  begin
331
    if rising_edge(clk_i) then
332
      cp_res <= cp0_data_i or cp1_data_i or cp2_data_i or cp3_data_i; -- only the *actually selected* co-processor may output data != 0
333
    end if;
334
  end process cp_read_back;
335 24 zero_gravi
 
336
 
337 39 zero_gravi
  -- ALU Logic Core -------------------------------------------------------------------------
338
  -- -------------------------------------------------------------------------------------------
339
  alu_logic_core: process(ctrl_i, rs1_i, opb)
340
  begin
341
    case ctrl_i(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) is
342
      when alu_logic_cmd_movb_c => logic_res <= opb; -- (default)
343
      when alu_logic_cmd_xor_c  => logic_res <= rs1_i xor opb; -- only rs1 required for logic ops (opa would also contain pc)
344
      when alu_logic_cmd_or_c   => logic_res <= rs1_i or  opb;
345
      when alu_logic_cmd_and_c  => logic_res <= rs1_i and opb;
346
      when others               => logic_res <= opb; -- undefined
347
    end case;
348
  end process alu_logic_core;
349
 
350
 
351 2 zero_gravi
  -- ALU Function Select --------------------------------------------------------------------
352
  -- -------------------------------------------------------------------------------------------
353 39 zero_gravi
  alu_function_mux: process(ctrl_i, arith_res, logic_res, shifter.sreg, cp_res)
354 2 zero_gravi
  begin
355 39 zero_gravi
    case ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) is
356
      when alu_func_cmd_arith_c => res_o <= arith_res; -- (default)
357
      when alu_func_cmd_logic_c => res_o <= logic_res;
358
      when alu_func_cmd_shift_c => res_o <= shifter.sreg;
359
      when alu_func_cmd_copro_c => res_o <= cp_res;
360
      when others               => res_o <= arith_res; -- undefined
361 2 zero_gravi
    end case;
362
  end process alu_function_mux;
363
 
364
 
365 29 zero_gravi
  -- ALU Busy -------------------------------------------------------------------------------
366 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
367 19 zero_gravi
  wait_o <= shifter.halt or cp_ctrl.halt; -- wait until iterative units have completed
368 2 zero_gravi
 
369
 
370
end neorv32_cpu_cpu_rtl;

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