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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_alu.vhd] - Blame information for rev 68

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1 2 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - Arithmetical/Logical Unit >>                                                     #
3
-- # ********************************************************************************************* #
4 47 zero_gravi
-- # Main data and address ALU and co-processor interface/arbiter.                                 #
5 2 zero_gravi
-- # ********************************************************************************************* #
6
-- # BSD 3-Clause License                                                                          #
7
-- #                                                                                               #
8 44 zero_gravi
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
9 2 zero_gravi
-- #                                                                                               #
10
-- # Redistribution and use in source and binary forms, with or without modification, are          #
11
-- # permitted provided that the following conditions are met:                                     #
12
-- #                                                                                               #
13
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
14
-- #    conditions and the following disclaimer.                                                   #
15
-- #                                                                                               #
16
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
17
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
18
-- #    provided with the distribution.                                                            #
19
-- #                                                                                               #
20
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
21
-- #    endorse or promote products derived from this software without specific prior written      #
22
-- #    permission.                                                                                #
23
-- #                                                                                               #
24
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
25
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
26
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
27
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
28
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
29
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
30
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
31
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
32
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
33
-- # ********************************************************************************************* #
34
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
35
-- #################################################################################################
36
 
37
library ieee;
38
use ieee.std_logic_1164.all;
39
use ieee.numeric_std.all;
40
 
41
library neorv32;
42
use neorv32.neorv32_package.all;
43
 
44
entity neorv32_cpu_alu is
45 11 zero_gravi
  generic (
46 61 zero_gravi
    -- RISC-V CPU Extensions --
47 66 zero_gravi
    CPU_EXTENSION_RISCV_B     : boolean; -- implement bit-manipulation extension?
48 62 zero_gravi
    CPU_EXTENSION_RISCV_M     : boolean; -- implement mul/div extension?
49
    CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
50
    CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
51 61 zero_gravi
    -- Extension Options --
52 62 zero_gravi
    FAST_MUL_EN               : boolean; -- use DSPs for M extension's multiplier
53
    FAST_SHIFT_EN             : boolean  -- use barrel shifter for shift operations
54 11 zero_gravi
  );
55 2 zero_gravi
  port (
56
    -- global control --
57
    clk_i       : in  std_ulogic; -- global clock, rising edge
58
    rstn_i      : in  std_ulogic; -- global reset, low-active, async
59
    ctrl_i      : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
60
    -- data input --
61
    rs1_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
62
    rs2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
63 68 zero_gravi
    pc_i        : in  std_ulogic_vector(data_width_c-1 downto 0); -- current PC
64
    pc2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- next PC
65 2 zero_gravi
    imm_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- immediate
66 61 zero_gravi
    csr_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
67 2 zero_gravi
    -- data output --
68 65 zero_gravi
    cmp_o       : out std_ulogic_vector(1 downto 0); -- comparator status
69 2 zero_gravi
    res_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
70 36 zero_gravi
    add_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
71 61 zero_gravi
    fpu_flags_o : out std_ulogic_vector(4 downto 0); -- FPU exception flags
72 2 zero_gravi
    -- status --
73 61 zero_gravi
    idone_o     : out std_ulogic -- iterative processing units done?
74 2 zero_gravi
  );
75
end neorv32_cpu_alu;
76
 
77
architecture neorv32_cpu_cpu_rtl of neorv32_cpu_alu is
78
 
79 65 zero_gravi
  -- comparator --
80
  signal cmp_opx : std_ulogic_vector(data_width_c downto 0);
81
  signal cmp_opy : std_ulogic_vector(data_width_c downto 0);
82
  signal cmp     : std_ulogic_vector(1 downto 0); -- comparator status
83
 
84 2 zero_gravi
  -- operands --
85 29 zero_gravi
  signal opa, opb : std_ulogic_vector(data_width_c-1 downto 0);
86 2 zero_gravi
 
87
  -- results --
88 36 zero_gravi
  signal addsub_res : std_ulogic_vector(data_width_c downto 0);
89 68 zero_gravi
  signal alu_res    : std_ulogic_vector(data_width_c-1 downto 0);
90 29 zero_gravi
  signal cp_res     : std_ulogic_vector(data_width_c-1 downto 0);
91 2 zero_gravi
 
92 19 zero_gravi
  -- co-processor arbiter and interface --
93
  type cp_ctrl_t is record
94 55 zero_gravi
    cmd     : std_ulogic;
95
    cmd_ff  : std_ulogic;
96 61 zero_gravi
    start   : std_ulogic;
97 55 zero_gravi
    busy    : std_ulogic;
98
    timeout : std_ulogic_vector(9 downto 0);
99 19 zero_gravi
  end record;
100
  signal cp_ctrl : cp_ctrl_t;
101 2 zero_gravi
 
102 61 zero_gravi
  -- co-processor interface --
103
  signal cp_start  : std_ulogic_vector(3 downto 0); -- trigger co-processor i
104
  signal cp_valid  : std_ulogic_vector(3 downto 0); -- co-processor i done
105
  signal cp_result : cp_data_if_t; -- co-processor result
106
 
107 2 zero_gravi
begin
108
 
109 65 zero_gravi
  -- Comparator Unit (for conditional branches) ---------------------------------------------
110 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
111 65 zero_gravi
  cmp_opx <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i;
112
  cmp_opy <= (rs2_i(rs2_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs2_i;
113
 
114
  cmp(cmp_equal_c) <= '1' when (rs1_i = rs2_i) else '0';
115
  cmp(cmp_less_c)  <= '1' when (signed(cmp_opx) < signed(cmp_opy)) else '0';
116
  cmp_o            <= cmp;
117
 
118
 
119
  -- ALU Input Operand Mux ------------------------------------------------------------------
120
  -- -------------------------------------------------------------------------------------------
121 68 zero_gravi
  opa <= pc_i  when (ctrl_i(ctrl_alu_opa_mux_c) = '1') else rs1_i; -- operand a (first ALU input operand), only required for arithmetic ops
122 29 zero_gravi
  opb <= imm_i when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else rs2_i; -- operand b (second ALU input operand)
123 2 zero_gravi
 
124
 
125 61 zero_gravi
  -- Binary Adder/Subtracter ----------------------------------------------------------------
126 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
127 29 zero_gravi
  binary_arithmetic_core: process(ctrl_i, opa, opb)
128
    variable cin_v  : std_ulogic_vector(0 downto 0);
129
    variable op_a_v : std_ulogic_vector(data_width_c downto 0);
130
    variable op_b_v : std_ulogic_vector(data_width_c downto 0);
131
    variable op_y_v : std_ulogic_vector(data_width_c downto 0);
132
    variable res_v  : std_ulogic_vector(data_width_c downto 0);
133
  begin
134
    -- operand sign-extension --
135
    op_a_v := (opa(opa'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opa;
136
    op_b_v := (opb(opb'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opb;
137
    -- add/sub(slt) select --
138 68 zero_gravi
    if (ctrl_i(ctrl_alu_op0_c) = '1') then -- subtraction
139 29 zero_gravi
      op_y_v   := not op_b_v;
140
      cin_v(0) := '1';
141 36 zero_gravi
    else -- addition
142 29 zero_gravi
      op_y_v   := op_b_v;
143
      cin_v(0) := '0';
144
    end if;
145 68 zero_gravi
    -- adder core --
146 36 zero_gravi
    addsub_res <= std_ulogic_vector(unsigned(op_a_v) + unsigned(op_y_v) + unsigned(cin_v(0 downto 0)));
147 29 zero_gravi
  end process binary_arithmetic_core;
148
 
149 68 zero_gravi
  -- direct output of adder result --
150 36 zero_gravi
  add_o <= addsub_res(data_width_c-1 downto 0);
151 29 zero_gravi
 
152 68 zero_gravi
 
153
  -- ALU Operation Select -------------------------------------------------------------------
154
  -- -------------------------------------------------------------------------------------------
155
  alu_core: process(ctrl_i, addsub_res, rs1_i, opb)
156 39 zero_gravi
  begin
157 68 zero_gravi
    case ctrl_i(ctrl_alu_op2_c downto ctrl_alu_op0_c) is
158
      when alu_op_add_c  => alu_res <= addsub_res(data_width_c-1 downto 0); -- (default)
159
      when alu_op_sub_c  => alu_res <= addsub_res(data_width_c-1 downto 0);
160
--    when alu_op_mova_c => alu_res <= rs1_i; -- FIXME
161
      when alu_op_slt_c  => alu_res <= (others => '0'); alu_res(0) <= addsub_res(addsub_res'left); -- => carry/borrow
162
      when alu_op_movb_c => alu_res <= opb;
163
      when alu_op_xor_c  => alu_res <= rs1_i xor opb; -- only rs1 required for logic ops (opa would also contain pc)
164
      when alu_op_or_c   => alu_res <= rs1_i or  opb;
165
      when alu_op_and_c  => alu_res <= rs1_i and opb;
166
      when others        => alu_res <= addsub_res(data_width_c-1 downto 0);
167
    end case;
168
  end process alu_core;
169 36 zero_gravi
 
170 68 zero_gravi
  -- ALU Function Select --------------------------------------------------------------------
171
  -- -------------------------------------------------------------------------------------------
172
  alu_function_mux: process(ctrl_i, alu_res, pc2_i, csr_i, cp_res)
173
  begin
174
    case ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) is
175
      when alu_func_core_c  => res_o <= alu_res; -- (default)
176
      when alu_func_nxpc_c  => res_o <= pc2_i;
177
      when alu_func_csrr_c  => res_o <= csr_i;
178
      when alu_func_copro_c => res_o <= cp_res;
179
      when others           => res_o <= alu_res; -- undefined
180
    end case;
181
  end process alu_function_mux;
182 39 zero_gravi
 
183 68 zero_gravi
 
184
  -- **************************************************************************************************************************
185
  -- Co-Processors
186
  -- **************************************************************************************************************************
187
 
188 47 zero_gravi
  -- Co-Processor Arbiter -------------------------------------------------------------------
189 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
190 47 zero_gravi
  -- Interface:
191
  -- Co-processor "valid" signal has to be asserted (for one cycle) one cycle before asserting output data
192
  -- Co-processor "output data" has to be always zero unless co-processor was explicitly triggered
193 19 zero_gravi
  cp_arbiter: process(rstn_i, clk_i)
194 2 zero_gravi
  begin
195
    if (rstn_i = '0') then
196 55 zero_gravi
      cp_ctrl.cmd_ff  <= '0';
197
      cp_ctrl.busy    <= '0';
198
      cp_ctrl.timeout <= (others => '0');
199 2 zero_gravi
    elsif rising_edge(clk_i) then
200 40 zero_gravi
      cp_ctrl.cmd_ff <= cp_ctrl.cmd;
201 61 zero_gravi
      -- timeout counter --
202
      if (cp_ctrl.start = '1') then
203
        cp_ctrl.busy <= '1';
204
      elsif (or_reduce_f(cp_valid) = '1') then
205 40 zero_gravi
        cp_ctrl.busy <= '0';
206 2 zero_gravi
      end if;
207 55 zero_gravi
      if (cp_ctrl.busy = '1') and (cp_timeout_en_c = true) then
208
        cp_ctrl.timeout <= std_ulogic_vector(unsigned(cp_ctrl.timeout) + 1);
209
      else
210
        cp_ctrl.timeout <= (others => '0');
211
      end if;
212 61 zero_gravi
      if (cp_ctrl.timeout(cp_ctrl.timeout'left) = '1') and (cp_timeout_en_c = true) then -- timeout
213
        assert false report "NEORV32 CPU CO-PROCESSOR TIMEOUT ERROR!" severity warning;
214
      end if;
215 2 zero_gravi
    end if;
216 19 zero_gravi
  end process cp_arbiter;
217 2 zero_gravi
 
218
  -- is co-processor operation? --
219 68 zero_gravi
  cp_ctrl.cmd   <= '1' when (ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) = alu_func_copro_c) else '0';
220 29 zero_gravi
  cp_ctrl.start <= '1' when (cp_ctrl.cmd = '1') and (cp_ctrl.cmd_ff = '0') else '0';
221 2 zero_gravi
 
222 61 zero_gravi
  -- co-processor select / star trigger --
223
  cp_start(0) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "00") else '0';
224
  cp_start(1) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "01") else '0';
225
  cp_start(2) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "10") else '0';
226
  cp_start(3) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "11") else '0';
227 2 zero_gravi
 
228 61 zero_gravi
  -- co-processor operation done? --
229
  idone_o <= or_reduce_f(cp_valid);
230 39 zero_gravi
 
231 49 zero_gravi
  -- co-processor result - only the *actually selected* co-processor may output data != 0 --
232 61 zero_gravi
  cp_res <= cp_result(0) or cp_result(1) or cp_result(2) or cp_result(3);
233 24 zero_gravi
 
234
 
235 61 zero_gravi
  -- Co-Processor 0: Shifter (CPU Core ISA) --------------------------------------------------
236 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
237 65 zero_gravi
  neorv32_cpu_cp_shifter_inst: neorv32_cpu_cp_shifter
238
  generic map (
239
    FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
240
  )
241
  port map (
242
    -- global control --
243
    clk_i   => clk_i,           -- global clock, rising edge
244
    rstn_i  => rstn_i,          -- global reset, low-active, async
245
    ctrl_i  => ctrl_i,          -- main control bus
246
    start_i => cp_start(0),     -- trigger operation
247
    -- data input --
248
    rs1_i   => rs1_i,           -- rf source 1
249 66 zero_gravi
    shamt_i => opb(index_size_f(data_width_c)-1 downto 0), -- shift amount
250 65 zero_gravi
    -- result and status --
251
    res_o   => cp_result(0),    -- operation result
252
    valid_o => cp_valid(0)      -- data output valid
253
  );
254 2 zero_gravi
 
255
 
256 61 zero_gravi
  -- Co-Processor 1: Integer Multiplication/Division ('M' Extension) ------------------------
257
  -- -------------------------------------------------------------------------------------------
258
  neorv32_cpu_cp_muldiv_inst_true:
259
  if (CPU_EXTENSION_RISCV_M = true) or (CPU_EXTENSION_RISCV_Zmmul = true) generate
260
    neorv32_cpu_cp_muldiv_inst: neorv32_cpu_cp_muldiv
261
    generic map (
262
      FAST_MUL_EN => FAST_MUL_EN,          -- use DSPs for faster multiplication
263
      DIVISION_EN => CPU_EXTENSION_RISCV_M -- implement divider hardware
264
    )
265
    port map (
266
      -- global control --
267 66 zero_gravi
      clk_i   => clk_i,         -- global clock, rising edge
268
      rstn_i  => rstn_i,        -- global reset, low-active, async
269
      ctrl_i  => ctrl_i,        -- main control bus
270
      start_i => cp_start(1),   -- trigger operation
271 61 zero_gravi
      -- data input --
272 66 zero_gravi
      rs1_i   => rs1_i,         -- rf source 1
273
      rs2_i   => rs2_i,         -- rf source 2
274 61 zero_gravi
      -- result and status --
275 66 zero_gravi
      res_o   => cp_result(1),  -- operation result
276
      valid_o => cp_valid(1)    -- data output valid
277 61 zero_gravi
    );
278
  end generate;
279
 
280
  neorv32_cpu_cp_muldiv_inst_false:
281
  if (CPU_EXTENSION_RISCV_M = false) and (CPU_EXTENSION_RISCV_Zmmul = false) generate
282
    cp_result(1) <= (others => '0');
283
    cp_valid(1)  <= cp_start(1); -- to make sure CPU does not get stalled if there is an accidental access
284
  end generate;
285
 
286
 
287 66 zero_gravi
  -- Co-Processor 2: Bit-Manipulation Unit ('B' Extension) ----------------------------------
288 61 zero_gravi
  -- -------------------------------------------------------------------------------------------
289 63 zero_gravi
  neorv32_cpu_cp_bitmanip_inst_true:
290 66 zero_gravi
  if (CPU_EXTENSION_RISCV_B = true) generate
291 63 zero_gravi
    neorv32_cpu_cp_bitmanip_inst: neorv32_cpu_cp_bitmanip
292
    generic map (
293
      FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
294
    )
295
    port map (
296
      -- global control --
297 66 zero_gravi
      clk_i   => clk_i,        -- global clock, rising edge
298
      rstn_i  => rstn_i,       -- global reset, low-active, async
299
      ctrl_i  => ctrl_i,       -- main control bus
300
      start_i => cp_start(2),  -- trigger operation
301 63 zero_gravi
      -- data input --
302 66 zero_gravi
      cmp_i   => cmp,          -- comparator status
303
      rs1_i   => rs1_i,        -- rf source 1
304
      rs2_i   => rs2_i,        -- rf source 2
305
      shamt_i => opb(index_size_f(data_width_c)-1 downto 0), -- shift amount
306 63 zero_gravi
      -- result and status --
307 66 zero_gravi
      res_o   => cp_result(2), -- operation result
308
      valid_o => cp_valid(2)   -- data output valid
309 63 zero_gravi
    );
310
  end generate;
311 61 zero_gravi
 
312 63 zero_gravi
  neorv32_cpu_cp_bitmanip_inst_false:
313 66 zero_gravi
  if (CPU_EXTENSION_RISCV_B = false) generate
314 63 zero_gravi
    cp_result(2) <= (others => '0');
315
    cp_valid(2)  <= cp_start(2); -- to make sure CPU does not get stalled if there is an accidental access
316
  end generate;
317 61 zero_gravi
 
318 63 zero_gravi
 
319 61 zero_gravi
  -- Co-Processor 3: Single-Precision Floating-Point Unit ('Zfinx' Extension) ---------------
320
  -- -------------------------------------------------------------------------------------------
321
  neorv32_cpu_cp_fpu_inst_true:
322
  if (CPU_EXTENSION_RISCV_Zfinx = true) generate
323
    neorv32_cpu_cp_fpu_inst: neorv32_cpu_cp_fpu
324
    port map (
325
      -- global control --
326 66 zero_gravi
      clk_i    => clk_i,        -- global clock, rising edge  
327 61 zero_gravi
      rstn_i   => rstn_i,       -- global reset, low-active, async
328
      ctrl_i   => ctrl_i,       -- main control bus
329
      start_i  => cp_start(3),  -- trigger operation
330
      -- data input --
331 65 zero_gravi
      cmp_i    => cmp,          -- comparator status
332 61 zero_gravi
      rs1_i    => rs1_i,        -- rf source 1
333
      rs2_i    => rs2_i,        -- rf source 2
334
      -- result and status --
335
      res_o    => cp_result(3), -- operation result
336
      fflags_o => fpu_flags_o,  -- exception flags
337
      valid_o  => cp_valid(3)   -- data output valid
338
    );
339
  end generate;
340
 
341
  neorv32_cpu_cp_fpu_inst_false:
342
  if (CPU_EXTENSION_RISCV_Zfinx = false) generate
343
    cp_result(3) <= (others => '0');
344
    fpu_flags_o  <= (others => '0');
345
    cp_valid(3)  <= cp_start(3); -- to make sure CPU does not get stalled if there is an accidental access
346
  end generate;
347
 
348
 
349 2 zero_gravi
end neorv32_cpu_cpu_rtl;

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