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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_bus.vhd] - Blame information for rev 37

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1 2 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - Bus Interface Unit >>                                                            #
3
-- # ********************************************************************************************* #
4 18 zero_gravi
-- # Instruction and data bus interfaces and physical memory protection (PMP).                     #
5 2 zero_gravi
-- # ********************************************************************************************* #
6
-- # BSD 3-Clause License                                                                          #
7
-- #                                                                                               #
8
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
9
-- #                                                                                               #
10
-- # Redistribution and use in source and binary forms, with or without modification, are          #
11
-- # permitted provided that the following conditions are met:                                     #
12
-- #                                                                                               #
13
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
14
-- #    conditions and the following disclaimer.                                                   #
15
-- #                                                                                               #
16
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
17
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
18
-- #    provided with the distribution.                                                            #
19
-- #                                                                                               #
20
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
21
-- #    endorse or promote products derived from this software without specific prior written      #
22
-- #    permission.                                                                                #
23
-- #                                                                                               #
24
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
25
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
26
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
27
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
28
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
29
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
30
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
31
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
32
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
33
-- # ********************************************************************************************* #
34
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
35
-- #################################################################################################
36
 
37
library ieee;
38
use ieee.std_logic_1164.all;
39
use ieee.numeric_std.all;
40
 
41
library neorv32;
42
use neorv32.neorv32_package.all;
43
 
44
entity neorv32_cpu_bus is
45
  generic (
46 11 zero_gravi
    CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
47 15 zero_gravi
    -- Physical memory protection (PMP) --
48
    PMP_USE               : boolean := false; -- implement physical memory protection?
49
    PMP_NUM_REGIONS       : natural := 4; -- number of regions (1..4)
50 18 zero_gravi
    PMP_GRANULARITY       : natural := 16 -- granularity (1=8B, 2=16B, 3=32B, ...)
51 2 zero_gravi
  );
52
  port (
53
    -- global control --
54 12 zero_gravi
    clk_i          : in  std_ulogic; -- global clock, rising edge
55
    ctrl_i         : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
56
    -- cpu instruction fetch interface --
57
    fetch_pc_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
58
    instr_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
59
    i_wait_o       : out std_ulogic; -- wait for fetch to complete
60
    --
61
    ma_instr_o     : out std_ulogic; -- misaligned instruction address
62
    be_instr_o     : out std_ulogic; -- bus error on instruction access
63
    -- cpu data access interface --
64
    addr_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
65
    wdata_i        : in  std_ulogic_vector(data_width_c-1 downto 0); -- write data
66
    rdata_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
67
    mar_o          : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
68
    d_wait_o       : out std_ulogic; -- wait for access to complete
69
    --
70
    ma_load_o      : out std_ulogic; -- misaligned load data address
71
    ma_store_o     : out std_ulogic; -- misaligned store data address
72
    be_load_o      : out std_ulogic; -- bus error on load data access
73
    be_store_o     : out std_ulogic; -- bus error on store data access
74 15 zero_gravi
    -- physical memory protection --
75
    pmp_addr_i     : in  pmp_addr_if_t; -- addresses
76
    pmp_ctrl_i     : in  pmp_ctrl_if_t; -- configs
77 12 zero_gravi
    -- instruction bus --
78
    i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
79
    i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
80
    i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
81
    i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
82
    i_bus_we_o     : out std_ulogic; -- write enable
83
    i_bus_re_o     : out std_ulogic; -- read enable
84
    i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
85
    i_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
86
    i_bus_err_i    : in  std_ulogic; -- bus transfer error
87
    i_bus_fence_o  : out std_ulogic; -- fence operation
88
    -- data bus --
89
    d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
90
    d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
91
    d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
92
    d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
93
    d_bus_we_o     : out std_ulogic; -- write enable
94
    d_bus_re_o     : out std_ulogic; -- read enable
95
    d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
96
    d_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
97
    d_bus_err_i    : in  std_ulogic; -- bus transfer error
98
    d_bus_fence_o  : out std_ulogic  -- fence operation
99 2 zero_gravi
  );
100
end neorv32_cpu_bus;
101
 
102
architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
103
 
104 15 zero_gravi
  -- PMP modes --
105
  constant pmp_off_mode_c   : std_ulogic_vector(1 downto 0) := "00"; -- null region (disabled)
106 36 zero_gravi
--constant pmp_tor_mode_c   : std_ulogic_vector(1 downto 0) := "01"; -- top of range
107
--constant pmp_na4_mode_c   : std_ulogic_vector(1 downto 0) := "10"; -- naturally aligned four-byte region
108 15 zero_gravi
  constant pmp_napot_mode_c : std_ulogic_vector(1 downto 0) := "11"; -- naturally aligned power-of-two region (>= 8 bytes)
109
 
110
  -- PMP configuration register bits --
111
  constant pmp_cfg_r_c  : natural := 0; -- read permit
112
  constant pmp_cfg_w_c  : natural := 1; -- write permit
113
  constant pmp_cfg_x_c  : natural := 2; -- execute permit
114
  constant pmp_cfg_al_c : natural := 3; -- mode bit low
115
  constant pmp_cfg_ah_c : natural := 4; -- mode bit high
116
  constant pmp_cfg_l_c  : natural := 7; -- locked entry
117
 
118 12 zero_gravi
  -- data interface registers --
119 2 zero_gravi
  signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0);
120
 
121 12 zero_gravi
  -- data access --
122
  signal d_bus_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- write data
123
  signal d_bus_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- read data
124
  signal d_bus_ben   : std_ulogic_vector(3 downto 0); -- write data byte enable
125 2 zero_gravi
 
126
  -- misaligned access? --
127 12 zero_gravi
  signal d_misaligned, i_misaligned : std_ulogic;
128 2 zero_gravi
 
129 12 zero_gravi
  -- bus arbiter --
130
  type bus_arbiter_t is record
131
    rd_req    : std_ulogic; -- read access in progress
132
    wr_req    : std_ulogic; -- write access in progress
133
    err_align : std_ulogic; -- alignment error
134
    err_bus   : std_ulogic; -- bus access error
135 30 zero_gravi
    timeout   : std_ulogic_vector(index_size_f(bus_timeout_c)-1 downto 0);
136 12 zero_gravi
  end record;
137
  signal i_arbiter, d_arbiter : bus_arbiter_t;
138
 
139 15 zero_gravi
  -- physical memory protection --
140
  type pmp_addr34_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c+1 downto 0);
141 16 zero_gravi
  type pmp_addr_t   is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
142 15 zero_gravi
  type pmp_t is record
143 16 zero_gravi
    addr_mask     : pmp_addr34_t; -- 34-bit physical address
144
    region_base   : pmp_addr_t; -- masked region base address for comparator
145
    region_i_addr : pmp_addr_t; -- masked instruction access base address for comparator
146
    region_d_addr : pmp_addr_t; -- masked data access base address for comparator
147
    i_match       : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for instruction interface
148
    d_match       : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for data interface
149
    if_fault      : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for fetch operation
150
    ld_fault      : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for load operation
151
    st_fault      : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for store operation
152 15 zero_gravi
  end record;
153
  signal pmp : pmp_t;
154
 
155
  -- pmp faults anybody? --
156
  signal if_pmp_fault : std_ulogic; -- pmp instruction access fault
157
  signal ld_pmp_fault : std_ulogic; -- pmp load access fault
158
  signal st_pmp_fault : std_ulogic; -- pmp store access fault
159
 
160 2 zero_gravi
begin
161
 
162 12 zero_gravi
  -- Data Interface: Access Address ---------------------------------------------------------
163 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
164 36 zero_gravi
  mem_adr_reg: process(clk_i)
165 2 zero_gravi
  begin
166 11 zero_gravi
    if rising_edge(clk_i) then
167 2 zero_gravi
      if (ctrl_i(ctrl_bus_mar_we_c) = '1') then
168 12 zero_gravi
        mar <= addr_i;
169 2 zero_gravi
      end if;
170
    end if;
171
  end process mem_adr_reg;
172
 
173 12 zero_gravi
  -- read-back for exception controller --
174
  mar_o <= mar;
175 2 zero_gravi
 
176 12 zero_gravi
  -- alignment check --
177
  misaligned_d_check: process(mar, ctrl_i)
178
  begin
179
    -- check data access --
180
    d_misaligned <= '0'; -- default
181
    case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
182
      when "00" => -- byte
183
        d_misaligned <= '0';
184
      when "01" => -- half-word
185
        if (mar(0) /= '0') then
186
          d_misaligned <= '1';
187
        end if;
188
      when others => -- word
189
        if (mar(1 downto 0) /= "00") then
190
          d_misaligned <= '1';
191
        end if;
192
    end case;
193
  end process misaligned_d_check;
194 2 zero_gravi
 
195
 
196 12 zero_gravi
  -- Data Interface: Write Data -------------------------------------------------------------
197 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
198
  mem_do_reg: process(clk_i)
199
  begin
200
    if rising_edge(clk_i) then
201
      if (ctrl_i(ctrl_bus_mdo_we_c) = '1') then
202 36 zero_gravi
        mdo <= wdata_i; -- memory data out register (MDO)
203 2 zero_gravi
      end if;
204
    end if;
205
  end process mem_do_reg;
206
 
207
  -- byte enable and output data alignment --
208
  byte_enable: process(mar, mdo, ctrl_i)
209
  begin
210
    case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
211
      when "00" => -- byte
212 12 zero_gravi
        d_bus_wdata(07 downto 00) <= mdo(07 downto 00);
213
        d_bus_wdata(15 downto 08) <= mdo(07 downto 00);
214
        d_bus_wdata(23 downto 16) <= mdo(07 downto 00);
215
        d_bus_wdata(31 downto 24) <= mdo(07 downto 00);
216 36 zero_gravi
        case mar(1 downto 0) is
217
          when "00"   => d_bus_ben <= "0001";
218
          when "01"   => d_bus_ben <= "0010";
219
          when "10"   => d_bus_ben <= "0100";
220
          when others => d_bus_ben <= "1000";
221
        end case;
222 2 zero_gravi
      when "01" => -- half-word
223 12 zero_gravi
        d_bus_wdata(31 downto 16) <= mdo(15 downto 00);
224
        d_bus_wdata(15 downto 00) <= mdo(15 downto 00);
225 2 zero_gravi
        if (mar(1) = '0') then
226 12 zero_gravi
          d_bus_ben <= "0011"; -- low half-word
227 2 zero_gravi
        else
228 12 zero_gravi
          d_bus_ben <= "1100"; -- high half-word
229 2 zero_gravi
        end if;
230
      when others => -- word
231 12 zero_gravi
        d_bus_wdata <= mdo;
232
        d_bus_ben   <= "1111"; -- full word
233 2 zero_gravi
    end case;
234
  end process byte_enable;
235
 
236
 
237 12 zero_gravi
  -- Data Interface: Read Data --------------------------------------------------------------
238 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
239
  mem_out_buf: process(clk_i)
240
  begin
241
    if rising_edge(clk_i) then
242
      if (ctrl_i(ctrl_bus_mdi_we_c) = '1') then
243 36 zero_gravi
        mdi <= d_bus_rdata; -- memory data in register (MDI)
244 2 zero_gravi
      end if;
245
    end if;
246
  end process mem_out_buf;
247
 
248 12 zero_gravi
  -- input data alignment and sign extension --
249 2 zero_gravi
  read_align: process(mdi, mar, ctrl_i)
250 36 zero_gravi
    variable byte_in_v  : std_ulogic_vector(07 downto 0);
251
    variable hword_in_v : std_ulogic_vector(15 downto 0);
252 2 zero_gravi
  begin
253 36 zero_gravi
    -- sub-word input --
254
    case mar(1 downto 0) is
255
      when "00"   => byte_in_v := mdi(07 downto 00); hword_in_v := mdi(15 downto 00); -- byte 0 / half-word 0
256
      when "01"   => byte_in_v := mdi(15 downto 08); hword_in_v := mdi(15 downto 00); -- byte 1 / half-word 0
257
      when "10"   => byte_in_v := mdi(23 downto 16); hword_in_v := mdi(31 downto 16); -- byte 2 / half-word 1
258
      when others => byte_in_v := mdi(31 downto 24); hword_in_v := mdi(31 downto 16); -- byte 3 / half-word 1
259
    end case;
260
    -- actual data size --
261
    case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is
262 2 zero_gravi
      when "00" => -- byte
263 36 zero_gravi
        rdata_o(31 downto 08) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and byte_in_v(7))); -- sign extension
264
        rdata_o(07 downto 00) <= byte_in_v;
265 2 zero_gravi
      when "01" => -- half-word
266 36 zero_gravi
        rdata_o(31 downto 16) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and hword_in_v(15))); -- sign extension
267
        rdata_o(15 downto 00) <= hword_in_v; -- high half-word
268 2 zero_gravi
      when others => -- word
269
        rdata_o <= mdi; -- full word
270
    end case;
271
  end process read_align;
272
 
273
 
274 12 zero_gravi
  -- Instruction Interface: Check for Misaligned Access -------------------------------------
275 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
276 12 zero_gravi
  misaligned_i_check: process(ctrl_i, fetch_pc_i)
277 2 zero_gravi
  begin
278 12 zero_gravi
    -- check instruction access --
279
    i_misaligned <= '0'; -- default
280
    if (CPU_EXTENSION_RISCV_C = true) then -- 16-bit and 32-bit instruction accesses
281
      i_misaligned <= '0'; -- no alignment exceptions possible
282
    else -- 32-bit instruction accesses only
283
      if (fetch_pc_i(1) = '1') then -- PC(0) is always zero
284
        i_misaligned <= '1';
285
      end if;
286
    end if;
287
  end process misaligned_i_check;
288
 
289
 
290
  -- Instruction Fetch Arbiter --------------------------------------------------------------
291
  -- -------------------------------------------------------------------------------------------
292 36 zero_gravi
  ifetch_arbiter: process(clk_i)
293 12 zero_gravi
  begin
294 36 zero_gravi
    if rising_edge(clk_i) then
295 12 zero_gravi
      -- instruction fetch request --
296
      if (i_arbiter.rd_req = '0') then -- idle
297
        i_arbiter.rd_req    <= ctrl_i(ctrl_bus_if_c);
298
        i_arbiter.err_align <= i_misaligned;
299
        i_arbiter.err_bus   <= '0';
300 30 zero_gravi
        i_arbiter.timeout   <= std_ulogic_vector(to_unsigned(bus_timeout_c, index_size_f(bus_timeout_c)));
301 12 zero_gravi
      else -- in progress
302
        i_arbiter.timeout   <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1);
303
        i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned)                                     and (not ctrl_i(ctrl_bus_ierr_ack_c));
304
        i_arbiter.err_bus   <= (i_arbiter.err_bus   or (not or_all_f(i_arbiter.timeout)) or i_bus_err_i) and (not ctrl_i(ctrl_bus_ierr_ack_c));
305 28 zero_gravi
        if (i_bus_ack_i = '1') or (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for normal termination / CPU abort
306 23 zero_gravi
          i_arbiter.rd_req <= '0';
307 2 zero_gravi
        end if;
308
      end if;
309
    end if;
310 12 zero_gravi
  end process ifetch_arbiter;
311 2 zero_gravi
 
312 36 zero_gravi
  i_arbiter.wr_req <= '0'; -- instruction fetch is read-only
313
 
314 28 zero_gravi
  -- cancel bus access --
315
  i_bus_cancel_o <= i_arbiter.rd_req and ctrl_i(ctrl_bus_ierr_ack_c);
316 2 zero_gravi
 
317 12 zero_gravi
  -- wait for bus transaction to finish --
318
  i_wait_o <= i_arbiter.rd_req and (not i_bus_ack_i);
319 2 zero_gravi
 
320 12 zero_gravi
  -- output instruction fetch error to controller --
321
  ma_instr_o <= i_arbiter.err_align;
322
  be_instr_o <= i_arbiter.err_bus;
323 11 zero_gravi
 
324 12 zero_gravi
  -- instruction bus (read-only) --
325 31 zero_gravi
  i_bus_addr_o  <= fetch_pc_i(data_width_c-1 downto 2) & "00"; -- instruction access is always 4-byte aligned (even for compressed instructions)
326 12 zero_gravi
  i_bus_wdata_o <= (others => '0');
327
  i_bus_ben_o   <= (others => '0');
328
  i_bus_we_o    <= '0';
329 15 zero_gravi
  i_bus_re_o    <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault
330 12 zero_gravi
  i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
331
  instr_o       <= i_bus_rdata_i;
332 2 zero_gravi
 
333
 
334 12 zero_gravi
  -- Data Access Arbiter --------------------------------------------------------------------
335 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
336 36 zero_gravi
  data_access_arbiter: process(clk_i)
337 2 zero_gravi
  begin
338 36 zero_gravi
    if rising_edge(clk_i) then
339 12 zero_gravi
      -- data access request --
340
      if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
341
        d_arbiter.wr_req    <= ctrl_i(ctrl_bus_wr_c);
342
        d_arbiter.rd_req    <= ctrl_i(ctrl_bus_rd_c);
343
        d_arbiter.err_align <= d_misaligned;
344
        d_arbiter.err_bus   <= '0';
345 30 zero_gravi
        d_arbiter.timeout   <= std_ulogic_vector(to_unsigned(bus_timeout_c, index_size_f(bus_timeout_c)));
346 12 zero_gravi
      else -- in progress
347
        d_arbiter.timeout   <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1);
348
        d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned)                                     and (not ctrl_i(ctrl_bus_derr_ack_c));
349
        d_arbiter.err_bus   <= (d_arbiter.err_bus   or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i) and (not ctrl_i(ctrl_bus_derr_ack_c));
350 28 zero_gravi
        if (d_bus_ack_i = '1') or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort
351 12 zero_gravi
          d_arbiter.wr_req <= '0';
352
          d_arbiter.rd_req <= '0';
353 2 zero_gravi
        end if;
354 12 zero_gravi
      end if;
355 2 zero_gravi
    end if;
356 12 zero_gravi
  end process data_access_arbiter;
357 2 zero_gravi
 
358 28 zero_gravi
  -- cancel bus access --
359
  d_bus_cancel_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and ctrl_i(ctrl_bus_derr_ack_c);
360 2 zero_gravi
 
361 12 zero_gravi
  -- wait for bus transaction to finish --
362
  d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i);
363
 
364
  -- output data access error to controller --
365
  ma_load_o  <= d_arbiter.rd_req and d_arbiter.err_align;
366
  be_load_o  <= d_arbiter.rd_req and d_arbiter.err_bus;
367
  ma_store_o <= d_arbiter.wr_req and d_arbiter.err_align;
368
  be_store_o <= d_arbiter.wr_req and d_arbiter.err_bus;
369
 
370 15 zero_gravi
  -- data bus (read/write)--
371 12 zero_gravi
  d_bus_addr_o  <= mar;
372
  d_bus_wdata_o <= d_bus_wdata;
373
  d_bus_ben_o   <= d_bus_ben;
374 15 zero_gravi
  d_bus_we_o    <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned) and (not st_pmp_fault); -- no actual write when misaligned or PMP fault
375
  d_bus_re_o    <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault
376 12 zero_gravi
  d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
377
  d_bus_rdata   <= d_bus_rdata_i;
378
 
379
 
380 15 zero_gravi
  -- Physical Memory Protection (PMP) -------------------------------------------------------
381
  -- -------------------------------------------------------------------------------------------
382
  -- compute address masks --
383 17 zero_gravi
  pmp_masks: process(clk_i)
384 15 zero_gravi
  begin
385 17 zero_gravi
    if rising_edge(clk_i) then -- address configuration (not the actual address check!) has a latency of +1 cycles
386
      for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
387
        pmp.addr_mask(r) <= (others => '0'); -- default
388
        for i in PMP_GRANULARITY+1 to 33 loop
389
          if (i = PMP_GRANULARITY+1) then
390
            pmp.addr_mask(r)(i) <= '0';
391
          else -- current bit = not AND(all previous bits)
392
            pmp.addr_mask(r)(i) <= not (and_all_f(pmp_addr_i(r)(i-1 downto PMP_GRANULARITY)));
393
          end if;
394
        end loop; -- i
395
      end loop; -- r
396
    end if;
397 15 zero_gravi
  end process pmp_masks;
398
 
399
 
400 16 zero_gravi
  -- compute operands for comparator --
401
  pmp_prepare_check:
402
  for r in 0 to PMP_NUM_REGIONS-1 generate -- iterate over all regions
403
    -- ignore lowest 3 bits of access addresses -> minimal region size = 8 bytes
404
    pmp.region_i_addr(r) <= (fetch_pc_i(31 downto 3) & "000") and pmp.addr_mask(r)(33 downto 2);
405
    pmp.region_d_addr(r) <= (mar(31 downto 3) & "000")        and pmp.addr_mask(r)(33 downto 2);
406
    pmp.region_base(r)   <= pmp_addr_i(r)(33 downto 2)        and pmp.addr_mask(r)(33 downto 2);
407
  end generate; -- r
408 15 zero_gravi
 
409
 
410
  -- check for access address match --
411 16 zero_gravi
  pmp_addr_check: process (pmp)
412 15 zero_gravi
  begin
413
    for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
414
      -- instruction interface --
415 16 zero_gravi
      pmp.i_match(r) <= '0';
416
      if (pmp.region_i_addr(r)(31 downto PMP_GRANULARITY+2) = pmp.region_base(r)(31 downto PMP_GRANULARITY+2)) then
417 15 zero_gravi
        pmp.i_match(r) <= '1';
418
      end if;
419
      -- data interface --
420 16 zero_gravi
      pmp.d_match(r) <= '0';
421
      if (pmp.region_d_addr(r)(31 downto PMP_GRANULARITY+2) = pmp.region_base(r)(31 downto PMP_GRANULARITY+2)) then
422 15 zero_gravi
        pmp.d_match(r) <= '1';
423
      end if;
424
    end loop; -- r
425
  end process pmp_addr_check;
426
 
427
 
428
  -- check access type and regions's permissions --
429 36 zero_gravi
  pmp_check_permission: process(pmp, pmp_ctrl_i, ctrl_i)
430 15 zero_gravi
  begin
431
    for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
432 36 zero_gravi
      if ((ctrl_i(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) = priv_mode_u_c) or (pmp_ctrl_i(r)(pmp_cfg_l_c) = '1')) and -- user privilege level or locked pmp entry -> enforce permissions also for machine mode
433
         (pmp_ctrl_i(r)(pmp_cfg_ah_c downto pmp_cfg_al_c) /= pmp_off_mode_c) then -- active entry
434 15 zero_gravi
        pmp.if_fault(r) <= pmp.i_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_x_c)); -- fetch access match no execute permission
435
        pmp.ld_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_r_c)); -- load access match no read permission
436
        pmp.st_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_w_c)); -- store access match no write permission
437
      else
438
        pmp.if_fault(r) <= '0';
439
        pmp.ld_fault(r) <= '0';
440
        pmp.st_fault(r) <= '0';
441
      end if;
442
    end loop; -- r
443
  end process pmp_check_permission;
444
 
445
 
446
  -- final PMP access fault signals --
447
  if_pmp_fault <= or_all_f(pmp.if_fault) when (PMP_USE = true) else '0';
448
  ld_pmp_fault <= or_all_f(pmp.ld_fault) when (PMP_USE = true) else '0';
449
  st_pmp_fault <= or_all_f(pmp.st_fault) when (PMP_USE = true) else '0';
450
 
451
 
452 2 zero_gravi
end neorv32_cpu_bus_rtl;

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