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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_bus.vhd] - Blame information for rev 42

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1 2 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - Bus Interface Unit >>                                                            #
3
-- # ********************************************************************************************* #
4 18 zero_gravi
-- # Instruction and data bus interfaces and physical memory protection (PMP).                     #
5 2 zero_gravi
-- # ********************************************************************************************* #
6
-- # BSD 3-Clause License                                                                          #
7
-- #                                                                                               #
8 42 zero_gravi
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
9 2 zero_gravi
-- #                                                                                               #
10
-- # Redistribution and use in source and binary forms, with or without modification, are          #
11
-- # permitted provided that the following conditions are met:                                     #
12
-- #                                                                                               #
13
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
14
-- #    conditions and the following disclaimer.                                                   #
15
-- #                                                                                               #
16
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
17
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
18
-- #    provided with the distribution.                                                            #
19
-- #                                                                                               #
20
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
21
-- #    endorse or promote products derived from this software without specific prior written      #
22
-- #    permission.                                                                                #
23
-- #                                                                                               #
24
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
25
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
26
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
27
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
28
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
29
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
30
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
31
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
32
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
33
-- # ********************************************************************************************* #
34
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
35
-- #################################################################################################
36
 
37
library ieee;
38
use ieee.std_logic_1164.all;
39
use ieee.numeric_std.all;
40
 
41
library neorv32;
42
use neorv32.neorv32_package.all;
43
 
44
entity neorv32_cpu_bus is
45
  generic (
46 41 zero_gravi
    CPU_EXTENSION_RISCV_C : boolean := true;  -- implement compressed extension?
47 15 zero_gravi
    -- Physical memory protection (PMP) --
48 42 zero_gravi
    PMP_NUM_REGIONS       : natural := 0;     -- number of regions (0..64)
49
    PMP_MIN_GRANULARITY   : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
50 41 zero_gravi
    -- Bus Timeout --
51
    BUS_TIMEOUT           : natural := 63     -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
52 2 zero_gravi
  );
53
  port (
54
    -- global control --
55 12 zero_gravi
    clk_i          : in  std_ulogic; -- global clock, rising edge
56 38 zero_gravi
    rstn_i         : in  std_ulogic := '0'; -- global reset, low-active, async
57 12 zero_gravi
    ctrl_i         : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
58
    -- cpu instruction fetch interface --
59
    fetch_pc_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
60
    instr_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
61
    i_wait_o       : out std_ulogic; -- wait for fetch to complete
62
    --
63
    ma_instr_o     : out std_ulogic; -- misaligned instruction address
64
    be_instr_o     : out std_ulogic; -- bus error on instruction access
65
    -- cpu data access interface --
66
    addr_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
67
    wdata_i        : in  std_ulogic_vector(data_width_c-1 downto 0); -- write data
68
    rdata_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
69
    mar_o          : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
70
    d_wait_o       : out std_ulogic; -- wait for access to complete
71
    --
72
    ma_load_o      : out std_ulogic; -- misaligned load data address
73
    ma_store_o     : out std_ulogic; -- misaligned store data address
74
    be_load_o      : out std_ulogic; -- bus error on load data access
75
    be_store_o     : out std_ulogic; -- bus error on store data access
76 15 zero_gravi
    -- physical memory protection --
77
    pmp_addr_i     : in  pmp_addr_if_t; -- addresses
78
    pmp_ctrl_i     : in  pmp_ctrl_if_t; -- configs
79 12 zero_gravi
    -- instruction bus --
80
    i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
81
    i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
82
    i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
83
    i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
84
    i_bus_we_o     : out std_ulogic; -- write enable
85
    i_bus_re_o     : out std_ulogic; -- read enable
86
    i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
87
    i_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
88
    i_bus_err_i    : in  std_ulogic; -- bus transfer error
89
    i_bus_fence_o  : out std_ulogic; -- fence operation
90 39 zero_gravi
    i_bus_lock_o   : out std_ulogic; -- locked/exclusive access
91 12 zero_gravi
    -- data bus --
92
    d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
93
    d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
94
    d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
95
    d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
96
    d_bus_we_o     : out std_ulogic; -- write enable
97
    d_bus_re_o     : out std_ulogic; -- read enable
98
    d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
99
    d_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
100
    d_bus_err_i    : in  std_ulogic; -- bus transfer error
101 39 zero_gravi
    d_bus_fence_o  : out std_ulogic; -- fence operation
102
    d_bus_lock_o   : out std_ulogic  -- locked/exclusive access
103 2 zero_gravi
  );
104
end neorv32_cpu_bus;
105
 
106
architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
107
 
108 15 zero_gravi
  -- PMP modes --
109
  constant pmp_off_mode_c   : std_ulogic_vector(1 downto 0) := "00"; -- null region (disabled)
110 36 zero_gravi
--constant pmp_tor_mode_c   : std_ulogic_vector(1 downto 0) := "01"; -- top of range
111
--constant pmp_na4_mode_c   : std_ulogic_vector(1 downto 0) := "10"; -- naturally aligned four-byte region
112 15 zero_gravi
  constant pmp_napot_mode_c : std_ulogic_vector(1 downto 0) := "11"; -- naturally aligned power-of-two region (>= 8 bytes)
113
 
114 40 zero_gravi
  -- PMP granularity --
115 42 zero_gravi
  constant pmp_g_c : natural := index_size_f(PMP_MIN_GRANULARITY);
116 40 zero_gravi
 
117 15 zero_gravi
  -- PMP configuration register bits --
118
  constant pmp_cfg_r_c  : natural := 0; -- read permit
119
  constant pmp_cfg_w_c  : natural := 1; -- write permit
120
  constant pmp_cfg_x_c  : natural := 2; -- execute permit
121
  constant pmp_cfg_al_c : natural := 3; -- mode bit low
122
  constant pmp_cfg_ah_c : natural := 4; -- mode bit high
123
  constant pmp_cfg_l_c  : natural := 7; -- locked entry
124
 
125 12 zero_gravi
  -- data interface registers --
126 2 zero_gravi
  signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0);
127
 
128 12 zero_gravi
  -- data access --
129
  signal d_bus_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- write data
130
  signal d_bus_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- read data
131
  signal d_bus_ben   : std_ulogic_vector(3 downto 0); -- write data byte enable
132 2 zero_gravi
 
133
  -- misaligned access? --
134 12 zero_gravi
  signal d_misaligned, i_misaligned : std_ulogic;
135 2 zero_gravi
 
136 12 zero_gravi
  -- bus arbiter --
137
  type bus_arbiter_t is record
138
    rd_req    : std_ulogic; -- read access in progress
139
    wr_req    : std_ulogic; -- write access in progress
140
    err_align : std_ulogic; -- alignment error
141
    err_bus   : std_ulogic; -- bus access error
142 41 zero_gravi
    timeout   : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0);
143 12 zero_gravi
  end record;
144
  signal i_arbiter, d_arbiter : bus_arbiter_t;
145
 
146 15 zero_gravi
  -- physical memory protection --
147 42 zero_gravi
  type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
148 15 zero_gravi
  type pmp_t is record
149 40 zero_gravi
    addr_mask     : pmp_addr_t;
150
    region_base   : pmp_addr_t; -- region config base address
151 16 zero_gravi
    region_i_addr : pmp_addr_t; -- masked instruction access base address for comparator
152
    region_d_addr : pmp_addr_t; -- masked data access base address for comparator
153 42 zero_gravi
    i_match       : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for instruction interface
154
    d_match       : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for data interface
155
    if_fault      : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for fetch operation
156
    ld_fault      : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for load operation
157
    st_fault      : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for store operation
158 15 zero_gravi
  end record;
159
  signal pmp : pmp_t;
160
 
161
  -- pmp faults anybody? --
162
  signal if_pmp_fault : std_ulogic; -- pmp instruction access fault
163
  signal ld_pmp_fault : std_ulogic; -- pmp load access fault
164
  signal st_pmp_fault : std_ulogic; -- pmp store access fault
165
 
166 2 zero_gravi
begin
167
 
168 12 zero_gravi
  -- Data Interface: Access Address ---------------------------------------------------------
169 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
170 36 zero_gravi
  mem_adr_reg: process(clk_i)
171 2 zero_gravi
  begin
172 11 zero_gravi
    if rising_edge(clk_i) then
173 39 zero_gravi
      if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
174 12 zero_gravi
        mar <= addr_i;
175 2 zero_gravi
      end if;
176
    end if;
177
  end process mem_adr_reg;
178
 
179 12 zero_gravi
  -- read-back for exception controller --
180
  mar_o <= mar;
181 2 zero_gravi
 
182 12 zero_gravi
  -- alignment check --
183
  misaligned_d_check: process(mar, ctrl_i)
184
  begin
185
    -- check data access --
186
    d_misaligned <= '0'; -- default
187
    case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
188
      when "00" => -- byte
189
        d_misaligned <= '0';
190
      when "01" => -- half-word
191
        if (mar(0) /= '0') then
192
          d_misaligned <= '1';
193
        end if;
194
      when others => -- word
195
        if (mar(1 downto 0) /= "00") then
196
          d_misaligned <= '1';
197
        end if;
198
    end case;
199
  end process misaligned_d_check;
200 2 zero_gravi
 
201
 
202 12 zero_gravi
  -- Data Interface: Write Data -------------------------------------------------------------
203 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
204
  mem_do_reg: process(clk_i)
205
  begin
206
    if rising_edge(clk_i) then
207 39 zero_gravi
      if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
208 40 zero_gravi
        mdo <= wdata_i; -- memory data output register (MDO)
209 2 zero_gravi
      end if;
210
    end if;
211
  end process mem_do_reg;
212
 
213
  -- byte enable and output data alignment --
214
  byte_enable: process(mar, mdo, ctrl_i)
215
  begin
216
    case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
217
      when "00" => -- byte
218 12 zero_gravi
        d_bus_wdata(07 downto 00) <= mdo(07 downto 00);
219
        d_bus_wdata(15 downto 08) <= mdo(07 downto 00);
220
        d_bus_wdata(23 downto 16) <= mdo(07 downto 00);
221
        d_bus_wdata(31 downto 24) <= mdo(07 downto 00);
222 36 zero_gravi
        case mar(1 downto 0) is
223
          when "00"   => d_bus_ben <= "0001";
224
          when "01"   => d_bus_ben <= "0010";
225
          when "10"   => d_bus_ben <= "0100";
226
          when others => d_bus_ben <= "1000";
227
        end case;
228 2 zero_gravi
      when "01" => -- half-word
229 12 zero_gravi
        d_bus_wdata(31 downto 16) <= mdo(15 downto 00);
230
        d_bus_wdata(15 downto 00) <= mdo(15 downto 00);
231 2 zero_gravi
        if (mar(1) = '0') then
232 12 zero_gravi
          d_bus_ben <= "0011"; -- low half-word
233 2 zero_gravi
        else
234 12 zero_gravi
          d_bus_ben <= "1100"; -- high half-word
235 2 zero_gravi
        end if;
236
      when others => -- word
237 12 zero_gravi
        d_bus_wdata <= mdo;
238
        d_bus_ben   <= "1111"; -- full word
239 2 zero_gravi
    end case;
240
  end process byte_enable;
241
 
242
 
243 12 zero_gravi
  -- Data Interface: Read Data --------------------------------------------------------------
244 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
245
  mem_out_buf: process(clk_i)
246
  begin
247
    if rising_edge(clk_i) then
248 39 zero_gravi
      if (ctrl_i(ctrl_bus_mi_we_c) = '1') then
249 40 zero_gravi
        mdi <= d_bus_rdata; -- memory data input register (MDI)
250 2 zero_gravi
      end if;
251
    end if;
252
  end process mem_out_buf;
253
 
254 12 zero_gravi
  -- input data alignment and sign extension --
255 2 zero_gravi
  read_align: process(mdi, mar, ctrl_i)
256 36 zero_gravi
    variable byte_in_v  : std_ulogic_vector(07 downto 0);
257
    variable hword_in_v : std_ulogic_vector(15 downto 0);
258 2 zero_gravi
  begin
259 36 zero_gravi
    -- sub-word input --
260
    case mar(1 downto 0) is
261
      when "00"   => byte_in_v := mdi(07 downto 00); hword_in_v := mdi(15 downto 00); -- byte 0 / half-word 0
262
      when "01"   => byte_in_v := mdi(15 downto 08); hword_in_v := mdi(15 downto 00); -- byte 1 / half-word 0
263
      when "10"   => byte_in_v := mdi(23 downto 16); hword_in_v := mdi(31 downto 16); -- byte 2 / half-word 1
264
      when others => byte_in_v := mdi(31 downto 24); hword_in_v := mdi(31 downto 16); -- byte 3 / half-word 1
265
    end case;
266
    -- actual data size --
267
    case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is
268 2 zero_gravi
      when "00" => -- byte
269 36 zero_gravi
        rdata_o(31 downto 08) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and byte_in_v(7))); -- sign extension
270
        rdata_o(07 downto 00) <= byte_in_v;
271 2 zero_gravi
      when "01" => -- half-word
272 36 zero_gravi
        rdata_o(31 downto 16) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and hword_in_v(15))); -- sign extension
273
        rdata_o(15 downto 00) <= hword_in_v; -- high half-word
274 2 zero_gravi
      when others => -- word
275
        rdata_o <= mdi; -- full word
276
    end case;
277
  end process read_align;
278
 
279
 
280 39 zero_gravi
  -- Data Access Arbiter --------------------------------------------------------------------
281 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
282 39 zero_gravi
  data_access_arbiter: process(rstn_i, clk_i)
283 2 zero_gravi
  begin
284 39 zero_gravi
    if (rstn_i = '0') then
285
      d_arbiter.wr_req    <= '0';
286
      d_arbiter.rd_req    <= '0';
287
      d_arbiter.err_align <= '0';
288
      d_arbiter.err_bus   <= '0';
289
      d_arbiter.timeout   <= (others => '0');
290
    elsif rising_edge(clk_i) then
291
      -- data access request --
292
      if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
293
        d_arbiter.wr_req    <= ctrl_i(ctrl_bus_wr_c);
294
        d_arbiter.rd_req    <= ctrl_i(ctrl_bus_rd_c);
295
        d_arbiter.err_align <= d_misaligned;
296
        d_arbiter.err_bus   <= '0';
297 41 zero_gravi
        d_arbiter.timeout   <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
298 39 zero_gravi
      else -- in progress
299
        d_arbiter.timeout   <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1);
300 40 zero_gravi
        d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
301
        d_arbiter.err_bus   <= (d_arbiter.err_bus   or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i or
302
                                (st_pmp_fault and d_arbiter.wr_req) or (ld_pmp_fault and d_arbiter.rd_req)) and (not ctrl_i(ctrl_bus_derr_ack_c));
303 39 zero_gravi
        if (d_bus_ack_i = '1') or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort
304
          d_arbiter.wr_req <= '0';
305
          d_arbiter.rd_req <= '0';
306
        end if;
307
      end if;
308 12 zero_gravi
    end if;
309 39 zero_gravi
  end process data_access_arbiter;
310 12 zero_gravi
 
311 39 zero_gravi
  -- cancel bus access --
312
  d_bus_cancel_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and ctrl_i(ctrl_bus_derr_ack_c);
313 12 zero_gravi
 
314 39 zero_gravi
  -- wait for bus transaction to finish --
315
  d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i);
316
 
317
  -- output data access error to controller --
318
  ma_load_o  <= d_arbiter.rd_req and d_arbiter.err_align;
319
  be_load_o  <= d_arbiter.rd_req and d_arbiter.err_bus;
320
  ma_store_o <= d_arbiter.wr_req and d_arbiter.err_align;
321
  be_store_o <= d_arbiter.wr_req and d_arbiter.err_bus;
322
 
323
  -- data bus (read/write)--
324
  d_bus_addr_o  <= mar;
325
  d_bus_wdata_o <= d_bus_wdata;
326
  d_bus_ben_o   <= d_bus_ben;
327
  d_bus_we_o    <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned) and (not st_pmp_fault); -- no actual write when misaligned or PMP fault
328
  d_bus_re_o    <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault
329
  d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
330
  d_bus_rdata   <= d_bus_rdata_i;
331
  d_bus_lock_o  <= ctrl_i(ctrl_bus_lock_c);
332
 
333
 
334 12 zero_gravi
  -- Instruction Fetch Arbiter --------------------------------------------------------------
335
  -- -------------------------------------------------------------------------------------------
336 38 zero_gravi
  ifetch_arbiter: process(rstn_i, clk_i)
337 12 zero_gravi
  begin
338 38 zero_gravi
    if (rstn_i = '0') then
339
      i_arbiter.rd_req    <= '0';
340
      i_arbiter.err_align <= '0';
341
      i_arbiter.err_bus   <= '0';
342
      i_arbiter.timeout   <= (others => '0');
343
    elsif rising_edge(clk_i) then
344 12 zero_gravi
      -- instruction fetch request --
345
      if (i_arbiter.rd_req = '0') then -- idle
346
        i_arbiter.rd_req    <= ctrl_i(ctrl_bus_if_c);
347
        i_arbiter.err_align <= i_misaligned;
348
        i_arbiter.err_bus   <= '0';
349 41 zero_gravi
        i_arbiter.timeout   <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
350 12 zero_gravi
      else -- in progress
351
        i_arbiter.timeout   <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1);
352 40 zero_gravi
        i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned)                                                     and (not ctrl_i(ctrl_bus_ierr_ack_c));
353
        i_arbiter.err_bus   <= (i_arbiter.err_bus   or (not or_all_f(i_arbiter.timeout)) or i_bus_err_i or if_pmp_fault) and (not ctrl_i(ctrl_bus_ierr_ack_c));
354 28 zero_gravi
        if (i_bus_ack_i = '1') or (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for normal termination / CPU abort
355 23 zero_gravi
          i_arbiter.rd_req <= '0';
356 2 zero_gravi
        end if;
357
      end if;
358
    end if;
359 12 zero_gravi
  end process ifetch_arbiter;
360 2 zero_gravi
 
361 36 zero_gravi
  i_arbiter.wr_req <= '0'; -- instruction fetch is read-only
362
 
363 28 zero_gravi
  -- cancel bus access --
364
  i_bus_cancel_o <= i_arbiter.rd_req and ctrl_i(ctrl_bus_ierr_ack_c);
365 2 zero_gravi
 
366 12 zero_gravi
  -- wait for bus transaction to finish --
367
  i_wait_o <= i_arbiter.rd_req and (not i_bus_ack_i);
368 2 zero_gravi
 
369 12 zero_gravi
  -- output instruction fetch error to controller --
370
  ma_instr_o <= i_arbiter.err_align;
371
  be_instr_o <= i_arbiter.err_bus;
372 11 zero_gravi
 
373 12 zero_gravi
  -- instruction bus (read-only) --
374 31 zero_gravi
  i_bus_addr_o  <= fetch_pc_i(data_width_c-1 downto 2) & "00"; -- instruction access is always 4-byte aligned (even for compressed instructions)
375 40 zero_gravi
  i_bus_wdata_o <= (others => '0'); -- instruction fetch is read-only
376 12 zero_gravi
  i_bus_ben_o   <= (others => '0');
377
  i_bus_we_o    <= '0';
378 15 zero_gravi
  i_bus_re_o    <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault
379 12 zero_gravi
  i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
380
  instr_o       <= i_bus_rdata_i;
381 39 zero_gravi
  i_bus_lock_o  <= '0'; -- instruction fetch cannot be atomic
382 2 zero_gravi
 
383
 
384 39 zero_gravi
  -- check instruction access --
385
  i_misaligned <= '0' when (CPU_EXTENSION_RISCV_C = true) else -- no alignment exceptions possible when using C-extension
386
                  '1' when (fetch_pc_i(1) = '1') else '0'; -- 32-bit accesses only
387 2 zero_gravi
 
388
 
389 15 zero_gravi
  -- Physical Memory Protection (PMP) -------------------------------------------------------
390
  -- -------------------------------------------------------------------------------------------
391 40 zero_gravi
  -- compute address masks (ITERATIVE!!!) --
392 17 zero_gravi
  pmp_masks: process(clk_i)
393 15 zero_gravi
  begin
394 40 zero_gravi
    if rising_edge(clk_i) then -- address mask computation (not the actual address check!) has a latency of max +32 cycles
395 42 zero_gravi
      for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
396 40 zero_gravi
        pmp.addr_mask(r) <= (others => '0');
397
        for i in pmp_g_c to data_width_c-1 loop
398
          pmp.addr_mask(r)(i) <= pmp.addr_mask(r)(i-1) or (not pmp_addr_i(r)(i-1));
399 17 zero_gravi
        end loop; -- i
400
      end loop; -- r
401
    end if;
402 15 zero_gravi
  end process pmp_masks;
403
 
404
 
405 40 zero_gravi
  -- address access check --
406
  pmp_address_check:
407 42 zero_gravi
  for r in 0 to PMP_NUM_REGIONS-1 generate -- iterate over all regions
408 40 zero_gravi
    pmp.region_i_addr(r) <= fetch_pc_i                             and pmp.addr_mask(r);
409
    pmp.region_d_addr(r) <= mar                                    and pmp.addr_mask(r);
410
    pmp.region_base(r)   <= pmp_addr_i(r)(data_width_c+1 downto 2) and pmp.addr_mask(r);
411
    --
412
    pmp.i_match(r) <= '1' when (pmp.region_i_addr(r)(data_width_c-1 downto pmp_g_c) = pmp.region_base(r)(data_width_c-1 downto pmp_g_c)) else '0';
413
    pmp.d_match(r) <= '1' when (pmp.region_d_addr(r)(data_width_c-1 downto pmp_g_c) = pmp.region_base(r)(data_width_c-1 downto pmp_g_c)) else '0';
414 16 zero_gravi
  end generate; -- r
415 15 zero_gravi
 
416
 
417
  -- check access type and regions's permissions --
418 36 zero_gravi
  pmp_check_permission: process(pmp, pmp_ctrl_i, ctrl_i)
419 15 zero_gravi
  begin
420 42 zero_gravi
    for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
421 36 zero_gravi
      if ((ctrl_i(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) = priv_mode_u_c) or (pmp_ctrl_i(r)(pmp_cfg_l_c) = '1')) and -- user privilege level or locked pmp entry -> enforce permissions also for machine mode
422
         (pmp_ctrl_i(r)(pmp_cfg_ah_c downto pmp_cfg_al_c) /= pmp_off_mode_c) then -- active entry
423 15 zero_gravi
        pmp.if_fault(r) <= pmp.i_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_x_c)); -- fetch access match no execute permission
424
        pmp.ld_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_r_c)); -- load access match no read permission
425
        pmp.st_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_w_c)); -- store access match no write permission
426
      else
427
        pmp.if_fault(r) <= '0';
428
        pmp.ld_fault(r) <= '0';
429
        pmp.st_fault(r) <= '0';
430
      end if;
431
    end loop; -- r
432
  end process pmp_check_permission;
433
 
434
 
435
  -- final PMP access fault signals --
436 42 zero_gravi
  if_pmp_fault <= or_all_f(pmp.if_fault) when (PMP_NUM_REGIONS > 0) else '0';
437
  ld_pmp_fault <= or_all_f(pmp.ld_fault) when (PMP_NUM_REGIONS > 0) else '0';
438
  st_pmp_fault <= or_all_f(pmp.st_fault) when (PMP_NUM_REGIONS > 0) else '0';
439 15 zero_gravi
 
440
 
441 2 zero_gravi
end neorv32_cpu_bus_rtl;

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