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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_bus.vhd] - Blame information for rev 65

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1 2 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - Bus Interface Unit >>                                                            #
3
-- # ********************************************************************************************* #
4 18 zero_gravi
-- # Instruction and data bus interfaces and physical memory protection (PMP).                     #
5 2 zero_gravi
-- # ********************************************************************************************* #
6
-- # BSD 3-Clause License                                                                          #
7
-- #                                                                                               #
8 42 zero_gravi
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
9 2 zero_gravi
-- #                                                                                               #
10
-- # Redistribution and use in source and binary forms, with or without modification, are          #
11
-- # permitted provided that the following conditions are met:                                     #
12
-- #                                                                                               #
13
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
14
-- #    conditions and the following disclaimer.                                                   #
15
-- #                                                                                               #
16
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
17
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
18
-- #    provided with the distribution.                                                            #
19
-- #                                                                                               #
20
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
21
-- #    endorse or promote products derived from this software without specific prior written      #
22
-- #    permission.                                                                                #
23
-- #                                                                                               #
24
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
25
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
26
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
27
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
28
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
29
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
30
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
31
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
32
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
34
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
35
-- #################################################################################################
36
 
37
library ieee;
38
use ieee.std_logic_1164.all;
39
use ieee.numeric_std.all;
40
 
41
library neorv32;
42
use neorv32.neorv32_package.all;
43
 
44
entity neorv32_cpu_bus is
45
  generic (
46 62 zero_gravi
    CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension?
47
    CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension?
48 15 zero_gravi
    -- Physical memory protection (PMP) --
49 62 zero_gravi
    PMP_NUM_REGIONS       : natural; -- number of regions (0..64)
50
    PMP_MIN_GRANULARITY   : natural  -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
51 2 zero_gravi
  );
52
  port (
53
    -- global control --
54 12 zero_gravi
    clk_i          : in  std_ulogic; -- global clock, rising edge
55 38 zero_gravi
    rstn_i         : in  std_ulogic := '0'; -- global reset, low-active, async
56 12 zero_gravi
    ctrl_i         : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
57
    -- cpu instruction fetch interface --
58
    fetch_pc_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
59
    instr_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
60
    i_wait_o       : out std_ulogic; -- wait for fetch to complete
61
    --
62
    ma_instr_o     : out std_ulogic; -- misaligned instruction address
63
    be_instr_o     : out std_ulogic; -- bus error on instruction access
64
    -- cpu data access interface --
65
    addr_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
66
    wdata_i        : in  std_ulogic_vector(data_width_c-1 downto 0); -- write data
67
    rdata_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
68
    mar_o          : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
69
    d_wait_o       : out std_ulogic; -- wait for access to complete
70
    --
71 57 zero_gravi
    excl_state_o   : out std_ulogic; -- atomic/exclusive access status
72 12 zero_gravi
    ma_load_o      : out std_ulogic; -- misaligned load data address
73
    ma_store_o     : out std_ulogic; -- misaligned store data address
74
    be_load_o      : out std_ulogic; -- bus error on load data access
75
    be_store_o     : out std_ulogic; -- bus error on store data access
76 15 zero_gravi
    -- physical memory protection --
77
    pmp_addr_i     : in  pmp_addr_if_t; -- addresses
78
    pmp_ctrl_i     : in  pmp_ctrl_if_t; -- configs
79 12 zero_gravi
    -- instruction bus --
80
    i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
81
    i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
82
    i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
83
    i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
84
    i_bus_we_o     : out std_ulogic; -- write enable
85
    i_bus_re_o     : out std_ulogic; -- read enable
86 57 zero_gravi
    i_bus_lock_o   : out std_ulogic; -- exclusive access request
87 12 zero_gravi
    i_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
88
    i_bus_err_i    : in  std_ulogic; -- bus transfer error
89
    i_bus_fence_o  : out std_ulogic; -- fence operation
90
    -- data bus --
91
    d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
92
    d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
93
    d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
94
    d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
95
    d_bus_we_o     : out std_ulogic; -- write enable
96
    d_bus_re_o     : out std_ulogic; -- read enable
97 57 zero_gravi
    d_bus_lock_o   : out std_ulogic; -- exclusive access request
98 12 zero_gravi
    d_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
99
    d_bus_err_i    : in  std_ulogic; -- bus transfer error
100 57 zero_gravi
    d_bus_fence_o  : out std_ulogic  -- fence operation
101 2 zero_gravi
  );
102
end neorv32_cpu_bus;
103
 
104
architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
105
 
106 15 zero_gravi
  -- PMP modes --
107
  constant pmp_off_mode_c   : std_ulogic_vector(1 downto 0) := "00"; -- null region (disabled)
108 36 zero_gravi
--constant pmp_tor_mode_c   : std_ulogic_vector(1 downto 0) := "01"; -- top of range
109
--constant pmp_na4_mode_c   : std_ulogic_vector(1 downto 0) := "10"; -- naturally aligned four-byte region
110 15 zero_gravi
  constant pmp_napot_mode_c : std_ulogic_vector(1 downto 0) := "11"; -- naturally aligned power-of-two region (>= 8 bytes)
111
 
112 40 zero_gravi
  -- PMP granularity --
113 42 zero_gravi
  constant pmp_g_c : natural := index_size_f(PMP_MIN_GRANULARITY);
114 40 zero_gravi
 
115 15 zero_gravi
  -- PMP configuration register bits --
116
  constant pmp_cfg_r_c  : natural := 0; -- read permit
117
  constant pmp_cfg_w_c  : natural := 1; -- write permit
118
  constant pmp_cfg_x_c  : natural := 2; -- execute permit
119
  constant pmp_cfg_al_c : natural := 3; -- mode bit low
120
  constant pmp_cfg_ah_c : natural := 4; -- mode bit high
121 62 zero_gravi
  --
122 15 zero_gravi
  constant pmp_cfg_l_c  : natural := 7; -- locked entry
123
 
124 12 zero_gravi
  -- data interface registers --
125 2 zero_gravi
  signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0);
126
 
127 12 zero_gravi
  -- data access --
128
  signal d_bus_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- write data
129
  signal d_bus_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- read data
130 57 zero_gravi
  signal rdata_align : std_ulogic_vector(data_width_c-1 downto 0); -- read-data alignment
131 12 zero_gravi
  signal d_bus_ben   : std_ulogic_vector(3 downto 0); -- write data byte enable
132 2 zero_gravi
 
133
  -- misaligned access? --
134 12 zero_gravi
  signal d_misaligned, i_misaligned : std_ulogic;
135 2 zero_gravi
 
136 12 zero_gravi
  -- bus arbiter --
137
  type bus_arbiter_t is record
138
    rd_req    : std_ulogic; -- read access in progress
139
    wr_req    : std_ulogic; -- write access in progress
140
    err_align : std_ulogic; -- alignment error
141
    err_bus   : std_ulogic; -- bus access error
142
  end record;
143
  signal i_arbiter, d_arbiter : bus_arbiter_t;
144
 
145 57 zero_gravi
  -- atomic/exclusive access - reservation controller --
146
  signal exclusive_lock        : std_ulogic;
147
  signal exclusive_lock_status : std_ulogic_vector(data_width_c-1 downto 0); -- read data
148
 
149 15 zero_gravi
  -- physical memory protection --
150 42 zero_gravi
  type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
151 15 zero_gravi
  type pmp_t is record
152 40 zero_gravi
    addr_mask     : pmp_addr_t;
153
    region_base   : pmp_addr_t; -- region config base address
154 16 zero_gravi
    region_i_addr : pmp_addr_t; -- masked instruction access base address for comparator
155
    region_d_addr : pmp_addr_t; -- masked data access base address for comparator
156 42 zero_gravi
    i_match       : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for instruction interface
157
    d_match       : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for data interface
158
    if_fault      : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for fetch operation
159
    ld_fault      : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for load operation
160
    st_fault      : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for store operation
161 15 zero_gravi
  end record;
162
  signal pmp : pmp_t;
163
 
164 47 zero_gravi
  -- memory control signal buffer (when using PMP) --
165
  signal d_bus_we, d_bus_we_buf : std_ulogic;
166
  signal d_bus_re, d_bus_re_buf : std_ulogic;
167
  signal i_bus_re, i_bus_re_buf : std_ulogic;
168
 
169
  -- pmp faults anyone? --
170 15 zero_gravi
  signal if_pmp_fault : std_ulogic; -- pmp instruction access fault
171
  signal ld_pmp_fault : std_ulogic; -- pmp load access fault
172
  signal st_pmp_fault : std_ulogic; -- pmp store access fault
173
 
174 2 zero_gravi
begin
175
 
176 47 zero_gravi
  -- Sanity Checks --------------------------------------------------------------------------
177
  -- -------------------------------------------------------------------------------------------
178 64 zero_gravi
  assert not (PMP_NUM_REGIONS > pmp_num_regions_critical_c) report "NEORV32 CPU CONFIG WARNING! Number of implemented PMP regions (PMP_NUM_REGIONS = " &
179
  integer'image(PMP_NUM_REGIONS) & ") beyond critical limit (pmp_num_regions_critical_c = " & integer'image(pmp_num_regions_critical_c) &
180
  "). Inserting another register stage (that will increase memory latency by +1 cycle)." severity warning;
181 47 zero_gravi
 
182
 
183 12 zero_gravi
  -- Data Interface: Access Address ---------------------------------------------------------
184 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
185 56 zero_gravi
  mem_adr_reg: process(rstn_i, clk_i)
186 2 zero_gravi
  begin
187 56 zero_gravi
    if (rstn_i = '0') then
188
      mar <= (others => def_rst_val_c);
189
    elsif rising_edge(clk_i) then
190 39 zero_gravi
      if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
191 12 zero_gravi
        mar <= addr_i;
192 2 zero_gravi
      end if;
193
    end if;
194
  end process mem_adr_reg;
195
 
196 12 zero_gravi
  -- read-back for exception controller --
197
  mar_o <= mar;
198 2 zero_gravi
 
199 12 zero_gravi
  -- alignment check --
200
  misaligned_d_check: process(mar, ctrl_i)
201
  begin
202
    -- check data access --
203
    d_misaligned <= '0'; -- default
204
    case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
205
      when "00" => -- byte
206
        d_misaligned <= '0';
207
      when "01" => -- half-word
208
        if (mar(0) /= '0') then
209
          d_misaligned <= '1';
210
        end if;
211
      when others => -- word
212
        if (mar(1 downto 0) /= "00") then
213
          d_misaligned <= '1';
214
        end if;
215
    end case;
216
  end process misaligned_d_check;
217 2 zero_gravi
 
218
 
219 12 zero_gravi
  -- Data Interface: Write Data -------------------------------------------------------------
220 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
221 56 zero_gravi
  mem_do_reg: process(rstn_i, clk_i)
222 2 zero_gravi
  begin
223 56 zero_gravi
    if (rstn_i = '0') then
224
      mdo <= (others => def_rst_val_c);
225
    elsif rising_edge(clk_i) then
226 39 zero_gravi
      if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
227 40 zero_gravi
        mdo <= wdata_i; -- memory data output register (MDO)
228 2 zero_gravi
      end if;
229
    end if;
230
  end process mem_do_reg;
231
 
232
  -- byte enable and output data alignment --
233
  byte_enable: process(mar, mdo, ctrl_i)
234
  begin
235
    case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
236
      when "00" => -- byte
237 12 zero_gravi
        d_bus_wdata(07 downto 00) <= mdo(07 downto 00);
238
        d_bus_wdata(15 downto 08) <= mdo(07 downto 00);
239
        d_bus_wdata(23 downto 16) <= mdo(07 downto 00);
240
        d_bus_wdata(31 downto 24) <= mdo(07 downto 00);
241 36 zero_gravi
        case mar(1 downto 0) is
242
          when "00"   => d_bus_ben <= "0001";
243
          when "01"   => d_bus_ben <= "0010";
244
          when "10"   => d_bus_ben <= "0100";
245
          when others => d_bus_ben <= "1000";
246
        end case;
247 2 zero_gravi
      when "01" => -- half-word
248 12 zero_gravi
        d_bus_wdata(31 downto 16) <= mdo(15 downto 00);
249
        d_bus_wdata(15 downto 00) <= mdo(15 downto 00);
250 2 zero_gravi
        if (mar(1) = '0') then
251 12 zero_gravi
          d_bus_ben <= "0011"; -- low half-word
252 2 zero_gravi
        else
253 12 zero_gravi
          d_bus_ben <= "1100"; -- high half-word
254 2 zero_gravi
        end if;
255
      when others => -- word
256 12 zero_gravi
        d_bus_wdata <= mdo;
257
        d_bus_ben   <= "1111"; -- full word
258 2 zero_gravi
    end case;
259
  end process byte_enable;
260
 
261
 
262 12 zero_gravi
  -- Data Interface: Read Data --------------------------------------------------------------
263 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
264 57 zero_gravi
  mem_di_reg: process(rstn_i, clk_i)
265 2 zero_gravi
  begin
266 56 zero_gravi
    if (rstn_i = '0') then
267
      mdi <= (others => def_rst_val_c);
268
    elsif rising_edge(clk_i) then
269 39 zero_gravi
      if (ctrl_i(ctrl_bus_mi_we_c) = '1') then
270 40 zero_gravi
        mdi <= d_bus_rdata; -- memory data input register (MDI)
271 2 zero_gravi
      end if;
272
    end if;
273 57 zero_gravi
  end process mem_di_reg;
274 2 zero_gravi
 
275 12 zero_gravi
  -- input data alignment and sign extension --
276 2 zero_gravi
  read_align: process(mdi, mar, ctrl_i)
277 36 zero_gravi
    variable byte_in_v  : std_ulogic_vector(07 downto 0);
278
    variable hword_in_v : std_ulogic_vector(15 downto 0);
279 2 zero_gravi
  begin
280 36 zero_gravi
    -- sub-word input --
281
    case mar(1 downto 0) is
282
      when "00"   => byte_in_v := mdi(07 downto 00); hword_in_v := mdi(15 downto 00); -- byte 0 / half-word 0
283
      when "01"   => byte_in_v := mdi(15 downto 08); hword_in_v := mdi(15 downto 00); -- byte 1 / half-word 0
284
      when "10"   => byte_in_v := mdi(23 downto 16); hword_in_v := mdi(31 downto 16); -- byte 2 / half-word 1
285
      when others => byte_in_v := mdi(31 downto 24); hword_in_v := mdi(31 downto 16); -- byte 3 / half-word 1
286
    end case;
287
    -- actual data size --
288
    case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is
289 2 zero_gravi
      when "00" => -- byte
290 57 zero_gravi
        rdata_align(31 downto 08) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and byte_in_v(7))); -- sign extension
291
        rdata_align(07 downto 00) <= byte_in_v;
292 2 zero_gravi
      when "01" => -- half-word
293 57 zero_gravi
        rdata_align(31 downto 16) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and hword_in_v(15))); -- sign extension
294
        rdata_align(15 downto 00) <= hword_in_v; -- high half-word
295 2 zero_gravi
      when others => -- word
296 57 zero_gravi
        rdata_align <= mdi; -- full word
297 2 zero_gravi
    end case;
298
  end process read_align;
299
 
300 57 zero_gravi
  -- insert exclusive lock status for SC operations only --
301
  rdata_o <= exclusive_lock_status when (CPU_EXTENSION_RISCV_A = true) and (ctrl_i(ctrl_bus_ch_lock_c) = '1') else rdata_align;
302 2 zero_gravi
 
303 57 zero_gravi
 
304 39 zero_gravi
  -- Data Access Arbiter --------------------------------------------------------------------
305 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
306 39 zero_gravi
  data_access_arbiter: process(rstn_i, clk_i)
307 2 zero_gravi
  begin
308 39 zero_gravi
    if (rstn_i = '0') then
309
      d_arbiter.wr_req    <= '0';
310
      d_arbiter.rd_req    <= '0';
311
      d_arbiter.err_align <= '0';
312
      d_arbiter.err_bus   <= '0';
313
    elsif rising_edge(clk_i) then
314
      -- data access request --
315
      if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
316
        d_arbiter.wr_req    <= ctrl_i(ctrl_bus_wr_c);
317
        d_arbiter.rd_req    <= ctrl_i(ctrl_bus_rd_c);
318
        d_arbiter.err_align <= d_misaligned;
319
        d_arbiter.err_bus   <= '0';
320
      else -- in progress
321 40 zero_gravi
        d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
322 57 zero_gravi
        d_arbiter.err_bus   <= (d_arbiter.err_bus or d_bus_err_i or (st_pmp_fault and d_arbiter.wr_req) or (ld_pmp_fault and d_arbiter.rd_req)) and
323
                               (not ctrl_i(ctrl_bus_derr_ack_c));
324 39 zero_gravi
        if (d_bus_ack_i = '1') or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort
325
          d_arbiter.wr_req <= '0';
326
          d_arbiter.rd_req <= '0';
327
        end if;
328
      end if;
329 12 zero_gravi
    end if;
330 39 zero_gravi
  end process data_access_arbiter;
331 12 zero_gravi
 
332 39 zero_gravi
  -- wait for bus transaction to finish --
333
  d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i);
334
 
335
  -- output data access error to controller --
336
  ma_load_o  <= d_arbiter.rd_req and d_arbiter.err_align;
337
  be_load_o  <= d_arbiter.rd_req and d_arbiter.err_bus;
338
  ma_store_o <= d_arbiter.wr_req and d_arbiter.err_align;
339
  be_store_o <= d_arbiter.wr_req and d_arbiter.err_bus;
340
 
341
  -- data bus (read/write)--
342
  d_bus_addr_o  <= mar;
343
  d_bus_wdata_o <= d_bus_wdata;
344
  d_bus_ben_o   <= d_bus_ben;
345 47 zero_gravi
  d_bus_we      <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned) and (not st_pmp_fault); -- no actual write when misaligned or PMP fault
346
  d_bus_re      <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault
347
  d_bus_we_o    <= d_bus_we_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_we;
348
  d_bus_re_o    <= d_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_re;
349 39 zero_gravi
  d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
350
  d_bus_rdata   <= d_bus_rdata_i;
351
 
352 47 zero_gravi
  -- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c --
353
  pmp_dbus_buffer: process(rstn_i, clk_i)
354
  begin
355
    if (rstn_i = '0') then
356
      d_bus_we_buf <= '0';
357
      d_bus_re_buf <= '0';
358
    elsif rising_edge(clk_i) then
359
      d_bus_we_buf <= d_bus_we;
360
      d_bus_re_buf <= d_bus_re;
361
    end if;
362
  end process pmp_dbus_buffer;
363 39 zero_gravi
 
364 57 zero_gravi
 
365
  -- Reservation Controller (LR/SC [A extension]) -------------------------------------------
366
  -- -------------------------------------------------------------------------------------------
367
  exclusive_access_controller: process(rstn_i, clk_i)
368 53 zero_gravi
  begin
369
    if (rstn_i = '0') then
370 57 zero_gravi
      exclusive_lock <= '0';
371 53 zero_gravi
    elsif rising_edge(clk_i) then
372
      if (CPU_EXTENSION_RISCV_A = true) then
373 57 zero_gravi
        if (ctrl_i(ctrl_trap_c) = '1') or (ctrl_i(ctrl_bus_de_lock_c) = '1') then -- remove lock if entering a trap or executing a non-load-reservate memory access
374
          exclusive_lock <= '0';
375
        elsif (ctrl_i(ctrl_bus_lock_c) = '1') then -- set new lock
376
          exclusive_lock <= '1';
377 53 zero_gravi
        end if;
378
      else
379 57 zero_gravi
        exclusive_lock <= '0';
380 53 zero_gravi
      end if;
381
    end if;
382 57 zero_gravi
  end process exclusive_access_controller;
383 47 zero_gravi
 
384 57 zero_gravi
  -- lock status for SC operation --
385
  exclusive_lock_status(data_width_c-1 downto 1) <= (others => '0');
386
  exclusive_lock_status(0) <= not exclusive_lock;
387 53 zero_gravi
 
388 57 zero_gravi
  -- output reservation status to control unit (to check if SC should write at all) --
389
  excl_state_o <= exclusive_lock;
390
 
391
  -- output to memory system --
392 64 zero_gravi
  i_bus_lock_o <= '0'; -- instruction fetches cannot be locked
393 57 zero_gravi
  d_bus_lock_o <= exclusive_lock;
394
 
395
 
396 12 zero_gravi
  -- Instruction Fetch Arbiter --------------------------------------------------------------
397
  -- -------------------------------------------------------------------------------------------
398 38 zero_gravi
  ifetch_arbiter: process(rstn_i, clk_i)
399 12 zero_gravi
  begin
400 38 zero_gravi
    if (rstn_i = '0') then
401
      i_arbiter.rd_req    <= '0';
402
      i_arbiter.err_align <= '0';
403
      i_arbiter.err_bus   <= '0';
404
    elsif rising_edge(clk_i) then
405 12 zero_gravi
      -- instruction fetch request --
406
      if (i_arbiter.rd_req = '0') then -- idle
407
        i_arbiter.rd_req    <= ctrl_i(ctrl_bus_if_c);
408
        i_arbiter.err_align <= i_misaligned;
409
        i_arbiter.err_bus   <= '0';
410 57 zero_gravi
      else -- in progres
411
        i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c));
412
        i_arbiter.err_bus   <= (i_arbiter.err_bus or i_bus_err_i or if_pmp_fault) and (not ctrl_i(ctrl_bus_ierr_ack_c));
413 28 zero_gravi
        if (i_bus_ack_i = '1') or (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for normal termination / CPU abort
414 23 zero_gravi
          i_arbiter.rd_req <= '0';
415 2 zero_gravi
        end if;
416
      end if;
417
    end if;
418 12 zero_gravi
  end process ifetch_arbiter;
419 2 zero_gravi
 
420 36 zero_gravi
  i_arbiter.wr_req <= '0'; -- instruction fetch is read-only
421
 
422 12 zero_gravi
  -- wait for bus transaction to finish --
423
  i_wait_o <= i_arbiter.rd_req and (not i_bus_ack_i);
424 2 zero_gravi
 
425 12 zero_gravi
  -- output instruction fetch error to controller --
426
  ma_instr_o <= i_arbiter.err_align;
427
  be_instr_o <= i_arbiter.err_bus;
428 11 zero_gravi
 
429 12 zero_gravi
  -- instruction bus (read-only) --
430 31 zero_gravi
  i_bus_addr_o  <= fetch_pc_i(data_width_c-1 downto 2) & "00"; -- instruction access is always 4-byte aligned (even for compressed instructions)
431 40 zero_gravi
  i_bus_wdata_o <= (others => '0'); -- instruction fetch is read-only
432 12 zero_gravi
  i_bus_ben_o   <= (others => '0');
433
  i_bus_we_o    <= '0';
434 47 zero_gravi
  i_bus_re      <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault
435
  i_bus_re_o    <= i_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else i_bus_re;
436 12 zero_gravi
  i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
437
  instr_o       <= i_bus_rdata_i;
438 2 zero_gravi
 
439 64 zero_gravi
  -- check instruction access address alignment --
440 39 zero_gravi
  i_misaligned <= '0' when (CPU_EXTENSION_RISCV_C = true) else -- no alignment exceptions possible when using C-extension
441
                  '1' when (fetch_pc_i(1) = '1') else '0'; -- 32-bit accesses only
442 2 zero_gravi
 
443 47 zero_gravi
  -- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c --
444
  pmp_ibus_buffer: process(rstn_i, clk_i)
445
  begin
446
    if (rstn_i = '0') then
447
      i_bus_re_buf <= '0';
448
    elsif rising_edge(clk_i) then
449
      i_bus_re_buf <= i_bus_re;
450
    end if;
451
  end process pmp_ibus_buffer;
452 2 zero_gravi
 
453 47 zero_gravi
 
454 15 zero_gravi
  -- Physical Memory Protection (PMP) -------------------------------------------------------
455
  -- -------------------------------------------------------------------------------------------
456 40 zero_gravi
  -- compute address masks (ITERATIVE!!!) --
457 56 zero_gravi
  pmp_masks: process(rstn_i, clk_i)
458 15 zero_gravi
  begin
459 56 zero_gravi
    if (rstn_i = '0') then
460
      pmp.addr_mask <= (others => (others => def_rst_val_c));
461
    elsif rising_edge(clk_i) then -- address mask computation (not the actual address check!) has a latency of max +32 cycles
462 42 zero_gravi
      for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
463 40 zero_gravi
        pmp.addr_mask(r) <= (others => '0');
464
        for i in pmp_g_c to data_width_c-1 loop
465
          pmp.addr_mask(r)(i) <= pmp.addr_mask(r)(i-1) or (not pmp_addr_i(r)(i-1));
466 17 zero_gravi
        end loop; -- i
467
      end loop; -- r
468
    end if;
469 15 zero_gravi
  end process pmp_masks;
470
 
471
 
472 40 zero_gravi
  -- address access check --
473
  pmp_address_check:
474 42 zero_gravi
  for r in 0 to PMP_NUM_REGIONS-1 generate -- iterate over all regions
475 40 zero_gravi
    pmp.region_i_addr(r) <= fetch_pc_i                             and pmp.addr_mask(r);
476
    pmp.region_d_addr(r) <= mar                                    and pmp.addr_mask(r);
477
    pmp.region_base(r)   <= pmp_addr_i(r)(data_width_c+1 downto 2) and pmp.addr_mask(r);
478
    --
479
    pmp.i_match(r) <= '1' when (pmp.region_i_addr(r)(data_width_c-1 downto pmp_g_c) = pmp.region_base(r)(data_width_c-1 downto pmp_g_c)) else '0';
480
    pmp.d_match(r) <= '1' when (pmp.region_d_addr(r)(data_width_c-1 downto pmp_g_c) = pmp.region_base(r)(data_width_c-1 downto pmp_g_c)) else '0';
481 16 zero_gravi
  end generate; -- r
482 15 zero_gravi
 
483
 
484 61 zero_gravi
  -- check access type and region's permissions --
485 36 zero_gravi
  pmp_check_permission: process(pmp, pmp_ctrl_i, ctrl_i)
486 15 zero_gravi
  begin
487 42 zero_gravi
    for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
488 36 zero_gravi
      if ((ctrl_i(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) = priv_mode_u_c) or (pmp_ctrl_i(r)(pmp_cfg_l_c) = '1')) and -- user privilege level or locked pmp entry -> enforce permissions also for machine mode
489 59 zero_gravi
         (pmp_ctrl_i(r)(pmp_cfg_ah_c downto pmp_cfg_al_c) /= pmp_off_mode_c) and -- active entry
490
         (ctrl_i(ctrl_debug_running_c) = '0') then -- disable PMP checks when in debug mode
491 15 zero_gravi
        pmp.if_fault(r) <= pmp.i_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_x_c)); -- fetch access match no execute permission
492
        pmp.ld_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_r_c)); -- load access match no read permission
493
        pmp.st_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_w_c)); -- store access match no write permission
494
      else
495
        pmp.if_fault(r) <= '0';
496
        pmp.ld_fault(r) <= '0';
497
        pmp.st_fault(r) <= '0';
498
      end if;
499
    end loop; -- r
500
  end process pmp_check_permission;
501
 
502
 
503
  -- final PMP access fault signals --
504 60 zero_gravi
  if_pmp_fault <= or_reduce_f(pmp.if_fault) when (PMP_NUM_REGIONS > 0) else '0';
505
  ld_pmp_fault <= or_reduce_f(pmp.ld_fault) when (PMP_NUM_REGIONS > 0) else '0';
506
  st_pmp_fault <= or_reduce_f(pmp.st_fault) when (PMP_NUM_REGIONS > 0) else '0';
507 15 zero_gravi
 
508
 
509 2 zero_gravi
end neorv32_cpu_bus_rtl;

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