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zero_gravi |
-- #################################################################################################
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-- # << NEORV32 - CPU Control >> #
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-- # ********************************************************************************************* #
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6 |
zero_gravi |
-- # CPU operation is split into a fetch engine (responsible for fetching an decompressing instr- #
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-- # uctions), an execute engine (responsible for actually executing the instructions), an inter- #
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-- # rupt and exception handling controller and the RISC-V status and control registers (CSRs). #
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zero_gravi |
-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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37 |
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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42 |
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library neorv32;
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use neorv32.neorv32_package.all;
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45 |
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46 |
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entity neorv32_cpu_control is
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47 |
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generic (
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48 |
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-- General --
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49 |
12 |
zero_gravi |
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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50 |
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HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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52 |
2 |
zero_gravi |
-- RISC-V CPU Extensions --
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12 |
zero_gravi |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true -- implement instruction stream sync.?
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2 |
zero_gravi |
);
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port (
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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63 |
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ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- status input --
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alu_wait_i : in std_ulogic; -- wait for ALU
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12 |
zero_gravi |
bus_i_wait_i : in std_ulogic; -- wait for bus
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bus_d_wait_i : in std_ulogic; -- wait for bus
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2 |
zero_gravi |
-- data input --
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instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
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alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU.add result
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-- data output --
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imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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6 |
zero_gravi |
fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
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curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
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next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)
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2 |
zero_gravi |
-- csr data interface --
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csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
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csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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14 |
zero_gravi |
-- interrupts (risc-v compliant) --
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msw_irq_i : in std_ulogic; -- machine software interrupt
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mext_irq_i : in std_ulogic; -- machine external interrupt
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2 |
zero_gravi |
mtime_irq_i : in std_ulogic; -- machine timer interrupt
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14 |
zero_gravi |
-- fast interrupts (custom) --
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firq_i : in std_ulogic_vector(3 downto 0);
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11 |
zero_gravi |
-- system time input from MTIME --
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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2 |
zero_gravi |
-- bus access exceptions --
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mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
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ma_instr_i : in std_ulogic; -- misaligned instruction address
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ma_load_i : in std_ulogic; -- misaligned load data address
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ma_store_i : in std_ulogic; -- misaligned store data address
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be_instr_i : in std_ulogic; -- bus error on instruction access
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be_load_i : in std_ulogic; -- bus error on load data access
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zero_gravi |
be_store_i : in std_ulogic -- bus error on store data access
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2 |
zero_gravi |
);
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end neorv32_cpu_control;
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architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
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6 |
zero_gravi |
-- instruction fetch enginge --
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zero_gravi |
type fetch_engine_state_t is (IFETCH_RESET, IFETCH_0, IFETCH_1, IFETCH_2);
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6 |
zero_gravi |
type fetch_engine_t is record
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state : fetch_engine_state_t;
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state_nxt : fetch_engine_state_t;
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i_buf : std_ulogic_vector(33 downto 0);
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i_buf_nxt : std_ulogic_vector(33 downto 0);
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i_buf2 : std_ulogic_vector(33 downto 0);
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i_buf2_nxt : std_ulogic_vector(33 downto 0);
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13 |
zero_gravi |
ci_input : std_ulogic_vector(15 downto 0); -- input to compressed instr. decoder
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6 |
zero_gravi |
i_buf_state : std_ulogic_vector(01 downto 0);
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i_buf_state_nxt : std_ulogic_vector(01 downto 0);
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pc_real : std_ulogic_vector(data_width_c-1 downto 0);
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pc_real_add : std_ulogic_vector(data_width_c-1 downto 0);
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pc_fetch : std_ulogic_vector(data_width_c-1 downto 0);
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pc_fetch_add : std_ulogic_vector(data_width_c-1 downto 0);
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reset : std_ulogic;
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bus_err_ack : std_ulogic;
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119 |
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end record;
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120 |
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signal fetch_engine : fetch_engine_t;
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121 |
2 |
zero_gravi |
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122 |
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-- pre-decoder --
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123 |
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signal ci_instr32 : std_ulogic_vector(31 downto 0);
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124 |
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signal ci_illegal : std_ulogic;
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125 |
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126 |
6 |
zero_gravi |
-- instrucion prefetch buffer (IPB) --
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type ipb_t is record
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128 |
13 |
zero_gravi |
wdata : std_ulogic_vector(35 downto 0);
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rdata : std_ulogic_vector(35 downto 0);
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130 |
6 |
zero_gravi |
waddr : std_ulogic_vector(31 downto 0);
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raddr : std_ulogic_vector(31 downto 0);
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status : std_ulogic;
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133 |
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free : std_ulogic;
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avail : std_ulogic;
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we : std_ulogic;
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re : std_ulogic;
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clear : std_ulogic;
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138 |
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end record;
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139 |
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signal ipb : ipb_t;
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140 |
2 |
zero_gravi |
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141 |
6 |
zero_gravi |
-- instruction execution engine --
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142 |
12 |
zero_gravi |
type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, CSR_ACCESS);
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143 |
6 |
zero_gravi |
type execute_engine_t is record
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144 |
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state : execute_engine_state_t;
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state_nxt : execute_engine_state_t;
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146 |
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i_reg : std_ulogic_vector(31 downto 0);
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147 |
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i_reg_nxt : std_ulogic_vector(31 downto 0);
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148 |
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is_ci : std_ulogic; -- current instruction is de-compressed instruction
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149 |
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is_ci_nxt : std_ulogic;
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150 |
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is_jump : std_ulogic; -- current instruction is jump instruction
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151 |
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is_jump_nxt : std_ulogic;
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152 |
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branch_taken : std_ulogic; -- branch condition fullfilled
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153 |
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pc : std_ulogic_vector(data_width_c-1 downto 0); -- actual PC, corresponding to current executed instruction
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154 |
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pc_nxt : std_ulogic_vector(data_width_c-1 downto 0);
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155 |
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next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next PC, corresponding to next instruction to be executed
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156 |
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last_pc : std_ulogic_vector(data_width_c-1 downto 0); -- PC of last executed instruction
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157 |
11 |
zero_gravi |
sleep : std_ulogic; -- CPU in sleep mode
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158 |
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sleep_nxt : std_ulogic; -- CPU in sleep mode
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159 |
6 |
zero_gravi |
end record;
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160 |
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signal execute_engine : execute_engine_t;
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161 |
2 |
zero_gravi |
|
162 |
12 |
zero_gravi |
signal next_pc_tmp : std_ulogic_vector(data_width_c-1 downto 0);
|
163 |
|
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|
164 |
6 |
zero_gravi |
-- trap controller --
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165 |
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type trap_ctrl_t is record
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166 |
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exc_buf : std_ulogic_vector(exception_width_c-1 downto 0);
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167 |
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exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer
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168 |
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irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0);
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169 |
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irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer
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170 |
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exc_ack : std_ulogic; -- acknowledge all exceptions
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171 |
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irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt
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172 |
|
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irq_ack_nxt : std_ulogic_vector(interrupt_width_c-1 downto 0);
|
173 |
14 |
zero_gravi |
cause : std_ulogic_vector(5 downto 0); -- trap ID (for "mcause"), only for hw
|
174 |
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cause_nxt : std_ulogic_vector(5 downto 0);
|
175 |
6 |
zero_gravi |
--
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176 |
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env_start : std_ulogic; -- start trap handler env
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177 |
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env_start_ack : std_ulogic; -- start of trap handler acknowledged
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178 |
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env_end : std_ulogic; -- end trap handler env
|
179 |
|
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--
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180 |
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instr_be : std_ulogic; -- instruction fetch bus error
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181 |
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instr_ma : std_ulogic; -- instruction fetch misaligned address
|
182 |
|
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instr_il : std_ulogic; -- illegal instruction
|
183 |
|
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env_call : std_ulogic;
|
184 |
|
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break_point : std_ulogic;
|
185 |
|
|
end record;
|
186 |
|
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signal trap_ctrl : trap_ctrl_t;
|
187 |
|
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|
188 |
|
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-- CPU control signals --
|
189 |
|
|
signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
|
190 |
2 |
zero_gravi |
|
191 |
6 |
zero_gravi |
-- fast bus access --
|
192 |
|
|
signal bus_fast_ir : std_ulogic;
|
193 |
2 |
zero_gravi |
|
194 |
6 |
zero_gravi |
-- RISC-V control and status registers (CSRs) --
|
195 |
|
|
type csr_t is record
|
196 |
|
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we : std_ulogic; -- write enable
|
197 |
|
|
we_nxt : std_ulogic;
|
198 |
|
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re : std_ulogic; -- read enable
|
199 |
|
|
re_nxt : std_ulogic;
|
200 |
|
|
mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
|
201 |
|
|
mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/-)
|
202 |
|
|
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
|
203 |
|
|
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
|
204 |
14 |
zero_gravi |
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W
|
205 |
|
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mie_firqe : std_ulogic_vector(3 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)
|
206 |
6 |
zero_gravi |
mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)
|
207 |
14 |
zero_gravi |
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/-)
|
208 |
12 |
zero_gravi |
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00
|
209 |
11 |
zero_gravi |
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W)
|
210 |
6 |
zero_gravi |
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
|
211 |
11 |
zero_gravi |
mcycle : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit
|
212 |
|
|
minstret : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit
|
213 |
12 |
zero_gravi |
mcycleh : std_ulogic_vector(19 downto 0); -- mcycleh (R/W) - REDUCED BIT-WIDTH!
|
214 |
|
|
minstreth : std_ulogic_vector(19 downto 0); -- minstreth (R/W) - REDUCED BIT-WIDTH!
|
215 |
6 |
zero_gravi |
end record;
|
216 |
|
|
signal csr : csr_t;
|
217 |
2 |
zero_gravi |
|
218 |
11 |
zero_gravi |
signal mcycle_msb : std_ulogic;
|
219 |
|
|
signal minstret_msb : std_ulogic;
|
220 |
12 |
zero_gravi |
signal systime : std_ulogic_vector(63 downto 0);
|
221 |
2 |
zero_gravi |
|
222 |
6 |
zero_gravi |
-- illegal instruction check --
|
223 |
2 |
zero_gravi |
signal illegal_instruction : std_ulogic;
|
224 |
|
|
signal illegal_register : std_ulogic; -- only for E-extension
|
225 |
|
|
signal illegal_compressed : std_ulogic; -- only fir C-extension
|
226 |
|
|
|
227 |
|
|
begin
|
228 |
|
|
|
229 |
6 |
zero_gravi |
-- ****************************************************************************************************************************
|
230 |
|
|
-- Instruction Fetch
|
231 |
|
|
-- ****************************************************************************************************************************
|
232 |
|
|
|
233 |
2 |
zero_gravi |
-- Compressed Instructions Recoding -------------------------------------------------------
|
234 |
|
|
-- -------------------------------------------------------------------------------------------
|
235 |
|
|
neorv32_cpu_decompressor_inst_true:
|
236 |
|
|
if (CPU_EXTENSION_RISCV_C = true) generate
|
237 |
|
|
neorv32_cpu_decompressor_inst: neorv32_cpu_decompressor
|
238 |
|
|
port map (
|
239 |
|
|
-- instruction input --
|
240 |
13 |
zero_gravi |
ci_instr16_i => fetch_engine.ci_input, -- compressed instruction input
|
241 |
2 |
zero_gravi |
-- instruction output --
|
242 |
|
|
ci_illegal_o => ci_illegal, -- is an illegal compressed instruction
|
243 |
|
|
ci_instr32_o => ci_instr32 -- 32-bit decompressed instruction
|
244 |
|
|
);
|
245 |
|
|
end generate;
|
246 |
|
|
|
247 |
|
|
neorv32_cpu_decompressor_inst_false:
|
248 |
|
|
if (CPU_EXTENSION_RISCV_C = false) generate
|
249 |
6 |
zero_gravi |
ci_instr32 <= (others => '0');
|
250 |
2 |
zero_gravi |
ci_illegal <= '0';
|
251 |
|
|
end generate;
|
252 |
|
|
|
253 |
|
|
|
254 |
6 |
zero_gravi |
-- Fetch Engine FSM Sync ------------------------------------------------------------------
|
255 |
|
|
-- -------------------------------------------------------------------------------------------
|
256 |
|
|
-- for registers that require a specific reset state --
|
257 |
|
|
fetch_engine_fsm_sync_rst: process(rstn_i, clk_i)
|
258 |
|
|
begin
|
259 |
|
|
if (rstn_i = '0') then
|
260 |
|
|
fetch_engine.state <= IFETCH_RESET;
|
261 |
|
|
elsif rising_edge(clk_i) then
|
262 |
|
|
if (fetch_engine.reset = '1') then
|
263 |
|
|
fetch_engine.state <= IFETCH_RESET;
|
264 |
|
|
else
|
265 |
|
|
fetch_engine.state <= fetch_engine.state_nxt;
|
266 |
|
|
end if;
|
267 |
|
|
end if;
|
268 |
|
|
end process fetch_engine_fsm_sync_rst;
|
269 |
|
|
|
270 |
|
|
|
271 |
|
|
-- for registers that DO NOT require a specific reset state --
|
272 |
|
|
fetch_engine_fsm_sync: process(clk_i)
|
273 |
|
|
begin
|
274 |
|
|
if rising_edge(clk_i) then
|
275 |
|
|
if (fetch_engine.state = IFETCH_RESET) then
|
276 |
|
|
fetch_engine.pc_fetch <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC
|
277 |
|
|
fetch_engine.pc_real <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC
|
278 |
|
|
else
|
279 |
|
|
fetch_engine.pc_real <= std_ulogic_vector(unsigned(fetch_engine.pc_real(data_width_c-1 downto 1) & '0') + unsigned(fetch_engine.pc_real_add(data_width_c-1 downto 1) & '0'));
|
280 |
|
|
fetch_engine.pc_fetch <= std_ulogic_vector(unsigned(fetch_engine.pc_fetch(data_width_c-1 downto 1) & '0') + unsigned(fetch_engine.pc_fetch_add(data_width_c-1 downto 1) & '0'));
|
281 |
|
|
end if;
|
282 |
|
|
--
|
283 |
|
|
fetch_engine.i_buf <= fetch_engine.i_buf_nxt;
|
284 |
|
|
fetch_engine.i_buf2 <= fetch_engine.i_buf2_nxt;
|
285 |
|
|
fetch_engine.i_buf_state <= fetch_engine.i_buf_state_nxt;
|
286 |
|
|
end if;
|
287 |
|
|
end process fetch_engine_fsm_sync;
|
288 |
|
|
|
289 |
12 |
zero_gravi |
-- PC output --
|
290 |
|
|
fetch_pc_o <= fetch_engine.pc_fetch(data_width_c-1 downto 1) & '0';
|
291 |
6 |
zero_gravi |
|
292 |
12 |
zero_gravi |
|
293 |
6 |
zero_gravi |
-- Fetch Engine FSM Comb ------------------------------------------------------------------
|
294 |
|
|
-- -------------------------------------------------------------------------------------------
|
295 |
13 |
zero_gravi |
fetch_engine_fsm_comb: process(fetch_engine, csr, ipb, instr_i, bus_i_wait_i, ci_instr32, ci_illegal, be_instr_i, ma_instr_i)
|
296 |
6 |
zero_gravi |
begin
|
297 |
|
|
-- arbiter defaults --
|
298 |
13 |
zero_gravi |
bus_fast_ir <= '0';
|
299 |
6 |
zero_gravi |
fetch_engine.state_nxt <= fetch_engine.state;
|
300 |
|
|
fetch_engine.pc_fetch_add <= (others => '0');
|
301 |
|
|
fetch_engine.pc_real_add <= (others => '0');
|
302 |
|
|
fetch_engine.i_buf_nxt <= fetch_engine.i_buf;
|
303 |
|
|
fetch_engine.i_buf2_nxt <= fetch_engine.i_buf2;
|
304 |
|
|
fetch_engine.i_buf_state_nxt <= fetch_engine.i_buf_state;
|
305 |
13 |
zero_gravi |
fetch_engine.ci_input <= fetch_engine.i_buf2(15 downto 00);
|
306 |
6 |
zero_gravi |
fetch_engine.bus_err_ack <= '0';
|
307 |
|
|
|
308 |
|
|
-- instruction prefetch buffer interface --
|
309 |
|
|
ipb.we <= '0';
|
310 |
|
|
ipb.clear <= '0';
|
311 |
13 |
zero_gravi |
ipb.wdata <= '0' & fetch_engine.i_buf2(33 downto 32) & '0' & fetch_engine.i_buf2(31 downto 0);
|
312 |
6 |
zero_gravi |
ipb.waddr <= fetch_engine.pc_real(data_width_c-1 downto 1) & '0';
|
313 |
|
|
|
314 |
|
|
-- state machine --
|
315 |
|
|
case fetch_engine.state is
|
316 |
|
|
|
317 |
11 |
zero_gravi |
when IFETCH_RESET => -- reset engine, prefetch buffer, get appilcation PC
|
318 |
6 |
zero_gravi |
-- ------------------------------------------------------------
|
319 |
|
|
fetch_engine.i_buf_state_nxt <= (others => '0');
|
320 |
|
|
ipb.clear <= '1'; -- clear instruction prefetch buffer
|
321 |
|
|
fetch_engine.state_nxt <= IFETCH_0;
|
322 |
|
|
|
323 |
|
|
when IFETCH_0 => -- output current PC to bus system, request 32-bit word
|
324 |
|
|
-- ------------------------------------------------------------
|
325 |
12 |
zero_gravi |
bus_fast_ir <= '1'; -- fast instruction fetch request
|
326 |
|
|
fetch_engine.state_nxt <= IFETCH_1;
|
327 |
6 |
zero_gravi |
|
328 |
|
|
when IFETCH_1 => -- store data from memory to buffer(s)
|
329 |
|
|
-- ------------------------------------------------------------
|
330 |
12 |
zero_gravi |
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
|
331 |
|
|
fetch_engine.i_buf_nxt <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store data word and exception info
|
332 |
|
|
fetch_engine.i_buf2_nxt <= fetch_engine.i_buf;
|
333 |
|
|
fetch_engine.i_buf_state_nxt <= fetch_engine.i_buf_state(0) & '1';
|
334 |
|
|
fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them
|
335 |
|
|
if (fetch_engine.i_buf_state(0) = '1') then -- buffer filled?
|
336 |
|
|
fetch_engine.state_nxt <= IFETCH_2;
|
337 |
|
|
else
|
338 |
|
|
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
|
339 |
|
|
fetch_engine.state_nxt <= IFETCH_0; -- get another instruction word
|
340 |
|
|
end if;
|
341 |
6 |
zero_gravi |
end if;
|
342 |
11 |
zero_gravi |
|
343 |
12 |
zero_gravi |
when IFETCH_2 => -- construct instruction word and issue
|
344 |
6 |
zero_gravi |
-- ------------------------------------------------------------
|
345 |
13 |
zero_gravi |
if (fetch_engine.pc_fetch(1) = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned
|
346 |
|
|
fetch_engine.ci_input <= fetch_engine.i_buf2(15 downto 00);
|
347 |
6 |
zero_gravi |
|
348 |
13 |
zero_gravi |
if (ipb.free = '1') then -- free entry in buffer?
|
349 |
|
|
ipb.we <= '1';
|
350 |
|
|
if (fetch_engine.i_buf2(01 downto 00) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed
|
351 |
|
|
ipb.wdata <= '0' & fetch_engine.i_buf2(33 downto 32) & '0' & fetch_engine.i_buf2(31 downto 0);
|
352 |
|
|
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
|
353 |
|
|
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
|
354 |
|
|
fetch_engine.state_nxt <= IFETCH_0;
|
355 |
|
|
else -- compressed
|
356 |
|
|
ipb.wdata <= ci_illegal & fetch_engine.i_buf2(33 downto 32) & '1' & ci_instr32;
|
357 |
|
|
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
|
358 |
|
|
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
|
359 |
|
|
fetch_engine.state_nxt <= IFETCH_2; -- try to get another 16-bit instruction word in next round
|
360 |
|
|
end if;
|
361 |
|
|
end if;
|
362 |
12 |
zero_gravi |
|
363 |
13 |
zero_gravi |
else -- 16-bit aligned
|
364 |
|
|
fetch_engine.ci_input <= fetch_engine.i_buf2(31 downto 16);
|
365 |
12 |
zero_gravi |
|
366 |
13 |
zero_gravi |
if (ipb.free = '1') then -- free entry in buffer?
|
367 |
|
|
ipb.we <= '1';
|
368 |
|
|
if (fetch_engine.i_buf2(17 downto 16) = "11") then -- uncompressed
|
369 |
|
|
ipb.wdata <= '0' & fetch_engine.i_buf(33 downto 32) & '0' & fetch_engine.i_buf(15 downto 00) & fetch_engine.i_buf2(31 downto 16);
|
370 |
|
|
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
|
371 |
|
|
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
|
372 |
|
|
fetch_engine.state_nxt <= IFETCH_0;
|
373 |
|
|
else -- uncompressed
|
374 |
|
|
ipb.wdata <= ci_illegal & fetch_engine.i_buf(33 downto 32) & '1' & ci_instr32;
|
375 |
|
|
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
|
376 |
|
|
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
|
377 |
|
|
fetch_engine.state_nxt <= IFETCH_0;
|
378 |
|
|
end if;
|
379 |
6 |
zero_gravi |
end if;
|
380 |
13 |
zero_gravi |
end if;
|
381 |
6 |
zero_gravi |
|
382 |
|
|
when others => -- undefined
|
383 |
|
|
-- ------------------------------------------------------------
|
384 |
|
|
fetch_engine.state_nxt <= IFETCH_RESET;
|
385 |
|
|
|
386 |
|
|
end case;
|
387 |
|
|
end process fetch_engine_fsm_comb;
|
388 |
|
|
|
389 |
|
|
|
390 |
|
|
-- ****************************************************************************************************************************
|
391 |
|
|
-- Instruction Prefetch Buffer
|
392 |
|
|
-- ****************************************************************************************************************************
|
393 |
|
|
|
394 |
|
|
|
395 |
|
|
-- Instruction Prefetch Buffer Stage ------------------------------------------------------
|
396 |
|
|
-- -------------------------------------------------------------------------------------------
|
397 |
13 |
zero_gravi |
instr_prefetch_buffer: process(rstn_i, clk_i) -- once upon a time, this was a fifo with 8 entries
|
398 |
6 |
zero_gravi |
begin
|
399 |
|
|
if (rstn_i = '0') then
|
400 |
|
|
ipb.status <= '0';
|
401 |
|
|
ipb.rdata <= (others => '0');
|
402 |
|
|
ipb.raddr <= (others => '0');
|
403 |
|
|
elsif rising_edge(clk_i) then
|
404 |
|
|
if (ipb.clear = '1') then
|
405 |
|
|
ipb.status <= '0';
|
406 |
|
|
elsif (ipb.we = '1') then
|
407 |
|
|
ipb.status <= '1';
|
408 |
|
|
elsif (ipb.re = '1') then
|
409 |
|
|
ipb.status <= '0';
|
410 |
|
|
end if;
|
411 |
|
|
if (ipb.we = '1') then
|
412 |
|
|
ipb.rdata <= ipb.wdata;
|
413 |
|
|
ipb.raddr <= ipb.waddr;
|
414 |
|
|
end if;
|
415 |
|
|
end if;
|
416 |
|
|
end process instr_prefetch_buffer;
|
417 |
|
|
|
418 |
|
|
-- status --
|
419 |
|
|
ipb.free <= not ipb.status;
|
420 |
|
|
ipb.avail <= ipb.status;
|
421 |
|
|
|
422 |
|
|
|
423 |
|
|
-- ****************************************************************************************************************************
|
424 |
|
|
-- Instruction Execution
|
425 |
|
|
-- ****************************************************************************************************************************
|
426 |
|
|
|
427 |
|
|
|
428 |
2 |
zero_gravi |
-- Immediate Generator --------------------------------------------------------------------
|
429 |
|
|
-- -------------------------------------------------------------------------------------------
|
430 |
|
|
imm_gen: process(clk_i)
|
431 |
|
|
begin
|
432 |
|
|
if rising_edge(clk_i) then
|
433 |
6 |
zero_gravi |
case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is
|
434 |
2 |
zero_gravi |
when opcode_store_c => -- S-immediate
|
435 |
6 |
zero_gravi |
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
|
436 |
|
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
437 |
|
|
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
|
438 |
|
|
imm_o(00) <= execute_engine.i_reg(07);
|
439 |
2 |
zero_gravi |
when opcode_branch_c => -- B-immediate
|
440 |
6 |
zero_gravi |
imm_o(31 downto 12) <= (others => execute_engine.i_reg(31)); -- sign extension
|
441 |
|
|
imm_o(11) <= execute_engine.i_reg(07);
|
442 |
|
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
443 |
|
|
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
|
444 |
|
|
imm_o(00) <= '0';
|
445 |
2 |
zero_gravi |
when opcode_lui_c | opcode_auipc_c => -- U-immediate
|
446 |
6 |
zero_gravi |
imm_o(31 downto 20) <= execute_engine.i_reg(31 downto 20);
|
447 |
|
|
imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);
|
448 |
|
|
imm_o(11 downto 00) <= (others => '0');
|
449 |
2 |
zero_gravi |
when opcode_jal_c => -- J-immediate
|
450 |
6 |
zero_gravi |
imm_o(31 downto 20) <= (others => execute_engine.i_reg(31)); -- sign extension
|
451 |
|
|
imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);
|
452 |
|
|
imm_o(11) <= execute_engine.i_reg(20);
|
453 |
|
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
454 |
|
|
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
|
455 |
|
|
imm_o(00) <= '0';
|
456 |
2 |
zero_gravi |
when opcode_syscsr_c => -- CSR-immediate
|
457 |
6 |
zero_gravi |
imm_o(31 downto 05) <= (others => '0');
|
458 |
|
|
imm_o(04 downto 00) <= execute_engine.i_reg(19 downto 15);
|
459 |
2 |
zero_gravi |
when others => -- I-immediate
|
460 |
6 |
zero_gravi |
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
|
461 |
|
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
462 |
|
|
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
|
463 |
|
|
imm_o(00) <= execute_engine.i_reg(20);
|
464 |
2 |
zero_gravi |
end case;
|
465 |
|
|
end if;
|
466 |
|
|
end process imm_gen;
|
467 |
|
|
|
468 |
|
|
|
469 |
|
|
-- Branch Condition Check -----------------------------------------------------------------
|
470 |
|
|
-- -------------------------------------------------------------------------------------------
|
471 |
6 |
zero_gravi |
branch_check: process(execute_engine.i_reg, cmp_i)
|
472 |
2 |
zero_gravi |
begin
|
473 |
6 |
zero_gravi |
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
474 |
2 |
zero_gravi |
when funct3_beq_c => -- branch if equal
|
475 |
6 |
zero_gravi |
execute_engine.branch_taken <= cmp_i(alu_cmp_equal_c);
|
476 |
2 |
zero_gravi |
when funct3_bne_c => -- branch if not equal
|
477 |
6 |
zero_gravi |
execute_engine.branch_taken <= not cmp_i(alu_cmp_equal_c);
|
478 |
2 |
zero_gravi |
when funct3_blt_c | funct3_bltu_c => -- branch if less (signed/unsigned)
|
479 |
6 |
zero_gravi |
execute_engine.branch_taken <= cmp_i(alu_cmp_less_c);
|
480 |
2 |
zero_gravi |
when funct3_bge_c | funct3_bgeu_c => -- branch if greater or equal (signed/unsigned)
|
481 |
6 |
zero_gravi |
execute_engine.branch_taken <= not cmp_i(alu_cmp_less_c);
|
482 |
2 |
zero_gravi |
when others => -- undefined
|
483 |
6 |
zero_gravi |
execute_engine.branch_taken <= '0';
|
484 |
2 |
zero_gravi |
end case;
|
485 |
|
|
end process branch_check;
|
486 |
|
|
|
487 |
|
|
|
488 |
6 |
zero_gravi |
-- Execute Engine FSM Sync ----------------------------------------------------------------
|
489 |
2 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
490 |
12 |
zero_gravi |
-- for registers that DO require a specific reset state --
|
491 |
6 |
zero_gravi |
execute_engine_fsm_sync_rst: process(rstn_i, clk_i)
|
492 |
2 |
zero_gravi |
begin
|
493 |
|
|
if (rstn_i = '0') then
|
494 |
12 |
zero_gravi |
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
|
495 |
|
|
execute_engine.last_pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
|
496 |
|
|
execute_engine.state <= SYS_WAIT;
|
497 |
13 |
zero_gravi |
execute_engine.sleep <= '0';
|
498 |
2 |
zero_gravi |
elsif rising_edge(clk_i) then
|
499 |
13 |
zero_gravi |
execute_engine.pc <= execute_engine.pc_nxt(data_width_c-1 downto 1) & '0';
|
500 |
6 |
zero_gravi |
if (execute_engine.state = EXECUTE) then
|
501 |
|
|
execute_engine.last_pc <= execute_engine.pc(data_width_c-1 downto 1) & '0';
|
502 |
|
|
end if;
|
503 |
12 |
zero_gravi |
execute_engine.state <= execute_engine.state_nxt;
|
504 |
11 |
zero_gravi |
execute_engine.sleep <= execute_engine.sleep_nxt;
|
505 |
2 |
zero_gravi |
end if;
|
506 |
6 |
zero_gravi |
end process execute_engine_fsm_sync_rst;
|
507 |
2 |
zero_gravi |
|
508 |
6 |
zero_gravi |
|
509 |
12 |
zero_gravi |
-- for registers that do NOT require a specific reset state --
|
510 |
6 |
zero_gravi |
execute_engine_fsm_sync: process(clk_i)
|
511 |
2 |
zero_gravi |
begin
|
512 |
|
|
if rising_edge(clk_i) then
|
513 |
6 |
zero_gravi |
execute_engine.i_reg <= execute_engine.i_reg_nxt;
|
514 |
|
|
execute_engine.is_ci <= execute_engine.is_ci_nxt;
|
515 |
|
|
execute_engine.is_jump <= execute_engine.is_jump_nxt;
|
516 |
|
|
-- control signals --
|
517 |
|
|
ctrl <= ctrl_nxt;
|
518 |
2 |
zero_gravi |
end if;
|
519 |
6 |
zero_gravi |
end process execute_engine_fsm_sync;
|
520 |
2 |
zero_gravi |
|
521 |
6 |
zero_gravi |
-- PC output --
|
522 |
12 |
zero_gravi |
next_pc_tmp <= std_ulogic_vector(unsigned(execute_engine.pc) + 2) when (execute_engine.is_ci = '1') else std_ulogic_vector(unsigned(execute_engine.pc) + 4);
|
523 |
|
|
execute_engine.next_pc <= next_pc_tmp(data_width_c-1 downto 1) & '0';
|
524 |
|
|
next_pc_o <= next_pc_tmp(data_width_c-1 downto 1) & '0';
|
525 |
|
|
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0';
|
526 |
6 |
zero_gravi |
|
527 |
|
|
|
528 |
|
|
-- CPU Control Bus Output -----------------------------------------------------------------
|
529 |
|
|
-- -------------------------------------------------------------------------------------------
|
530 |
11 |
zero_gravi |
ctrl_output: process(ctrl, execute_engine, fetch_engine, trap_ctrl, csr, bus_fast_ir)
|
531 |
2 |
zero_gravi |
begin
|
532 |
|
|
ctrl_o <= ctrl;
|
533 |
|
|
-- direct output of register addresses --
|
534 |
6 |
zero_gravi |
ctrl_o(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c);
|
535 |
|
|
ctrl_o(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c);
|
536 |
|
|
ctrl_o(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c);
|
537 |
12 |
zero_gravi |
-- fast bus access requests --
|
538 |
6 |
zero_gravi |
ctrl_o(ctrl_bus_if_c) <= ctrl(ctrl_bus_if_c) or bus_fast_ir;
|
539 |
12 |
zero_gravi |
-- bus error control --
|
540 |
|
|
ctrl_o(ctrl_bus_ierr_ack_c) <= fetch_engine.bus_err_ack;
|
541 |
|
|
ctrl_o(ctrl_bus_derr_ack_c) <= trap_ctrl.env_start_ack;
|
542 |
6 |
zero_gravi |
end process ctrl_output;
|
543 |
2 |
zero_gravi |
|
544 |
|
|
|
545 |
6 |
zero_gravi |
-- Execute Engine FSM Comb ----------------------------------------------------------------
|
546 |
|
|
-- -------------------------------------------------------------------------------------------
|
547 |
|
|
execute_engine_fsm_comb: process(execute_engine, fetch_engine, ipb, trap_ctrl, csr, ctrl,
|
548 |
12 |
zero_gravi |
alu_add_i, alu_wait_i, bus_d_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i)
|
549 |
2 |
zero_gravi |
variable alu_immediate_v : std_ulogic;
|
550 |
|
|
variable alu_operation_v : std_ulogic_vector(2 downto 0);
|
551 |
|
|
variable rs1_is_r0_v : std_ulogic;
|
552 |
|
|
begin
|
553 |
|
|
-- arbiter defaults --
|
554 |
6 |
zero_gravi |
execute_engine.state_nxt <= execute_engine.state;
|
555 |
|
|
execute_engine.i_reg_nxt <= execute_engine.i_reg;
|
556 |
|
|
execute_engine.is_jump_nxt <= '0';
|
557 |
|
|
execute_engine.is_ci_nxt <= execute_engine.is_ci;
|
558 |
13 |
zero_gravi |
execute_engine.pc_nxt <= execute_engine.pc;
|
559 |
11 |
zero_gravi |
execute_engine.sleep_nxt <= execute_engine.sleep;
|
560 |
2 |
zero_gravi |
|
561 |
6 |
zero_gravi |
-- instruction dispatch --
|
562 |
|
|
fetch_engine.reset <= '0';
|
563 |
|
|
ipb.re <= '0';
|
564 |
2 |
zero_gravi |
|
565 |
6 |
zero_gravi |
-- trap environment control --
|
566 |
|
|
trap_ctrl.env_start_ack <= '0';
|
567 |
|
|
trap_ctrl.env_end <= '0';
|
568 |
|
|
|
569 |
2 |
zero_gravi |
-- exception trigger --
|
570 |
6 |
zero_gravi |
trap_ctrl.instr_be <= '0';
|
571 |
|
|
trap_ctrl.instr_ma <= '0';
|
572 |
|
|
trap_ctrl.env_call <= '0';
|
573 |
|
|
trap_ctrl.break_point <= '0';
|
574 |
13 |
zero_gravi |
illegal_compressed <= '0';
|
575 |
2 |
zero_gravi |
|
576 |
6 |
zero_gravi |
-- CSR access --
|
577 |
|
|
csr.we_nxt <= '0';
|
578 |
|
|
csr.re_nxt <= '0';
|
579 |
|
|
|
580 |
2 |
zero_gravi |
-- control defaults --
|
581 |
|
|
ctrl_nxt <= (others => '0'); -- all off at first
|
582 |
6 |
zero_gravi |
if (execute_engine.i_reg(instr_opcode_lsb_c+4) = '1') then -- ALU ops
|
583 |
|
|
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation (SLTIU, SLTU)
|
584 |
2 |
zero_gravi |
else -- branches
|
585 |
6 |
zero_gravi |
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches (BLTU, BGEU)
|
586 |
2 |
zero_gravi |
end if;
|
587 |
12 |
zero_gravi |
ctrl_nxt(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU)
|
588 |
13 |
zero_gravi |
ctrl_nxt(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction (left/right)
|
589 |
|
|
ctrl_nxt(ctrl_alu_shift_ar_c) <= execute_engine.i_reg(30); -- is arithmetic shift
|
590 |
6 |
zero_gravi |
ctrl_nxt(ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- transfer size lsb (00=byte, 01=half-word)
|
591 |
|
|
ctrl_nxt(ctrl_bus_size_msb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- transfer size msb (10=word, 11=?)
|
592 |
|
|
ctrl_nxt(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c); -- CP operation
|
593 |
12 |
zero_gravi |
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- only CP0 (MULDIV) implemented yet
|
594 |
2 |
zero_gravi |
|
595 |
|
|
-- is immediate operation? --
|
596 |
|
|
alu_immediate_v := '0';
|
597 |
6 |
zero_gravi |
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') then
|
598 |
2 |
zero_gravi |
alu_immediate_v := '1';
|
599 |
|
|
end if;
|
600 |
|
|
|
601 |
6 |
zero_gravi |
-- alu operation re-coding --
|
602 |
|
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
603 |
2 |
zero_gravi |
when funct3_subadd_c => -- SUB / ADD(I)
|
604 |
6 |
zero_gravi |
if (alu_immediate_v = '0') and (execute_engine.i_reg(instr_funct7_msb_c-1) = '1') then -- not immediate and funct7 = SUB
|
605 |
2 |
zero_gravi |
alu_operation_v := alu_cmd_sub_c;
|
606 |
|
|
else
|
607 |
|
|
alu_operation_v := alu_cmd_add_c;
|
608 |
|
|
end if;
|
609 |
|
|
when funct3_sll_c => alu_operation_v := alu_cmd_shift_c; -- SLL(I)
|
610 |
6 |
zero_gravi |
when funct3_slt_c => alu_operation_v := alu_cmd_slt_c; -- SLT(I)
|
611 |
|
|
when funct3_sltu_c => alu_operation_v := alu_cmd_slt_c; -- SLTU(I)
|
612 |
|
|
when funct3_xor_c => alu_operation_v := alu_cmd_xor_c; -- XOR(I)
|
613 |
2 |
zero_gravi |
when funct3_sr_c => alu_operation_v := alu_cmd_shift_c; -- SRL(I) / SRA(I)
|
614 |
6 |
zero_gravi |
when funct3_or_c => alu_operation_v := alu_cmd_or_c; -- OR(I)
|
615 |
|
|
when funct3_and_c => alu_operation_v := alu_cmd_and_c; -- AND(I)
|
616 |
3 |
zero_gravi |
when others => alu_operation_v := (others => '0'); -- undefined
|
617 |
2 |
zero_gravi |
end case;
|
618 |
|
|
|
619 |
|
|
-- is rs1 = r0? --
|
620 |
|
|
rs1_is_r0_v := '0';
|
621 |
6 |
zero_gravi |
if (execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
|
622 |
2 |
zero_gravi |
rs1_is_r0_v := '1';
|
623 |
|
|
end if;
|
624 |
|
|
|
625 |
6 |
zero_gravi |
-- state machine --
|
626 |
|
|
case execute_engine.state is
|
627 |
2 |
zero_gravi |
|
628 |
7 |
zero_gravi |
when SYS_WAIT => -- Delay cycle (used to wait for side effects to kick in)
|
629 |
2 |
zero_gravi |
-- ------------------------------------------------------------
|
630 |
6 |
zero_gravi |
execute_engine.state_nxt <= DISPATCH;
|
631 |
2 |
zero_gravi |
|
632 |
6 |
zero_gravi |
when DISPATCH => -- Get new command from instruction prefetch buffer (IPB)
|
633 |
|
|
-- ------------------------------------------------------------
|
634 |
13 |
zero_gravi |
if (ipb.avail = '1') then -- instruction available?
|
635 |
|
|
ipb.re <= '1';
|
636 |
|
|
trap_ctrl.instr_ma <= ipb.rdata(33); -- misaligned instruction fetch address
|
637 |
|
|
trap_ctrl.instr_be <= ipb.rdata(34); -- bus access fault druing instrucion fetch
|
638 |
|
|
illegal_compressed <= ipb.rdata(35); -- invalid decompressed instruction
|
639 |
14 |
zero_gravi |
execute_engine.is_ci_nxt <= ipb.rdata(32); -- flag to indicate this is a compressed instruction beeing executed
|
640 |
|
|
execute_engine.i_reg_nxt <= ipb.rdata(31 downto 0);
|
641 |
|
|
execute_engine.pc_nxt <= ipb.raddr; -- the PC according to the current instruction
|
642 |
|
|
-- ipb.rdata(35) is not immediately checked here!
|
643 |
|
|
if (execute_engine.sleep = '1') or (trap_ctrl.env_start = '1') or ((ipb.rdata(33) or ipb.rdata(34)) = '1') then
|
644 |
13 |
zero_gravi |
execute_engine.state_nxt <= TRAP;
|
645 |
|
|
else
|
646 |
14 |
zero_gravi |
execute_engine.state_nxt <= EXECUTE;
|
647 |
13 |
zero_gravi |
end if;
|
648 |
|
|
end if;
|
649 |
2 |
zero_gravi |
|
650 |
11 |
zero_gravi |
when TRAP => -- Start trap environment (also used as cpu sleep state)
|
651 |
2 |
zero_gravi |
-- ------------------------------------------------------------
|
652 |
11 |
zero_gravi |
fetch_engine.reset <= '1';
|
653 |
13 |
zero_gravi |
if (trap_ctrl.env_start = '1') then -- check here again if we came directly from DISPATCH
|
654 |
6 |
zero_gravi |
trap_ctrl.env_start_ack <= '1';
|
655 |
13 |
zero_gravi |
execute_engine.pc_nxt <= csr.mtvec;
|
656 |
11 |
zero_gravi |
execute_engine.sleep_nxt <= '0'; -- waky waky
|
657 |
7 |
zero_gravi |
execute_engine.state_nxt <= SYS_WAIT;
|
658 |
2 |
zero_gravi |
end if;
|
659 |
|
|
|
660 |
6 |
zero_gravi |
when EXECUTE => -- Decode and execute instruction
|
661 |
2 |
zero_gravi |
-- ------------------------------------------------------------
|
662 |
6 |
zero_gravi |
case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is
|
663 |
2 |
zero_gravi |
|
664 |
|
|
when opcode_alu_c | opcode_alui_c => -- ALU operation
|
665 |
|
|
-- ------------------------------------------------------------
|
666 |
|
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- use RS1 as ALU.OPA
|
667 |
|
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= alu_immediate_v; -- use IMM as ALU.OPB for immediate operations
|
668 |
|
|
ctrl_nxt(ctrl_alu_opc_mux_c) <= not alu_immediate_v;
|
669 |
|
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_operation_v; -- actual ALU operation
|
670 |
|
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
|
671 |
11 |
zero_gravi |
-- multi cycle alu operation? --
|
672 |
|
|
if (alu_operation_v = alu_cmd_shift_c) or -- shift operation
|
673 |
|
|
((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and
|
674 |
12 |
zero_gravi |
(execute_engine.i_reg(instr_funct7_lsb_c) = '1')) then -- MULDIV?
|
675 |
6 |
zero_gravi |
execute_engine.state_nxt <= ALU_WAIT;
|
676 |
2 |
zero_gravi |
else
|
677 |
|
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
678 |
6 |
zero_gravi |
execute_engine.state_nxt <= DISPATCH;
|
679 |
2 |
zero_gravi |
end if;
|
680 |
11 |
zero_gravi |
-- cp access? --
|
681 |
|
|
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and
|
682 |
12 |
zero_gravi |
(execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV?
|
683 |
11 |
zero_gravi |
ctrl_nxt(ctrl_cp_use_c) <= '1'; -- use CP
|
684 |
|
|
end if;
|
685 |
2 |
zero_gravi |
|
686 |
11 |
zero_gravi |
|
687 |
2 |
zero_gravi |
when opcode_lui_c | opcode_auipc_c => -- load upper immediate (add to PC)
|
688 |
|
|
-- ------------------------------------------------------------
|
689 |
12 |
zero_gravi |
ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- force RS1 = r0 (only relevant for LUI)
|
690 |
6 |
zero_gravi |
if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_auipc_c) then -- AUIPC
|
691 |
2 |
zero_gravi |
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '1'; -- use PC as ALU.OPA
|
692 |
|
|
else -- LUI
|
693 |
|
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- use RS1 as ALU.OPA
|
694 |
|
|
end if;
|
695 |
6 |
zero_gravi |
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- use IMM as ALU.OPB
|
696 |
2 |
zero_gravi |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_add_c; -- actual ALU operation
|
697 |
|
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
|
698 |
|
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
699 |
6 |
zero_gravi |
execute_engine.state_nxt <= DISPATCH;
|
700 |
2 |
zero_gravi |
|
701 |
|
|
when opcode_load_c | opcode_store_c => -- load/store
|
702 |
|
|
-- ------------------------------------------------------------
|
703 |
|
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- use RS1 as ALU.OPA
|
704 |
|
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- use IMM as ALU.OPB
|
705 |
|
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_add_c; -- actual ALU operation
|
706 |
6 |
zero_gravi |
ctrl_nxt(ctrl_bus_mar_we_c) <= '1'; -- write to MAR
|
707 |
|
|
ctrl_nxt(ctrl_bus_mdo_we_c) <= '1'; -- write to MDO (only relevant for stores)
|
708 |
12 |
zero_gravi |
execute_engine.state_nxt <= LOADSTORE_0;
|
709 |
2 |
zero_gravi |
|
710 |
|
|
when opcode_branch_c => -- branch instruction
|
711 |
|
|
-- ------------------------------------------------------------
|
712 |
|
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '1'; -- use PC as ALU.OPA
|
713 |
|
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- use IMM as ALU.OPB
|
714 |
6 |
zero_gravi |
ctrl_nxt(ctrl_alu_opc_mux_c) <= '1'; -- use RS2 as ALU.OPC
|
715 |
|
|
execute_engine.state_nxt <= BRANCH;
|
716 |
2 |
zero_gravi |
|
717 |
|
|
when opcode_jal_c | opcode_jalr_c => -- jump and link (with register)
|
718 |
|
|
-- ------------------------------------------------------------
|
719 |
|
|
-- compute target address --
|
720 |
6 |
zero_gravi |
if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_jal_c) then -- JAL
|
721 |
2 |
zero_gravi |
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '1'; -- use PC as ALU.OPA
|
722 |
|
|
else -- JALR
|
723 |
|
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- use RS1 as ALU.OPA
|
724 |
|
|
end if;
|
725 |
|
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- use IMM as ALU.OPB
|
726 |
|
|
-- save return address --
|
727 |
13 |
zero_gravi |
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "10"; -- RF input = next PC (save return address)
|
728 |
2 |
zero_gravi |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
729 |
6 |
zero_gravi |
--
|
730 |
|
|
execute_engine.is_jump_nxt <= '1'; -- this is a jump operation
|
731 |
|
|
execute_engine.state_nxt <= BRANCH;
|
732 |
2 |
zero_gravi |
|
733 |
8 |
zero_gravi |
when opcode_fence_c => -- fence operations
|
734 |
|
|
-- ------------------------------------------------------------
|
735 |
12 |
zero_gravi |
execute_engine.pc_nxt <= execute_engine.next_pc; -- "refetch" next instruction (only relevant for fencei)
|
736 |
|
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCEI
|
737 |
|
|
fetch_engine.reset <= '1';
|
738 |
|
|
ctrl_nxt(ctrl_bus_fencei_c) <= '1';
|
739 |
8 |
zero_gravi |
end if;
|
740 |
12 |
zero_gravi |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
|
741 |
|
|
ctrl_nxt(ctrl_bus_fence_c) <= '1';
|
742 |
|
|
end if;
|
743 |
|
|
execute_engine.state_nxt <= SYS_WAIT;
|
744 |
8 |
zero_gravi |
|
745 |
2 |
zero_gravi |
when opcode_syscsr_c => -- system/csr access
|
746 |
|
|
-- ------------------------------------------------------------
|
747 |
13 |
zero_gravi |
csr.re_nxt <= '1'; -- always read CSR - regardless of actual operation
|
748 |
6 |
zero_gravi |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system
|
749 |
|
|
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is
|
750 |
11 |
zero_gravi |
when funct12_ecall_c => -- ECALL
|
751 |
6 |
zero_gravi |
trap_ctrl.env_call <= '1';
|
752 |
11 |
zero_gravi |
when funct12_ebreak_c => -- EBREAK
|
753 |
6 |
zero_gravi |
trap_ctrl.break_point <= '1';
|
754 |
11 |
zero_gravi |
when funct12_mret_c => -- MRET
|
755 |
|
|
trap_ctrl.env_end <= '1';
|
756 |
13 |
zero_gravi |
execute_engine.pc_nxt <= csr.mepc;
|
757 |
11 |
zero_gravi |
fetch_engine.reset <= '1';
|
758 |
|
|
when funct12_wfi_c => -- WFI = "CPU sleep"
|
759 |
|
|
execute_engine.sleep_nxt <= '1'; -- good night
|
760 |
6 |
zero_gravi |
when others => -- undefined
|
761 |
|
|
NULL;
|
762 |
2 |
zero_gravi |
end case;
|
763 |
11 |
zero_gravi |
execute_engine.state_nxt <= SYS_WAIT;
|
764 |
13 |
zero_gravi |
else -- CSR access
|
765 |
|
|
execute_engine.state_nxt <= CSR_ACCESS;
|
766 |
2 |
zero_gravi |
end if;
|
767 |
|
|
|
768 |
|
|
when others => -- undefined
|
769 |
|
|
-- ------------------------------------------------------------
|
770 |
6 |
zero_gravi |
execute_engine.state_nxt <= DISPATCH;
|
771 |
2 |
zero_gravi |
|
772 |
|
|
end case;
|
773 |
|
|
|
774 |
|
|
when CSR_ACCESS => -- write CSR data to RF, write ALU.res to CSR
|
775 |
|
|
-- ------------------------------------------------------------
|
776 |
|
|
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '0'; -- default
|
777 |
|
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- default
|
778 |
|
|
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '0'; -- default
|
779 |
|
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '0'; -- default
|
780 |
12 |
zero_gravi |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- default ALU operation = OR
|
781 |
6 |
zero_gravi |
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
782 |
7 |
zero_gravi |
-- register operations --
|
783 |
6 |
zero_gravi |
when funct3_csrrw_c => -- CSRRW
|
784 |
2 |
zero_gravi |
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- OPA = rs1
|
785 |
|
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '0'; -- OPB = rs2
|
786 |
|
|
ctrl_nxt(ctrl_rf_clear_rs2_c) <= '1'; -- rs2 = 0
|
787 |
12 |
zero_gravi |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR
|
788 |
6 |
zero_gravi |
csr.we_nxt <= '1'; -- always write CSR
|
789 |
|
|
when funct3_csrrs_c => -- CSRRS
|
790 |
2 |
zero_gravi |
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr
|
791 |
12 |
zero_gravi |
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '1'; -- OPB = rs1
|
792 |
2 |
zero_gravi |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR
|
793 |
6 |
zero_gravi |
csr.we_nxt <= not rs1_is_r0_v; -- write CSR if rs1 is not zero_reg
|
794 |
|
|
when funct3_csrrc_c => -- CSRRC
|
795 |
2 |
zero_gravi |
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr
|
796 |
|
|
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '1'; -- OPB = rs1
|
797 |
|
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_bitc_c; -- actual ALU operation = bit clear
|
798 |
6 |
zero_gravi |
csr.we_nxt <= not rs1_is_r0_v; -- write CSR if rs1 is not zero_reg
|
799 |
7 |
zero_gravi |
-- immediate operations --
|
800 |
6 |
zero_gravi |
when funct3_csrrwi_c => -- CSRRWI
|
801 |
2 |
zero_gravi |
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- OPA = rs1
|
802 |
|
|
ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- rs1 = 0
|
803 |
|
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- OPB = immediate
|
804 |
12 |
zero_gravi |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR
|
805 |
6 |
zero_gravi |
csr.we_nxt <= '1'; -- always write CSR
|
806 |
|
|
when funct3_csrrsi_c => -- CSRRSI
|
807 |
2 |
zero_gravi |
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr
|
808 |
|
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- OPB = immediate
|
809 |
|
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR
|
810 |
6 |
zero_gravi |
csr.we_nxt <= not rs1_is_r0_v; -- write CSR if UIMM5 is not zero (bits from rs1 filed)
|
811 |
|
|
when funct3_csrrci_c => -- CSRRCI
|
812 |
2 |
zero_gravi |
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr
|
813 |
|
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- OPB = immediate
|
814 |
|
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_bitc_c; -- actual ALU operation = bit clear
|
815 |
6 |
zero_gravi |
csr.we_nxt <= not rs1_is_r0_v; -- write CSR if UIMM5 is not zero (bits from rs1 filed)
|
816 |
2 |
zero_gravi |
when others => -- undefined
|
817 |
|
|
NULL;
|
818 |
|
|
end case;
|
819 |
|
|
-- RF write back --
|
820 |
12 |
zero_gravi |
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output
|
821 |
2 |
zero_gravi |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
822 |
11 |
zero_gravi |
execute_engine.state_nxt <= DISPATCH; -- FIXME should be SYS_WAIT? have another cycle to let side-effects kick in
|
823 |
2 |
zero_gravi |
|
824 |
6 |
zero_gravi |
when ALU_WAIT => -- wait for multi-cycle ALU operation to finish
|
825 |
2 |
zero_gravi |
-- ------------------------------------------------------------
|
826 |
6 |
zero_gravi |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_operation_v; -- actual ALU operation
|
827 |
|
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
|
828 |
12 |
zero_gravi |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (permanent write-back)
|
829 |
6 |
zero_gravi |
if (alu_wait_i = '0') then
|
830 |
12 |
zero_gravi |
execute_engine.state_nxt <= DISPATCH;
|
831 |
2 |
zero_gravi |
end if;
|
832 |
|
|
|
833 |
6 |
zero_gravi |
when BRANCH => -- update PC for taken branches and jumps
|
834 |
|
|
-- ------------------------------------------------------------
|
835 |
13 |
zero_gravi |
execute_engine.pc_nxt <= alu_add_i; -- branch/jump destination
|
836 |
6 |
zero_gravi |
if (execute_engine.is_jump = '1') or (execute_engine.branch_taken = '1') then
|
837 |
13 |
zero_gravi |
fetch_engine.reset <= '1'; -- trigger new instruction fetch from modified PC
|
838 |
11 |
zero_gravi |
execute_engine.state_nxt <= SYS_WAIT;
|
839 |
|
|
else
|
840 |
|
|
execute_engine.state_nxt <= DISPATCH;
|
841 |
6 |
zero_gravi |
end if;
|
842 |
|
|
|
843 |
12 |
zero_gravi |
when LOADSTORE_0 => -- trigger memory request
|
844 |
6 |
zero_gravi |
-- ------------------------------------------------------------
|
845 |
12 |
zero_gravi |
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') then -- LOAD
|
846 |
|
|
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- read request
|
847 |
|
|
else -- STORE
|
848 |
|
|
ctrl_nxt(ctrl_bus_wr_c) <= '1'; -- write request
|
849 |
|
|
end if;
|
850 |
|
|
execute_engine.state_nxt <= LOADSTORE_1;
|
851 |
6 |
zero_gravi |
|
852 |
12 |
zero_gravi |
when LOADSTORE_1 => -- memory latency
|
853 |
6 |
zero_gravi |
-- ------------------------------------------------------------
|
854 |
|
|
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- write input data to MDI (only relevant for LOAD)
|
855 |
12 |
zero_gravi |
execute_engine.state_nxt <= LOADSTORE_2;
|
856 |
6 |
zero_gravi |
|
857 |
12 |
zero_gravi |
when LOADSTORE_2 => -- wait for bus transaction to finish
|
858 |
6 |
zero_gravi |
-- ------------------------------------------------------------
|
859 |
|
|
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for LOAD)
|
860 |
|
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "01"; -- RF input = memory input (only relevant for LOAD)
|
861 |
|
|
if (ma_load_i = '1') or (be_load_i = '1') or (ma_store_i = '1') or (be_store_i = '1') then -- abort if exception
|
862 |
7 |
zero_gravi |
execute_engine.state_nxt <= SYS_WAIT;
|
863 |
12 |
zero_gravi |
elsif (bus_d_wait_i = '0') then -- wait here for bus to finish transaction
|
864 |
6 |
zero_gravi |
if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_load_c) then -- LOAD?
|
865 |
|
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
866 |
|
|
end if;
|
867 |
|
|
execute_engine.state_nxt <= DISPATCH;
|
868 |
|
|
end if;
|
869 |
|
|
|
870 |
2 |
zero_gravi |
when others => -- undefined
|
871 |
|
|
-- ------------------------------------------------------------
|
872 |
7 |
zero_gravi |
execute_engine.state_nxt <= SYS_WAIT;
|
873 |
2 |
zero_gravi |
|
874 |
|
|
end case;
|
875 |
6 |
zero_gravi |
end process execute_engine_fsm_comb;
|
876 |
2 |
zero_gravi |
|
877 |
|
|
|
878 |
|
|
-- Illegal Instruction Check --------------------------------------------------------------
|
879 |
|
|
-- -------------------------------------------------------------------------------------------
|
880 |
13 |
zero_gravi |
illegal_instruction_check: process(execute_engine, csr, ctrl_nxt)
|
881 |
2 |
zero_gravi |
begin
|
882 |
11 |
zero_gravi |
-- illegal instructions are checked in the EXECUTE stage
|
883 |
|
|
-- the execute engine will only commit valid instructions
|
884 |
6 |
zero_gravi |
if (execute_engine.state = EXECUTE) then
|
885 |
2 |
zero_gravi |
-- defaults --
|
886 |
|
|
illegal_instruction <= '0';
|
887 |
|
|
illegal_register <= '0';
|
888 |
|
|
|
889 |
|
|
-- check if using reg >= 16 for E-CPUs --
|
890 |
13 |
zero_gravi |
--if (CPU_EXTENSION_RISCV_E = true) then
|
891 |
|
|
-- illegal_register <= ????? FIXME
|
892 |
|
|
--else
|
893 |
|
|
-- illegal_register <= '0';
|
894 |
|
|
--end if;
|
895 |
2 |
zero_gravi |
|
896 |
|
|
-- check instructions --
|
897 |
6 |
zero_gravi |
case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is
|
898 |
2 |
zero_gravi |
|
899 |
|
|
-- OPCODE check sufficient: LUI, UIPC, JAL --
|
900 |
|
|
when opcode_lui_c | opcode_auipc_c | opcode_jal_c =>
|
901 |
|
|
illegal_instruction <= '0';
|
902 |
|
|
|
903 |
|
|
when opcode_alui_c => -- check ALUI funct7
|
904 |
6 |
zero_gravi |
if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and
|
905 |
|
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000")) or -- shift logical left
|
906 |
|
|
((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and
|
907 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000") and
|
908 |
|
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0100000"))) then -- shift right
|
909 |
2 |
zero_gravi |
illegal_instruction <= '1';
|
910 |
|
|
else
|
911 |
|
|
illegal_instruction <= '0';
|
912 |
|
|
end if;
|
913 |
|
|
|
914 |
|
|
when opcode_load_c => -- check LOAD funct3
|
915 |
6 |
zero_gravi |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lb_c) or
|
916 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lh_c) or
|
917 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lw_c) or
|
918 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lbu_c) or
|
919 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lhu_c) then
|
920 |
2 |
zero_gravi |
illegal_instruction <= '0';
|
921 |
|
|
else
|
922 |
|
|
illegal_instruction <= '1';
|
923 |
|
|
end if;
|
924 |
|
|
|
925 |
|
|
when opcode_store_c => -- check STORE funct3
|
926 |
6 |
zero_gravi |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sb_c) or
|
927 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sh_c) or
|
928 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sw_c) then
|
929 |
2 |
zero_gravi |
illegal_instruction <= '0';
|
930 |
|
|
else
|
931 |
|
|
illegal_instruction <= '1';
|
932 |
|
|
end if;
|
933 |
|
|
|
934 |
|
|
when opcode_branch_c => -- check BRANCH funct3
|
935 |
6 |
zero_gravi |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_beq_c) or
|
936 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bne_c) or
|
937 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_blt_c) or
|
938 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bge_c) or
|
939 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bltu_c) or
|
940 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bgeu_c) then
|
941 |
2 |
zero_gravi |
illegal_instruction <= '0';
|
942 |
|
|
else
|
943 |
|
|
illegal_instruction <= '1';
|
944 |
|
|
end if;
|
945 |
|
|
|
946 |
|
|
when opcode_jalr_c => -- check JALR funct3
|
947 |
6 |
zero_gravi |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") then
|
948 |
2 |
zero_gravi |
illegal_instruction <= '0';
|
949 |
|
|
else
|
950 |
|
|
illegal_instruction <= '1';
|
951 |
|
|
end if;
|
952 |
|
|
|
953 |
|
|
when opcode_alu_c => -- check ALU funct3 & funct7
|
954 |
6 |
zero_gravi |
if (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV
|
955 |
11 |
zero_gravi |
if (CPU_EXTENSION_RISCV_M = false) then -- not implemented
|
956 |
2 |
zero_gravi |
illegal_instruction <= '1';
|
957 |
|
|
end if;
|
958 |
6 |
zero_gravi |
elsif ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or
|
959 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c)) and -- ADD/SUB or SRA/SRL check
|
960 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000") and
|
961 |
|
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0100000")) then -- ADD/SUB or SRA/SRL select
|
962 |
2 |
zero_gravi |
illegal_instruction <= '1';
|
963 |
|
|
else
|
964 |
|
|
illegal_instruction <= '0';
|
965 |
|
|
end if;
|
966 |
|
|
|
967 |
8 |
zero_gravi |
when opcode_fence_c => -- fence instructions --
|
968 |
|
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I
|
969 |
|
|
illegal_instruction <= '0';
|
970 |
|
|
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
|
971 |
|
|
illegal_instruction <= '0';
|
972 |
|
|
else
|
973 |
|
|
illegal_instruction <= '1';
|
974 |
|
|
end if;
|
975 |
|
|
|
976 |
2 |
zero_gravi |
when opcode_syscsr_c => -- check system instructions --
|
977 |
|
|
-- CSR access --
|
978 |
6 |
zero_gravi |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
|
979 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrs_c) or
|
980 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrc_c) or
|
981 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) or
|
982 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrsi_c) or
|
983 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrci_c) then
|
984 |
2 |
zero_gravi |
-- valid CSR? --
|
985 |
6 |
zero_gravi |
if (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"300") or -- mstatus
|
986 |
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"301") or -- misa
|
987 |
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"304") or -- mie
|
988 |
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"305") or -- mtvev
|
989 |
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"340") or -- mscratch
|
990 |
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"341") or -- mepc
|
991 |
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"342") or -- mcause
|
992 |
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"343") or -- mtval
|
993 |
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"344") or -- mip
|
994 |
2 |
zero_gravi |
--
|
995 |
12 |
zero_gravi |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c00") and (CSR_COUNTERS_USE = true)) or -- cycle
|
996 |
|
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c01") and (CSR_COUNTERS_USE = true)) or -- time
|
997 |
|
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c02") and (CSR_COUNTERS_USE = true)) or -- instret
|
998 |
|
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c80") and (CSR_COUNTERS_USE = true)) or -- cycleh
|
999 |
|
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c81") and (CSR_COUNTERS_USE = true)) or -- timeh
|
1000 |
|
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c82") and (CSR_COUNTERS_USE = true)) or -- instreth
|
1001 |
2 |
zero_gravi |
--
|
1002 |
12 |
zero_gravi |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b00") and (CSR_COUNTERS_USE = true)) or -- mcycle
|
1003 |
|
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b02") and (CSR_COUNTERS_USE = true)) or -- minstret
|
1004 |
|
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b80") and (CSR_COUNTERS_USE = true)) or -- mcycleh
|
1005 |
|
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b82") and (CSR_COUNTERS_USE = true)) or -- minstreth
|
1006 |
2 |
zero_gravi |
--
|
1007 |
12 |
zero_gravi |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f11") or -- mvendorid
|
1008 |
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f12") or -- marchid
|
1009 |
6 |
zero_gravi |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f13") or -- mimpid
|
1010 |
12 |
zero_gravi |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f14") then -- mhartid
|
1011 |
2 |
zero_gravi |
illegal_instruction <= '0';
|
1012 |
|
|
else
|
1013 |
|
|
illegal_instruction <= '1';
|
1014 |
|
|
end if;
|
1015 |
|
|
|
1016 |
|
|
-- ecall, ebreak, mret, wfi --
|
1017 |
6 |
zero_gravi |
elsif (execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c) = "00000") and
|
1018 |
|
|
(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
|
1019 |
13 |
zero_gravi |
if (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ecall_c) or -- ECALL
|
1020 |
11 |
zero_gravi |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ebreak_c) or -- EBREAK
|
1021 |
13 |
zero_gravi |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_mret_c) or -- MRET
|
1022 |
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_wfi_c) then -- WFI
|
1023 |
2 |
zero_gravi |
illegal_instruction <= '0';
|
1024 |
|
|
else
|
1025 |
|
|
illegal_instruction <= '1';
|
1026 |
|
|
end if;
|
1027 |
|
|
else
|
1028 |
|
|
illegal_instruction <= '1';
|
1029 |
|
|
end if;
|
1030 |
|
|
|
1031 |
|
|
when others => -- compressed instruction or undefined instruction
|
1032 |
6 |
zero_gravi |
if (execute_engine.i_reg(1 downto 0) = "11") then -- undefined/unimplemented opcode
|
1033 |
2 |
zero_gravi |
illegal_instruction <= '1';
|
1034 |
|
|
end if;
|
1035 |
|
|
|
1036 |
|
|
end case;
|
1037 |
|
|
else
|
1038 |
|
|
illegal_instruction <= '0';
|
1039 |
|
|
illegal_register <= '0';
|
1040 |
|
|
end if;
|
1041 |
|
|
end process illegal_instruction_check;
|
1042 |
|
|
|
1043 |
|
|
-- any illegal condition? --
|
1044 |
6 |
zero_gravi |
trap_ctrl.instr_il <= illegal_instruction or illegal_register or illegal_compressed;
|
1045 |
2 |
zero_gravi |
|
1046 |
|
|
|
1047 |
6 |
zero_gravi |
-- ****************************************************************************************************************************
|
1048 |
|
|
-- Exception and Interrupt Control
|
1049 |
|
|
-- ****************************************************************************************************************************
|
1050 |
2 |
zero_gravi |
|
1051 |
|
|
|
1052 |
6 |
zero_gravi |
-- Trap Controller ------------------------------------------------------------------------
|
1053 |
2 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
1054 |
6 |
zero_gravi |
trap_controller: process(rstn_i, clk_i)
|
1055 |
2 |
zero_gravi |
begin
|
1056 |
|
|
if (rstn_i = '0') then
|
1057 |
6 |
zero_gravi |
trap_ctrl.exc_buf <= (others => '0');
|
1058 |
|
|
trap_ctrl.irq_buf <= (others => '0');
|
1059 |
|
|
trap_ctrl.exc_ack <= '0';
|
1060 |
|
|
trap_ctrl.irq_ack <= (others => '0');
|
1061 |
|
|
trap_ctrl.cause <= (others => '0');
|
1062 |
|
|
trap_ctrl.env_start <= '0';
|
1063 |
2 |
zero_gravi |
elsif rising_edge(clk_i) then
|
1064 |
|
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
1065 |
|
|
-- exception buffer: misaligned load/store/instruction address
|
1066 |
6 |
zero_gravi |
trap_ctrl.exc_buf(exception_lalign_c) <= (trap_ctrl.exc_buf(exception_lalign_c) or ma_load_i) and (not trap_ctrl.exc_ack);
|
1067 |
|
|
trap_ctrl.exc_buf(exception_salign_c) <= (trap_ctrl.exc_buf(exception_salign_c) or ma_store_i) and (not trap_ctrl.exc_ack);
|
1068 |
|
|
trap_ctrl.exc_buf(exception_ialign_c) <= (trap_ctrl.exc_buf(exception_ialign_c) or trap_ctrl.instr_ma) and (not trap_ctrl.exc_ack);
|
1069 |
2 |
zero_gravi |
-- exception buffer: load/store/instruction bus access error
|
1070 |
6 |
zero_gravi |
trap_ctrl.exc_buf(exception_laccess_c) <= (trap_ctrl.exc_buf(exception_laccess_c) or be_load_i) and (not trap_ctrl.exc_ack);
|
1071 |
|
|
trap_ctrl.exc_buf(exception_saccess_c) <= (trap_ctrl.exc_buf(exception_saccess_c) or be_store_i) and (not trap_ctrl.exc_ack);
|
1072 |
|
|
trap_ctrl.exc_buf(exception_iaccess_c) <= (trap_ctrl.exc_buf(exception_iaccess_c) or trap_ctrl.instr_be) and (not trap_ctrl.exc_ack);
|
1073 |
2 |
zero_gravi |
-- exception buffer: illegal instruction / env call / break point
|
1074 |
6 |
zero_gravi |
trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or trap_ctrl.env_call) and (not trap_ctrl.exc_ack);
|
1075 |
|
|
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack);
|
1076 |
|
|
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack);
|
1077 |
14 |
zero_gravi |
-- interrupt buffer (RISC-V compliant): machine software/external/timer interrupt
|
1078 |
|
|
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not trap_ctrl.irq_ack(interrupt_msw_irq_c));
|
1079 |
|
|
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or mext_irq_i) and (not trap_ctrl.irq_ack(interrupt_mext_irq_c));
|
1080 |
|
|
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not trap_ctrl.irq_ack(interrupt_mtime_irq_c));
|
1081 |
|
|
-- interrupt buffer (custom): fast interrupts
|
1082 |
|
|
trap_ctrl.irq_buf(interrupt_firq_0_c) <= csr.mie_firqe(0) and (trap_ctrl.irq_buf(interrupt_firq_0_c) or firq_i(0)) and (not trap_ctrl.irq_ack(interrupt_firq_0_c));
|
1083 |
|
|
trap_ctrl.irq_buf(interrupt_firq_1_c) <= csr.mie_firqe(1) and (trap_ctrl.irq_buf(interrupt_firq_1_c) or firq_i(1)) and (not trap_ctrl.irq_ack(interrupt_firq_1_c));
|
1084 |
|
|
trap_ctrl.irq_buf(interrupt_firq_2_c) <= csr.mie_firqe(2) and (trap_ctrl.irq_buf(interrupt_firq_2_c) or firq_i(2)) and (not trap_ctrl.irq_ack(interrupt_firq_2_c));
|
1085 |
|
|
trap_ctrl.irq_buf(interrupt_firq_3_c) <= csr.mie_firqe(3) and (trap_ctrl.irq_buf(interrupt_firq_3_c) or firq_i(3)) and (not trap_ctrl.irq_ack(interrupt_firq_3_c));
|
1086 |
2 |
zero_gravi |
|
1087 |
6 |
zero_gravi |
-- trap control --
|
1088 |
|
|
if (trap_ctrl.env_start = '0') then -- no started trap handler
|
1089 |
11 |
zero_gravi |
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception/IRQ detected!
|
1090 |
13 |
zero_gravi |
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only -> continue execution even if permanent IRQ
|
1091 |
|
|
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr)
|
1092 |
7 |
zero_gravi |
trap_ctrl.exc_ack <= '1'; -- clear execption
|
1093 |
|
|
trap_ctrl.irq_ack <= trap_ctrl.irq_ack_nxt; -- capture and clear with interrupt ACK mask
|
1094 |
13 |
zero_gravi |
trap_ctrl.env_start <= '1'; -- now execute engine can start trap handler
|
1095 |
2 |
zero_gravi |
end if;
|
1096 |
6 |
zero_gravi |
else -- trap waiting to get started
|
1097 |
|
|
if (trap_ctrl.env_start_ack = '1') then -- start of trap handler acknowledged by execution engine
|
1098 |
|
|
trap_ctrl.exc_ack <= '0';
|
1099 |
|
|
trap_ctrl.irq_ack <= (others => '0');
|
1100 |
|
|
trap_ctrl.env_start <= '0';
|
1101 |
2 |
zero_gravi |
end if;
|
1102 |
|
|
end if;
|
1103 |
|
|
end if;
|
1104 |
|
|
end if;
|
1105 |
6 |
zero_gravi |
end process trap_controller;
|
1106 |
2 |
zero_gravi |
|
1107 |
|
|
-- any exception/interrupt? --
|
1108 |
13 |
zero_gravi |
trap_ctrl.exc_fire <= or_all_f(trap_ctrl.exc_buf); -- exceptions/faults cannot be masked
|
1109 |
|
|
trap_ctrl.irq_fire <= or_all_f(trap_ctrl.irq_buf) and csr.mstatus_mie; -- interrupts can be masked
|
1110 |
2 |
zero_gravi |
|
1111 |
|
|
|
1112 |
6 |
zero_gravi |
-- Trap Priority Detector -----------------------------------------------------------------
|
1113 |
|
|
-- -------------------------------------------------------------------------------------------
|
1114 |
|
|
trap_priority: process(trap_ctrl)
|
1115 |
2 |
zero_gravi |
begin
|
1116 |
|
|
-- defaults --
|
1117 |
6 |
zero_gravi |
trap_ctrl.cause_nxt <= (others => '0');
|
1118 |
|
|
trap_ctrl.irq_ack_nxt <= (others => '0');
|
1119 |
2 |
zero_gravi |
|
1120 |
9 |
zero_gravi |
-- the following traps are caused by asynchronous exceptions (-> interrupts)
|
1121 |
12 |
zero_gravi |
-- here we do need a specific acknowledge mask since several sources can trigger at once
|
1122 |
9 |
zero_gravi |
|
1123 |
2 |
zero_gravi |
-- interrupt: 1.11 machine external interrupt --
|
1124 |
6 |
zero_gravi |
if (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
|
1125 |
12 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_mei_c;
|
1126 |
6 |
zero_gravi |
trap_ctrl.irq_ack_nxt(interrupt_mext_irq_c) <= '1';
|
1127 |
2 |
zero_gravi |
|
1128 |
|
|
-- interrupt: 1.7 machine timer interrupt --
|
1129 |
6 |
zero_gravi |
elsif (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then
|
1130 |
12 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_mti_c;
|
1131 |
6 |
zero_gravi |
trap_ctrl.irq_ack_nxt(interrupt_mtime_irq_c) <= '1';
|
1132 |
2 |
zero_gravi |
|
1133 |
|
|
-- interrupt: 1.3 machine SW interrupt --
|
1134 |
6 |
zero_gravi |
elsif (trap_ctrl.irq_buf(interrupt_msw_irq_c) = '1') then
|
1135 |
12 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_msi_c;
|
1136 |
6 |
zero_gravi |
trap_ctrl.irq_ack_nxt(interrupt_msw_irq_c) <= '1';
|
1137 |
2 |
zero_gravi |
|
1138 |
|
|
|
1139 |
14 |
zero_gravi |
-- interrupt: 1.16 fast interrupt channel 0 --
|
1140 |
|
|
elsif (trap_ctrl.irq_buf(interrupt_firq_0_c) = '1') then
|
1141 |
|
|
trap_ctrl.cause_nxt <= trap_firq0_c;
|
1142 |
|
|
trap_ctrl.irq_ack_nxt(interrupt_firq_0_c) <= '1';
|
1143 |
|
|
|
1144 |
|
|
-- interrupt: 1.17 fast interrupt channel 1 --
|
1145 |
|
|
elsif (trap_ctrl.irq_buf(interrupt_firq_1_c) = '1') then
|
1146 |
|
|
trap_ctrl.cause_nxt <= trap_firq1_c;
|
1147 |
|
|
trap_ctrl.irq_ack_nxt(interrupt_firq_1_c) <= '1';
|
1148 |
|
|
|
1149 |
|
|
-- interrupt: 1.18 fast interrupt channel 2 --
|
1150 |
|
|
elsif (trap_ctrl.irq_buf(interrupt_firq_2_c) = '1') then
|
1151 |
|
|
trap_ctrl.cause_nxt <= trap_firq2_c;
|
1152 |
|
|
trap_ctrl.irq_ack_nxt(interrupt_firq_2_c) <= '1';
|
1153 |
|
|
|
1154 |
|
|
-- interrupt: 1.19 fast interrupt channel 3 --
|
1155 |
|
|
elsif (trap_ctrl.irq_buf(interrupt_firq_3_c) = '1') then
|
1156 |
|
|
trap_ctrl.cause_nxt <= trap_firq3_c;
|
1157 |
|
|
trap_ctrl.irq_ack_nxt(interrupt_firq_3_c) <= '1';
|
1158 |
|
|
|
1159 |
|
|
|
1160 |
4 |
zero_gravi |
-- the following traps are caused by synchronous exceptions
|
1161 |
12 |
zero_gravi |
-- here we do not need a specific acknowledge mask since only one exception (the one
|
1162 |
9 |
zero_gravi |
-- with highest priority) can trigger at once
|
1163 |
4 |
zero_gravi |
|
1164 |
2 |
zero_gravi |
-- trap/fault: 0.1 instruction access fault --
|
1165 |
6 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exception_iaccess_c) = '1') then
|
1166 |
12 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_iba_c;
|
1167 |
2 |
zero_gravi |
|
1168 |
|
|
-- trap/fault: 0.2 illegal instruction --
|
1169 |
6 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then
|
1170 |
12 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_iil_c;
|
1171 |
2 |
zero_gravi |
|
1172 |
12 |
zero_gravi |
-- trap/fault: 0.0 instruction address misaligned --
|
1173 |
|
|
elsif (trap_ctrl.exc_buf(exception_ialign_c) = '1') then
|
1174 |
|
|
trap_ctrl.cause_nxt <= trap_ima_c;
|
1175 |
2 |
zero_gravi |
|
1176 |
12 |
zero_gravi |
|
1177 |
2 |
zero_gravi |
-- trap/fault: 0.11 environment call from M-mode --
|
1178 |
6 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exception_m_envcall_c) = '1') then
|
1179 |
14 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_menv_c;
|
1180 |
2 |
zero_gravi |
|
1181 |
|
|
-- trap/fault: 0.3 breakpoint --
|
1182 |
6 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exception_break_c) = '1') then
|
1183 |
12 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_brk_c;
|
1184 |
2 |
zero_gravi |
|
1185 |
|
|
|
1186 |
|
|
-- trap/fault: 0.6 store address misaligned -
|
1187 |
6 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exception_salign_c) = '1') then
|
1188 |
12 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_sma_c;
|
1189 |
2 |
zero_gravi |
|
1190 |
|
|
-- trap/fault: 0.4 load address misaligned --
|
1191 |
6 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exception_lalign_c) = '1') then
|
1192 |
12 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_lma_c;
|
1193 |
2 |
zero_gravi |
|
1194 |
|
|
-- trap/fault: 0.7 store access fault --
|
1195 |
6 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exception_saccess_c) = '1') then
|
1196 |
12 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_sbe_c;
|
1197 |
2 |
zero_gravi |
|
1198 |
|
|
-- trap/fault: 0.5 load access fault --
|
1199 |
6 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then
|
1200 |
12 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_lbe_c;
|
1201 |
2 |
zero_gravi |
|
1202 |
|
|
-- undefined / not implemented --
|
1203 |
|
|
else
|
1204 |
6 |
zero_gravi |
trap_ctrl.cause_nxt <= (others => '0');
|
1205 |
|
|
trap_ctrl.irq_ack_nxt <= (others => '0');
|
1206 |
2 |
zero_gravi |
end if;
|
1207 |
6 |
zero_gravi |
end process trap_priority;
|
1208 |
|
|
|
1209 |
2 |
zero_gravi |
|
1210 |
6 |
zero_gravi |
-- ****************************************************************************************************************************
|
1211 |
|
|
-- Control and Status Registers (CSRs)
|
1212 |
|
|
-- ****************************************************************************************************************************
|
1213 |
2 |
zero_gravi |
|
1214 |
|
|
-- Control and Status Registers Write Access ----------------------------------------------
|
1215 |
|
|
-- -------------------------------------------------------------------------------------------
|
1216 |
|
|
csr_write_access: process(rstn_i, clk_i)
|
1217 |
|
|
begin
|
1218 |
|
|
if (rstn_i = '0') then
|
1219 |
11 |
zero_gravi |
csr.we <= '0';
|
1220 |
|
|
csr.re <= '0';
|
1221 |
|
|
--
|
1222 |
6 |
zero_gravi |
csr.mstatus_mie <= '0';
|
1223 |
|
|
csr.mstatus_mpie <= '0';
|
1224 |
|
|
csr.mie_msie <= '0';
|
1225 |
|
|
csr.mie_meie <= '0';
|
1226 |
|
|
csr.mie_mtie <= '0';
|
1227 |
14 |
zero_gravi |
csr.mie_firqe <= (others => '0');
|
1228 |
6 |
zero_gravi |
csr.mtvec <= (others => '0');
|
1229 |
12 |
zero_gravi |
csr.mscratch <= (others => '0');
|
1230 |
|
|
csr.mepc <= (others => '0');
|
1231 |
|
|
csr.mcause <= (others => '0');
|
1232 |
6 |
zero_gravi |
csr.mtval <= (others => '0');
|
1233 |
2 |
zero_gravi |
elsif rising_edge(clk_i) then
|
1234 |
|
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
1235 |
11 |
zero_gravi |
-- access --
|
1236 |
|
|
csr.we <= csr.we_nxt;
|
1237 |
|
|
csr.re <= csr.re_nxt;
|
1238 |
|
|
|
1239 |
|
|
-- registers that can be modified by user --
|
1240 |
6 |
zero_gravi |
if (csr.we = '1') then -- manual update
|
1241 |
4 |
zero_gravi |
|
1242 |
11 |
zero_gravi |
-- Machine CSRs: Standard read/write
|
1243 |
|
|
if (execute_engine.i_reg(31 downto 28) = x"3") then
|
1244 |
|
|
-- machine trap setup --
|
1245 |
|
|
if (execute_engine.i_reg(27 downto 24) = x"0") then
|
1246 |
|
|
case execute_engine.i_reg(23 downto 20) is
|
1247 |
12 |
zero_gravi |
when x"0" => -- R/W: mstatus - machine status register
|
1248 |
|
|
csr.mstatus_mie <= csr_wdata_i(03);
|
1249 |
|
|
csr.mstatus_mpie <= csr_wdata_i(07);
|
1250 |
|
|
when x"4" => -- R/W: mie - machine interrupt-enable register
|
1251 |
14 |
zero_gravi |
csr.mie_msie <= csr_wdata_i(03); -- machine SW IRQ enable
|
1252 |
|
|
csr.mie_mtie <= csr_wdata_i(07); -- machine TIMER IRQ enable
|
1253 |
|
|
csr.mie_meie <= csr_wdata_i(11); -- machine EXT IRQ enable
|
1254 |
|
|
--
|
1255 |
|
|
csr.mie_firqe(0) <= csr_wdata_i(16); -- fast interrupt channel 0
|
1256 |
|
|
csr.mie_firqe(1) <= csr_wdata_i(17); -- fast interrupt channel 1
|
1257 |
|
|
csr.mie_firqe(2) <= csr_wdata_i(18); -- fast interrupt channel 2
|
1258 |
|
|
csr.mie_firqe(3) <= csr_wdata_i(19); -- fast interrupt channel 3
|
1259 |
12 |
zero_gravi |
when x"5" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
|
1260 |
|
|
csr.mtvec <= csr_wdata_i(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
|
1261 |
|
|
when others =>
|
1262 |
|
|
NULL;
|
1263 |
11 |
zero_gravi |
end case;
|
1264 |
4 |
zero_gravi |
end if;
|
1265 |
11 |
zero_gravi |
-- machine trap handling --
|
1266 |
|
|
if (execute_engine.i_reg(27 downto 24) = x"4") then
|
1267 |
|
|
case execute_engine.i_reg(23 downto 20) is
|
1268 |
|
|
when x"0" => -- R/W: mscratch - machine scratch register
|
1269 |
|
|
csr.mscratch <= csr_wdata_i;
|
1270 |
|
|
when x"1" => -- R/W: mepc - machine exception program counter
|
1271 |
12 |
zero_gravi |
csr.mepc <= csr_wdata_i(data_width_c-1 downto 1) & '0';
|
1272 |
11 |
zero_gravi |
when x"3" => -- R/W: mtval - machine bad address or instruction
|
1273 |
|
|
csr.mtval <= csr_wdata_i;
|
1274 |
|
|
when others =>
|
1275 |
|
|
NULL;
|
1276 |
|
|
end case;
|
1277 |
4 |
zero_gravi |
end if;
|
1278 |
|
|
end if;
|
1279 |
|
|
|
1280 |
11 |
zero_gravi |
-- automatic update by hardware --
|
1281 |
|
|
else
|
1282 |
2 |
zero_gravi |
|
1283 |
14 |
zero_gravi |
-- machine exception PC & machine trap value register --
|
1284 |
12 |
zero_gravi |
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
|
1285 |
14 |
zero_gravi |
csr.mcause <= trap_ctrl.cause(trap_ctrl.cause'left) & "000" & x"00000" & "000" & trap_ctrl.cause(4 downto 0);
|
1286 |
|
|
if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS only (is mcause(31))
|
1287 |
6 |
zero_gravi |
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
|
1288 |
12 |
zero_gravi |
csr.mtval <= (others => '0'); -- mtval is zero for interrupts
|
1289 |
9 |
zero_gravi |
else -- for EXCEPTIONS (according to their priority)
|
1290 |
6 |
zero_gravi |
csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
|
1291 |
14 |
zero_gravi |
if (trap_ctrl.cause(4 downto 0) = trap_iba_c(4 downto 0)) or -- instr access error OR
|
1292 |
|
|
(trap_ctrl.cause(4 downto 0) = trap_ima_c(4 downto 0)) or -- misaligned instruction OR
|
1293 |
|
|
(trap_ctrl.cause(4 downto 0) = trap_brk_c(4 downto 0)) or -- breakpoint OR
|
1294 |
|
|
(trap_ctrl.cause(4 downto 0) = trap_menv_c(4 downto 0)) then -- env call OR
|
1295 |
9 |
zero_gravi |
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
|
1296 |
14 |
zero_gravi |
elsif (trap_ctrl.cause(4 downto 0) = trap_iil_c(4 downto 0)) then -- illegal instruction
|
1297 |
12 |
zero_gravi |
csr.mtval <= execute_engine.i_reg; -- faulting instruction itself
|
1298 |
|
|
else -- load/store misalignments/access errors
|
1299 |
9 |
zero_gravi |
csr.mtval <= mar_i; -- faulting data access address
|
1300 |
2 |
zero_gravi |
end if;
|
1301 |
|
|
end if;
|
1302 |
|
|
end if;
|
1303 |
|
|
|
1304 |
|
|
-- context switch in mstatus --
|
1305 |
12 |
zero_gravi |
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
|
1306 |
6 |
zero_gravi |
csr.mstatus_mie <= '0';
|
1307 |
9 |
zero_gravi |
if (csr.mstatus_mpie = '0') then -- prevent loosing the prev MIE state in nested traps
|
1308 |
6 |
zero_gravi |
csr.mstatus_mpie <= csr.mstatus_mie;
|
1309 |
2 |
zero_gravi |
end if;
|
1310 |
6 |
zero_gravi |
elsif (trap_ctrl.env_end = '1') then -- return from exception
|
1311 |
|
|
csr.mstatus_mie <= csr.mstatus_mpie;
|
1312 |
2 |
zero_gravi |
end if;
|
1313 |
9 |
zero_gravi |
|
1314 |
2 |
zero_gravi |
end if;
|
1315 |
|
|
end if;
|
1316 |
|
|
end if;
|
1317 |
|
|
end process csr_write_access;
|
1318 |
|
|
|
1319 |
|
|
|
1320 |
|
|
-- Control and Status Registers Read Access -----------------------------------------------
|
1321 |
|
|
-- -------------------------------------------------------------------------------------------
|
1322 |
|
|
csr_read_access: process(clk_i)
|
1323 |
|
|
begin
|
1324 |
|
|
if rising_edge(clk_i) then
|
1325 |
|
|
csr_rdata_o <= (others => '0'); -- default
|
1326 |
11 |
zero_gravi |
if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.re = '1') then
|
1327 |
|
|
case execute_engine.i_reg(31 downto 20) is
|
1328 |
|
|
|
1329 |
|
|
-- machine trap setup --
|
1330 |
|
|
when x"300" => -- R/W: mstatus - machine status register
|
1331 |
|
|
csr_rdata_o(03) <= csr.mstatus_mie; -- MIE
|
1332 |
|
|
csr_rdata_o(07) <= csr.mstatus_mpie; -- MPIE
|
1333 |
12 |
zero_gravi |
csr_rdata_o(11) <= '1'; -- MPP low - M-mode
|
1334 |
|
|
csr_rdata_o(12) <= '1'; -- MPP high - M-mode
|
1335 |
11 |
zero_gravi |
when x"301" => -- R/-: misa - ISA and extensions
|
1336 |
|
|
csr_rdata_o(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
|
1337 |
|
|
csr_rdata_o(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
|
1338 |
|
|
csr_rdata_o(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
|
1339 |
|
|
csr_rdata_o(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension
|
1340 |
14 |
zero_gravi |
csr_rdata_o(23) <= '1'; -- X CPU extension (non-std extensions)
|
1341 |
11 |
zero_gravi |
csr_rdata_o(25) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr) and bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Z CPU extension
|
1342 |
|
|
csr_rdata_o(30) <= '1'; -- 32-bit architecture (MXL lo)
|
1343 |
|
|
csr_rdata_o(31) <= '0'; -- 32-bit architecture (MXL hi)
|
1344 |
|
|
when x"304" => -- R/W: mie - machine interrupt-enable register
|
1345 |
14 |
zero_gravi |
csr_rdata_o(03) <= csr.mie_msie; -- machine software IRQ enable
|
1346 |
|
|
csr_rdata_o(07) <= csr.mie_mtie; -- machine timer IRQ enable
|
1347 |
|
|
csr_rdata_o(11) <= csr.mie_meie; -- machine external IRQ enable
|
1348 |
|
|
--
|
1349 |
|
|
csr_rdata_o(16) <= csr.mie_firqe(0); -- fast interrupt channel 0
|
1350 |
|
|
csr_rdata_o(17) <= csr.mie_firqe(1); -- fast interrupt channel 1
|
1351 |
|
|
csr_rdata_o(18) <= csr.mie_firqe(2); -- fast interrupt channel 2
|
1352 |
|
|
csr_rdata_o(19) <= csr.mie_firqe(3); -- fast interrupt channel 3
|
1353 |
11 |
zero_gravi |
when x"305" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
|
1354 |
12 |
zero_gravi |
csr_rdata_o <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
|
1355 |
11 |
zero_gravi |
|
1356 |
|
|
-- machine trap handling --
|
1357 |
|
|
when x"340" => -- R/W: mscratch - machine scratch register
|
1358 |
|
|
csr_rdata_o <= csr.mscratch;
|
1359 |
|
|
when x"341" => -- R/W: mepc - machine exception program counter
|
1360 |
12 |
zero_gravi |
csr_rdata_o <= csr.mepc(data_width_c-1 downto 1) & '0';
|
1361 |
14 |
zero_gravi |
when x"342" => -- R/-: mcause - machine trap cause
|
1362 |
11 |
zero_gravi |
csr_rdata_o <= csr.mcause;
|
1363 |
|
|
when x"343" => -- R/W: mtval - machine bad address or instruction
|
1364 |
|
|
csr_rdata_o <= csr.mtval;
|
1365 |
|
|
when x"344" => -- R/W: mip - machine interrupt pending
|
1366 |
|
|
csr_rdata_o(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c);
|
1367 |
|
|
csr_rdata_o(07) <= trap_ctrl.irq_buf(interrupt_mtime_irq_c);
|
1368 |
|
|
csr_rdata_o(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c);
|
1369 |
14 |
zero_gravi |
--
|
1370 |
|
|
csr_rdata_o(16) <= trap_ctrl.irq_buf(interrupt_firq_0_c);
|
1371 |
|
|
csr_rdata_o(17) <= trap_ctrl.irq_buf(interrupt_firq_1_c);
|
1372 |
|
|
csr_rdata_o(18) <= trap_ctrl.irq_buf(interrupt_firq_2_c);
|
1373 |
|
|
csr_rdata_o(19) <= trap_ctrl.irq_buf(interrupt_firq_3_c);
|
1374 |
11 |
zero_gravi |
|
1375 |
|
|
-- counter and timers --
|
1376 |
|
|
when x"c00" | x"b00" => -- R/(W): cycle/mcycle: Cycle counter LOW
|
1377 |
|
|
csr_rdata_o <= csr.mcycle(31 downto 0);
|
1378 |
12 |
zero_gravi |
when x"c01" => -- R/-: time: System time LOW (from MTIME unit)
|
1379 |
|
|
csr_rdata_o <= systime(31 downto 0);
|
1380 |
11 |
zero_gravi |
when x"c02" | x"b02" => -- R/(W): instret/minstret: Instructions-retired counter LOW
|
1381 |
|
|
csr_rdata_o <= csr.minstret(31 downto 0);
|
1382 |
|
|
when x"c80" | x"b80" => -- R/(W): cycleh/mcycleh: Cycle counter HIGH
|
1383 |
12 |
zero_gravi |
csr_rdata_o <= x"000" & csr.mcycleh(19 downto 0); -- only the lowest 20 bit!
|
1384 |
|
|
when x"c81" => -- R/-: timeh: System time HIGH (from MTIME unit)
|
1385 |
|
|
csr_rdata_o <= systime(63 downto 32);
|
1386 |
11 |
zero_gravi |
when x"c82" | x"b82" => -- R/(W): instreth/minstreth: Instructions-retired counter HIGH
|
1387 |
12 |
zero_gravi |
csr_rdata_o <= x"000" & csr.minstreth(19 downto 0); -- only the lowest 20 bit!
|
1388 |
11 |
zero_gravi |
|
1389 |
|
|
-- machine information registers --
|
1390 |
12 |
zero_gravi |
when x"f11" => -- R/-: mvendorid
|
1391 |
|
|
csr_rdata_o <= (others => '0'); -- not yet assigned for NEORV32
|
1392 |
|
|
when x"f12" => -- R/-: marchid
|
1393 |
|
|
csr_rdata_o <= (others => '0'); -- not yet assigned for NEORV32
|
1394 |
|
|
when x"f13" => -- R/-: mimpid - implementation ID / NEORV32: version
|
1395 |
11 |
zero_gravi |
csr_rdata_o <= hw_version_c;
|
1396 |
|
|
when x"f14" => -- R/-: mhartid - hardware thread ID
|
1397 |
12 |
zero_gravi |
csr_rdata_o <= HW_THREAD_ID;
|
1398 |
11 |
zero_gravi |
|
1399 |
|
|
-- undefined/unavailable --
|
1400 |
|
|
when others =>
|
1401 |
|
|
csr_rdata_o <= (others => '0'); -- not implemented
|
1402 |
|
|
|
1403 |
|
|
end case;
|
1404 |
12 |
zero_gravi |
else
|
1405 |
|
|
csr_rdata_o <= (others => '0');
|
1406 |
2 |
zero_gravi |
end if;
|
1407 |
|
|
end if;
|
1408 |
|
|
end process csr_read_access;
|
1409 |
|
|
|
1410 |
12 |
zero_gravi |
-- time[h] CSR --
|
1411 |
|
|
systime <= time_i when (CSR_COUNTERS_USE = true) else (others => '0');
|
1412 |
2 |
zero_gravi |
|
1413 |
12 |
zero_gravi |
|
1414 |
6 |
zero_gravi |
-- RISC-V Counter CSRs --------------------------------------------------------------------
|
1415 |
2 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
1416 |
|
|
csr_counters: process(rstn_i, clk_i)
|
1417 |
|
|
begin
|
1418 |
6 |
zero_gravi |
if (rstn_i = '0') then
|
1419 |
11 |
zero_gravi |
csr.mcycle <= (others => '0');
|
1420 |
|
|
csr.minstret <= (others => '0');
|
1421 |
|
|
csr.mcycleh <= (others => '0');
|
1422 |
|
|
csr.minstreth <= (others => '0');
|
1423 |
|
|
mcycle_msb <= '0';
|
1424 |
|
|
minstret_msb <= '0';
|
1425 |
6 |
zero_gravi |
elsif rising_edge(clk_i) then
|
1426 |
12 |
zero_gravi |
if (CSR_COUNTERS_USE = true) then
|
1427 |
11 |
zero_gravi |
|
1428 |
|
|
-- mcycle (cycle) --
|
1429 |
|
|
mcycle_msb <= csr.mcycle(csr.mcycle'left);
|
1430 |
|
|
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b00") then -- write access
|
1431 |
|
|
csr.mcycle(31 downto 0) <= csr_wdata_i;
|
1432 |
|
|
csr.mcycle(32) <= '0';
|
1433 |
|
|
elsif (execute_engine.sleep = '0') then -- automatic update
|
1434 |
|
|
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
|
1435 |
2 |
zero_gravi |
end if;
|
1436 |
11 |
zero_gravi |
|
1437 |
|
|
-- mcycleh (cycleh) --
|
1438 |
|
|
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b80") then -- write access
|
1439 |
12 |
zero_gravi |
csr.mcycleh <= csr_wdata_i(19 downto 0);
|
1440 |
11 |
zero_gravi |
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update
|
1441 |
|
|
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
|
1442 |
2 |
zero_gravi |
end if;
|
1443 |
11 |
zero_gravi |
|
1444 |
|
|
-- minstret (instret) --
|
1445 |
|
|
minstret_msb <= csr.minstret(csr.minstret'left);
|
1446 |
|
|
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b02") then -- write access
|
1447 |
|
|
csr.minstret(31 downto 0) <= csr_wdata_i;
|
1448 |
|
|
csr.minstret(32) <= '0';
|
1449 |
12 |
zero_gravi |
elsif (execute_engine.state_nxt /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update
|
1450 |
11 |
zero_gravi |
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
|
1451 |
2 |
zero_gravi |
end if;
|
1452 |
11 |
zero_gravi |
|
1453 |
|
|
-- minstreth (instreth) --
|
1454 |
|
|
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b82") then -- write access
|
1455 |
12 |
zero_gravi |
csr.minstreth <= csr_wdata_i(19 downto 0);
|
1456 |
11 |
zero_gravi |
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update
|
1457 |
|
|
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
|
1458 |
|
|
end if;
|
1459 |
|
|
|
1460 |
12 |
zero_gravi |
else -- if not implemented
|
1461 |
|
|
csr.mcycle <= (others => '0');
|
1462 |
|
|
csr.minstret <= (others => '0');
|
1463 |
|
|
csr.mcycleh <= (others => '0');
|
1464 |
|
|
csr.minstreth <= (others => '0');
|
1465 |
|
|
mcycle_msb <= '0';
|
1466 |
|
|
minstret_msb <= '0';
|
1467 |
2 |
zero_gravi |
end if;
|
1468 |
|
|
end if;
|
1469 |
|
|
end process csr_counters;
|
1470 |
|
|
|
1471 |
|
|
|
1472 |
|
|
end neorv32_cpu_control_rtl;
|