Subversion Repositories neorv32

-- #################################################################################################

-- # << NEORV32 - CPU Control >>                                                                   #

-- # ********************************************************************************************* #

-- # CPU operation is split into a fetch engine (responsible for fetching an decompressing instr-  #

-- # uctions), an execute engine (responsible for actually executing the instructions), an inter-  #

-- # rupt and exception handling controller and the RISC-V status and control registers (CSRs).    #

-- # ********************************************************************************************* #

-- # BSD 3-Clause License                                                                          #

-- #                                                                                               #

-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #

-- #                                                                                               #

-- # Redistribution and use in source and binary forms, with or without modification, are          #

-- # permitted provided that the following conditions are met:                                     #

-- #                                                                                               #

-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #

-- #    conditions and the following disclaimer.                                                   #

-- #                                                                                               #

-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #

-- #    conditions and the following disclaimer in the documentation and/or other materials        #

-- #    provided with the distribution.                                                            #

-- #                                                                                               #

-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #

-- #    endorse or promote products derived from this software without specific prior written      #

-- #    permission.                                                                                #

-- #                                                                                               #

-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #

-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #

-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #

-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #

-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #

-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #

-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #

-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #

-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #

-- # ********************************************************************************************* #

-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #

-- #################################################################################################

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

library neorv32;

use neorv32.neorv32_package.all;

entity neorv32_cpu_control is

  generic (

    -- General --

    CSR_COUNTERS_USE             : boolean := true;  -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?

    HW_THREAD_ID                 : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id

    CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address

    -- RISC-V CPU Extensions --

    CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?

    CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?

    CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?

    CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?

    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?

    CPU_EXTENSION_RISCV_Zifencei : boolean := true;  -- implement instruction stream sync.?

    -- Physical memory protection (PMP) --

    PMP_USE                      : boolean := false; -- implement physical memory protection?

    PMP_NUM_REGIONS              : natural := 4; -- number of regions (1..4)

    PMP_GRANULARITY              : natural := 0  -- granularity (0=none, 1=8B, 2=16B, 3=32B, ...)

  );

  port (

    -- global control --

    clk_i         : in  std_ulogic; -- global clock, rising edge

    rstn_i        : in  std_ulogic; -- global reset, low-active, async

    ctrl_o        : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus

    -- status input --

    alu_wait_i    : in  std_ulogic; -- wait for ALU

    bus_i_wait_i  : in  std_ulogic; -- wait for bus

    bus_d_wait_i  : in  std_ulogic; -- wait for bus

    -- data input --

    instr_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- instruction

    cmp_i         : in  std_ulogic_vector(1 downto 0); -- comparator status

    alu_add_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU.add result

    -- data output --

    imm_o         : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate

    fetch_pc_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch

    curr_pc_o     : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)

    next_pc_o     : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)

    -- csr data interface --

    csr_wdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data

    csr_rdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data

    -- interrupts (risc-v compliant) --

    msw_irq_i     : in  std_ulogic; -- machine software interrupt

    mext_irq_i    : in  std_ulogic; -- machine external interrupt

    mtime_irq_i   : in  std_ulogic; -- machine timer interrupt

    -- fast interrupts (custom) --

    firq_i        : in  std_ulogic_vector(3 downto 0);

    -- system time input from MTIME --

    time_i        : in  std_ulogic_vector(63 downto 0); -- current system time

    -- physical memory protection --

    pmp_addr_o     : out pmp_addr_if_t; -- addresses

    pmp_maddr_i    : in  pmp_addr_if_t; -- masked addresses

    pmp_ctrl_o     : out pmp_ctrl_if_t; -- configs

    priv_mode_o    : out std_ulogic_vector(1 downto 0); -- current CPU privilege level

    -- bus access exceptions --

    mar_i         : in  std_ulogic_vector(data_width_c-1 downto 0);  -- memory address register

    ma_instr_i    : in  std_ulogic; -- misaligned instruction address

    ma_load_i     : in  std_ulogic; -- misaligned load data address

    ma_store_i    : in  std_ulogic; -- misaligned store data address

    be_instr_i    : in  std_ulogic; -- bus error on instruction access

    be_load_i     : in  std_ulogic; -- bus error on load data access

    be_store_i    : in  std_ulogic  -- bus error on store data access

  );

end neorv32_cpu_control;

architecture neorv32_cpu_control_rtl of neorv32_cpu_control is

  -- instruction fetch enginge --

  type fetch_engine_state_t is (IFETCH_RESET, IFETCH_0, IFETCH_1, IFETCH_2);

  type fetch_engine_t is record

    state           : fetch_engine_state_t;

    state_nxt       : fetch_engine_state_t;

    i_buf           : std_ulogic_vector(33 downto 0);

    i_buf_nxt       : std_ulogic_vector(33 downto 0);

    i_buf2          : std_ulogic_vector(33 downto 0);

    i_buf2_nxt      : std_ulogic_vector(33 downto 0);

    ci_input        : std_ulogic_vector(15 downto 0); -- input to compressed instr. decoder

    i_buf_state     : std_ulogic_vector(01 downto 0);

    i_buf_state_nxt : std_ulogic_vector(01 downto 0);

    pc_real         : std_ulogic_vector(data_width_c-1 downto 0);

    pc_real_add     : std_ulogic_vector(data_width_c-1 downto 0);

    pc_fetch        : std_ulogic_vector(data_width_c-1 downto 0);

    pc_fetch_add    : std_ulogic_vector(data_width_c-1 downto 0);

    reset           : std_ulogic;

    bus_err_ack     : std_ulogic;

  end record;

  signal fetch_engine : fetch_engine_t;

  -- pre-decoder --

  signal ci_instr32 : std_ulogic_vector(31 downto 0);

  signal ci_illegal : std_ulogic;

  -- instrucion prefetch buffer (IPB) --

  type ipb_t is record

    wdata  : std_ulogic_vector(35 downto 0);

    rdata  : std_ulogic_vector(35 downto 0);

    waddr  : std_ulogic_vector(31 downto 0);

    raddr  : std_ulogic_vector(31 downto 0);

    status : std_ulogic;

    free   : std_ulogic;

    avail  : std_ulogic;

    we     : std_ulogic;

    re     : std_ulogic;

    clear  : std_ulogic;

  end record;

  signal ipb : ipb_t;

  -- instruction execution engine --

  type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, CSR_ACCESS);

  type execute_engine_t is record

    state        : execute_engine_state_t;

    state_nxt    : execute_engine_state_t;

    i_reg        : std_ulogic_vector(31 downto 0);

    i_reg_nxt    : std_ulogic_vector(31 downto 0);

    is_ci        : std_ulogic; -- current instruction is de-compressed instruction

    is_ci_nxt    : std_ulogic;

    is_jump      : std_ulogic; -- current instruction is jump instruction

    is_jump_nxt  : std_ulogic;

    branch_taken : std_ulogic; -- branch condition fullfilled

    pc           : std_ulogic_vector(data_width_c-1 downto 0); -- actual PC, corresponding to current executed instruction

    pc_nxt       : std_ulogic_vector(data_width_c-1 downto 0);

    next_pc      : std_ulogic_vector(data_width_c-1 downto 0); -- next PC, corresponding to next instruction to be executed

    last_pc      : std_ulogic_vector(data_width_c-1 downto 0); -- PC of last executed instruction

    sleep        : std_ulogic; -- CPU in sleep mode

    sleep_nxt    : std_ulogic; -- CPU in sleep mode

  end record;

  signal execute_engine : execute_engine_t;

  signal next_pc_tmp : std_ulogic_vector(data_width_c-1 downto 0);

  -- trap controller --

  type trap_ctrl_t is record

    exc_buf       : std_ulogic_vector(exception_width_c-1 downto 0);

    exc_fire      : std_ulogic; -- set if there is a valid source in the exception buffer

    irq_buf       : std_ulogic_vector(interrupt_width_c-1 downto 0);

    irq_fire      : std_ulogic; -- set if there is a valid source in the interrupt buffer

    exc_ack       : std_ulogic; -- acknowledge all exceptions

    irq_ack       : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt

    irq_ack_nxt   : std_ulogic_vector(interrupt_width_c-1 downto 0);

    cause         : std_ulogic_vector(5 downto 0); -- trap ID (for "mcause"), only for hw

    cause_nxt     : std_ulogic_vector(5 downto 0);

    --

    env_start     : std_ulogic; -- start trap handler env

    env_start_ack : std_ulogic; -- start of trap handler acknowledged

    env_end       : std_ulogic; -- end trap handler env

    --

    instr_be      : std_ulogic; -- instruction fetch bus error

    instr_ma      : std_ulogic; -- instruction fetch misaligned address

    instr_il      : std_ulogic; -- illegal instruction

    env_call      : std_ulogic;

    break_point   : std_ulogic;

  end record;

  signal trap_ctrl : trap_ctrl_t;

  -- CPU control signals --

  signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);

  -- fast bus access --

  signal bus_fast_ir : std_ulogic;

  -- RISC-V control and status registers (CSRs) --

  type pmp_ctrl_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(7 downto 0);

  type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);

  type csr_t is record

    we           : std_ulogic; -- write enable

    we_nxt       : std_ulogic;

    re           : std_ulogic; -- read enable

    re_nxt       : std_ulogic;

    mstatus_mie  : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)

    mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/-)

    mie_msie     : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)

    mie_meie     : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)

    mie_mtie     : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W

    mie_firqe    : std_ulogic_vector(3 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)

    mpp          : std_ulogic_vector(1 downto 0); -- machine previous privilege mode

    privilege    : std_ulogic_vector(1 downto 0); -- hart's current previous privilege mode

    mepc         : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)

    mcause       : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/-)

    mtvec        : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00

    mtval        : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W)

    mscratch     : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)

    mcycle       : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit

    minstret     : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit

    mcycleh      : std_ulogic_vector(19 downto 0); -- mcycleh (R/W) - REDUCED BIT-WIDTH!

    minstreth    : std_ulogic_vector(19 downto 0); -- minstreth (R/W) - REDUCED BIT-WIDTH!

    pmpcfg       : pmp_ctrl_t; -- physical memory protection - configuration registers

    pmpaddr      : pmp_addr_t; -- physical memory protection - address registers

  end record;

  signal csr : csr_t;

  signal mcycle_msb   : std_ulogic;

  signal minstret_msb : std_ulogic;

  signal systime      : std_ulogic_vector(63 downto 0);

  -- illegal instruction check --

  signal illegal_instruction : std_ulogic;

  signal illegal_register    : std_ulogic; -- only for E-extension

  signal illegal_compressed  : std_ulogic; -- only fir C-extension

  -- access (privilege) check --

  signal csr_acc_valid : std_ulogic; -- valid CSR access (implemented and valid access rights)

begin

-- ****************************************************************************************************************************

-- Instruction Fetch

-- ****************************************************************************************************************************

  -- Compressed Instructions Recoding -------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  neorv32_cpu_decompressor_inst_true:

  if (CPU_EXTENSION_RISCV_C = true) generate

    neorv32_cpu_decompressor_inst: neorv32_cpu_decompressor

    port map (

      -- instruction input --

      ci_instr16_i => fetch_engine.ci_input, -- compressed instruction input

      -- instruction output --

      ci_illegal_o => ci_illegal, -- is an illegal compressed instruction

      ci_instr32_o => ci_instr32  -- 32-bit decompressed instruction

    );

  end generate;

  neorv32_cpu_decompressor_inst_false:

  if (CPU_EXTENSION_RISCV_C = false) generate

    ci_instr32 <= (others => '0');

    ci_illegal <= '0';

  end generate;

  -- Fetch Engine FSM Sync ------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- for registers that require a specific reset state --

  fetch_engine_fsm_sync_rst: process(rstn_i, clk_i)

  begin

    if (rstn_i = '0') then

      fetch_engine.state <= IFETCH_RESET;

    elsif rising_edge(clk_i) then

      if (fetch_engine.reset = '1') then

        fetch_engine.state <= IFETCH_RESET;

      else

        fetch_engine.state <= fetch_engine.state_nxt;

      end if;

    end if;

  end process fetch_engine_fsm_sync_rst;

  -- for registers that DO NOT require a specific reset state --

  fetch_engine_fsm_sync: process(clk_i)

  begin

    if rising_edge(clk_i) then

      if (fetch_engine.state = IFETCH_RESET) then

        fetch_engine.pc_fetch  <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC

        fetch_engine.pc_real   <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC

      else

        fetch_engine.pc_real   <= std_ulogic_vector(unsigned(fetch_engine.pc_real(data_width_c-1 downto 1) & '0')  + unsigned(fetch_engine.pc_real_add(data_width_c-1 downto 1) & '0'));

        fetch_engine.pc_fetch  <= std_ulogic_vector(unsigned(fetch_engine.pc_fetch(data_width_c-1 downto 1) & '0') + unsigned(fetch_engine.pc_fetch_add(data_width_c-1 downto 1) & '0'));

      end if;

      --

      fetch_engine.i_buf       <= fetch_engine.i_buf_nxt;

      fetch_engine.i_buf2      <= fetch_engine.i_buf2_nxt;

      fetch_engine.i_buf_state <= fetch_engine.i_buf_state_nxt;

    end if;

  end process fetch_engine_fsm_sync;

  -- PC output --

  fetch_pc_o <= fetch_engine.pc_fetch(data_width_c-1 downto 1) & '0';

  -- Fetch Engine FSM Comb ------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  fetch_engine_fsm_comb: process(fetch_engine, csr, ipb, instr_i, bus_i_wait_i, ci_instr32, ci_illegal, be_instr_i, ma_instr_i)

  begin

    -- arbiter defaults --

    bus_fast_ir                  <= '0';

    fetch_engine.state_nxt       <= fetch_engine.state;

    fetch_engine.pc_fetch_add    <= (others => '0');

    fetch_engine.pc_real_add     <= (others => '0');

    fetch_engine.i_buf_nxt       <= fetch_engine.i_buf;

    fetch_engine.i_buf2_nxt      <= fetch_engine.i_buf2;

    fetch_engine.i_buf_state_nxt <= fetch_engine.i_buf_state;

    fetch_engine.ci_input        <= fetch_engine.i_buf2(15 downto 00);

    fetch_engine.bus_err_ack     <= '0';

    -- instruction prefetch buffer interface --

    ipb.we    <= '0';

    ipb.clear <= '0';

    ipb.wdata <= '0' & fetch_engine.i_buf2(33 downto 32) & '0' & fetch_engine.i_buf2(31 downto 0);

    ipb.waddr <= fetch_engine.pc_real(data_width_c-1 downto 1) & '0';

    -- state machine --

    case fetch_engine.state is

      when IFETCH_RESET => -- reset engine, prefetch buffer, get appilcation PC

      -- ------------------------------------------------------------

        fetch_engine.i_buf_state_nxt <= (others => '0');

        ipb.clear                    <= '1'; -- clear instruction prefetch buffer

        fetch_engine.state_nxt       <= IFETCH_0;

      when IFETCH_0 => -- output current PC to bus system, request 32-bit word

      -- ------------------------------------------------------------

        bus_fast_ir            <= '1'; -- fast instruction fetch request

        fetch_engine.state_nxt <= IFETCH_1;

      when IFETCH_1 => -- store data from memory to buffer(s)

      -- ------------------------------------------------------------

        if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response

          fetch_engine.i_buf_nxt       <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store data word and exception info

          fetch_engine.i_buf2_nxt      <= fetch_engine.i_buf;

          fetch_engine.i_buf_state_nxt <= fetch_engine.i_buf_state(0) & '1';

          fetch_engine.bus_err_ack     <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them

          if (fetch_engine.i_buf_state(0) = '1') then -- buffer filled?

            fetch_engine.state_nxt <= IFETCH_2;

          else

            fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));

            fetch_engine.state_nxt    <= IFETCH_0; -- get another instruction word

          end if;

        end if;

      when IFETCH_2 => -- construct instruction word and issue

      -- ------------------------------------------------------------

        if (fetch_engine.pc_fetch(1) = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned

          fetch_engine.ci_input <= fetch_engine.i_buf2(15 downto 00);

          if (ipb.free = '1') then -- free entry in buffer?

            ipb.we <= '1';

            if (fetch_engine.i_buf2(01 downto 00) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed

              ipb.wdata                 <= '0' & fetch_engine.i_buf2(33 downto 32) & '0' & fetch_engine.i_buf2(31 downto 0);

              fetch_engine.pc_real_add  <= std_ulogic_vector(to_unsigned(4, data_width_c));

              fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));

              fetch_engine.state_nxt    <= IFETCH_0;

            else -- compressed

              ipb.wdata                 <= ci_illegal & fetch_engine.i_buf2(33 downto 32) & '1' & ci_instr32;

              fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(2, data_width_c));

              fetch_engine.pc_real_add  <= std_ulogic_vector(to_unsigned(2, data_width_c));

              fetch_engine.state_nxt    <= IFETCH_2; -- try to get another 16-bit instruction word in next round

            end if;

          end if;

        else -- 16-bit aligned

          fetch_engine.ci_input <= fetch_engine.i_buf2(31 downto 16);

          if (ipb.free = '1') then -- free entry in buffer?

            ipb.we <= '1';

            if (fetch_engine.i_buf2(17 downto 16) = "11") then -- uncompressed

              ipb.wdata                 <= '0' & fetch_engine.i_buf(33 downto 32) & '0' & fetch_engine.i_buf(15 downto 00) & fetch_engine.i_buf2(31 downto 16);

              fetch_engine.pc_real_add  <= std_ulogic_vector(to_unsigned(4, data_width_c));

              fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));

              fetch_engine.state_nxt    <= IFETCH_0;

            else -- uncompressed

              ipb.wdata                 <= ci_illegal & fetch_engine.i_buf(33 downto 32) & '1' & ci_instr32;

              fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(2, data_width_c));

              fetch_engine.pc_real_add  <= std_ulogic_vector(to_unsigned(2, data_width_c));

              fetch_engine.state_nxt    <= IFETCH_0;

            end if;

          end if;

       end if;

      when others => -- undefined

      -- ------------------------------------------------------------

        fetch_engine.state_nxt <= IFETCH_RESET;

    end case;

  end process fetch_engine_fsm_comb;

-- ****************************************************************************************************************************

-- Instruction Prefetch Buffer

-- ****************************************************************************************************************************

  -- Instruction Prefetch Buffer Stage ------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  instr_prefetch_buffer: process(rstn_i, clk_i) -- once upon a time, this was a fifo with 8 entries

  begin

    if (rstn_i = '0') then

      ipb.status <= '0';

      ipb.rdata  <= (others => '0');

      ipb.raddr  <= (others => '0');

    elsif rising_edge(clk_i) then

      if (ipb.clear = '1') then

        ipb.status <= '0';

      elsif (ipb.we = '1') then

        ipb.status <= '1';

      elsif (ipb.re = '1') then

        ipb.status <= '0';

      end if;

      if (ipb.we = '1') then

        ipb.rdata <= ipb.wdata;

        ipb.raddr <= ipb.waddr;

      end if;

    end if;

  end process instr_prefetch_buffer;

  -- status --

  ipb.free  <= not ipb.status;

  ipb.avail <= ipb.status;

-- ****************************************************************************************************************************

-- Instruction Execution

-- ****************************************************************************************************************************

  -- Immediate Generator --------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  imm_gen: process(clk_i)

  begin

    if rising_edge(clk_i) then

      case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is

        when opcode_store_c => -- S-immediate

          imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension

          imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);

          imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);

          imm_o(00)           <= execute_engine.i_reg(07);

        when opcode_branch_c => -- B-immediate

          imm_o(31 downto 12) <= (others => execute_engine.i_reg(31)); -- sign extension

          imm_o(11)           <= execute_engine.i_reg(07);

          imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);

          imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);

          imm_o(00)           <= '0';

        when opcode_lui_c | opcode_auipc_c => -- U-immediate

          imm_o(31 downto 20) <= execute_engine.i_reg(31 downto 20);

          imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);

          imm_o(11 downto 00) <= (others => '0');

        when opcode_jal_c => -- J-immediate

          imm_o(31 downto 20) <= (others => execute_engine.i_reg(31)); -- sign extension

          imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);

          imm_o(11)           <= execute_engine.i_reg(20);

          imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);

          imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);

          imm_o(00)           <= '0';

        when opcode_syscsr_c => -- CSR-immediate

          imm_o(31 downto 05) <= (others => '0');

          imm_o(04 downto 00) <= execute_engine.i_reg(19 downto 15);

        when others => -- I-immediate

          imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension

          imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);

          imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);

          imm_o(00)           <= execute_engine.i_reg(20);

      end case;

    end if;

  end process imm_gen;

  -- Branch Condition Check -----------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  branch_check: process(execute_engine.i_reg, cmp_i)

  begin

    case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is

      when funct3_beq_c => -- branch if equal

        execute_engine.branch_taken <= cmp_i(alu_cmp_equal_c);

      when funct3_bne_c => -- branch if not equal

        execute_engine.branch_taken <= not cmp_i(alu_cmp_equal_c);

      when funct3_blt_c | funct3_bltu_c => -- branch if less (signed/unsigned)

        execute_engine.branch_taken <= cmp_i(alu_cmp_less_c);

      when funct3_bge_c | funct3_bgeu_c => -- branch if greater or equal (signed/unsigned)

        execute_engine.branch_taken <= not cmp_i(alu_cmp_less_c);

      when others => -- undefined

        execute_engine.branch_taken <= '0';

    end case;

  end process branch_check;

  -- Execute Engine FSM Sync ----------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- for registers that DO require a specific reset state --

  execute_engine_fsm_sync_rst: process(rstn_i, clk_i)

  begin

    if (rstn_i = '0') then

      execute_engine.pc      <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';

      execute_engine.last_pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';

      execute_engine.state   <= SYS_WAIT;

      execute_engine.sleep   <= '0';

    elsif rising_edge(clk_i) then

      execute_engine.pc    <= execute_engine.pc_nxt(data_width_c-1 downto 1) & '0';

      if (execute_engine.state = EXECUTE) then

        execute_engine.last_pc <= execute_engine.pc(data_width_c-1 downto 1) & '0';

      end if;

      execute_engine.state <= execute_engine.state_nxt;

      execute_engine.sleep <= execute_engine.sleep_nxt;

    end if;

  end process execute_engine_fsm_sync_rst;

  -- for registers that do NOT require a specific reset state --

  execute_engine_fsm_sync: process(clk_i)

  begin

    if rising_edge(clk_i) then

      execute_engine.i_reg   <= execute_engine.i_reg_nxt;

      execute_engine.is_ci   <= execute_engine.is_ci_nxt;

      execute_engine.is_jump <= execute_engine.is_jump_nxt;

      -- control signals --

      ctrl <= ctrl_nxt;

    end if;

  end process execute_engine_fsm_sync;

  -- PC output --

  next_pc_tmp <= std_ulogic_vector(unsigned(execute_engine.pc) + 2) when (execute_engine.is_ci = '1') else std_ulogic_vector(unsigned(execute_engine.pc) + 4);

  execute_engine.next_pc <= next_pc_tmp(data_width_c-1 downto 1) & '0';

  next_pc_o              <= next_pc_tmp(data_width_c-1 downto 1) & '0';

  curr_pc_o              <= execute_engine.pc(data_width_c-1 downto 1) & '0';

  -- CPU Control Bus Output -----------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  ctrl_output: process(ctrl, execute_engine, fetch_engine, trap_ctrl, csr, bus_fast_ir)

  begin

    ctrl_o <= ctrl;

    -- direct output of register addresses --

    ctrl_o(ctrl_rf_rd_adr4_c  downto ctrl_rf_rd_adr0_c)  <= execute_engine.i_reg(instr_rd_msb_c  downto instr_rd_lsb_c);

    ctrl_o(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c);

    ctrl_o(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c);

    -- fast bus access requests --

    ctrl_o(ctrl_bus_if_c) <= ctrl(ctrl_bus_if_c) or bus_fast_ir;

    -- bus error control --

    ctrl_o(ctrl_bus_ierr_ack_c) <= fetch_engine.bus_err_ack;

    ctrl_o(ctrl_bus_derr_ack_c) <= trap_ctrl.env_start_ack;

  end process ctrl_output;

  -- Execute Engine FSM Comb ----------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  execute_engine_fsm_comb: process(execute_engine, fetch_engine, ipb, trap_ctrl, csr, ctrl, csr_acc_valid,

                                   alu_add_i, alu_wait_i, bus_d_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i)

    variable alu_immediate_v : std_ulogic;

    variable alu_operation_v : std_ulogic_vector(2 downto 0);

    variable rs1_is_r0_v     : std_ulogic;

  begin

    -- arbiter defaults --

    execute_engine.state_nxt   <= execute_engine.state;

    execute_engine.i_reg_nxt   <= execute_engine.i_reg;

    execute_engine.is_jump_nxt <= '0';

    execute_engine.is_ci_nxt   <= execute_engine.is_ci;

    execute_engine.pc_nxt      <= execute_engine.pc;

    execute_engine.sleep_nxt   <= execute_engine.sleep;

    -- instruction dispatch --

    fetch_engine.reset         <= '0';

    ipb.re                     <= '0';

    -- trap environment control --

    trap_ctrl.env_start_ack    <= '0';