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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_control.vhd] - Blame information for rev 52

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1 2 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - CPU Control >>                                                                   #
3
-- # ********************************************************************************************* #
4 31 zero_gravi
-- # CPU operation is split into a fetch engine (responsible for fetching instruction data), an    #
5
-- # issue engine (for recoding compressed instructions and for constructing 32-bit instruction    #
6
-- # words) and an execute engine (responsible for actually executing the instructions), a trap    #
7 44 zero_gravi
-- # handling controller and the RISC-V status and control register set (CSRs) including the       #
8
-- # hardware performance monitor counters.                                                        #
9 2 zero_gravi
-- # ********************************************************************************************* #
10
-- # BSD 3-Clause License                                                                          #
11
-- #                                                                                               #
12 42 zero_gravi
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
13 2 zero_gravi
-- #                                                                                               #
14
-- # Redistribution and use in source and binary forms, with or without modification, are          #
15
-- # permitted provided that the following conditions are met:                                     #
16
-- #                                                                                               #
17
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
18
-- #    conditions and the following disclaimer.                                                   #
19
-- #                                                                                               #
20
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
21
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
22
-- #    provided with the distribution.                                                            #
23
-- #                                                                                               #
24
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
25
-- #    endorse or promote products derived from this software without specific prior written      #
26
-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
29
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
30
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
31
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
32
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
33
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
35
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
36
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
38
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
39
-- #################################################################################################
40
 
41
library ieee;
42
use ieee.std_logic_1164.all;
43
use ieee.numeric_std.all;
44
 
45
library neorv32;
46
use neorv32.neorv32_package.all;
47
 
48
entity neorv32_cpu_control is
49
  generic (
50
    -- General --
51 49 zero_gravi
    HW_THREAD_ID                 : natural := 0;     -- hardware thread id (32-bit)
52 12 zero_gravi
    CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
53 2 zero_gravi
    -- RISC-V CPU Extensions --
54 39 zero_gravi
    CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
55 44 zero_gravi
    CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
56 12 zero_gravi
    CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
57
    CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
58 52 zero_gravi
    CPU_EXTENSION_RISCV_F        : boolean := false; -- implement 32-bit floating-point extension?
59 12 zero_gravi
    CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
60 15 zero_gravi
    CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
61 12 zero_gravi
    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
62 49 zero_gravi
    CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
63 15 zero_gravi
    -- Physical memory protection (PMP) --
64 42 zero_gravi
    PMP_NUM_REGIONS              : natural := 0;       -- number of regions (0..64)
65
    PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
66
    -- Hardware Performance Monitors (HPM) --
67 47 zero_gravi
    HPM_NUM_CNTS                 : natural := 0      -- number of implemented HPM counters (0..29)
68 2 zero_gravi
  );
69
  port (
70
    -- global control --
71
    clk_i         : in  std_ulogic; -- global clock, rising edge
72
    rstn_i        : in  std_ulogic; -- global reset, low-active, async
73
    ctrl_o        : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
74
    -- status input --
75
    alu_wait_i    : in  std_ulogic; -- wait for ALU
76 12 zero_gravi
    bus_i_wait_i  : in  std_ulogic; -- wait for bus
77
    bus_d_wait_i  : in  std_ulogic; -- wait for bus
78 2 zero_gravi
    -- data input --
79
    instr_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- instruction
80
    cmp_i         : in  std_ulogic_vector(1 downto 0); -- comparator status
81 36 zero_gravi
    alu_add_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result
82
    rs1_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
83 2 zero_gravi
    -- data output --
84
    imm_o         : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
85 6 zero_gravi
    fetch_pc_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
86
    curr_pc_o     : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
87 2 zero_gravi
    csr_rdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
88 52 zero_gravi
    -- FPU interface --
89
    fpu_rm_o      : out std_ulogic_vector(02 downto 0); -- rounding mode
90
    fpu_flags_i   : in  std_ulogic_vector(04 downto 0); -- exception flags
91 14 zero_gravi
    -- interrupts (risc-v compliant) --
92
    msw_irq_i     : in  std_ulogic; -- machine software interrupt
93
    mext_irq_i    : in  std_ulogic; -- machine external interrupt
94 2 zero_gravi
    mtime_irq_i   : in  std_ulogic; -- machine timer interrupt
95 14 zero_gravi
    -- fast interrupts (custom) --
96 48 zero_gravi
    firq_i        : in  std_ulogic_vector(15 downto 0);
97
    firq_ack_o    : out std_ulogic_vector(15 downto 0);
98 11 zero_gravi
    -- system time input from MTIME --
99
    time_i        : in  std_ulogic_vector(63 downto 0); -- current system time
100 15 zero_gravi
    -- physical memory protection --
101 23 zero_gravi
    pmp_addr_o    : out pmp_addr_if_t; -- addresses
102
    pmp_ctrl_o    : out pmp_ctrl_if_t; -- configs
103 2 zero_gravi
    -- bus access exceptions --
104
    mar_i         : in  std_ulogic_vector(data_width_c-1 downto 0);  -- memory address register
105
    ma_instr_i    : in  std_ulogic; -- misaligned instruction address
106
    ma_load_i     : in  std_ulogic; -- misaligned load data address
107
    ma_store_i    : in  std_ulogic; -- misaligned store data address
108
    be_instr_i    : in  std_ulogic; -- bus error on instruction access
109
    be_load_i     : in  std_ulogic; -- bus error on load data access
110 12 zero_gravi
    be_store_i    : in  std_ulogic  -- bus error on store data access
111 2 zero_gravi
  );
112
end neorv32_cpu_control;
113
 
114
architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
115
 
116 6 zero_gravi
  -- instruction fetch enginge --
117 31 zero_gravi
  type fetch_engine_state_t is (IFETCH_RESET, IFETCH_REQUEST, IFETCH_ISSUE);
118 6 zero_gravi
  type fetch_engine_t is record
119 31 zero_gravi
    state       : fetch_engine_state_t;
120
    state_nxt   : fetch_engine_state_t;
121 42 zero_gravi
    state_prev  : fetch_engine_state_t;
122 31 zero_gravi
    pc          : std_ulogic_vector(data_width_c-1 downto 0);
123
    pc_nxt      : std_ulogic_vector(data_width_c-1 downto 0);
124
    reset       : std_ulogic;
125
    bus_err_ack : std_ulogic;
126 6 zero_gravi
  end record;
127
  signal fetch_engine : fetch_engine_t;
128 2 zero_gravi
 
129 32 zero_gravi
  -- instrucion prefetch buffer (IPB, real FIFO) --
130 31 zero_gravi
  type ipb_data_fifo_t is array (0 to ipb_entries_c-1) of std_ulogic_vector(2+31 downto 0);
131 6 zero_gravi
  type ipb_t is record
132 31 zero_gravi
    wdata : std_ulogic_vector(2+31 downto 0); -- write status (bus_error, align_error) + 32-bit instruction data
133
    we    : std_ulogic; -- trigger write
134
    free  : std_ulogic; -- free entry available?
135
    clear : std_ulogic; -- clear all entries
136 20 zero_gravi
    --
137 31 zero_gravi
    rdata : std_ulogic_vector(2+31 downto 0); -- read data: status (bus_error, align_error) + 32-bit instruction data
138
    re    : std_ulogic; -- read enable
139
    avail : std_ulogic; -- data available?
140 20 zero_gravi
    --
141 31 zero_gravi
    w_pnt : std_ulogic_vector(index_size_f(ipb_entries_c) downto 0); -- write pointer
142
    r_pnt : std_ulogic_vector(index_size_f(ipb_entries_c) downto 0); -- read pointer
143 34 zero_gravi
    match : std_ulogic;
144 31 zero_gravi
    empty : std_ulogic;
145
    full  : std_ulogic;
146 20 zero_gravi
    --
147 31 zero_gravi
    data  : ipb_data_fifo_t; -- fifo memory
148 6 zero_gravi
  end record;
149
  signal ipb : ipb_t;
150 2 zero_gravi
 
151 31 zero_gravi
  -- pre-decoder --
152
  signal ci_instr16 : std_ulogic_vector(15 downto 0);
153
  signal ci_instr32 : std_ulogic_vector(31 downto 0);
154
  signal ci_illegal : std_ulogic;
155
 
156
  -- instruction issue enginge --
157
  type issue_engine_state_t is (ISSUE_ACTIVE, ISSUE_REALIGN);
158
  type issue_engine_t is record
159
    state     : issue_engine_state_t;
160
    state_nxt : issue_engine_state_t;
161
    align     : std_ulogic;
162
    align_nxt : std_ulogic;
163
    buf       : std_ulogic_vector(2+15 downto 0);
164
    buf_nxt   : std_ulogic_vector(2+15 downto 0);
165
  end record;
166
  signal issue_engine : issue_engine_t;
167
 
168 37 zero_gravi
  -- instruction issue interface --
169
  type cmd_issue_t is record
170
    data  : std_ulogic_vector(35 downto 0); -- 4-bit status + 32-bit instruction
171
    valid : std_ulogic; -- data word is valid when set
172 31 zero_gravi
  end record;
173 37 zero_gravi
  signal cmd_issue : cmd_issue_t;
174 31 zero_gravi
 
175 44 zero_gravi
  -- instruction decoding helper logic --
176
  type decode_aux_t is record
177
    alu_immediate   : std_ulogic;
178
    rs1_is_r0       : std_ulogic;
179
    is_atomic_lr    : std_ulogic;
180
    is_atomic_sc    : std_ulogic;
181
    is_bitmanip_imm : std_ulogic;
182
    is_bitmanip_reg : std_ulogic;
183 52 zero_gravi
    is_float_f_reg  : std_ulogic;
184
    is_float_i_reg  : std_ulogic;
185 49 zero_gravi
    sys_env_cmd     : std_ulogic_vector(11 downto 0);
186 44 zero_gravi
  end record;
187
  signal decode_aux : decode_aux_t;
188
 
189 6 zero_gravi
  -- instruction execution engine --
190 49 zero_gravi
  type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP_ENTER, TRAP_EXIT, TRAP_EXECUTE, EXECUTE, ALU_WAIT,
191
                                  BRANCH, FENCE_OP,LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, SYS_ENV, CSR_ACCESS);
192 6 zero_gravi
  type execute_engine_t is record
193
    state        : execute_engine_state_t;
194
    state_nxt    : execute_engine_state_t;
195 42 zero_gravi
    state_prev   : execute_engine_state_t;
196 39 zero_gravi
    --
197 6 zero_gravi
    i_reg        : std_ulogic_vector(31 downto 0);
198
    i_reg_nxt    : std_ulogic_vector(31 downto 0);
199 33 zero_gravi
    i_reg_last   : std_ulogic_vector(31 downto 0); -- last executed instruction
200 39 zero_gravi
    --
201 6 zero_gravi
    is_ci        : std_ulogic; -- current instruction is de-compressed instruction
202
    is_ci_nxt    : std_ulogic;
203 29 zero_gravi
    is_cp_op     : std_ulogic; -- current instruction is a co-processor operation
204
    is_cp_op_nxt : std_ulogic;
205 52 zero_gravi
    is_fp        : std_ulogic; -- floating-point operation - do not access to integer register file
206
    is_fp_nxt    : std_ulogic;
207 39 zero_gravi
    --
208 6 zero_gravi
    branch_taken : std_ulogic; -- branch condition fullfilled
209
    pc           : std_ulogic_vector(data_width_c-1 downto 0); -- actual PC, corresponding to current executed instruction
210 49 zero_gravi
    pc_mux_sel   : std_ulogic; -- source select for PC update
211 39 zero_gravi
    pc_we        : std_ulogic; -- PC update enabled
212 6 zero_gravi
    next_pc      : std_ulogic_vector(data_width_c-1 downto 0); -- next PC, corresponding to next instruction to be executed
213 49 zero_gravi
    next_pc_inc  : std_ulogic_vector(data_width_c-1 downto 0); -- increment to get next PC
214 6 zero_gravi
    last_pc      : std_ulogic_vector(data_width_c-1 downto 0); -- PC of last executed instruction
215 39 zero_gravi
    --
216 11 zero_gravi
    sleep        : std_ulogic; -- CPU in sleep mode
217 39 zero_gravi
    sleep_nxt    : std_ulogic;
218 49 zero_gravi
    branched     : std_ulogic; -- instruction fetch was reset
219
    branched_nxt : std_ulogic;
220 6 zero_gravi
  end record;
221
  signal execute_engine : execute_engine_t;
222 2 zero_gravi
 
223 6 zero_gravi
  -- trap controller --
224
  type trap_ctrl_t is record
225
    exc_buf       : std_ulogic_vector(exception_width_c-1 downto 0);
226
    exc_fire      : std_ulogic; -- set if there is a valid source in the exception buffer
227
    irq_buf       : std_ulogic_vector(interrupt_width_c-1 downto 0);
228 48 zero_gravi
    firq_sync     : std_ulogic_vector(15 downto 0);
229 6 zero_gravi
    irq_fire      : std_ulogic; -- set if there is a valid source in the interrupt buffer
230
    exc_ack       : std_ulogic; -- acknowledge all exceptions
231
    irq_ack       : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt
232
    irq_ack_nxt   : std_ulogic_vector(interrupt_width_c-1 downto 0);
233 40 zero_gravi
    cause         : std_ulogic_vector(5 downto 0); -- trap ID for mcause CSR
234 14 zero_gravi
    cause_nxt     : std_ulogic_vector(5 downto 0);
235 6 zero_gravi
    --
236
    env_start     : std_ulogic; -- start trap handler env
237
    env_start_ack : std_ulogic; -- start of trap handler acknowledged
238
    env_end       : std_ulogic; -- end trap handler env
239
    --
240
    instr_be      : std_ulogic; -- instruction fetch bus error
241
    instr_ma      : std_ulogic; -- instruction fetch misaligned address
242
    instr_il      : std_ulogic; -- illegal instruction
243
    env_call      : std_ulogic;
244
    break_point   : std_ulogic;
245
  end record;
246
  signal trap_ctrl : trap_ctrl_t;
247 39 zero_gravi
 
248
  -- atomic operations controller --
249
  type atomic_ctrl_t is record
250
    env_start  : std_ulogic; -- begin atomic operations
251
    env_end    : std_ulogic; -- end atomic operations
252
    env_end_ff : std_ulogic; -- end atomic operations dealyed
253
    env_abort  : std_ulogic; -- atomic operations abort (results in failure)
254
    lock       : std_ulogic; -- lock status
255
  end record;
256
  signal atomic_ctrl : atomic_ctrl_t;
257 6 zero_gravi
 
258 40 zero_gravi
  -- CPU main control bus --
259 6 zero_gravi
  signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
260 2 zero_gravi
 
261 40 zero_gravi
  -- fast instruction fetch access --
262 6 zero_gravi
  signal bus_fast_ir : std_ulogic;
263 2 zero_gravi
 
264 6 zero_gravi
  -- RISC-V control and status registers (CSRs) --
265 42 zero_gravi
  type pmp_ctrl_t     is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(7 downto 0);
266
  type pmp_addr_t     is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
267
  type pmp_ctrl_rd_t  is array (0 to 63) of std_ulogic_vector(7 downto 0);
268
  type pmp_addr_rd_t  is array (0 to 63) of std_ulogic_vector(data_width_c-1 downto 0);
269
  type mhpmevent_t    is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
270
  type mhpmcnt_t      is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(32 downto 0);
271
  type mhpmcnth_t     is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(31 downto 0);
272
  type mhpmevent_rd_t is array (0 to 29) of std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
273
  type mhpmcnt_rd_t   is array (0 to 29) of std_ulogic_vector(32 downto 0);
274
  type mhpmcnth_rd_t  is array (0 to 29) of std_ulogic_vector(31 downto 0);
275 6 zero_gravi
  type csr_t is record
276 42 zero_gravi
    addr              : std_ulogic_vector(11 downto 0); -- csr address
277
    we                : std_ulogic; -- csr write enable
278
    we_nxt            : std_ulogic;
279
    re                : std_ulogic; -- csr read enable
280
    re_nxt            : std_ulogic;
281
    wdata             : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data
282
    rdata             : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
283 29 zero_gravi
    --
284 42 zero_gravi
    mstatus_mie       : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
285
    mstatus_mpie      : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/W)
286
    mstatus_mpp       : std_ulogic_vector(1 downto 0); -- mstatus.MPP: machine previous privilege mode
287 29 zero_gravi
    --
288 42 zero_gravi
    mie_msie          : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
289
    mie_meie          : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
290
    mie_mtie          : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)
291 48 zero_gravi
    mie_firqe         : std_ulogic_vector(15 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)
292 29 zero_gravi
    --
293 42 zero_gravi
    mcounteren_cy     : std_ulogic; -- mcounteren.cy: allow cycle[h] access from user-mode
294
    mcounteren_tm     : std_ulogic; -- mcounteren.tm: allow time[h] access from user-mode
295
    mcounteren_ir     : std_ulogic; -- mcounteren.ir: allow instret[h] access from user-mode
296
    mcounteren_hpm    : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0); -- mcounteren.hpmx: allow mhpmcounterx[h] access from user-mode
297 29 zero_gravi
    --
298 42 zero_gravi
    mcountinhibit_cy  : std_ulogic; -- mcounterinhibit.cy: enable auto-increment for [m]cycle[h]
299
    mcountinhibit_ir  : std_ulogic; -- mcounterinhibit.ir: enable auto-increment for [m]instret[h]
300
    mcountinhibit_hpm : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0); -- mcounterinhibit.hpm3: enable auto-increment for mhpmcounterx[h]
301 40 zero_gravi
    --
302 42 zero_gravi
    mip_status        : std_ulogic_vector(interrupt_width_c-1  downto 0); -- current buffered IRQs
303
    mip_clear         : std_ulogic_vector(interrupt_width_c-1  downto 0); -- set bits clear the according buffered IRQ
304 41 zero_gravi
    --
305 42 zero_gravi
    privilege         : std_ulogic_vector(1 downto 0); -- hart's current privilege mode
306
    priv_m_mode       : std_ulogic; -- CPU in M-mode
307
    priv_u_mode       : std_ulogic; -- CPU in u-mode
308 41 zero_gravi
    --
309 42 zero_gravi
    mepc              : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)
310 49 zero_gravi
    mcause            : std_ulogic_vector(5 downto 0); -- mcause: machine trap cause (R/W)
311 42 zero_gravi
    mtvec             : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00
312 49 zero_gravi
    mtval             : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or instruction (R/W)
313 42 zero_gravi
    --
314
    mhpmevent         : mhpmevent_t; -- mhpmevent*: machine performance-monitoring event selector (R/W)
315
    mhpmevent_rd      : mhpmevent_rd_t; -- mhpmevent*: actual read data
316
    --
317
    mscratch          : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
318
    mcycle            : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit
319
    minstret          : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit
320
    --
321
    mcycleh           : std_ulogic_vector(31 downto 0); -- mcycleh (R/W)
322
    minstreth         : std_ulogic_vector(31 downto 0); -- minstreth (R/W)
323
    --
324
    mhpmcounter       : mhpmcnt_t; -- mhpmcounter* (R/W), plus carry bit
325
    mhpmcounterh      : mhpmcnth_t; -- mhpmcounter*h (R/W)
326
    mhpmcounter_rd    : mhpmcnt_rd_t; -- mhpmcounter* (R/W): actual read data
327
    mhpmcounterh_rd   : mhpmcnth_rd_t; -- mhpmcounter*h (R/W): actual read data
328
    --
329
    pmpcfg            : pmp_ctrl_t; -- physical memory protection - configuration registers
330
    pmpcfg_rd         : pmp_ctrl_rd_t; -- physical memory protection - actual read data
331
    pmpaddr           : pmp_addr_t; -- physical memory protection - address registers
332
    pmpaddr_rd        : pmp_addr_rd_t; -- physical memory protection - actual read data
333 52 zero_gravi
    --
334
    frm               : std_ulogic_vector(02 downto 0); -- frm (R/W): FPU rounding mode
335
    fflags            : std_ulogic_vector(04 downto 0); -- fflags (R/W): FPU exception flags
336 6 zero_gravi
  end record;
337
  signal csr : csr_t;
338 2 zero_gravi
 
339 42 zero_gravi
  -- counter low-to-high-word carry --
340
  signal mcycle_msb      : std_ulogic;
341
  signal minstret_msb    : std_ulogic;
342
  signal mhpmcounter_msb : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0);
343 2 zero_gravi
 
344 42 zero_gravi
  -- (hpm) counter events --
345
  signal cnt_event, cnt_event_nxt : std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
346
  signal hpmcnt_trigger           : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0);
347
 
348 6 zero_gravi
  -- illegal instruction check --
349 36 zero_gravi
  signal illegal_opcode_lsbs : std_ulogic; -- if opcode != rv32
350 2 zero_gravi
  signal illegal_instruction : std_ulogic;
351
  signal illegal_register    : std_ulogic; -- only for E-extension
352
  signal illegal_compressed  : std_ulogic; -- only fir C-extension
353
 
354 15 zero_gravi
  -- access (privilege) check --
355
  signal csr_acc_valid : std_ulogic; -- valid CSR access (implemented and valid access rights)
356
 
357 2 zero_gravi
begin
358
 
359 6 zero_gravi
-- ****************************************************************************************************************************
360 31 zero_gravi
-- Instruction Fetch (always fetches aligned 32-bit chunks of data)
361 6 zero_gravi
-- ****************************************************************************************************************************
362
 
363
  -- Fetch Engine FSM Sync ------------------------------------------------------------------
364
  -- -------------------------------------------------------------------------------------------
365 31 zero_gravi
  fetch_engine_fsm_sync: process(rstn_i, clk_i)
366 6 zero_gravi
  begin
367
    if (rstn_i = '0') then
368 42 zero_gravi
      fetch_engine.state      <= IFETCH_RESET;
369
      fetch_engine.state_prev <= IFETCH_RESET;
370
      fetch_engine.pc         <= (others => '0');
371 6 zero_gravi
    elsif rising_edge(clk_i) then
372
      if (fetch_engine.reset = '1') then
373
        fetch_engine.state <= IFETCH_RESET;
374
      else
375
        fetch_engine.state <= fetch_engine.state_nxt;
376
      end if;
377 42 zero_gravi
      fetch_engine.state_prev <= fetch_engine.state;
378
      fetch_engine.pc         <= fetch_engine.pc_nxt;
379 6 zero_gravi
    end if;
380
  end process fetch_engine_fsm_sync;
381
 
382 12 zero_gravi
  -- PC output --
383 31 zero_gravi
  fetch_pc_o <= fetch_engine.pc(data_width_c-1 downto 1) & '0'; -- half-word aligned
384 6 zero_gravi
 
385 12 zero_gravi
 
386 6 zero_gravi
  -- Fetch Engine FSM Comb ------------------------------------------------------------------
387
  -- -------------------------------------------------------------------------------------------
388 31 zero_gravi
  fetch_engine_fsm_comb: process(fetch_engine, execute_engine, ipb, instr_i, bus_i_wait_i, be_instr_i, ma_instr_i)
389 6 zero_gravi
  begin
390
    -- arbiter defaults --
391 31 zero_gravi
    bus_fast_ir              <= '0';
392
    fetch_engine.state_nxt   <= fetch_engine.state;
393
    fetch_engine.pc_nxt      <= fetch_engine.pc;
394
    fetch_engine.bus_err_ack <= '0';
395 6 zero_gravi
 
396
    -- instruction prefetch buffer interface --
397
    ipb.we    <= '0';
398 31 zero_gravi
    ipb.wdata <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store exception info and instruction word
399 6 zero_gravi
    ipb.clear <= '0';
400
 
401
    -- state machine --
402
    case fetch_engine.state is
403
 
404 49 zero_gravi
      when IFETCH_RESET => -- reset engine and prefetch buffer, get application PC
405 6 zero_gravi
      -- ------------------------------------------------------------
406 31 zero_gravi
        fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them / terminate current transfer
407
        fetch_engine.pc_nxt      <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC
408
        ipb.clear                <= '1'; -- clear prefetch buffer
409
        fetch_engine.state_nxt   <= IFETCH_REQUEST;
410 6 zero_gravi
 
411 31 zero_gravi
      when IFETCH_REQUEST => -- output current PC to bus system and request 32-bit (aligned!) instruction data
412 6 zero_gravi
      -- ------------------------------------------------------------
413 31 zero_gravi
        if (ipb.free = '1') then -- free entry in buffer?
414
          bus_fast_ir            <= '1'; -- fast instruction fetch request
415
          fetch_engine.state_nxt <= IFETCH_ISSUE;
416
        end if;
417 6 zero_gravi
 
418 31 zero_gravi
      when IFETCH_ISSUE => -- store instruction data to prefetch buffer
419 6 zero_gravi
      -- ------------------------------------------------------------
420 41 zero_gravi
        fetch_engine.bus_err_ack <= be_instr_i or ma_instr_i; -- ACK bus/alignment errors
421 12 zero_gravi
        if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
422 39 zero_gravi
          fetch_engine.pc_nxt    <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4);
423
          ipb.we                 <= '1';
424
          fetch_engine.state_nxt <= IFETCH_REQUEST;
425 6 zero_gravi
        end if;
426 11 zero_gravi
 
427 6 zero_gravi
      when others => -- undefined
428
      -- ------------------------------------------------------------
429
        fetch_engine.state_nxt <= IFETCH_RESET;
430
 
431
    end case;
432
  end process fetch_engine_fsm_comb;
433
 
434
 
435
-- ****************************************************************************************************************************
436
-- Instruction Prefetch Buffer
437
-- ****************************************************************************************************************************
438
 
439
 
440 20 zero_gravi
  -- Instruction Prefetch Buffer (FIFO) -----------------------------------------------------
441 6 zero_gravi
  -- -------------------------------------------------------------------------------------------
442 36 zero_gravi
  instr_prefetch_buffer: process(clk_i)
443 6 zero_gravi
  begin
444 36 zero_gravi
    if rising_edge(clk_i) then
445 20 zero_gravi
      -- write port --
446 6 zero_gravi
      if (ipb.clear = '1') then
447 20 zero_gravi
        ipb.w_pnt <= (others => '0');
448 6 zero_gravi
      elsif (ipb.we = '1') then
449 20 zero_gravi
        ipb.w_pnt <= std_ulogic_vector(unsigned(ipb.w_pnt) + 1);
450
      end if;
451 37 zero_gravi
      if (ipb.we = '1') then -- write data
452 36 zero_gravi
        ipb.data(to_integer(unsigned(ipb.w_pnt(ipb.w_pnt'left-1 downto 0)))) <= ipb.wdata;
453
      end if;
454
      -- read port --
455 20 zero_gravi
      if (ipb.clear = '1') then
456
        ipb.r_pnt <= (others => '0');
457 6 zero_gravi
      elsif (ipb.re = '1') then
458 20 zero_gravi
        ipb.r_pnt <= std_ulogic_vector(unsigned(ipb.r_pnt) + 1);
459 6 zero_gravi
      end if;
460 20 zero_gravi
    end if;
461 36 zero_gravi
  end process instr_prefetch_buffer;
462 20 zero_gravi
 
463
  -- async read --
464 31 zero_gravi
  ipb.rdata <= ipb.data(to_integer(unsigned(ipb.r_pnt(ipb.r_pnt'left-1 downto 0))));
465 20 zero_gravi
 
466 6 zero_gravi
  -- status --
467 40 zero_gravi
  ipb.match <= '1' when (ipb.r_pnt(ipb.r_pnt'left-1 downto 0) = ipb.w_pnt(ipb.w_pnt'left-1 downto 0))  else '0';
468 34 zero_gravi
  ipb.full  <= '1' when (ipb.r_pnt(ipb.r_pnt'left) /= ipb.w_pnt(ipb.w_pnt'left)) and (ipb.match = '1') else '0';
469
  ipb.empty <= '1' when (ipb.r_pnt(ipb.r_pnt'left)  = ipb.w_pnt(ipb.w_pnt'left)) and (ipb.match = '1') else '0';
470 20 zero_gravi
  ipb.free  <= not ipb.full;
471
  ipb.avail <= not ipb.empty;
472 6 zero_gravi
 
473
 
474
-- ****************************************************************************************************************************
475 31 zero_gravi
-- Instruction Issue (recoding of compressed instructions and 32-bit instruction word construction)
476
-- ****************************************************************************************************************************
477
 
478
 
479
  -- Issue Engine FSM Sync ------------------------------------------------------------------
480
  -- -------------------------------------------------------------------------------------------
481
  issue_engine_fsm_sync: process(rstn_i, clk_i)
482
  begin
483
    if (rstn_i = '0') then
484
      issue_engine.state <= ISSUE_ACTIVE;
485 40 zero_gravi
      issue_engine.align <= CPU_BOOT_ADDR(1); -- 32- or 16-bit boundary
486 31 zero_gravi
      issue_engine.buf   <= (others => '0');
487
    elsif rising_edge(clk_i) then
488
      if (ipb.clear = '1') then
489
        if (CPU_EXTENSION_RISCV_C = true) then
490
          if (execute_engine.pc(1) = '1') then -- branch to unaligned address?
491
            issue_engine.state <= ISSUE_REALIGN;
492
            issue_engine.align <= '1'; -- aligned on 16-bit boundary
493
          else
494
            issue_engine.state <= issue_engine.state_nxt;
495
            issue_engine.align <= '0'; -- aligned on 32-bit boundary
496
          end if;
497
        else
498
          issue_engine.state <= issue_engine.state_nxt;
499
          issue_engine.align <= '0'; -- always aligned on 32-bit boundaries
500
        end if;
501
      else
502
        issue_engine.state <= issue_engine.state_nxt;
503
        issue_engine.align <= issue_engine.align_nxt;
504
      end if;
505
      issue_engine.buf <= issue_engine.buf_nxt;
506
    end if;
507
  end process issue_engine_fsm_sync;
508
 
509
 
510
  -- Issue Engine FSM Comb ------------------------------------------------------------------
511
  -- -------------------------------------------------------------------------------------------
512 37 zero_gravi
  issue_engine_fsm_comb: process(issue_engine, ipb, execute_engine, ci_illegal, ci_instr32)
513 31 zero_gravi
  begin
514
    -- arbiter defaults --
515
    issue_engine.state_nxt <= issue_engine.state;
516
    issue_engine.align_nxt <= issue_engine.align;
517
    issue_engine.buf_nxt   <= issue_engine.buf;
518
 
519
    -- instruction prefetch buffer interface defaults --
520
    ipb.re <= '0';
521
 
522 37 zero_gravi
    -- instruction issue interface defaults --
523
    -- cmd_issue.data = <illegal_compressed_instruction> & <bus_error & alignment_error> & <is_compressed_instrucion> & <32-bit_instruction_word>
524
    cmd_issue.data  <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);
525
    cmd_issue.valid <= '0';
526 31 zero_gravi
 
527
    -- state machine --
528
    case issue_engine.state is
529
 
530
      when ISSUE_ACTIVE => -- issue instruction if available
531
      -- ------------------------------------------------------------
532
        if (ipb.avail = '1') then -- instructions available?
533
 
534
          if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word
535 41 zero_gravi
            if (execute_engine.state = DISPATCH) then -- ready to issue new command?
536 39 zero_gravi
              cmd_issue.valid      <= '1';
537 31 zero_gravi
              issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction
538
              if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed and "aligned"
539 37 zero_gravi
                ipb.re <= '1';
540
                cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);
541 31 zero_gravi
              else -- compressed
542 37 zero_gravi
                ipb.re <= '1';
543
                cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
544 31 zero_gravi
                issue_engine.align_nxt <= '1';
545
              end if;
546
            end if;
547
 
548
          else -- begin check in HIGH instruction half-word
549 41 zero_gravi
            if (execute_engine.state = DISPATCH) then -- ready to issue new command?
550 39 zero_gravi
              cmd_issue.valid      <= '1';
551 31 zero_gravi
              issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction
552
              if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and "unaligned"
553 37 zero_gravi
                ipb.re <= '1';
554
                cmd_issue.data <= '0' & issue_engine.buf(17 downto 16) & '0' & (ipb.rdata(15 downto 0) & issue_engine.buf(15 downto 0));
555 31 zero_gravi
              else -- compressed
556 36 zero_gravi
                -- do not read from ipb here!
557 37 zero_gravi
                cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
558 31 zero_gravi
                issue_engine.align_nxt <= '0';
559
              end if;
560
            end if;
561
          end if;
562
        end if;
563
 
564
      when ISSUE_REALIGN => -- re-align input fifos after a branch to an unaligned address
565
      -- ------------------------------------------------------------
566
        issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16);
567
        if (ipb.avail = '1') then -- instructions available?
568
          ipb.re <= '1';
569
          issue_engine.state_nxt <= ISSUE_ACTIVE;
570
        end if;
571
 
572
      when others => -- undefined
573
      -- ------------------------------------------------------------
574
        issue_engine.state_nxt <= ISSUE_ACTIVE;
575
 
576
    end case;
577
  end process issue_engine_fsm_comb;
578
 
579 41 zero_gravi
  -- 16-bit instructions: half-word select --
580 31 zero_gravi
  ci_instr16 <= ipb.rdata(15 downto 0) when (issue_engine.align = '0') else issue_engine.buf(15 downto 0);
581
 
582
 
583
  -- Compressed Instructions Recoding -------------------------------------------------------
584
  -- -------------------------------------------------------------------------------------------
585
  neorv32_cpu_decompressor_inst_true:
586
  if (CPU_EXTENSION_RISCV_C = true) generate
587
    neorv32_cpu_decompressor_inst: neorv32_cpu_decompressor
588
    port map (
589
      -- instruction input --
590
      ci_instr16_i => ci_instr16, -- compressed instruction input
591
      -- instruction output --
592
      ci_illegal_o => ci_illegal, -- is an illegal compressed instruction
593
      ci_instr32_o => ci_instr32  -- 32-bit decompressed instruction
594
    );
595
  end generate;
596
 
597
  neorv32_cpu_decompressor_inst_false:
598
  if (CPU_EXTENSION_RISCV_C = false) generate
599
    ci_instr32 <= (others => '0');
600
    ci_illegal <= '0';
601
  end generate;
602
 
603
 
604
-- ****************************************************************************************************************************
605 6 zero_gravi
-- Instruction Execution
606
-- ****************************************************************************************************************************
607
 
608
 
609 2 zero_gravi
  -- Immediate Generator --------------------------------------------------------------------
610
  -- -------------------------------------------------------------------------------------------
611 38 zero_gravi
  imm_gen: process(execute_engine.i_reg, clk_i)
612 37 zero_gravi
    variable opcode_v : std_ulogic_vector(6 downto 0);
613 2 zero_gravi
  begin
614 38 zero_gravi
    opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11";
615 2 zero_gravi
    if rising_edge(clk_i) then
616 49 zero_gravi
      if (execute_engine.state = BRANCH) then -- next_PC as immediate for jump-and-link operations (=return address) via ALU.MOV_B
617 39 zero_gravi
        imm_o <= execute_engine.next_pc;
618 49 zero_gravi
      else -- "normal" immediate from instruction word
619
        case opcode_v is -- save some bits here, the two LSBs are always "11" for rv32
620 52 zero_gravi
          when opcode_store_c | opcode_fsw_c => -- S-immediate
621 39 zero_gravi
            imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
622
            imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
623
            imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
624
            imm_o(00)           <= execute_engine.i_reg(07);
625
          when opcode_branch_c => -- B-immediate
626
            imm_o(31 downto 12) <= (others => execute_engine.i_reg(31)); -- sign extension
627
            imm_o(11)           <= execute_engine.i_reg(07);
628
            imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
629
            imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
630
            imm_o(00)           <= '0';
631
          when opcode_lui_c | opcode_auipc_c => -- U-immediate
632
            imm_o(31 downto 20) <= execute_engine.i_reg(31 downto 20);
633
            imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);
634
            imm_o(11 downto 00) <= (others => '0');
635
          when opcode_jal_c => -- J-immediate
636
            imm_o(31 downto 20) <= (others => execute_engine.i_reg(31)); -- sign extension
637
            imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);
638
            imm_o(11)           <= execute_engine.i_reg(20);
639
            imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
640
            imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
641
            imm_o(00)           <= '0';
642
          when opcode_atomic_c => -- atomic memory access
643 40 zero_gravi
            imm_o               <= (others => '0'); -- effective address is addr = reg + 0 = reg
644 39 zero_gravi
          when others => -- I-immediate
645
            imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
646
            imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
647
            imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
648
            imm_o(00)           <= execute_engine.i_reg(20);
649
        end case;
650
      end if;
651 2 zero_gravi
    end if;
652
  end process imm_gen;
653
 
654
 
655
  -- Branch Condition Check -----------------------------------------------------------------
656
  -- -------------------------------------------------------------------------------------------
657 6 zero_gravi
  branch_check: process(execute_engine.i_reg, cmp_i)
658 2 zero_gravi
  begin
659 6 zero_gravi
    case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
660 2 zero_gravi
      when funct3_beq_c => -- branch if equal
661 47 zero_gravi
        execute_engine.branch_taken <= cmp_i(cmp_equal_c);
662 2 zero_gravi
      when funct3_bne_c => -- branch if not equal
663 47 zero_gravi
        execute_engine.branch_taken <= not cmp_i(cmp_equal_c);
664 2 zero_gravi
      when funct3_blt_c | funct3_bltu_c => -- branch if less (signed/unsigned)
665 47 zero_gravi
        execute_engine.branch_taken <= cmp_i(cmp_less_c);
666 2 zero_gravi
      when funct3_bge_c | funct3_bgeu_c => -- branch if greater or equal (signed/unsigned)
667 47 zero_gravi
        execute_engine.branch_taken <= not cmp_i(cmp_less_c);
668 2 zero_gravi
      when others => -- undefined
669 6 zero_gravi
        execute_engine.branch_taken <= '0';
670 2 zero_gravi
    end case;
671
  end process branch_check;
672
 
673
 
674 6 zero_gravi
  -- Execute Engine FSM Sync ----------------------------------------------------------------
675 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
676 12 zero_gravi
  -- for registers that DO require a specific reset state --
677 6 zero_gravi
  execute_engine_fsm_sync_rst: process(rstn_i, clk_i)
678 2 zero_gravi
  begin
679
    if (rstn_i = '0') then
680 49 zero_gravi
      execute_engine.pc       <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
681
      execute_engine.state    <= SYS_WAIT;
682
      execute_engine.sleep    <= '0';
683
      execute_engine.branched <= '1'; -- reset is a branch from "somewhere"
684 2 zero_gravi
    elsif rising_edge(clk_i) then
685 39 zero_gravi
      -- PC update --
686
      if (execute_engine.pc_we = '1') then
687 49 zero_gravi
        if (execute_engine.pc_mux_sel = '0') then
688
          execute_engine.pc <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- normal (linear) increment
689
        else
690
          execute_engine.pc <= alu_add_i(data_width_c-1 downto 1) & '0'; -- jump/taken_branch
691
        end if;
692 39 zero_gravi
      end if;
693
      --
694 49 zero_gravi
      execute_engine.state    <= execute_engine.state_nxt;
695
      execute_engine.sleep    <= execute_engine.sleep_nxt;
696
      execute_engine.branched <= execute_engine.branched_nxt;
697 2 zero_gravi
    end if;
698 6 zero_gravi
  end process execute_engine_fsm_sync_rst;
699 2 zero_gravi
 
700 6 zero_gravi
 
701 12 zero_gravi
  -- for registers that do NOT require a specific reset state --
702 6 zero_gravi
  execute_engine_fsm_sync: process(clk_i)
703 2 zero_gravi
  begin
704
    if rising_edge(clk_i) then
705 42 zero_gravi
      execute_engine.state_prev <= execute_engine.state;
706
      execute_engine.i_reg      <= execute_engine.i_reg_nxt;
707
      execute_engine.is_ci      <= execute_engine.is_ci_nxt;
708
      execute_engine.is_cp_op   <= execute_engine.is_cp_op_nxt;
709 52 zero_gravi
      execute_engine.is_fp      <= execute_engine.is_fp_nxt;
710 49 zero_gravi
      -- PC & IR of "last executed" instruction --
711 40 zero_gravi
      if (execute_engine.state = EXECUTE) then
712
        execute_engine.last_pc    <= execute_engine.pc;
713 39 zero_gravi
        execute_engine.i_reg_last <= execute_engine.i_reg;
714
      end if;
715 49 zero_gravi
      -- next PC --
716
      case execute_engine.state is
717
        when TRAP_ENTER => execute_engine.next_pc <= csr.mtvec(data_width_c-1 downto 1) & '0'; -- trap enter
718
        when TRAP_EXIT  => execute_engine.next_pc <= csr.mepc(data_width_c-1 downto 1) & '0'; -- trap exit
719
        when EXECUTE    => execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc) + unsigned(execute_engine.next_pc_inc)); -- next linear PC
720
        when others     => NULL;
721
      end case;
722 39 zero_gravi
      -- main control bus --
723 6 zero_gravi
      ctrl <= ctrl_nxt;
724 2 zero_gravi
    end if;
725 6 zero_gravi
  end process execute_engine_fsm_sync;
726 2 zero_gravi
 
727 49 zero_gravi
  -- PC increment for next linear instruction (+2 for compressed instr., +4 otherwise) --
728
  execute_engine.next_pc_inc <= x"00000004" when ((execute_engine.is_ci = '0') or (CPU_EXTENSION_RISCV_C = false)) else x"00000002";
729 41 zero_gravi
 
730 20 zero_gravi
  -- PC output --
731 39 zero_gravi
  curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- PC for ALU ops
732 6 zero_gravi
 
733 49 zero_gravi
  -- CSR access address --
734
  csr.addr <= execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c);
735 20 zero_gravi
 
736 49 zero_gravi
 
737 6 zero_gravi
  -- CPU Control Bus Output -----------------------------------------------------------------
738
  -- -------------------------------------------------------------------------------------------
739 40 zero_gravi
  ctrl_output: process(ctrl, fetch_engine, trap_ctrl, atomic_ctrl, bus_fast_ir, execute_engine, csr)
740 2 zero_gravi
  begin
741 36 zero_gravi
    -- signals from execute engine --
742 2 zero_gravi
    ctrl_o <= ctrl;
743 36 zero_gravi
    -- current privilege level --
744
    ctrl_o(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) <= csr.privilege;
745
    -- register addresses --
746 40 zero_gravi
    ctrl_o(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c);
747
    ctrl_o(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c);
748
    ctrl_o(ctrl_rf_rd_adr4_c  downto ctrl_rf_rd_adr0_c)  <= execute_engine.i_reg(instr_rd_msb_c  downto instr_rd_lsb_c);
749 12 zero_gravi
    -- fast bus access requests --
750 36 zero_gravi
    ctrl_o(ctrl_bus_if_c) <= bus_fast_ir;
751 12 zero_gravi
    -- bus error control --
752 47 zero_gravi
    ctrl_o(ctrl_bus_ierr_ack_c) <= fetch_engine.bus_err_ack; -- instruction fetch bus access error ACK
753
    ctrl_o(ctrl_bus_derr_ack_c) <= trap_ctrl.env_start_ack; -- data access bus error access ACK
754
    -- memory access size / sign --
755
    ctrl_o(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU)
756
    ctrl_o(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c); -- mem transfer size
757
    -- alu.shifter --
758
    ctrl_o(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction (left/right)
759
    ctrl_o(ctrl_alu_shift_ar_c)  <= execute_engine.i_reg(30); -- is arithmetic shift
760 36 zero_gravi
    -- instruction's function blocks (for co-processors) --
761 44 zero_gravi
    ctrl_o(ctrl_ir_opcode7_6_c  downto ctrl_ir_opcode7_0_c) <= execute_engine.i_reg(instr_opcode_msb_c  downto instr_opcode_lsb_c);
762 36 zero_gravi
    ctrl_o(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_0_c) <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c);
763
    ctrl_o(ctrl_ir_funct3_2_c   downto ctrl_ir_funct3_0_c)  <= execute_engine.i_reg(instr_funct3_msb_c  downto instr_funct3_lsb_c);
764 47 zero_gravi
    -- locked bus operation (for atomic memory operations) --
765 39 zero_gravi
    ctrl_o(ctrl_bus_lock_c) <= atomic_ctrl.lock; -- (bus) lock status
766 47 zero_gravi
    -- cpu status --
767
    ctrl_o(ctrl_sleep_c) <= execute_engine.sleep; -- cpu is in sleep mode
768 6 zero_gravi
  end process ctrl_output;
769 2 zero_gravi
 
770
 
771 44 zero_gravi
  -- Decoding Helper Logic ------------------------------------------------------------------
772
  -- -------------------------------------------------------------------------------------------
773
  decode_helper: process(execute_engine)
774 49 zero_gravi
    variable sys_env_cmd_mask_v : std_ulogic_vector(11 downto 0);
775 44 zero_gravi
  begin
776
    -- defaults --
777
    decode_aux.alu_immediate   <= '0';
778
    decode_aux.rs1_is_r0       <= '0';
779
    decode_aux.is_atomic_lr    <= '0';
780
    decode_aux.is_atomic_sc    <= '0';
781
    decode_aux.is_bitmanip_imm <= '0';
782
    decode_aux.is_bitmanip_reg <= '0';
783 52 zero_gravi
    decode_aux.is_float_f_reg  <= '0';
784
    decode_aux.is_float_i_reg  <= '0';
785 44 zero_gravi
 
786
    -- is immediate ALU operation? --
787
    decode_aux.alu_immediate <= not execute_engine.i_reg(instr_opcode_msb_c-1);
788
 
789
    -- is rs1 == r0? --
790
    decode_aux.rs1_is_r0 <= not or_all_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c));
791
 
792
    -- is atomic load-reservate/store-conditional? --
793 52 zero_gravi
    if (CPU_EXTENSION_RISCV_A = true) and (execute_engine.i_reg(instr_opcode_lsb_c+3 downto instr_opcode_lsb_c+2) = "11") then -- valid atomic sub-opcode
794 44 zero_gravi
      decode_aux.is_atomic_lr <= not execute_engine.i_reg(instr_funct5_lsb_c);
795
      decode_aux.is_atomic_sc <=     execute_engine.i_reg(instr_funct5_lsb_c);
796
    end if;
797
 
798 51 zero_gravi
    -- is BITMANIP instruction? --
799 44 zero_gravi
    -- pretty complex as we have to extract this from the ALU/ALUI instruction space --
800
    -- immediate operation --
801
    if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001") and
802
         (
803
          (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00000") or -- CLZ
804
          (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00001") or -- CTZ
805
          (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00010") or -- PCNT
806
          (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00100") or -- SEXT.B
807
          (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00101")    -- SEXT.H
808
         )
809
       ) or
810 51 zero_gravi
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "01001") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- SBCLRI
811
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- SBSETI
812
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "01101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- SBINVI
813
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "01001") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- SBEXTI
814
       --
815 44 zero_gravi
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "01100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- RORI
816
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_imm12_lsb_c+6 downto instr_imm12_lsb_c) = "0000111")) or -- GORCI.b 7 (orc.b)
817
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "01101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_imm12_lsb_c+6 downto instr_imm12_lsb_c) = "0011000")) then -- GREVI.-8 (rev8)
818 51 zero_gravi
      decode_aux.is_bitmanip_imm <= '1';
819 44 zero_gravi
    end if;
820
    -- register operation --
821
    if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c-1 downto instr_funct3_lsb_c) = "01")) or -- ROR / ROL
822
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c) = '1')) or -- MIN[U] / MAX[U]
823
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100")) or -- PACK
824
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100000") and
825
        (
826
         (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "111") or -- ANDN
827
         (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "110") or -- ORN
828
         (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100")    -- XORN
829
         )
830 51 zero_gravi
        ) or
831
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- SBCLR
832
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- SBSET
833
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- SBINV
834
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) then -- SBSEXT
835
      decode_aux.is_bitmanip_reg <= '1';
836 44 zero_gravi
    end if;
837 52 zero_gravi
 
838
    -- floating-point FLOAT_register operations --
839
    if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11110")) or -- FMV.W.X
840
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00000")) or -- FADD.S
841
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00001")) or -- FSUB.S
842
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00010")) or -- FMUL.S
843
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00011")) or -- FDIV.S
844
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "01011") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00000")) or -- FSQRT.S
845
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00100") and (execute_engine.i_reg(instr_funct3_msb_c) = '0')) or -- FSGNJ[N/X].S
846
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_msb_c-1) = "00")) or -- FMIN.S / FMAX.S
847
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11010") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c+1) = "0000")) then -- FCVT.S.W*
848
      decode_aux.is_float_f_reg <= '1';
849
    end if;
850
    -- floating-point INTEGER_register operations --
851
    if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_msb_c-1) = "00")) or -- FMV.X.W / FCLASS.S
852
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "10100") and (execute_engine.i_reg(instr_funct3_msb_c) = '0')) or -- FEQ.S / FLT.S / FLE.S
853
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11000") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c+1) = "0000")) then -- FCVT.W*.S
854
      decode_aux.is_float_i_reg <= '1';
855
    end if;
856
 
857 49 zero_gravi
    -- system/environment instructions --
858
    sys_env_cmd_mask_v := funct12_ecall_c or funct12_ebreak_c or funct12_mret_c or funct12_wfi_c; -- sum-up set bits
859
    decode_aux.sys_env_cmd(11 downto 0) <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) and sys_env_cmd_mask_v; -- set unsued bits to always-zero
860 44 zero_gravi
  end process decode_helper;
861
 
862
 
863 6 zero_gravi
  -- Execute Engine FSM Comb ----------------------------------------------------------------
864
  -- -------------------------------------------------------------------------------------------
865 44 zero_gravi
  execute_engine_fsm_comb: process(execute_engine, decode_aux, fetch_engine, cmd_issue, trap_ctrl, csr, ctrl, csr_acc_valid,
866 39 zero_gravi
                                   alu_wait_i, bus_d_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i)
867 44 zero_gravi
    variable opcode_v : std_ulogic_vector(6 downto 0);
868 2 zero_gravi
  begin
869
    -- arbiter defaults --
870 29 zero_gravi
    execute_engine.state_nxt    <= execute_engine.state;
871
    execute_engine.i_reg_nxt    <= execute_engine.i_reg;
872
    execute_engine.is_cp_op_nxt <= execute_engine.is_cp_op;
873
    execute_engine.is_ci_nxt    <= execute_engine.is_ci;
874 52 zero_gravi
    execute_engine.is_fp_nxt    <= execute_engine.is_fp;
875 29 zero_gravi
    execute_engine.sleep_nxt    <= execute_engine.sleep;
876 49 zero_gravi
    execute_engine.branched_nxt <= execute_engine.branched;
877 39 zero_gravi
    --
878 49 zero_gravi
    execute_engine.pc_mux_sel   <= '0';
879 39 zero_gravi
    execute_engine.pc_we        <= '0';
880 2 zero_gravi
 
881 6 zero_gravi
    -- instruction dispatch --
882 37 zero_gravi
    fetch_engine.reset          <= '0';
883 2 zero_gravi
 
884 6 zero_gravi
    -- trap environment control --
885 37 zero_gravi
    trap_ctrl.env_start_ack     <= '0';
886
    trap_ctrl.env_end           <= '0';
887 6 zero_gravi
 
888 2 zero_gravi
    -- exception trigger --
889 37 zero_gravi
    trap_ctrl.instr_be          <= '0';
890
    trap_ctrl.instr_ma          <= '0';
891
    trap_ctrl.env_call          <= '0';
892
    trap_ctrl.break_point       <= '0';
893
    illegal_compressed          <= '0';
894 2 zero_gravi
 
895 6 zero_gravi
    -- CSR access --
896 37 zero_gravi
    csr.we_nxt                  <= '0';
897
    csr.re_nxt                  <= '0';
898 6 zero_gravi
 
899 39 zero_gravi
    -- atomic operations control --
900
    atomic_ctrl.env_start       <= '0';
901
    atomic_ctrl.env_end         <= '0';
902
    atomic_ctrl.env_abort       <= '0';
903
 
904
    -- CONTROL DEFAULTS --
905 36 zero_gravi
    ctrl_nxt <= (others => '0'); -- default: all off
906 47 zero_gravi
    -- ALU main control --
907
    ctrl_nxt(ctrl_alu_addsub_c) <= '0'; -- ADD(I)
908
    ctrl_nxt(ctrl_alu_func1_c  downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c; -- default ALU function select: arithmetic
909
    ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c; -- default ALU arithmetic operation: ADDSUB
910
    -- ALU sign control --
911 6 zero_gravi
    if (execute_engine.i_reg(instr_opcode_lsb_c+4) = '1') then -- ALU ops
912 36 zero_gravi
      ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation? (SLTIU, SLTU)
913 2 zero_gravi
    else -- branches
914 36 zero_gravi
      ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches? (BLTU, BGEU)
915 2 zero_gravi
    end if;
916
 
917
 
918 6 zero_gravi
    -- state machine --
919
    case execute_engine.state is
920 2 zero_gravi
 
921 44 zero_gravi
      when SYS_WAIT => -- System delay cycle (used to wait for side effects to kick in) [and to init r0 with zero if it is a physical register]
922 2 zero_gravi
      -- ------------------------------------------------------------
923 26 zero_gravi
        -- set reg_file's r0 to zero --
924 25 zero_gravi
        if (rf_r0_is_reg_c = true) then -- is r0 implemented as physical register, which has to be set to zero?
925 49 zero_gravi
          ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c; -- hacky! CSR read-access CP selected without a valid CSR-read -> results zero
926
          ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_csr_rd_c; -- use CSR-READ CP
927
          ctrl_nxt(ctrl_rf_r0_we_c)                          <= '1'; -- force RF write access and force rd=r0
928 25 zero_gravi
        end if;
929
        --
930 6 zero_gravi
        execute_engine.state_nxt <= DISPATCH;
931 2 zero_gravi
 
932 39 zero_gravi
 
933 37 zero_gravi
      when DISPATCH => -- Get new command from instruction issue engine
934 25 zero_gravi
      -- ------------------------------------------------------------
935 52 zero_gravi
        -- housekeeping --
936
        execute_engine.is_cp_op_nxt <= '0'; -- init
937
        execute_engine.is_fp_nxt    <= '0'; -- init
938 49 zero_gravi
        -- PC update --
939
        execute_engine.pc_mux_sel <= '0'; -- linear next PC
940 40 zero_gravi
        -- IR update --
941 49 zero_gravi
        execute_engine.is_ci_nxt <= cmd_issue.data(32); -- flag to indicate a de-compressed instruction
942
        execute_engine.i_reg_nxt <= cmd_issue.data(31 downto 0);
943 40 zero_gravi
        --
944 37 zero_gravi
        if (cmd_issue.valid = '1') then -- instruction available?
945 49 zero_gravi
          -- PC update --
946
          execute_engine.branched_nxt <= '0';
947
          execute_engine.pc_we        <= not execute_engine.branched; -- update PC with linear next_pc if there was no actual branch
948 40 zero_gravi
          -- IR update - exceptions --
949
          trap_ctrl.instr_ma <= cmd_issue.data(33); -- misaligned instruction fetch address
950
          trap_ctrl.instr_be <= cmd_issue.data(34); -- bus access fault during instruction fetch
951
          illegal_compressed <= cmd_issue.data(35); -- invalid decompressed instruction
952
          -- any reason to go to trap state? --
953 37 zero_gravi
          if (execute_engine.sleep = '1') or (trap_ctrl.env_start = '1') or (trap_ctrl.exc_fire = '1') or ((cmd_issue.data(33) or cmd_issue.data(34)) = '1') then
954 49 zero_gravi
            execute_engine.state_nxt <= TRAP_ENTER;
955 13 zero_gravi
          else
956 14 zero_gravi
            execute_engine.state_nxt <= EXECUTE;
957 13 zero_gravi
          end if;
958
        end if;
959 2 zero_gravi
 
960 39 zero_gravi
 
961 49 zero_gravi
      when TRAP_ENTER => -- Start trap environment - get MTVEC, stay here for sleep mode
962 2 zero_gravi
      -- ------------------------------------------------------------
963 34 zero_gravi
        if (trap_ctrl.env_start = '1') then -- trap triggered?
964
          trap_ctrl.env_start_ack   <= '1';
965 49 zero_gravi
          execute_engine.state_nxt  <= TRAP_EXECUTE;
966 2 zero_gravi
        end if;
967
 
968 49 zero_gravi
      when TRAP_EXIT => -- Return from trap environment - get MEPC
969
      -- ------------------------------------------------------------
970
        trap_ctrl.env_end        <= '1';
971
        execute_engine.state_nxt <= TRAP_EXECUTE;
972 39 zero_gravi
 
973 49 zero_gravi
      when TRAP_EXECUTE => -- Start trap environment - jump to MTVEC / return from trap environment - jump to MEPC
974
      -- ------------------------------------------------------------
975
        execute_engine.pc_mux_sel <= '0'; -- next PC (csr.mtvec)
976
        fetch_engine.reset        <= '1';
977
        execute_engine.pc_we      <= '1';
978
        execute_engine.sleep_nxt  <= '0'; -- disable sleep mode
979
        execute_engine.state_nxt  <= SYS_WAIT;
980
 
981
 
982 40 zero_gravi
      when EXECUTE => -- Decode and execute instruction (control has to be here for excatly 1 cyle in any case!)
983 2 zero_gravi
      -- ------------------------------------------------------------
984 36 zero_gravi
        opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; -- save some bits here, LSBs are always 11 for rv32
985
        case opcode_v is
986 2 zero_gravi
 
987 25 zero_gravi
          when opcode_alu_c | opcode_alui_c => -- (immediate) ALU operation
988 2 zero_gravi
          -- ------------------------------------------------------------
989 49 zero_gravi
            ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA
990
            ctrl_nxt(ctrl_alu_opb_mux_c) <= decode_aux.alu_immediate; -- use IMM as ALU.OPB for immediate operations
991
            ctrl_nxt(ctrl_rf_in_mux_c)   <= '0'; -- RF input = ALU result
992 25 zero_gravi
 
993 39 zero_gravi
            -- ALU arithmetic operation type and ADD/SUB --
994
            if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or
995
               (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) then
996
              ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_slt_c;
997 29 zero_gravi
            else
998 39 zero_gravi
              ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c;
999 25 zero_gravi
            end if;
1000
 
1001 29 zero_gravi
            -- ADD/SUB --
1002 44 zero_gravi
            if ((decode_aux.alu_immediate = '0') and (execute_engine.i_reg(instr_funct7_msb_c-1) = '1')) or -- not an immediate op and funct7.6 set => SUB
1003 29 zero_gravi
               (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or -- SLT operation
1004
               (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) then -- SLTU operation
1005
              ctrl_nxt(ctrl_alu_addsub_c) <= '1'; -- SUB/SLT
1006
            else
1007
              ctrl_nxt(ctrl_alu_addsub_c) <= '0'; -- ADD(I)
1008
            end if;
1009
 
1010 39 zero_gravi
            -- ALU logic operation --
1011
            case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is -- actual ALU.logic operation (re-coding)
1012
              when funct3_xor_c => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_xor_c; -- XOR(I)
1013
              when funct3_or_c  => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_or_c;  -- OR(I)
1014 40 zero_gravi
              when others       => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_and_c; -- AND(I)
1015 39 zero_gravi
            end case;
1016
 
1017 44 zero_gravi
            -- co-processor MULDIV operation? --
1018
            if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV CP op?
1019
              ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- use MULDIV CP
1020 39 zero_gravi
              execute_engine.is_cp_op_nxt                        <= '1'; -- this is a CP operation
1021
              ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
1022 44 zero_gravi
            -- co-processor bit manipulation operation? --
1023
            elsif (CPU_EXTENSION_RISCV_B = true) and
1024
              (((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5))  and (decode_aux.is_bitmanip_reg = '1')) or -- register operation
1025
               ((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_bitmanip_imm = '1'))) then -- immediate operation
1026
              ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_bitmanip_c; -- use BITMANIP CP
1027
              execute_engine.is_cp_op_nxt                        <= '1'; -- this is a CP operation
1028
              ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
1029
            -- ALU operation, function select --
1030 39 zero_gravi
            else
1031
              execute_engine.is_cp_op_nxt <= '0'; -- no CP operation
1032
              case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is -- actual ALU.func operation (re-coding)
1033
                when funct3_xor_c | funct3_or_c | funct3_and_c => ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_logic_c;
1034
                when funct3_sll_c | funct3_sr_c                => ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_shift_c;
1035
                when others                                    => ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c;
1036
              end case;
1037
            end if;
1038
 
1039 11 zero_gravi
            -- multi cycle alu operation? --
1040 25 zero_gravi
            if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or -- SLL shift operation?
1041
               (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) or -- SR shift operation?
1042 44 zero_gravi
               ((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1')) or -- MULDIV CP op?
1043
               ((CPU_EXTENSION_RISCV_B = true) and (
1044
                 ((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5))  and (decode_aux.is_bitmanip_reg = '1')) or -- BITMANIP CP register operation?
1045
                 ((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_bitmanip_imm = '1'))) ) then -- BITMANIP CP immediate operation?
1046 6 zero_gravi
              execute_engine.state_nxt <= ALU_WAIT;
1047 26 zero_gravi
            else -- single cycle ALU operation
1048 2 zero_gravi
              ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
1049 6 zero_gravi
              execute_engine.state_nxt <= DISPATCH;
1050 2 zero_gravi
            end if;
1051
 
1052 25 zero_gravi
          when opcode_lui_c | opcode_auipc_c => -- load upper immediate / add upper immediate to PC
1053 2 zero_gravi
          -- ------------------------------------------------------------
1054 27 zero_gravi
            ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- ALU.OPA = PC (for AUIPC only)
1055
            ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB
1056 39 zero_gravi
            ctrl_nxt(ctrl_alu_arith_c)   <= alu_arith_cmd_addsub_c; -- actual ALU operation = ADD
1057
            ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_movb_c; -- MOVB
1058 25 zero_gravi
            if (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_lui_c(5)) then -- LUI
1059 39 zero_gravi
              ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_logic_c; -- actual ALU operation = MOVB
1060 27 zero_gravi
            else -- AUIPC
1061 39 zero_gravi
              ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c; -- actual ALU operation = ADD
1062 2 zero_gravi
            end if;
1063 49 zero_gravi
            ctrl_nxt(ctrl_rf_in_mux_c) <= '0'; -- RF input = ALU result
1064
            ctrl_nxt(ctrl_rf_wb_en_c)  <= '1'; -- valid RF write-back
1065
            execute_engine.state_nxt   <= DISPATCH;
1066 2 zero_gravi
 
1067 52 zero_gravi
          when opcode_load_c | opcode_store_c | opcode_atomic_c | opcode_flw_c | opcode_fsw_c => -- load/store / atomic memory access / floating-point load/store 
1068 2 zero_gravi
          -- ------------------------------------------------------------
1069 27 zero_gravi
            ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA
1070
            ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB
1071 39 zero_gravi
            ctrl_nxt(ctrl_bus_mo_we_c)   <= '1'; -- write to MAR and MDO (MDO only relevant for store)
1072 52 zero_gravi
            if (CPU_EXTENSION_RISCV_F = true) and (execute_engine.i_reg(instr_opcode_lsb_c+3 downto instr_opcode_lsb_c+2) = "01") then -- floating-point load/store
1073
              execute_engine.is_fp_nxt    <= decode_aux.is_float_f_reg; -- no integer register file write back for FPU internal operations
1074
              ctrl_nxt(ctrl_bus_wd_sel_c) <= '1'; -- use memory-write-data from FPU co-processor (only relevant for float STORE)
1075
            end if;
1076 39 zero_gravi
            --
1077 52 zero_gravi
            if (CPU_EXTENSION_RISCV_A = false) or -- atomic extension disabled
1078
               (execute_engine.i_reg(instr_opcode_lsb_c+3 downto instr_opcode_lsb_c+2) = "00") or  -- normal integerload/store
1079
               ((CPU_EXTENSION_RISCV_F = true) and (execute_engine.i_reg(instr_opcode_lsb_c+3 downto instr_opcode_lsb_c+2) = "01")) then -- floating-point load/store
1080 39 zero_gravi
              execute_engine.state_nxt <= LOADSTORE_0;
1081
            else -- atomic operation
1082
              atomic_ctrl.env_start <= not execute_engine.i_reg(instr_funct5_lsb_c); -- LR: start LOCKED memory access environment
1083
              if (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = funct5_a_sc_c) or -- store-conditional
1084
                 (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = funct5_a_lr_c) then -- load-reservate
1085
                execute_engine.state_nxt <= LOADSTORE_0;
1086
              else -- unimplemented (atomic) instruction
1087
                execute_engine.state_nxt <= SYS_WAIT;
1088
              end if;
1089
            end if;
1090 2 zero_gravi
 
1091 29 zero_gravi
          when opcode_branch_c | opcode_jal_c | opcode_jalr_c => -- branch / jump and link (with register)
1092 2 zero_gravi
          -- ------------------------------------------------------------
1093 49 zero_gravi
            -- target address (ALU.ADD) operands --
1094 29 zero_gravi
            if (execute_engine.i_reg(instr_opcode_lsb_c+3 downto instr_opcode_lsb_c+2) = opcode_jalr_c(3 downto 2)) then -- JALR
1095
              ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA (branch target address base)
1096 49 zero_gravi
            else -- JAL
1097 29 zero_gravi
              ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- use PC as ALU.OPA (branch target address base)
1098 2 zero_gravi
            end if;
1099 29 zero_gravi
            ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB (branch target address offset)
1100 49 zero_gravi
            execute_engine.state_nxt     <= BRANCH;
1101 2 zero_gravi
 
1102 8 zero_gravi
          when opcode_fence_c => -- fence operations
1103
          -- ------------------------------------------------------------
1104 39 zero_gravi
            execute_engine.state_nxt <= FENCE_OP;
1105 8 zero_gravi
 
1106 2 zero_gravi
          when opcode_syscsr_c => -- system/csr access
1107
          -- ------------------------------------------------------------
1108 45 zero_gravi
            if (CPU_EXTENSION_RISCV_Zicsr = true) then
1109
              csr.re_nxt <= csr_acc_valid; -- always read CSR if valid access, only relevant for CSR-instructions
1110 49 zero_gravi
              ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c; -- only relevant for CSR-instructions
1111
              ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_csr_rd_c; -- use CSR-READ CP, only relevant for CSR-instructions
1112 45 zero_gravi
              if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system/environment
1113
                execute_engine.state_nxt <= SYS_ENV;
1114
              else -- CSR access
1115
                execute_engine.state_nxt <= CSR_ACCESS;
1116
              end if;
1117
            else
1118
              execute_engine.state_nxt <= SYS_WAIT;
1119 2 zero_gravi
            end if;
1120
 
1121 52 zero_gravi
          when opcode_fop_c => -- floating-point operations (1 or 2 operands)
1122
          -- ------------------------------------------------------------
1123
            execute_engine.state_nxt <= SYS_WAIT;
1124
            if (CPU_EXTENSION_RISCV_F = true) then
1125
              execute_engine.is_fp_nxt                           <= decode_aux.is_float_f_reg; -- no integer register file write back for FPU internal operations
1126
              ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_fpu_c; -- use FPU CP
1127
              execute_engine.is_cp_op_nxt                        <= '1'; -- this is a CP operation
1128
              ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
1129
              execute_engine.state_nxt                           <= ALU_WAIT;
1130
            end if;
1131
 
1132 2 zero_gravi
          when others => -- undefined
1133
          -- ------------------------------------------------------------
1134 39 zero_gravi
            execute_engine.state_nxt <= SYS_WAIT;
1135 2 zero_gravi
 
1136
        end case;
1137
 
1138 39 zero_gravi
 
1139
      when SYS_ENV => -- system environment operation - execution
1140 2 zero_gravi
      -- ------------------------------------------------------------
1141 49 zero_gravi
        execute_engine.state_nxt <= SYS_WAIT;
1142
        case decode_aux.sys_env_cmd is -- use a simplified input here (with permanent zeros)
1143
          when funct12_ecall_c  => trap_ctrl.env_call       <= '1'; -- ECALL
1144
          when funct12_ebreak_c => trap_ctrl.break_point    <= '1'; -- EBREAK
1145
          when funct12_mret_c   => execute_engine.state_nxt <= TRAP_EXIT; -- MRET
1146
          when funct12_wfi_c    => execute_engine.sleep_nxt <= '1'; -- WFI
1147
          when others           => NULL;-- undefined
1148 39 zero_gravi
        end case;
1149
 
1150
 
1151
      when CSR_ACCESS => -- read & write status and control register (CSR)
1152
      -- ------------------------------------------------------------
1153 27 zero_gravi
        -- CSR write access --
1154 6 zero_gravi
        case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
1155 25 zero_gravi
          when funct3_csrrw_c | funct3_csrrwi_c => -- CSRRW(I)
1156 15 zero_gravi
            csr.we_nxt <= csr_acc_valid; -- always write CSR if valid access
1157 27 zero_gravi
          when funct3_csrrs_c | funct3_csrrsi_c | funct3_csrrc_c | funct3_csrrci_c => -- CSRRS(I) / CSRRC(I)
1158 44 zero_gravi
            csr.we_nxt <= (not decode_aux.rs1_is_r0) and csr_acc_valid; -- write CSR if rs1/imm is not zero and if valid access
1159 29 zero_gravi
          when others => -- invalid
1160 27 zero_gravi
            csr.we_nxt <= '0';
1161 2 zero_gravi
        end case;
1162 27 zero_gravi
        -- register file write back --
1163 49 zero_gravi
        ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
1164
        ctrl_nxt(ctrl_rf_in_mux_c)                         <= '0'; -- RF input = ALU result
1165
        ctrl_nxt(ctrl_rf_wb_en_c)                          <= '1'; -- valid RF write-back
1166
        execute_engine.state_nxt                           <= DISPATCH;
1167 2 zero_gravi
 
1168 39 zero_gravi
 
1169 19 zero_gravi
      when ALU_WAIT => -- wait for multi-cycle ALU operation (shifter or CP) to finish
1170 2 zero_gravi
      -- ------------------------------------------------------------
1171 49 zero_gravi
        ctrl_nxt(ctrl_rf_in_mux_c) <= '0'; -- RF input = ALU result
1172 52 zero_gravi
        if (CPU_EXTENSION_RISCV_F = false) then
1173
          ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (permanent write-back)
1174
        else
1175
          ctrl_nxt(ctrl_rf_wb_en_c) <= not execute_engine.is_fp; -- allow write back if NOT <FPU-internal operation>
1176
        end if;
1177 44 zero_gravi
        -- cp access or alu.shift? --
1178 29 zero_gravi
        if (execute_engine.is_cp_op = '1') then
1179 39 zero_gravi
          ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
1180 29 zero_gravi
        else
1181 39 zero_gravi
          ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_shift_c;
1182 19 zero_gravi
        end if;
1183
        -- wait for result --
1184 6 zero_gravi
        if (alu_wait_i = '0') then
1185 29 zero_gravi
          execute_engine.state_nxt <= DISPATCH;
1186 2 zero_gravi
        end if;
1187
 
1188 39 zero_gravi
 
1189 6 zero_gravi
      when BRANCH => -- update PC for taken branches and jumps
1190
      -- ------------------------------------------------------------
1191 39 zero_gravi
        -- get and store return address (only relevant for jump-and-link operations) --
1192
        ctrl_nxt(ctrl_alu_opb_mux_c)                         <= '1'; -- use IMM as ALU.OPB (next_pc from immediate generator = return address)
1193
        ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_movb_c; -- MOVB
1194
        ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c)   <= alu_func_cmd_logic_c; -- actual ALU operation = MOVB
1195 49 zero_gravi
        ctrl_nxt(ctrl_rf_in_mux_c)                           <= '0'; -- RF input = ALU result
1196 40 zero_gravi
        ctrl_nxt(ctrl_rf_wb_en_c)                            <= execute_engine.i_reg(instr_opcode_lsb_c+2); -- valid RF write-back? (is jump-and-link?)
1197 39 zero_gravi
        -- destination address --
1198 49 zero_gravi
        execute_engine.pc_mux_sel <= '1'; -- alu.add = branch/jump destination
1199 40 zero_gravi
        if (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') or (execute_engine.branch_taken = '1') then -- JAL/JALR or taken branch
1200 49 zero_gravi
          execute_engine.pc_we        <= '1'; -- update PC
1201
          execute_engine.branched_nxt <= '1'; -- this is an actual branch
1202
          fetch_engine.reset          <= '1'; -- trigger new instruction fetch from modified PC
1203
          execute_engine.state_nxt    <= SYS_WAIT;
1204 11 zero_gravi
        else
1205
          execute_engine.state_nxt <= DISPATCH;
1206 6 zero_gravi
        end if;
1207
 
1208 39 zero_gravi
 
1209
      when FENCE_OP => -- fence operations - execution
1210
      -- ------------------------------------------------------------
1211 47 zero_gravi
        execute_engine.state_nxt <= SYS_WAIT;
1212 39 zero_gravi
        -- FENCE.I --
1213 47 zero_gravi
        if (CPU_EXTENSION_RISCV_Zifencei = true) then
1214 49 zero_gravi
          execute_engine.pc_mux_sel <= '0'; -- linear next PC = start *new* instruction fetch with next instruction (only relevant for fence.i)
1215 47 zero_gravi
          if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fencei_c(0)) then
1216 49 zero_gravi
            execute_engine.pc_we        <= '1'; -- update PC
1217
            execute_engine.branched_nxt <= '1'; -- this is an actual branch
1218
            fetch_engine.reset          <= '1'; -- trigger new instruction fetch from modified PC
1219 47 zero_gravi
            ctrl_nxt(ctrl_bus_fencei_c) <= '1';
1220
          end if;
1221 39 zero_gravi
        end if;
1222
        -- FENCE --
1223
        if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fence_c(0)) then
1224
          ctrl_nxt(ctrl_bus_fence_c) <= '1';
1225
        end if;
1226
 
1227
 
1228 12 zero_gravi
      when LOADSTORE_0 => -- trigger memory request
1229 6 zero_gravi
      -- ------------------------------------------------------------
1230 44 zero_gravi
        if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (decode_aux.is_atomic_lr = '1') then -- normal load or atomic load-reservate
1231 12 zero_gravi
          ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- read request
1232 39 zero_gravi
        else -- store
1233 12 zero_gravi
          ctrl_nxt(ctrl_bus_wr_c) <= '1'; -- write request
1234
        end if;
1235
        execute_engine.state_nxt <= LOADSTORE_1;
1236 6 zero_gravi
 
1237 39 zero_gravi
 
1238 12 zero_gravi
      when LOADSTORE_1 => -- memory latency
1239 6 zero_gravi
      -- ------------------------------------------------------------
1240 39 zero_gravi
        ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- write input data to MDI (only relevant for LOAD)
1241
        execute_engine.state_nxt   <= LOADSTORE_2;
1242 6 zero_gravi
 
1243 39 zero_gravi
 
1244 12 zero_gravi
      when LOADSTORE_2 => -- wait for bus transaction to finish
1245 6 zero_gravi
      -- ------------------------------------------------------------
1246 40 zero_gravi
        -- ALU control (only relevant for atomic memory operations) --
1247
        if (CPU_EXTENSION_RISCV_A = true) then
1248
          ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_atomic_c; -- atomic.SC: result comes from "atomic co-processor"
1249 39 zero_gravi
          ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
1250
        end if;
1251 40 zero_gravi
        -- register file write-back --
1252 44 zero_gravi
        if (decode_aux.is_atomic_sc = '1') then
1253 49 zero_gravi
          ctrl_nxt(ctrl_rf_in_mux_c) <= '0'; -- RF input = ALU.res (only relevant for atomic.SC)
1254 39 zero_gravi
        else
1255 49 zero_gravi
          ctrl_nxt(ctrl_rf_in_mux_c) <= '1'; -- RF input = memory input (only relevant for LOADs)
1256 39 zero_gravi
        end if;
1257
        --
1258
        ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for load operations)
1259
        -- wait for memory response --
1260 37 zero_gravi
        if ((ma_load_i or be_load_i or ma_store_i or be_store_i) = '1') then -- abort if exception
1261 39 zero_gravi
          atomic_ctrl.env_abort     <= '1'; -- LOCKED (atomic) memory access environment failed (forces SC result to be non-zero => failure)
1262 44 zero_gravi
          ctrl_nxt(ctrl_rf_wb_en_c) <= decode_aux.is_atomic_sc; -- SC failes: allow write back of non-zero result
1263 39 zero_gravi
          execute_engine.state_nxt  <= DISPATCH;
1264 26 zero_gravi
        elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction
1265 44 zero_gravi
          if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (decode_aux.is_atomic_lr = '1') or (decode_aux.is_atomic_sc = '1') then -- load / load-reservate / store conditional
1266 52 zero_gravi
            ctrl_nxt(ctrl_rf_wb_en_c) <= not execute_engine.is_fp; -- allow write back if NOT <FPU-internal operation>
1267 6 zero_gravi
          end if;
1268 52 zero_gravi
          if (CPU_EXTENSION_RISCV_F = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) = opcode_flw_c(6 downto 2)) then -- floating-point LOAD.word
1269
            ctrl_nxt(ctrl_cp_fpu_mem_we_c) <= '1'; -- co-processor register file write-back
1270
          end if;
1271 48 zero_gravi
          atomic_ctrl.env_end      <= not decode_aux.is_atomic_lr; -- normal end of LOCKED (atomic) memory access environment - if we are not starting it via LR instruction
1272 6 zero_gravi
          execute_engine.state_nxt <= DISPATCH;
1273
        end if;
1274
 
1275 39 zero_gravi
 
1276 2 zero_gravi
      when others => -- undefined
1277
      -- ------------------------------------------------------------
1278 7 zero_gravi
        execute_engine.state_nxt <= SYS_WAIT;
1279 2 zero_gravi
 
1280
    end case;
1281 6 zero_gravi
  end process execute_engine_fsm_comb;
1282 2 zero_gravi
 
1283
 
1284 15 zero_gravi
-- ****************************************************************************************************************************
1285
-- Invalid Instruction / CSR access check
1286
-- ****************************************************************************************************************************
1287
 
1288
 
1289 49 zero_gravi
  -- CSR Access Check -----------------------------------------------------------------------
1290 15 zero_gravi
  -- -------------------------------------------------------------------------------------------
1291 49 zero_gravi
  csr_access_check: process(execute_engine.i_reg, csr)
1292 42 zero_gravi
    variable csr_wacc_v           : std_ulogic; -- to check access to read-only CSRs
1293 44 zero_gravi
--  variable csr_racc_v           : std_ulogic; -- to check access to write-only CSRs
1294 42 zero_gravi
    variable csr_mcounteren_hpm_v : std_ulogic_vector(28 downto 0); -- max 29 HPM counters
1295 15 zero_gravi
  begin
1296 30 zero_gravi
    -- is this CSR instruction really going to write/read to/from a CSR? --
1297
    if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
1298
       (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then
1299
      csr_wacc_v := '1'; -- always write CSR
1300
--    csr_racc_v := or_all_f(execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c)); -- read allowed if rd != 0
1301
    else
1302
      csr_wacc_v := or_all_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c)); -- write allowed if rs1/uimm5 != 0
1303
--    csr_racc_v := '1'; -- always read CSR
1304
    end if;
1305
 
1306 42 zero_gravi
    -- low privilege level access to hpm counters? --
1307
    csr_mcounteren_hpm_v := (others => '0');
1308 52 zero_gravi
    if (CPU_EXTENSION_RISCV_U = true) then
1309 51 zero_gravi
      csr_mcounteren_hpm_v(HPM_NUM_CNTS-1 downto 0) := csr.mcounteren_hpm(HPM_NUM_CNTS-1 downto 0);
1310 52 zero_gravi
    else -- 'mcounteren' CSR is hardwired to zero if user mode is not implemented
1311
      csr_mcounteren_hpm_v := (others => '0');
1312 51 zero_gravi
    end if;
1313 42 zero_gravi
 
1314 15 zero_gravi
    -- check CSR access --
1315 41 zero_gravi
    case csr.addr is
1316
      -- standard read/write CSRs --
1317 52 zero_gravi
      when csr_fflags_c | csr_frm_c | csr_fcsr_c => csr_acc_valid <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_F); -- full access for everyone if F extension is enabled
1318
      --
1319 42 zero_gravi
      when csr_mstatus_c       => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1320
      when csr_mstatush_c      => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1321
      when csr_misa_c          => csr_acc_valid <= csr.priv_m_mode;-- and (not csr_wacc_v); -- M-mode only, MISA is read-only in the NEORV32 but we do not cause an exception here for compatibility
1322
      when csr_mie_c           => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1323
      when csr_mtvec_c         => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1324
      when csr_mscratch_c      => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1325
      when csr_mepc_c          => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1326
      when csr_mcause_c        => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1327
      when csr_mcounteren_c    => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1328
      when csr_mtval_c         => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1329
      when csr_mip_c           => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1330 15 zero_gravi
      --
1331 42 zero_gravi
      when csr_pmpcfg0_c | csr_pmpcfg1_c | csr_pmpcfg2_c  | csr_pmpcfg3_c  | csr_pmpcfg4_c  | csr_pmpcfg5_c  | csr_pmpcfg6_c  | csr_pmpcfg7_c |
1332
           csr_pmpcfg8_c | csr_pmpcfg9_c | csr_pmpcfg10_c | csr_pmpcfg11_c | csr_pmpcfg12_c | csr_pmpcfg13_c | csr_pmpcfg14_c | csr_pmpcfg15_c =>
1333
        csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1334 15 zero_gravi
      --
1335 42 zero_gravi
      when csr_pmpaddr0_c  | csr_pmpaddr1_c  | csr_pmpaddr2_c  | csr_pmpaddr3_c  | csr_pmpaddr4_c  | csr_pmpaddr5_c  | csr_pmpaddr6_c  | csr_pmpaddr7_c  |
1336
           csr_pmpaddr8_c  | csr_pmpaddr9_c  | csr_pmpaddr10_c | csr_pmpaddr11_c | csr_pmpaddr12_c | csr_pmpaddr13_c | csr_pmpaddr14_c | csr_pmpaddr15_c |
1337
           csr_pmpaddr16_c | csr_pmpaddr17_c | csr_pmpaddr18_c | csr_pmpaddr19_c | csr_pmpaddr20_c | csr_pmpaddr21_c | csr_pmpaddr22_c | csr_pmpaddr23_c |
1338
           csr_pmpaddr24_c | csr_pmpaddr25_c | csr_pmpaddr26_c | csr_pmpaddr27_c | csr_pmpaddr28_c | csr_pmpaddr29_c | csr_pmpaddr30_c | csr_pmpaddr31_c |
1339
           csr_pmpaddr32_c | csr_pmpaddr33_c | csr_pmpaddr34_c | csr_pmpaddr35_c | csr_pmpaddr36_c | csr_pmpaddr37_c | csr_pmpaddr38_c | csr_pmpaddr39_c |
1340
           csr_pmpaddr40_c | csr_pmpaddr41_c | csr_pmpaddr42_c | csr_pmpaddr43_c | csr_pmpaddr44_c | csr_pmpaddr45_c | csr_pmpaddr46_c | csr_pmpaddr47_c |
1341
           csr_pmpaddr48_c | csr_pmpaddr49_c | csr_pmpaddr50_c | csr_pmpaddr51_c | csr_pmpaddr52_c | csr_pmpaddr53_c | csr_pmpaddr54_c | csr_pmpaddr55_c |
1342
           csr_pmpaddr56_c | csr_pmpaddr57_c | csr_pmpaddr58_c | csr_pmpaddr59_c | csr_pmpaddr60_c | csr_pmpaddr61_c | csr_pmpaddr62_c | csr_pmpaddr63_c =>
1343
        csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1344 15 zero_gravi
      --
1345 41 zero_gravi
      when csr_mcountinhibit_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1346 15 zero_gravi
      --
1347 42 zero_gravi
      when csr_mhpmevent3_c  | csr_mhpmevent4_c  | csr_mhpmevent5_c  | csr_mhpmevent6_c  | csr_mhpmevent7_c  | csr_mhpmevent8_c  |
1348
           csr_mhpmevent9_c  | csr_mhpmevent10_c | csr_mhpmevent11_c | csr_mhpmevent12_c | csr_mhpmevent13_c | csr_mhpmevent14_c |
1349
           csr_mhpmevent15_c | csr_mhpmevent16_c | csr_mhpmevent17_c | csr_mhpmevent18_c | csr_mhpmevent19_c | csr_mhpmevent20_c |
1350
           csr_mhpmevent21_c | csr_mhpmevent22_c | csr_mhpmevent23_c | csr_mhpmevent24_c | csr_mhpmevent25_c | csr_mhpmevent26_c |
1351
           csr_mhpmevent27_c | csr_mhpmevent28_c | csr_mhpmevent29_c | csr_mhpmevent30_c | csr_mhpmevent31_c =>
1352
        csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1353 15 zero_gravi
      --
1354 42 zero_gravi
      when csr_mcycle_c        => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1355
      when csr_minstret_c      => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1356
      --
1357
      when csr_mhpmcounter3_c  | csr_mhpmcounter4_c  | csr_mhpmcounter5_c  | csr_mhpmcounter6_c  | csr_mhpmcounter7_c  | csr_mhpmcounter8_c  |
1358
           csr_mhpmcounter9_c  | csr_mhpmcounter10_c | csr_mhpmcounter11_c | csr_mhpmcounter12_c | csr_mhpmcounter13_c | csr_mhpmcounter14_c |
1359
           csr_mhpmcounter15_c | csr_mhpmcounter16_c | csr_mhpmcounter17_c | csr_mhpmcounter18_c | csr_mhpmcounter19_c | csr_mhpmcounter20_c |
1360
           csr_mhpmcounter21_c | csr_mhpmcounter22_c | csr_mhpmcounter23_c | csr_mhpmcounter24_c | csr_mhpmcounter25_c | csr_mhpmcounter26_c |
1361
           csr_mhpmcounter27_c | csr_mhpmcounter28_c | csr_mhpmcounter29_c | csr_mhpmcounter30_c | csr_mhpmcounter31_c =>
1362
        csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1363
      --
1364
      when csr_mcycleh_c       => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1365
      when csr_minstreth_c     => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1366
      --
1367
      when csr_mhpmcounter3h_c  | csr_mhpmcounter4h_c  | csr_mhpmcounter5h_c  | csr_mhpmcounter6h_c  | csr_mhpmcounter7h_c  | csr_mhpmcounter8h_c  |
1368
           csr_mhpmcounter9h_c  | csr_mhpmcounter10h_c | csr_mhpmcounter11h_c | csr_mhpmcounter12h_c | csr_mhpmcounter13h_c | csr_mhpmcounter14h_c |
1369
           csr_mhpmcounter15h_c | csr_mhpmcounter16h_c | csr_mhpmcounter17h_c | csr_mhpmcounter18h_c | csr_mhpmcounter19h_c | csr_mhpmcounter20h_c |
1370
           csr_mhpmcounter21h_c | csr_mhpmcounter22h_c | csr_mhpmcounter23h_c | csr_mhpmcounter24h_c | csr_mhpmcounter25h_c | csr_mhpmcounter26h_c |
1371
           csr_mhpmcounter27h_c | csr_mhpmcounter28h_c | csr_mhpmcounter29h_c | csr_mhpmcounter30h_c | csr_mhpmcounter31h_c =>
1372
        csr_acc_valid <= csr.priv_m_mode; -- M-mode only
1373
 
1374 41 zero_gravi
      -- standard read-only CSRs --
1375 42 zero_gravi
      when csr_cycle_c         => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_cy); -- M-mode, U-mode if authorized, read-only
1376
      when csr_time_c          => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_tm); -- M-mode, U-mode if authorized, read-only
1377
      when csr_instret_c       => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_ir); -- M-mode, U-mode if authorized, read-only
1378 15 zero_gravi
      --
1379 44 zero_gravi
      when csr_hpmcounter3_c   => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(00)); -- M-mode, U-mode if authorized, read-only
1380
      when csr_hpmcounter4_c   => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(01)); -- M-mode, U-mode if authorized, read-only
1381
      when csr_hpmcounter5_c   => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(02)); -- M-mode, U-mode if authorized, read-only
1382
      when csr_hpmcounter6_c   => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(03)); -- M-mode, U-mode if authorized, read-only
1383
      when csr_hpmcounter7_c   => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(04)); -- M-mode, U-mode if authorized, read-only
1384
      when csr_hpmcounter8_c   => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(05)); -- M-mode, U-mode if authorized, read-only
1385
      when csr_hpmcounter9_c   => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(06)); -- M-mode, U-mode if authorized, read-only
1386
      when csr_hpmcounter10_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(07)); -- M-mode, U-mode if authorized, read-only
1387
      when csr_hpmcounter11_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(08)); -- M-mode, U-mode if authorized, read-only
1388
      when csr_hpmcounter12_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(09)); -- M-mode, U-mode if authorized, read-only
1389 42 zero_gravi
      when csr_hpmcounter13_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(10)); -- M-mode, U-mode if authorized, read-only
1390
      when csr_hpmcounter14_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(11)); -- M-mode, U-mode if authorized, read-only
1391
      when csr_hpmcounter15_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(12)); -- M-mode, U-mode if authorized, read-only
1392
      when csr_hpmcounter16_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(13)); -- M-mode, U-mode if authorized, read-only
1393
      when csr_hpmcounter17_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(14)); -- M-mode, U-mode if authorized, read-only
1394
      when csr_hpmcounter18_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(15)); -- M-mode, U-mode if authorized, read-only
1395
      when csr_hpmcounter19_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(16)); -- M-mode, U-mode if authorized, read-only
1396
      when csr_hpmcounter20_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(17)); -- M-mode, U-mode if authorized, read-only
1397
      when csr_hpmcounter21_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(18)); -- M-mode, U-mode if authorized, read-only
1398
      when csr_hpmcounter22_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(19)); -- M-mode, U-mode if authorized, read-only
1399
      when csr_hpmcounter23_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(20)); -- M-mode, U-mode if authorized, read-only
1400
      when csr_hpmcounter24_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(21)); -- M-mode, U-mode if authorized, read-only
1401
      when csr_hpmcounter25_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(22)); -- M-mode, U-mode if authorized, read-only
1402
      when csr_hpmcounter26_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(23)); -- M-mode, U-mode if authorized, read-only
1403
      when csr_hpmcounter27_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(24)); -- M-mode, U-mode if authorized, read-only
1404
      when csr_hpmcounter28_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(25)); -- M-mode, U-mode if authorized, read-only
1405
      when csr_hpmcounter29_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(26)); -- M-mode, U-mode if authorized, read-only
1406
      when csr_hpmcounter30_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(27)); -- M-mode, U-mode if authorized, read-only
1407
      when csr_hpmcounter31_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(28)); -- M-mode, U-mode if authorized, read-only
1408 22 zero_gravi
      --
1409 42 zero_gravi
      when csr_cycleh_c        => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_cy); -- M-mode, U-mode if authorized, read-only
1410
      when csr_timeh_c         => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_tm); -- M-mode, U-mode if authorized, read-only
1411
      when csr_instreth_c      => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_ir); -- M-mode, U-mode if authorized, read-only
1412
      --
1413 44 zero_gravi
      when csr_hpmcounter3h_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(00)); -- M-mode, U-mode if authorized, read-only
1414
      when csr_hpmcounter4h_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(01)); -- M-mode, U-mode if authorized, read-only
1415
      when csr_hpmcounter5h_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(02)); -- M-mode, U-mode if authorized, read-only
1416
      when csr_hpmcounter6h_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(03)); -- M-mode, U-mode if authorized, read-only
1417
      when csr_hpmcounter7h_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(04)); -- M-mode, U-mode if authorized, read-only
1418
      when csr_hpmcounter8h_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(05)); -- M-mode, U-mode if authorized, read-only
1419
      when csr_hpmcounter9h_c  => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(06)); -- M-mode, U-mode if authorized, read-only
1420
      when csr_hpmcounter10h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(07)); -- M-mode, U-mode if authorized, read-only
1421
      when csr_hpmcounter11h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(08)); -- M-mode, U-mode if authorized, read-only
1422
      when csr_hpmcounter12h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(09)); -- M-mode, U-mode if authorized, read-only
1423 42 zero_gravi
      when csr_hpmcounter13h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(10)); -- M-mode, U-mode if authorized, read-only
1424
      when csr_hpmcounter14h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(11)); -- M-mode, U-mode if authorized, read-only
1425
      when csr_hpmcounter15h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(12)); -- M-mode, U-mode if authorized, read-only
1426
      when csr_hpmcounter16h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(13)); -- M-mode, U-mode if authorized, read-only
1427
      when csr_hpmcounter17h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(14)); -- M-mode, U-mode if authorized, read-only
1428
      when csr_hpmcounter18h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(15)); -- M-mode, U-mode if authorized, read-only
1429
      when csr_hpmcounter19h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(16)); -- M-mode, U-mode if authorized, read-only
1430
      when csr_hpmcounter20h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(17)); -- M-mode, U-mode if authorized, read-only
1431
      when csr_hpmcounter21h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(18)); -- M-mode, U-mode if authorized, read-only
1432
      when csr_hpmcounter22h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(19)); -- M-mode, U-mode if authorized, read-only
1433
      when csr_hpmcounter23h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(20)); -- M-mode, U-mode if authorized, read-only
1434
      when csr_hpmcounter24h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(21)); -- M-mode, U-mode if authorized, read-only
1435
      when csr_hpmcounter25h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(22)); -- M-mode, U-mode if authorized, read-only
1436
      when csr_hpmcounter26h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(23)); -- M-mode, U-mode if authorized, read-only
1437
      when csr_hpmcounter27h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(24)); -- M-mode, U-mode if authorized, read-only
1438
      when csr_hpmcounter28h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(25)); -- M-mode, U-mode if authorized, read-only
1439
      when csr_hpmcounter29h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(26)); -- M-mode, U-mode if authorized, read-only
1440
      when csr_hpmcounter30h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(27)); -- M-mode, U-mode if authorized, read-only
1441
      when csr_hpmcounter31h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(28)); -- M-mode, U-mode if authorized, read-only
1442
      --
1443
      when csr_mvendorid_c     => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
1444
      when csr_marchid_c       => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
1445
      when csr_mimpid_c        => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
1446
      when csr_mhartid_c       => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
1447 41 zero_gravi
      -- custom read-only CSRs --
1448 42 zero_gravi
      when csr_mzext_c         => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
1449 29 zero_gravi
      --
1450 42 zero_gravi
      when others              => csr_acc_valid <= '0'; -- invalid access
1451 15 zero_gravi
    end case;
1452 49 zero_gravi
  end process csr_access_check;
1453 15 zero_gravi
 
1454
 
1455 2 zero_gravi
  -- Illegal Instruction Check --------------------------------------------------------------
1456
  -- -------------------------------------------------------------------------------------------
1457 44 zero_gravi
  illegal_instruction_check: process(execute_engine, decode_aux, csr_acc_valid)
1458 36 zero_gravi
    variable opcode_v : std_ulogic_vector(6 downto 0);
1459 2 zero_gravi
  begin
1460 11 zero_gravi
    -- illegal instructions are checked in the EXECUTE stage
1461 36 zero_gravi
    -- the execute engine should not commit any illegal instruction
1462 6 zero_gravi
    if (execute_engine.state = EXECUTE) then
1463 2 zero_gravi
      -- defaults --
1464
      illegal_instruction <= '0';
1465
      illegal_register    <= '0';
1466
 
1467 36 zero_gravi
      -- check opcode for rv32 --
1468
      if (execute_engine.i_reg(instr_opcode_lsb_c+1 downto instr_opcode_lsb_c) = "11") then
1469
        illegal_opcode_lsbs <= '0';
1470
      else
1471
        illegal_opcode_lsbs <= '1';
1472
      end if;
1473
 
1474 2 zero_gravi
      -- check instructions --
1475 36 zero_gravi
      opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11";
1476
      case opcode_v is
1477 2 zero_gravi
 
1478 44 zero_gravi
        -- check sufficient LUI, UIPC, JAL (only check actual OPCODE) --
1479 52 zero_gravi
        -- ------------------------------------------------------------
1480 2 zero_gravi
        when opcode_lui_c | opcode_auipc_c | opcode_jal_c =>
1481
          illegal_instruction <= '0';
1482 23 zero_gravi
          -- illegal E-CPU register? --
1483
          if (CPU_EXTENSION_RISCV_E = true) and (execute_engine.i_reg(instr_rd_msb_c) = '1') then
1484
            illegal_register <= '1';
1485
          end if;
1486 2 zero_gravi
 
1487 44 zero_gravi
        when opcode_alu_c => -- check ALU.funct3 & ALU.funct7
1488 52 zero_gravi
        -- ------------------------------------------------------------
1489 44 zero_gravi
          if (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV
1490
            if (CPU_EXTENSION_RISCV_M = false) then -- not implemented
1491
              illegal_instruction <= '1';
1492
            end if;
1493
          elsif (decode_aux.is_bitmanip_reg = '1') then -- bit manipulation
1494
            if (CPU_EXTENSION_RISCV_B = false) then -- not implemented
1495
              illegal_instruction <= '1';
1496
            end if;
1497
          elsif ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or
1498
                 (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c)) and -- ADD/SUB or SRA/SRL check
1499
                ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000") and
1500
                 (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0100000")) then -- ADD/SUB or SRA/SRL select
1501
            illegal_instruction <= '1';
1502
          else
1503
            illegal_instruction <= '0';
1504
          end if;
1505
          -- illegal E-CPU register? --
1506
          if (CPU_EXTENSION_RISCV_E = true) and
1507
             ((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
1508
            illegal_register <= '1';
1509
          end if;
1510
 
1511
        when opcode_alui_c => -- check ALUI.funct7
1512 52 zero_gravi
        -- ------------------------------------------------------------
1513 44 zero_gravi
          if (decode_aux.is_bitmanip_imm = '1') then -- bit manipulation
1514
            if (CPU_EXTENSION_RISCV_B = false) then -- not implemented
1515
              illegal_instruction <= '1';
1516
            end if;
1517
          elsif ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and
1518 6 zero_gravi
              (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000")) or -- shift logical left
1519
             ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and
1520
              ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000") and
1521
               (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0100000"))) then -- shift right
1522 2 zero_gravi
            illegal_instruction <= '1';
1523
          else
1524
            illegal_instruction <= '0';
1525
          end if;
1526 23 zero_gravi
          -- illegal E-CPU register? --
1527
          if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
1528
            illegal_register <= '1';
1529
          end if;
1530 39 zero_gravi
 
1531 44 zero_gravi
        when opcode_load_c => -- check LOAD.funct3
1532 52 zero_gravi
        -- ------------------------------------------------------------
1533 6 zero_gravi
          if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lb_c) or
1534
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lh_c) or
1535
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lw_c) or
1536
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lbu_c) or
1537
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lhu_c) then
1538 2 zero_gravi
            illegal_instruction <= '0';
1539
          else
1540
            illegal_instruction <= '1';
1541
          end if;
1542 23 zero_gravi
          -- illegal E-CPU register? --
1543
          if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
1544
            illegal_register <= '1';
1545
          end if;
1546 39 zero_gravi
 
1547 44 zero_gravi
        when opcode_store_c => -- check STORE.funct3
1548 52 zero_gravi
        -- ------------------------------------------------------------
1549 6 zero_gravi
          if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sb_c) or
1550
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sh_c) or
1551
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sw_c) then
1552 2 zero_gravi
            illegal_instruction <= '0';
1553
          else
1554
            illegal_instruction <= '1';
1555
          end if;
1556 23 zero_gravi
          -- illegal E-CPU register? --
1557
          if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1')) then
1558
            illegal_register <= '1';
1559
          end if;
1560 2 zero_gravi
 
1561 44 zero_gravi
        when opcode_branch_c => -- check BRANCH.funct3
1562 52 zero_gravi
        -- ------------------------------------------------------------
1563 6 zero_gravi
          if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_beq_c) or
1564
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bne_c) or
1565
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_blt_c) or
1566
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bge_c) or
1567
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bltu_c) or
1568
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bgeu_c) then
1569 2 zero_gravi
            illegal_instruction <= '0';
1570
          else
1571
            illegal_instruction <= '1';
1572
          end if;
1573 23 zero_gravi
          -- illegal E-CPU register? --
1574
          if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1')) then
1575
            illegal_register <= '1';
1576
          end if;
1577 2 zero_gravi
 
1578 44 zero_gravi
        when opcode_jalr_c => -- check JALR.funct3
1579 52 zero_gravi
        -- ------------------------------------------------------------
1580 6 zero_gravi
          if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") then
1581 2 zero_gravi
            illegal_instruction <= '0';
1582
          else
1583
            illegal_instruction <= '1';
1584
          end if;
1585 23 zero_gravi
          -- illegal E-CPU register? --
1586
          if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
1587
            illegal_register <= '1';
1588
          end if;
1589 2 zero_gravi
 
1590 52 zero_gravi
        when opcode_fence_c => -- fence instructions
1591
        -- ------------------------------------------------------------
1592 8 zero_gravi
          if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I
1593
            illegal_instruction <= '0';
1594
          elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
1595
            illegal_instruction <= '0';
1596
          else
1597
            illegal_instruction <= '1';
1598
          end if;
1599
 
1600 52 zero_gravi
        when opcode_syscsr_c => -- check system instructions
1601
        -- ------------------------------------------------------------
1602 2 zero_gravi
          -- CSR access --
1603 6 zero_gravi
          if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
1604
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrs_c) or
1605
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrc_c) or
1606
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) or
1607
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrsi_c) or
1608
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrci_c) then
1609 15 zero_gravi
            -- valid CSR access? --
1610
            if (csr_acc_valid = '1') then
1611 2 zero_gravi
              illegal_instruction <= '0';
1612
            else
1613
              illegal_instruction <= '1';
1614
            end if;
1615 23 zero_gravi
            -- illegal E-CPU register? --
1616
            if (CPU_EXTENSION_RISCV_E = true) then
1617
              if (execute_engine.i_reg(instr_funct3_msb_c) = '0') then -- reg-reg CSR
1618
                illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
1619
              else -- reg-imm CSR
1620
                illegal_register <= execute_engine.i_reg(instr_rd_msb_c);
1621
              end if;
1622
            end if;
1623 2 zero_gravi
 
1624
          -- ecall, ebreak, mret, wfi --
1625 6 zero_gravi
          elsif (execute_engine.i_reg(instr_rd_msb_c  downto instr_rd_lsb_c)  = "00000") and
1626
                (execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
1627 13 zero_gravi
            if (execute_engine.i_reg(instr_funct12_msb_c  downto instr_funct12_lsb_c) = funct12_ecall_c)  or -- ECALL
1628 11 zero_gravi
               (execute_engine.i_reg(instr_funct12_msb_c  downto instr_funct12_lsb_c) = funct12_ebreak_c) or -- EBREAK 
1629 13 zero_gravi
               (execute_engine.i_reg(instr_funct12_msb_c  downto instr_funct12_lsb_c) = funct12_mret_c)   or -- MRET
1630
               (execute_engine.i_reg(instr_funct12_msb_c  downto instr_funct12_lsb_c) = funct12_wfi_c) then  -- WFI
1631 2 zero_gravi
              illegal_instruction <= '0';
1632
            else
1633
              illegal_instruction <= '1';
1634
            end if;
1635
          else
1636
            illegal_instruction <= '1';
1637
          end if;
1638
 
1639 52 zero_gravi
        when opcode_atomic_c => -- atomic instructions
1640
        -- ------------------------------------------------------------
1641 39 zero_gravi
          if (CPU_EXTENSION_RISCV_A = true) and -- atomic memory operations (A extension) enabled
1642
             ((execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = funct5_a_lr_c) or -- LR
1643
              (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = funct5_a_sc_c)) then -- SC
1644
            illegal_instruction <= '0';
1645
          else
1646
            illegal_instruction <= '1';
1647
          end if;
1648
 
1649 52 zero_gravi
        when opcode_fop_c => -- floating point operations (dual-operand)
1650
        -- ------------------------------------------------------------
1651
          if (CPU_EXTENSION_RISCV_F = true) and -- F extension enabled
1652
             (execute_engine.i_reg(instr_funct7_lsb_c+1 downto instr_funct7_lsb_c) = float_single_c) and -- single-precision operations
1653
             ((decode_aux.is_float_f_reg = '1') or (decode_aux.is_float_i_reg = '1')) then -- float_reg or int_reg operations
1654
            illegal_instruction <= '0';
1655
          else
1656
            illegal_instruction <= '1';
1657
          end if;
1658
 
1659
        when opcode_flw_c | opcode_fsw_c => -- floating point load/store word
1660
        -- ------------------------------------------------------------
1661
          if (CPU_EXTENSION_RISCV_F = true) and -- F extension enabled
1662
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010") then -- 32-bit transfer size
1663
            illegal_instruction <= '0';
1664
          else
1665
            illegal_instruction <= '1';
1666
          end if;
1667
 
1668 36 zero_gravi
        when others => -- undefined instruction -> illegal!
1669 52 zero_gravi
        -- ------------------------------------------------------------
1670 36 zero_gravi
          illegal_instruction <= '1';
1671 2 zero_gravi
 
1672
      end case;
1673
    else
1674 36 zero_gravi
      illegal_opcode_lsbs <= '0';
1675 2 zero_gravi
      illegal_instruction <= '0';
1676
      illegal_register    <= '0';
1677
    end if;
1678
  end process illegal_instruction_check;
1679
 
1680
  -- any illegal condition? --
1681 36 zero_gravi
  trap_ctrl.instr_il <= illegal_instruction or illegal_opcode_lsbs or illegal_register or illegal_compressed;
1682 2 zero_gravi
 
1683
 
1684 6 zero_gravi
-- ****************************************************************************************************************************
1685 38 zero_gravi
-- Exception and Interrupt (= Trap) Control
1686 6 zero_gravi
-- ****************************************************************************************************************************
1687 2 zero_gravi
 
1688
 
1689 6 zero_gravi
  -- Trap Controller ------------------------------------------------------------------------
1690 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
1691 6 zero_gravi
  trap_controller: process(rstn_i, clk_i)
1692 40 zero_gravi
    variable mode_m_v, mode_u_v : std_ulogic;
1693 2 zero_gravi
  begin
1694
    if (rstn_i = '0') then
1695 6 zero_gravi
      trap_ctrl.exc_buf   <= (others => '0');
1696
      trap_ctrl.irq_buf   <= (others => '0');
1697
      trap_ctrl.exc_ack   <= '0';
1698
      trap_ctrl.irq_ack   <= (others => '0');
1699 47 zero_gravi
      trap_ctrl.env_start <= '0';
1700 40 zero_gravi
      trap_ctrl.cause     <= trap_reset_c;
1701 47 zero_gravi
      trap_ctrl.firq_sync <= (others => '0');
1702 2 zero_gravi
    elsif rising_edge(clk_i) then
1703
      if (CPU_EXTENSION_RISCV_Zicsr = true) then
1704
        -- exception buffer: misaligned load/store/instruction address
1705 40 zero_gravi
        trap_ctrl.exc_buf(exception_lalign_c)    <= (trap_ctrl.exc_buf(exception_lalign_c)    or ma_load_i)          and (not trap_ctrl.exc_ack);
1706
        trap_ctrl.exc_buf(exception_salign_c)    <= (trap_ctrl.exc_buf(exception_salign_c)    or ma_store_i)         and (not trap_ctrl.exc_ack);
1707
        trap_ctrl.exc_buf(exception_ialign_c)    <= (trap_ctrl.exc_buf(exception_ialign_c)    or trap_ctrl.instr_ma) and (not trap_ctrl.exc_ack);
1708 2 zero_gravi
        -- exception buffer: load/store/instruction bus access error
1709 40 zero_gravi
        trap_ctrl.exc_buf(exception_laccess_c)   <= (trap_ctrl.exc_buf(exception_laccess_c)   or be_load_i)          and (not trap_ctrl.exc_ack);
1710
        trap_ctrl.exc_buf(exception_saccess_c)   <= (trap_ctrl.exc_buf(exception_saccess_c)   or be_store_i)         and (not trap_ctrl.exc_ack);
1711
        trap_ctrl.exc_buf(exception_iaccess_c)   <= (trap_ctrl.exc_buf(exception_iaccess_c)   or trap_ctrl.instr_be) and (not trap_ctrl.exc_ack);
1712 2 zero_gravi
        -- exception buffer: illegal instruction / env call / break point
1713 40 zero_gravi
        trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or (trap_ctrl.env_call and csr.priv_m_mode)) and (not trap_ctrl.exc_ack);
1714
        trap_ctrl.exc_buf(exception_u_envcall_c) <= (trap_ctrl.exc_buf(exception_u_envcall_c) or (trap_ctrl.env_call and csr.priv_u_mode)) and (not trap_ctrl.exc_ack);
1715
        trap_ctrl.exc_buf(exception_break_c)     <= (trap_ctrl.exc_buf(exception_break_c)     or trap_ctrl.break_point)                    and (not trap_ctrl.exc_ack);
1716
        trap_ctrl.exc_buf(exception_iillegal_c)  <= (trap_ctrl.exc_buf(exception_iillegal_c)  or trap_ctrl.instr_il)                       and (not trap_ctrl.exc_ack);
1717 18 zero_gravi
        -- interrupt buffer: machine software/external/timer interrupt
1718 40 zero_gravi
        trap_ctrl.irq_buf(interrupt_msw_irq_c)   <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c)   or msw_irq_i)   and (not (trap_ctrl.irq_ack(interrupt_msw_irq_c)   or csr.mip_clear(interrupt_msw_irq_c)));
1719
        trap_ctrl.irq_buf(interrupt_mext_irq_c)  <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c)  or mext_irq_i)  and (not (trap_ctrl.irq_ack(interrupt_mext_irq_c)  or csr.mip_clear(interrupt_mext_irq_c)));
1720
        trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mtime_irq_c) or csr.mip_clear(interrupt_mtime_irq_c)));
1721 48 zero_gravi
        -- interrupt buffer: NEORV32-specific fast interrupts
1722 47 zero_gravi
        trap_ctrl.firq_sync <= firq_i;
1723 48 zero_gravi
        for i in 0 to 15 loop
1724
          trap_ctrl.irq_buf(interrupt_firq_0_c+i) <= csr.mie_firqe(i) and (trap_ctrl.irq_buf(interrupt_firq_0_c+i) or trap_ctrl.firq_sync(i)) and (not (trap_ctrl.irq_ack(interrupt_firq_0_c+i) or csr.mip_clear(interrupt_firq_0_c+i)));
1725
        end loop;
1726 6 zero_gravi
        -- trap control --
1727
        if (trap_ctrl.env_start = '0') then -- no started trap handler
1728 49 zero_gravi
          if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- trap triggered!
1729
             ((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP_ENTER))) then -- fire IRQs in EXECUTE or TRAP state only to continue execution even on permanent IRQ
1730 13 zero_gravi
            trap_ctrl.cause     <= trap_ctrl.cause_nxt;   -- capture source ID for program (for mcause csr)
1731 7 zero_gravi
            trap_ctrl.exc_ack   <= '1';                   -- clear execption
1732 42 zero_gravi
            trap_ctrl.irq_ack   <= trap_ctrl.irq_ack_nxt; -- clear interrupt with interrupt ACK mask
1733 13 zero_gravi
            trap_ctrl.env_start <= '1';                   -- now execute engine can start trap handler
1734 2 zero_gravi
          end if;
1735 6 zero_gravi
        else -- trap waiting to get started
1736
          if (trap_ctrl.env_start_ack = '1') then -- start of trap handler acknowledged by execution engine
1737
            trap_ctrl.exc_ack   <= '0';
1738
            trap_ctrl.irq_ack   <= (others => '0');
1739
            trap_ctrl.env_start <= '0';
1740 2 zero_gravi
          end if;
1741
        end if;
1742
      end if;
1743
    end if;
1744 6 zero_gravi
  end process trap_controller;
1745 2 zero_gravi
 
1746
  -- any exception/interrupt? --
1747 27 zero_gravi
  trap_ctrl.exc_fire <= or_all_f(trap_ctrl.exc_buf); -- exceptions/faults CANNOT be masked
1748
  trap_ctrl.irq_fire <= or_all_f(trap_ctrl.irq_buf) and csr.mstatus_mie; -- interrupts CAN be masked
1749 2 zero_gravi
 
1750 40 zero_gravi
  -- current pending interrupts (for CSR.MIP register) --
1751
  csr.mip_status <= trap_ctrl.irq_buf;
1752 2 zero_gravi
 
1753 47 zero_gravi
  -- acknowledge mask output --
1754 48 zero_gravi
  firq_ack_o <= trap_ctrl.irq_ack(interrupt_firq_15_c downto interrupt_firq_0_c);
1755 40 zero_gravi
 
1756 47 zero_gravi
 
1757 42 zero_gravi
  -- Trap Priority Encoder ------------------------------------------------------------------
1758 6 zero_gravi
  -- -------------------------------------------------------------------------------------------
1759
  trap_priority: process(trap_ctrl)
1760 2 zero_gravi
  begin
1761
    -- defaults --
1762 6 zero_gravi
    trap_ctrl.cause_nxt   <= (others => '0');
1763
    trap_ctrl.irq_ack_nxt <= (others => '0');
1764 2 zero_gravi
 
1765 38 zero_gravi
    -- the following traps are caused by *asynchronous* exceptions (= interrupts)
1766 12 zero_gravi
    -- here we do need a specific acknowledge mask since several sources can trigger at once
1767 9 zero_gravi
 
1768 2 zero_gravi
    -- interrupt: 1.11 machine external interrupt --
1769 6 zero_gravi
    if (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
1770 12 zero_gravi
      trap_ctrl.cause_nxt <= trap_mei_c;
1771 6 zero_gravi
      trap_ctrl.irq_ack_nxt(interrupt_mext_irq_c) <= '1';
1772 2 zero_gravi
 
1773 40 zero_gravi
    -- interrupt: 1.3 machine SW interrupt --
1774
    elsif (trap_ctrl.irq_buf(interrupt_msw_irq_c) = '1') then
1775
      trap_ctrl.cause_nxt <= trap_msi_c;
1776
      trap_ctrl.irq_ack_nxt(interrupt_msw_irq_c) <= '1';
1777
 
1778 2 zero_gravi
    -- interrupt: 1.7 machine timer interrupt --
1779 6 zero_gravi
    elsif (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then
1780 12 zero_gravi
      trap_ctrl.cause_nxt <= trap_mti_c;
1781 6 zero_gravi
      trap_ctrl.irq_ack_nxt(interrupt_mtime_irq_c) <= '1';
1782 2 zero_gravi
 
1783
 
1784 14 zero_gravi
    -- interrupt: 1.16 fast interrupt channel 0 --
1785
    elsif (trap_ctrl.irq_buf(interrupt_firq_0_c) = '1') then
1786
      trap_ctrl.cause_nxt <= trap_firq0_c;
1787
      trap_ctrl.irq_ack_nxt(interrupt_firq_0_c) <= '1';
1788
 
1789
    -- interrupt: 1.17 fast interrupt channel 1 --
1790
    elsif (trap_ctrl.irq_buf(interrupt_firq_1_c) = '1') then
1791
      trap_ctrl.cause_nxt <= trap_firq1_c;
1792
      trap_ctrl.irq_ack_nxt(interrupt_firq_1_c) <= '1';
1793
 
1794
    -- interrupt: 1.18 fast interrupt channel 2 --
1795
    elsif (trap_ctrl.irq_buf(interrupt_firq_2_c) = '1') then
1796
      trap_ctrl.cause_nxt <= trap_firq2_c;
1797
      trap_ctrl.irq_ack_nxt(interrupt_firq_2_c) <= '1';
1798
 
1799
    -- interrupt: 1.19 fast interrupt channel 3 --
1800
    elsif (trap_ctrl.irq_buf(interrupt_firq_3_c) = '1') then
1801
      trap_ctrl.cause_nxt <= trap_firq3_c;
1802
      trap_ctrl.irq_ack_nxt(interrupt_firq_3_c) <= '1';
1803
 
1804 47 zero_gravi
    -- interrupt: 1.20 fast interrupt channel 4 --
1805
    elsif (trap_ctrl.irq_buf(interrupt_firq_4_c) = '1') then
1806
      trap_ctrl.cause_nxt <= trap_firq4_c;
1807
      trap_ctrl.irq_ack_nxt(interrupt_firq_4_c) <= '1';
1808 14 zero_gravi
 
1809 47 zero_gravi
    -- interrupt: 1.21 fast interrupt channel 5 --
1810
    elsif (trap_ctrl.irq_buf(interrupt_firq_5_c) = '1') then
1811
      trap_ctrl.cause_nxt <= trap_firq5_c;
1812
      trap_ctrl.irq_ack_nxt(interrupt_firq_5_c) <= '1';
1813
 
1814
    -- interrupt: 1.22 fast interrupt channel 6 --
1815
    elsif (trap_ctrl.irq_buf(interrupt_firq_6_c) = '1') then
1816
      trap_ctrl.cause_nxt <= trap_firq6_c;
1817
      trap_ctrl.irq_ack_nxt(interrupt_firq_6_c) <= '1';
1818
 
1819
    -- interrupt: 1.23 fast interrupt channel 7 --
1820
    elsif (trap_ctrl.irq_buf(interrupt_firq_7_c) = '1') then
1821
      trap_ctrl.cause_nxt <= trap_firq7_c;
1822
      trap_ctrl.irq_ack_nxt(interrupt_firq_7_c) <= '1';
1823
 
1824 48 zero_gravi
    -- interrupt: 1.24 fast interrupt channel 8 --
1825
    elsif (trap_ctrl.irq_buf(interrupt_firq_8_c) = '1') then
1826
      trap_ctrl.cause_nxt <= trap_firq8_c;
1827
      trap_ctrl.irq_ack_nxt(interrupt_firq_8_c) <= '1';
1828 47 zero_gravi
 
1829 48 zero_gravi
    -- interrupt: 1.25 fast interrupt channel 9 --
1830
    elsif (trap_ctrl.irq_buf(interrupt_firq_9_c) = '1') then
1831
      trap_ctrl.cause_nxt <= trap_firq9_c;
1832
      trap_ctrl.irq_ack_nxt(interrupt_firq_9_c) <= '1';
1833
 
1834
    -- interrupt: 1.26 fast interrupt channel 10 --
1835
    elsif (trap_ctrl.irq_buf(interrupt_firq_10_c) = '1') then
1836
      trap_ctrl.cause_nxt <= trap_firq10_c;
1837
      trap_ctrl.irq_ack_nxt(interrupt_firq_10_c) <= '1';
1838
 
1839
    -- interrupt: 1.27 fast interrupt channel 11 --
1840
    elsif (trap_ctrl.irq_buf(interrupt_firq_11_c) = '1') then
1841
      trap_ctrl.cause_nxt <= trap_firq11_c;
1842
      trap_ctrl.irq_ack_nxt(interrupt_firq_11_c) <= '1';
1843
 
1844
    -- interrupt: 1.28 fast interrupt channel 12 --
1845
    elsif (trap_ctrl.irq_buf(interrupt_firq_12_c) = '1') then
1846
      trap_ctrl.cause_nxt <= trap_firq12_c;
1847
      trap_ctrl.irq_ack_nxt(interrupt_firq_12_c) <= '1';
1848
 
1849
    -- interrupt: 1.29 fast interrupt channel 13 --
1850
    elsif (trap_ctrl.irq_buf(interrupt_firq_13_c) = '1') then
1851
      trap_ctrl.cause_nxt <= trap_firq13_c;
1852
      trap_ctrl.irq_ack_nxt(interrupt_firq_13_c) <= '1';
1853
 
1854
    -- interrupt: 1.30 fast interrupt channel 14 --
1855
    elsif (trap_ctrl.irq_buf(interrupt_firq_14_c) = '1') then
1856
      trap_ctrl.cause_nxt <= trap_firq14_c;
1857
      trap_ctrl.irq_ack_nxt(interrupt_firq_14_c) <= '1';
1858
 
1859
    -- interrupt: 1.31 fast interrupt channel 15 --
1860
    elsif (trap_ctrl.irq_buf(interrupt_firq_15_c) = '1') then
1861
      trap_ctrl.cause_nxt <= trap_firq15_c;
1862
      trap_ctrl.irq_ack_nxt(interrupt_firq_15_c) <= '1';
1863
 
1864
 
1865 42 zero_gravi
    -- the following traps are caused by *synchronous* exceptions (= 'classic' exceptions)
1866 12 zero_gravi
    -- here we do not need a specific acknowledge mask since only one exception (the one
1867 38 zero_gravi
    -- with highest priority) is evaluated at once
1868 4 zero_gravi
 
1869 38 zero_gravi
    -- exception: 0.1 instruction access fault --
1870 6 zero_gravi
    elsif (trap_ctrl.exc_buf(exception_iaccess_c) = '1') then
1871 12 zero_gravi
      trap_ctrl.cause_nxt <= trap_iba_c;
1872 2 zero_gravi
 
1873 38 zero_gravi
    -- exception: 0.2 illegal instruction --
1874 6 zero_gravi
    elsif (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then
1875 12 zero_gravi
      trap_ctrl.cause_nxt <= trap_iil_c;
1876 2 zero_gravi
 
1877 38 zero_gravi
    -- exception: 0.0 instruction address misaligned --
1878 12 zero_gravi
    elsif (trap_ctrl.exc_buf(exception_ialign_c) = '1') then
1879
      trap_ctrl.cause_nxt <= trap_ima_c;
1880 2 zero_gravi
 
1881 12 zero_gravi
 
1882 38 zero_gravi
    -- exception: 0.11 environment call from M-mode --
1883 6 zero_gravi
    elsif (trap_ctrl.exc_buf(exception_m_envcall_c) = '1') then
1884 14 zero_gravi
      trap_ctrl.cause_nxt <= trap_menv_c;
1885 2 zero_gravi
 
1886 40 zero_gravi
    -- exception: 0.8 environment call from U-mode --
1887
    elsif (trap_ctrl.exc_buf(exception_u_envcall_c) = '1') then
1888
      trap_ctrl.cause_nxt <= trap_uenv_c;
1889
 
1890 38 zero_gravi
    -- exception: 0.3 breakpoint --
1891 6 zero_gravi
    elsif (trap_ctrl.exc_buf(exception_break_c) = '1') then
1892 12 zero_gravi
      trap_ctrl.cause_nxt <= trap_brk_c;
1893 2 zero_gravi
 
1894
 
1895 38 zero_gravi
    -- exception: 0.6 store address misaligned -
1896 6 zero_gravi
    elsif (trap_ctrl.exc_buf(exception_salign_c) = '1') then
1897 12 zero_gravi
      trap_ctrl.cause_nxt <= trap_sma_c;
1898 2 zero_gravi
 
1899 38 zero_gravi
    -- exception: 0.4 load address misaligned --
1900 6 zero_gravi
    elsif (trap_ctrl.exc_buf(exception_lalign_c) = '1') then
1901 12 zero_gravi
      trap_ctrl.cause_nxt <= trap_lma_c;
1902 2 zero_gravi
 
1903 38 zero_gravi
    -- exception: 0.7 store access fault --
1904 6 zero_gravi
    elsif (trap_ctrl.exc_buf(exception_saccess_c) = '1') then
1905 12 zero_gravi
      trap_ctrl.cause_nxt <= trap_sbe_c;
1906 2 zero_gravi
 
1907 38 zero_gravi
    -- exception: 0.5 load access fault --
1908 6 zero_gravi
    elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then
1909 12 zero_gravi
      trap_ctrl.cause_nxt <= trap_lbe_c;
1910 2 zero_gravi
 
1911 42 zero_gravi
    -- not implemented --
1912 2 zero_gravi
    else
1913 6 zero_gravi
      trap_ctrl.cause_nxt   <= (others => '0');
1914
      trap_ctrl.irq_ack_nxt <= (others => '0');
1915 2 zero_gravi
    end if;
1916 6 zero_gravi
  end process trap_priority;
1917 39 zero_gravi
 
1918
 
1919 49 zero_gravi
  -- Atomic Memory Access - Status Controller -----------------------------------------------
1920 39 zero_gravi
  -- -------------------------------------------------------------------------------------------
1921 49 zero_gravi
  atomic_memacc_controller: process(rstn_i, clk_i)
1922 39 zero_gravi
  begin
1923
    if (rstn_i = '0') then
1924
      atomic_ctrl.lock       <= '0';
1925
      atomic_ctrl.env_end_ff <= '0';
1926
    elsif rising_edge(clk_i) then
1927
      if (CPU_EXTENSION_RISCV_A = true) then
1928
        if (atomic_ctrl.env_end_ff = '1') or -- normal termination
1929 40 zero_gravi
           (atomic_ctrl.env_abort = '1') or  -- fast termination (error)
1930
           (trap_ctrl.env_start = '1') then  -- triggered trap -> failure
1931 39 zero_gravi
          atomic_ctrl.lock <= '0';
1932
        elsif (atomic_ctrl.env_start = '1') then
1933
          atomic_ctrl.lock <= '1';
1934
        end if;
1935
        atomic_ctrl.env_end_ff <= atomic_ctrl.env_end;
1936
      else
1937
        atomic_ctrl.lock       <= '0';
1938
        atomic_ctrl.env_end_ff <= '0';
1939
      end if;
1940
    end if;
1941 49 zero_gravi
  end process atomic_memacc_controller;
1942 6 zero_gravi
 
1943 2 zero_gravi
 
1944 6 zero_gravi
-- ****************************************************************************************************************************
1945
-- Control and Status Registers (CSRs)
1946
-- ****************************************************************************************************************************
1947 2 zero_gravi
 
1948 27 zero_gravi
  -- Control and Status Registers Write Data ------------------------------------------------
1949
  -- -------------------------------------------------------------------------------------------
1950 36 zero_gravi
  csr_write_data: process(execute_engine.i_reg, csr.rdata, rs1_i)
1951
    variable csr_operand_v : std_ulogic_vector(data_width_c-1 downto 0);
1952 27 zero_gravi
  begin
1953 36 zero_gravi
    -- CSR operand source --
1954
    if (execute_engine.i_reg(instr_funct3_msb_c) = '1') then -- immediate
1955
      csr_operand_v := (others => '0');
1956 38 zero_gravi
      csr_operand_v(4 downto 0) := execute_engine.i_reg(19 downto 15); -- uimm5
1957 36 zero_gravi
    else -- register
1958
      csr_operand_v := rs1_i;
1959
    end if;
1960 40 zero_gravi
    -- tiny ALU for CSR write operations --
1961 27 zero_gravi
    case execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c) is
1962 36 zero_gravi
      when "10"   => csr.wdata <= csr.rdata or csr_operand_v; -- CSRRS(I)
1963
      when "11"   => csr.wdata <= csr.rdata and (not csr_operand_v); -- CSRRC(I)
1964
      when others => csr.wdata <= csr_operand_v; -- CSRRW(I)
1965 27 zero_gravi
    end case;
1966
  end process csr_write_data;
1967
 
1968
 
1969 52 zero_gravi
  -- Control and Status Registers - Write Access --------------------------------------------
1970 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
1971
  csr_write_access: process(rstn_i, clk_i)
1972
  begin
1973
    if (rstn_i = '0') then
1974 40 zero_gravi
      csr.we           <= '0';
1975 11 zero_gravi
      --
1976 6 zero_gravi
      csr.mstatus_mie  <= '0';
1977
      csr.mstatus_mpie <= '0';
1978 29 zero_gravi
      csr.mstatus_mpp  <= priv_mode_m_c; -- start in MACHINE mode
1979
      csr.privilege    <= priv_mode_m_c; -- start in MACHINE mode
1980 6 zero_gravi
      csr.mie_msie     <= '0';
1981
      csr.mie_meie     <= '0';
1982
      csr.mie_mtie     <= '0';
1983 14 zero_gravi
      csr.mie_firqe    <= (others => '0');
1984 6 zero_gravi
      csr.mtvec        <= (others => '0');
1985 36 zero_gravi
      csr.mscratch     <= x"19880704"; -- :)
1986 12 zero_gravi
      csr.mepc         <= (others => '0');
1987 49 zero_gravi
      csr.mcause       <= trap_reset_c; -- mcause = TRAP_CODE_RESET (hardware reset, "non-maskable interrupt")
1988
      csr.mtval        <= (others => '0');
1989
      csr.mip_clear    <= (others => '0');
1990 42 zero_gravi
      --
1991 52 zero_gravi
      csr.pmpcfg  <= (others => (others => '0'));
1992
      csr.pmpaddr <= (others => (others => '1'));
1993 34 zero_gravi
      --
1994 52 zero_gravi
      csr.mhpmevent <= (others => (others => '0'));
1995 41 zero_gravi
      --
1996 52 zero_gravi
      csr.mcounteren_cy  <= '0';
1997
      csr.mcounteren_tm  <= '0';
1998
      csr.mcounteren_ir  <= '0';
1999
      csr.mcounteren_hpm <= (others => '0');
2000 42 zero_gravi
      --
2001
      csr.mcountinhibit_cy  <= '0';
2002
      csr.mcountinhibit_ir  <= '0';
2003
      csr.mcountinhibit_hpm <= (others => '0');
2004 52 zero_gravi
      --
2005
      csr.fflags <= (others => '0');
2006
      csr.frm    <= (others => '0');
2007 49 zero_gravi
 
2008 2 zero_gravi
    elsif rising_edge(clk_i) then
2009 29 zero_gravi
      -- write access? --
2010
      csr.we <= csr.we_nxt;
2011 36 zero_gravi
      if (CPU_EXTENSION_RISCV_Zicsr = true) then
2012 4 zero_gravi
 
2013 40 zero_gravi
        -- defaults --
2014
        csr.mip_clear <= (others => '0');
2015
 
2016 36 zero_gravi
        -- --------------------------------------------------------------------------------
2017
        -- CSR access by application software
2018
        -- --------------------------------------------------------------------------------
2019
        if (csr.we = '1') then -- manual update
2020 52 zero_gravi
 
2021
          -- user floating-point CSRs --
2022
          -- --------------------------------------------------------------------
2023
          if (csr.addr(11 downto 4) = csr_class_float_c) then -- floating point CSR class
2024
            -- R/W: fflags - floating-point (FPU) exception flags --
2025
            if (csr.addr(3 downto 0) = csr_fflags_c(3 downto 0)) and (CPU_EXTENSION_RISCV_F = true) then
2026
              csr.fflags <= csr.wdata(4 downto 0);
2027
            end if;
2028
            -- R/W: frm - floating-point (FPU) rounding mode --
2029
            if (csr.addr(3 downto 0) = csr_frm_c(3 downto 0)) and (CPU_EXTENSION_RISCV_F = true) then
2030
              csr.frm <= csr.wdata(2 downto 0);
2031
            end if;
2032
            -- R/W: fflags - floating-point (FPU) control/status (frm + fflags) --
2033
            if (csr.addr(3 downto 0) = csr_fcsr_c(3 downto 0)) and (CPU_EXTENSION_RISCV_F = true) then
2034
              csr.frm    <= csr.wdata(7 downto 5);
2035
              csr.fflags <= csr.wdata(4 downto 0);
2036
            end if;
2037
          end if;
2038
 
2039
          -- machine trap setup --
2040
          -- --------------------------------------------------------------------
2041
          if (csr.addr(11 downto 4) = csr_setup_c) then -- ftrap setup CSR class
2042
            -- R/W: mstatus - machine status register --
2043
            if (csr.addr(3 downto 0) = csr_mstatus_c(3 downto 0)) then
2044 36 zero_gravi
              csr.mstatus_mie  <= csr.wdata(03);
2045
              csr.mstatus_mpie <= csr.wdata(07);
2046
              if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
2047
                csr.mstatus_mpp(0) <= csr.wdata(11) or csr.wdata(12);
2048
                csr.mstatus_mpp(1) <= csr.wdata(11) or csr.wdata(12);
2049 40 zero_gravi
              else -- only machine mode is available
2050
                csr.mstatus_mpp <= priv_mode_m_c;
2051 36 zero_gravi
              end if;
2052 52 zero_gravi
            end if;
2053
            -- R/W: mie - machine interrupt enable register --
2054
            if (csr.addr(3 downto 0) = csr_mie_c(3 downto 0)) then
2055 29 zero_gravi
              csr.mie_msie <= csr.wdata(03); -- machine SW IRQ enable
2056
              csr.mie_mtie <= csr.wdata(07); -- machine TIMER IRQ enable
2057
              csr.mie_meie <= csr.wdata(11); -- machine EXT IRQ enable
2058 48 zero_gravi
              for i in 0 to 15 loop -- fast interrupt channels 0..15
2059
                csr.mie_firqe(i) <= csr.wdata(16+i);
2060
              end loop; -- i
2061 52 zero_gravi
            end if;
2062
            -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) --
2063
            if (csr.addr(3 downto 0) = csr_mtvec_c(3 downto 0)) then
2064 29 zero_gravi
              csr.mtvec <= csr.wdata(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
2065 52 zero_gravi
            end if;
2066
            -- R/W: machine counter enable register --
2067
            if (csr.addr(3 downto 0) = csr_mcounteren_c(3 downto 0)) then
2068 51 zero_gravi
              if (CPU_EXTENSION_RISCV_U = true) then -- this CSR is hardwired to zero if user mode is not implemented
2069
                csr.mcounteren_cy  <= csr.wdata(0); -- enable user-level access to cycle[h]
2070
                csr.mcounteren_tm  <= csr.wdata(1); -- enable user-level access to time[h]
2071
                csr.mcounteren_ir  <= csr.wdata(2); -- enable user-level access to instret[h]
2072
                csr.mcounteren_hpm <= csr.wdata(csr.mcounteren_hpm'left+3 downto 3); -- enable user-level access to hpmcounterx[h]
2073
              end if;
2074 52 zero_gravi
            end if;
2075
          end if;
2076 29 zero_gravi
 
2077 52 zero_gravi
          -- machine trap handling --
2078
          -- --------------------------------------------------------------------
2079
          if (csr.addr(11 downto 4) = csr_class_trap_c) then -- machine trap handling CSR class
2080
            -- R/W: mscratch - machine scratch register --
2081
            if (csr.addr(3 downto 0) = csr_mscratch_c(3 downto 0)) then
2082 36 zero_gravi
              csr.mscratch <= csr.wdata;
2083 52 zero_gravi
            end if;
2084
            -- R/W: mepc - machine exception program counter --
2085
            if (csr.addr(3 downto 0) = csr_mepc_c(3 downto 0)) then
2086 36 zero_gravi
              csr.mepc <= csr.wdata(data_width_c-1 downto 1) & '0';
2087 52 zero_gravi
            end if;
2088
            -- R/W: mcause - machine trap cause --
2089
            if (csr.addr(3 downto 0) = csr_mcause_c(3 downto 0)) then
2090 36 zero_gravi
              csr.mcause(csr.mcause'left) <= csr.wdata(31); -- 1: interrupt, 0: exception
2091
              csr.mcause(4 downto 0)      <= csr.wdata(4 downto 0); -- identifier
2092 52 zero_gravi
            end if;
2093
            -- R/W: mtval - machine bad address/instruction --
2094
            if (csr.addr(3 downto 0) = csr_mtval_c(3 downto 0)) then
2095 36 zero_gravi
              csr.mtval <= csr.wdata;
2096 52 zero_gravi
            end if;
2097
            -- R/W: mip - machine interrupt pending --
2098
            if (csr.addr(3 downto 0) = csr_mip_c(3 downto 0)) then
2099 40 zero_gravi
              csr.mip_clear(interrupt_msw_irq_c)   <= not csr.wdata(03);
2100
              csr.mip_clear(interrupt_mtime_irq_c) <= not csr.wdata(07);
2101
              csr.mip_clear(interrupt_mext_irq_c)  <= not csr.wdata(11);
2102 48 zero_gravi
              for i in 0 to 15 loop -- fast interrupt channels 0..15
2103
                csr.mip_clear(interrupt_firq_0_c+i) <= not csr.wdata(16+i);
2104
              end loop; -- i
2105 52 zero_gravi
            end if;
2106
          end if;
2107 29 zero_gravi
 
2108 52 zero_gravi
          -- physical memory protection: R/W: pmpcfg* - PMP configuration registers --
2109
          -- --------------------------------------------------------------------
2110
          if (csr.addr(11 downto 4) = csr_class_pmpcfg_c) then -- pmp configuration CSR class
2111
            if (PMP_NUM_REGIONS > 0) then
2112
              for i in 0 to PMP_NUM_REGIONS-1 loop
2113
                if (csr.addr(3 downto 0) = std_ulogic_vector(to_unsigned(i, 4))) then
2114
                  if (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpcfg access
2115
                    csr.pmpcfg(i)(0) <= csr.wdata((i mod 4)*8+0); -- R (rights.read)
2116
                    csr.pmpcfg(i)(1) <= csr.wdata((i mod 4)*8+1); -- W (rights.write)
2117
                    csr.pmpcfg(i)(2) <= csr.wdata((i mod 4)*8+2); -- X (rights.execute)
2118
                    csr.pmpcfg(i)(3) <= csr.wdata((i mod 4)*8+3) and csr.wdata((i mod 4)*8+4); -- A_L
2119
                    csr.pmpcfg(i)(4) <= csr.wdata((i mod 4)*8+3) and csr.wdata((i mod 4)*8+4); -- A_H - NAPOT/OFF only
2120
                    csr.pmpcfg(i)(5) <= '0'; -- reserved
2121
                    csr.pmpcfg(i)(6) <= '0'; -- reserved
2122
                    csr.pmpcfg(i)(7) <= csr.wdata((i mod 4)*8+7); -- L (locked / rights also enforced in m-mode)
2123 36 zero_gravi
                  end if;
2124 52 zero_gravi
                end if;
2125
              end loop; -- i (PMP regions)
2126
            end if;
2127
          end if;
2128 4 zero_gravi
 
2129 52 zero_gravi
          -- physical memory protection: R/W: pmpaddr* - PMP address registers --
2130
          -- --------------------------------------------------------------------
2131
          if (csr.addr(11 downto 4) =  csr_pmpaddr0_c(11 downto 4)) or (csr.addr(11 downto 4) = csr_pmpaddr16_c(11 downto 4)) or
2132
             (csr.addr(11 downto 4) = csr_pmpaddr32_c(11 downto 4)) or (csr.addr(11 downto 4) = csr_pmpaddr48_c(11 downto 4)) then
2133
            if (PMP_NUM_REGIONS > 0) then
2134
              for i in 0 to PMP_NUM_REGIONS-1 loop
2135
                if (csr.addr(6 downto 0) = std_ulogic_vector(unsigned(csr_pmpaddr0_c(6 downto 0)) + i)) and (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpaddr access
2136
                  csr.pmpaddr(i) <= csr.wdata;
2137
                  csr.pmpaddr(i)(index_size_f(PMP_MIN_GRANULARITY)-4 downto 0) <= (others => '1');
2138
                end if;
2139
              end loop; -- i (PMP regions)
2140
            end if;
2141
          end if;
2142 2 zero_gravi
 
2143 52 zero_gravi
          -- machine counter setup --
2144
          -- --------------------------------------------------------------------
2145
          -- R/W: mcountinhibit - machine counter-inhibit register --
2146
          if (csr.addr = csr_mcountinhibit_c) then
2147
            csr.mcountinhibit_cy  <= csr.wdata(0); -- enable auto-increment of [m]cycle[h] counter
2148
            csr.mcountinhibit_ir  <= csr.wdata(2); -- enable auto-increment of [m]instret[h] counter
2149
            csr.mcountinhibit_hpm <= csr.wdata(csr.mcountinhibit_hpm'left+3 downto 3); -- enable auto-increment of [m]hpmcounter*[h] counter
2150
          end if;
2151 41 zero_gravi
 
2152 52 zero_gravi
          -- machine performance-monitoring event selector --
2153
          -- --------------------------------------------------------------------
2154
          if (unsigned(csr.addr) >= unsigned(csr_mhpmevent3_c)) and (unsigned(csr.addr) <= unsigned(csr_mhpmevent31_c)) then
2155
            if (HPM_NUM_CNTS > 0) then
2156
              for i in 0 to HPM_NUM_CNTS-1 loop
2157
                if (csr.addr(4 downto 0) = std_ulogic_vector(to_unsigned(i+3, 5))) then
2158
                  csr.mhpmevent(i) <= csr.wdata(csr.mhpmevent(i)'left downto 0);
2159
                  csr.mhpmevent(i)(1) <= '0'; -- would be used for "TIME"
2160
                end if;
2161
              end loop; -- i (CSRs)
2162
            end if;
2163
          end if;
2164 42 zero_gravi
 
2165 29 zero_gravi
 
2166 36 zero_gravi
        -- --------------------------------------------------------------------------------
2167
        -- CSR access by hardware
2168
        -- --------------------------------------------------------------------------------
2169
        else
2170
 
2171 52 zero_gravi
          -- floating-point (FPU) exception flags --
2172
          -- --------------------------------------------------------------------
2173
          if (CPU_EXTENSION_RISCV_F = true) and (execute_engine.state = ALU_WAIT) then -- FIXME?
2174
            csr.fflags <= csr.fflags or fpu_flags_i; -- accumulate flags ("accrued exception flags")
2175
          end if;
2176
 
2177 40 zero_gravi
          -- mcause, mepc, mtval: machine trap cause, PC and value register --
2178 36 zero_gravi
          -- --------------------------------------------------------------------
2179
          if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
2180 40 zero_gravi
            -- trap cause ID code --
2181
            csr.mcause(csr.mcause'left) <= trap_ctrl.cause(trap_ctrl.cause'left); -- 1: interrupt, 0: exception
2182
            csr.mcause(4 downto 0)      <= trap_ctrl.cause(4 downto 0); -- identifier
2183
            -- trap PC --
2184 36 zero_gravi
            if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS
2185 49 zero_gravi
              csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
2186 40 zero_gravi
            else -- for EXCEPTIONS
2187 36 zero_gravi
              csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
2188 40 zero_gravi
            end if;
2189
            -- trap value --
2190
            case trap_ctrl.cause is
2191
              when trap_ima_c | trap_iba_c => -- misaligned instruction address OR instruction access error
2192 36 zero_gravi
                csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
2193 40 zero_gravi
              when trap_brk_c => -- breakpoint
2194
                csr.mtval <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- address of breakpoint instruction
2195
              when trap_lma_c | trap_lbe_c | trap_sma_c | trap_sbe_c => -- misaligned load/store address OR load/store access error
2196
                csr.mtval <= mar_i; -- faulting data access address
2197
              when trap_iil_c => -- illegal instruction
2198 36 zero_gravi
                csr.mtval <= execute_engine.i_reg_last; -- faulting instruction itself
2199 47 zero_gravi
              when others => -- everything else including all interrupts
2200 40 zero_gravi
                csr.mtval <= (others => '0');
2201
            end case;
2202 2 zero_gravi
          end if;
2203
 
2204 36 zero_gravi
          -- mstatus: context switch --
2205
          -- --------------------------------------------------------------------
2206
          if (trap_ctrl.env_start_ack = '1') then -- ENTER: trap handler starting?
2207
            csr.mstatus_mie  <= '0'; -- disable interrupts
2208
            csr.mstatus_mpie <= csr.mstatus_mie; -- buffer previous mie state
2209
            if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
2210
              csr.privilege   <= priv_mode_m_c; -- execute trap in machine mode
2211
              csr.mstatus_mpp <= csr.privilege; -- buffer previous privilege mode
2212 2 zero_gravi
            end if;
2213 36 zero_gravi
          elsif (trap_ctrl.env_end = '1') then -- EXIT: return from exception
2214
            csr.mstatus_mie  <= csr.mstatus_mpie; -- restore global IRQ enable flag
2215
            csr.mstatus_mpie <= '1';
2216
            if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
2217
              csr.privilege   <= csr.mstatus_mpp; -- go back to previous privilege mode
2218 40 zero_gravi
              csr.mstatus_mpp <= priv_mode_m_c;
2219 30 zero_gravi
            end if;
2220 2 zero_gravi
          end if;
2221 36 zero_gravi
          -- user mode NOT implemented --
2222
          if (CPU_EXTENSION_RISCV_U = false) then
2223
            csr.privilege   <= priv_mode_m_c;
2224
            csr.mstatus_mpp <= priv_mode_m_c;
2225 15 zero_gravi
          end if;
2226 29 zero_gravi
 
2227 52 zero_gravi
        end if; -- /hardware csr access
2228
      end if;
2229 29 zero_gravi
 
2230 52 zero_gravi
      -- --------------------------------------------------------------------------------
2231
      -- override write access for disabled functions
2232
      -- --------------------------------------------------------------------------------
2233
 
2234
      -- user mode disabled --
2235
      if (CPU_EXTENSION_RISCV_U = false) then
2236
        csr.privilege      <= priv_mode_m_c;
2237
        csr.mstatus_mpp    <= priv_mode_m_c;
2238
        csr.mcounteren_cy  <= '0';
2239
        csr.mcounteren_tm  <= '0';
2240
        csr.mcounteren_ir  <= '0';
2241
        csr.mcounteren_hpm <= (others => '0');
2242 34 zero_gravi
      end if;
2243 52 zero_gravi
 
2244
      -- pmp disabled --
2245
      if (PMP_NUM_REGIONS = 0) then
2246
        csr.pmpcfg  <= (others => (others => '0'));
2247
        csr.pmpaddr <= (others => (others => '1'));
2248
      end if;
2249
 
2250
      -- hpms disabled --
2251
      if (HPM_NUM_CNTS = 0) then
2252
        csr.mhpmevent         <= (others => (others => '0'));
2253
        csr.mcounteren_hpm    <= (others => '0');
2254
        csr.mcountinhibit_hpm <= (others => '0');
2255
      end if;
2256
 
2257
      -- floating-point extension disabled --
2258
      if (CPU_EXTENSION_RISCV_F = false) then
2259
        csr.fflags <= (others => '0');
2260
        csr.frm    <= (others => '0');
2261
      end if;
2262
 
2263 2 zero_gravi
    end if;
2264
  end process csr_write_access;
2265
 
2266 40 zero_gravi
  -- decode privilege mode --
2267 51 zero_gravi
  csr.priv_m_mode <= '1' when (csr.privilege = priv_mode_m_c) else '0';
2268
  csr.priv_u_mode <= '1' when (csr.privilege = priv_mode_u_c) else '0';
2269 40 zero_gravi
 
2270 36 zero_gravi
  -- PMP configuration output to bus unit --
2271 34 zero_gravi
  pmp_output: process(csr)
2272
  begin
2273
    pmp_addr_o <= (others => (others => '0'));
2274
    pmp_ctrl_o <= (others => (others => '0'));
2275 42 zero_gravi
    for i in 0 to PMP_NUM_REGIONS-1 loop
2276
      pmp_addr_o(i) <= csr.pmpaddr(i) & "11";
2277
      pmp_addr_o(i)(index_size_f(PMP_MIN_GRANULARITY)-4 downto 0) <= (others => '1');
2278
      pmp_ctrl_o(i) <= csr.pmpcfg(i);
2279
    end loop; -- i
2280
  end process pmp_output;
2281
 
2282
  -- PMP read dummy --
2283
  pmp_rd_dummy: process(csr)
2284
  begin
2285
    csr.pmpcfg_rd  <= (others => (others => '0'));
2286
    csr.pmpaddr_rd <= (others => (others => '0'));
2287
    for i in 0 to PMP_NUM_REGIONS-1 loop
2288
      csr.pmpcfg_rd(i)  <= csr.pmpcfg(i);
2289
      csr.pmpaddr_rd(i) <= csr.pmpaddr(i);
2290
      if (csr.pmpcfg(i)(4 downto 3) = "00") then -- mode = off
2291
        csr.pmpaddr_rd(i)(index_size_f(PMP_MIN_GRANULARITY)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
2292
      end if;
2293
    end loop; -- i
2294
  end process pmp_rd_dummy;
2295
 
2296 52 zero_gravi
  -- FPU rounding mode --
2297
  fpu_rm_o <= csr.frm;
2298 42 zero_gravi
 
2299 52 zero_gravi
 
2300 42 zero_gravi
  -- Control and Status Registers - Counters ------------------------------------------------
2301
  -- -------------------------------------------------------------------------------------------
2302
  csr_counters: process(clk_i)
2303
  begin
2304
    -- Counter CSRs (each counter is split into two 32-bit counters)
2305
    if rising_edge(clk_i) then
2306
 
2307
      -- [m]cycle --
2308
      if (csr.we = '1') and (csr.addr = csr_mcycle_c) then -- write access
2309
        csr.mcycle <= '0' & csr.wdata;
2310
        mcycle_msb <= '0';
2311
      elsif (csr.mcountinhibit_cy = '0') and (cnt_event(hpmcnt_event_cy_c) = '1') then -- non-inhibited automatic update
2312
        csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
2313
        mcycle_msb <= csr.mcycle(csr.mcycle'left);
2314
      end if;
2315
 
2316
      -- [m]cycleh --
2317
      if (csr.we = '1') and (csr.addr = csr_mcycleh_c) then -- write access
2318
        csr.mcycleh <= csr.wdata;
2319
      elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update (continued)
2320
        csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
2321
      end if;
2322
 
2323
      -- [m]instret --
2324
      if (csr.we = '1') and (csr.addr = csr_minstret_c) then -- write access
2325
        csr.minstret <= '0' & csr.wdata;
2326
        minstret_msb <= '0';
2327
      elsif (csr.mcountinhibit_ir = '0') and (cnt_event(hpmcnt_event_ir_c) = '1') and (cnt_event(hpmcnt_event_cy_c) = '1') then -- non-inhibited automatic update
2328
        csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
2329
        minstret_msb <= csr.minstret(csr.minstret'left);
2330
      end if;
2331
 
2332
      -- [m]instreth --
2333
      if (csr.we = '1') and (csr.addr = csr_minstreth_c) then -- write access
2334
        csr.minstreth <= csr.wdata;
2335
      elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update (continued)
2336
        csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
2337
      end if;
2338
 
2339 45 zero_gravi
      -- [machine] hardware performance monitors (counters) --
2340 42 zero_gravi
      for i in 0 to HPM_NUM_CNTS-1 loop
2341
        -- [m]hpmcounter* --
2342
        if (csr.we = '1') and (csr.addr = std_ulogic_vector(unsigned(csr_mhpmcounter3_c) + i)) then -- write access
2343
          csr.mhpmcounter(i) <= '0' & csr.wdata;
2344
          mhpmcounter_msb(i) <= '0';
2345
        elsif (csr.mcountinhibit_hpm(i) = '0') and (hpmcnt_trigger(i) = '1') then -- non-inhibited automatic update
2346
          csr.mhpmcounter(i) <= std_ulogic_vector(unsigned(csr.mhpmcounter(i)) + 1);
2347
          mhpmcounter_msb(i) <= csr.mhpmcounter(i)(csr.mhpmcounter(i)'left);
2348
        end if;
2349
 
2350
        -- [m]hpmcounter*h --
2351
        if (csr.we = '1') and (csr.addr = std_ulogic_vector(unsigned(csr_mhpmcounter3h_c) + i)) then -- write access
2352
          csr.mhpmcounterh(i) <= csr.wdata;
2353
        elsif ((mhpmcounter_msb(i) xor csr.mhpmcounter(i)(csr.mhpmcounter(i)'left)) = '1') then -- automatic update (continued)
2354
          csr.mhpmcounterh(i) <= std_ulogic_vector(unsigned(csr.mhpmcounterh(i)) + 1);
2355
        end if;
2356 34 zero_gravi
      end loop; -- i
2357 42 zero_gravi
 
2358 34 zero_gravi
    end if;
2359 42 zero_gravi
  end process csr_counters;
2360 34 zero_gravi
 
2361 42 zero_gravi
  -- hpm read dummy --
2362
  hpm_rd_dummy: process(csr)
2363
  begin
2364
    csr.mhpmevent_rd    <= (others => (others => '0'));
2365
    csr.mhpmcounter_rd  <= (others => (others => '0'));
2366
    csr.mhpmcounterh_rd <= (others => (others => '0'));
2367
    for i in 0 to HPM_NUM_CNTS-1 loop
2368
      csr.mhpmevent_rd(i)    <= csr.mhpmevent(i);
2369
      csr.mhpmcounter_rd(i)  <= csr.mhpmcounter(i);
2370
      csr.mhpmcounterh_rd(i) <= csr.mhpmcounterh(i);
2371
    end loop; -- i
2372
  end process hpm_rd_dummy;
2373 34 zero_gravi
 
2374 42 zero_gravi
 
2375
  -- (HPM) Counter Event Control ------------------------------------------------------------
2376
  -- -------------------------------------------------------------------------------------------
2377
  hpmcnt_ctrl: process(clk_i)
2378
  begin
2379
    if rising_edge(clk_i) then
2380 47 zero_gravi
      -- buffer event sources --
2381
      cnt_event <= cnt_event_nxt;
2382
      -- enable selected triggers by ANDing actual events and according CSR configuration bits --
2383
      -- OR everything to see if counter should increment --
2384 42 zero_gravi
      hpmcnt_trigger <= (others => '0'); -- default
2385
      for i in 0 to HPM_NUM_CNTS-1 loop
2386 47 zero_gravi
        hpmcnt_trigger(i) <= or_all_f(cnt_event and csr.mhpmevent(i)(cnt_event'left downto 0));
2387 42 zero_gravi
      end loop; -- i
2388
    end if;
2389
  end process hpmcnt_ctrl;
2390
 
2391
  -- counter event trigger - RISC-V specific --
2392
  cnt_event_nxt(hpmcnt_event_cy_c)    <= not execute_engine.sleep; -- active cycle
2393
  cnt_event_nxt(hpmcnt_event_never_c) <= '0'; -- undefined (never)
2394
  cnt_event_nxt(hpmcnt_event_ir_c)    <= '1' when (execute_engine.state = EXECUTE) else '0'; -- retired instruction
2395
 
2396
  -- counter event trigger - custom / NEORV32-specific --
2397 47 zero_gravi
  cnt_event_nxt(hpmcnt_event_cir_c)     <= '1' when (execute_engine.state = EXECUTE)      and (execute_engine.is_ci = '1')             else '0'; -- retired compressed instruction
2398
  cnt_event_nxt(hpmcnt_event_wait_if_c) <= '1' when (fetch_engine.state   = IFETCH_ISSUE) and (fetch_engine.state_prev = IFETCH_ISSUE) else '0'; -- instruction fetch memory wait cycle
2399
  cnt_event_nxt(hpmcnt_event_wait_ii_c) <= '1' when (execute_engine.state = DISPATCH)     and (execute_engine.state_prev = DISPATCH)   else '0'; -- instruction issue wait cycle
2400
  cnt_event_nxt(hpmcnt_event_wait_mc_c) <= '1' when (execute_engine.state = ALU_WAIT)     and (execute_engine.state_prev = ALU_WAIT)   else '0'; -- multi-cycle alu-operation wait cycle
2401 42 zero_gravi
 
2402
  cnt_event_nxt(hpmcnt_event_load_c)    <= '1' when (execute_engine.state = LOADSTORE_1) and (ctrl(ctrl_bus_rd_c) = '1')               else '0'; -- load operation
2403
  cnt_event_nxt(hpmcnt_event_store_c)   <= '1' when (execute_engine.state = LOADSTORE_1) and (ctrl(ctrl_bus_wr_c) = '1')               else '0'; -- store operation
2404
  cnt_event_nxt(hpmcnt_event_wait_ls_c) <= '1' when (execute_engine.state = LOADSTORE_2) and (execute_engine.state_prev = LOADSTORE_2) else '0'; -- load/store memory wait cycle
2405
 
2406
  cnt_event_nxt(hpmcnt_event_jump_c)    <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') else '0'; -- jump (unconditional)
2407
  cnt_event_nxt(hpmcnt_event_branch_c)  <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') else '0'; -- branch (conditional, taken or not taken)
2408
  cnt_event_nxt(hpmcnt_event_tbranch_c) <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') and (execute_engine.branch_taken = '1') else '0'; -- taken branch (conditional)
2409
 
2410
  cnt_event_nxt(hpmcnt_event_trap_c)    <= '1' when (trap_ctrl.env_start_ack = '1')                                    else '0'; -- entered trap
2411
  cnt_event_nxt(hpmcnt_event_illegal_c) <= '1' when (trap_ctrl.env_start_ack = '1') and (trap_ctrl.cause = trap_iil_c) else '0'; -- illegal operation
2412
 
2413
 
2414 52 zero_gravi
  -- Control and Status Registers - Read Access ---------------------------------------------
2415 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
2416
  csr_read_access: process(clk_i)
2417
  begin
2418
    if rising_edge(clk_i) then
2419 29 zero_gravi
      csr.re    <= csr.re_nxt; -- read access?
2420 35 zero_gravi
      csr.rdata <= (others => '0'); -- default output
2421 11 zero_gravi
      if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.re = '1') then
2422 41 zero_gravi
        case csr.addr is
2423 11 zero_gravi
 
2424 52 zero_gravi
          -- user floating-point CSRs --
2425
          -- --------------------------------------------------------------------
2426
          when csr_fflags_c => -- R/W: fflags - floating-point (FPU) exception flags
2427
            csr.rdata <= (others => '0');
2428
            if (CPU_EXTENSION_RISCV_F = true) then -- FPU implemented
2429
              csr.rdata(4 downto 0) <= csr.fflags;
2430
            end if;
2431
          when csr_frm_c => -- R/W: frm - floating-point (FPU) rounding mode
2432
            csr.rdata <= (others => '0');
2433
            if (CPU_EXTENSION_RISCV_F = true) then -- FPU implemented
2434
              csr.rdata(2 downto 0) <= csr.frm;
2435
            end if;
2436
          when csr_fcsr_c => -- R/W: fflags - floating-point (FPU) control/status (frm + fflags)
2437
            csr.rdata <= (others => '0');
2438
            if (CPU_EXTENSION_RISCV_F = true) then -- FPU implemented
2439
              csr.rdata(7 downto 5) <= csr.frm;
2440
              csr.rdata(4 downto 0) <= csr.fflags;
2441
            end if;
2442
 
2443 11 zero_gravi
          -- machine trap setup --
2444 29 zero_gravi
          when csr_mstatus_c => -- R/W: mstatus - machine status register
2445 41 zero_gravi
            csr.rdata(03) <= csr.mstatus_mie; -- MIE
2446
            csr.rdata(06) <= '1' and bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- UBE: CPU/Processor is BIG-ENDIAN (in user-mode)
2447 27 zero_gravi
            csr.rdata(07) <= csr.mstatus_mpie; -- MPIE
2448 29 zero_gravi
            csr.rdata(11) <= csr.mstatus_mpp(0); -- MPP: machine previous privilege mode low
2449
            csr.rdata(12) <= csr.mstatus_mpp(1); -- MPP: machine previous privilege mode high
2450 40 zero_gravi
          when csr_mstatush_c => -- R/-: mstatush - machine status register - high part
2451 41 zero_gravi
            csr.rdata(05) <= '1'; -- MBE: CPU/Processor is BIG-ENDIAN (in machine-mode)
2452 29 zero_gravi
          when csr_misa_c => -- R/-: misa - ISA and extensions
2453 39 zero_gravi
            csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A);     -- A CPU extension
2454 44 zero_gravi
            csr.rdata(01) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B);     -- B CPU extension
2455 27 zero_gravi
            csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C);     -- C CPU extension
2456
            csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E);     -- E CPU extension
2457 52 zero_gravi
            csr.rdata(05) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_F);     -- F CPU extension
2458 27 zero_gravi
            csr.rdata(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
2459
            csr.rdata(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M);     -- M CPU extension
2460
            csr.rdata(20) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_U);     -- U CPU extension
2461
            csr.rdata(23) <= '1';                                         -- X CPU extension (non-std extensions)
2462
            csr.rdata(30) <= '1'; -- 32-bit architecture (MXL lo)
2463
            csr.rdata(31) <= '0'; -- 32-bit architecture (MXL hi)
2464 29 zero_gravi
          when csr_mie_c => -- R/W: mie - machine interrupt-enable register
2465 27 zero_gravi
            csr.rdata(03) <= csr.mie_msie; -- machine software IRQ enable
2466
            csr.rdata(07) <= csr.mie_mtie; -- machine timer IRQ enable
2467
            csr.rdata(11) <= csr.mie_meie; -- machine external IRQ enable
2468 48 zero_gravi
            for i in 0 to 15 loop -- fast interrupt channels 0..15 enable
2469
              csr.rdata(16+i) <= csr.mie_firqe(i);
2470
            end loop; -- i
2471 29 zero_gravi
          when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
2472 27 zero_gravi
            csr.rdata <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
2473 41 zero_gravi
          when csr_mcounteren_c => -- R/W: machine counter enable register
2474 51 zero_gravi
            if (CPU_EXTENSION_RISCV_U = true) then -- this CSR is hardwired to zero if user mode is not implemented
2475
              csr.rdata(0) <= csr.mcounteren_cy; -- enable user-level access to cycle[h]
2476
              csr.rdata(1) <= csr.mcounteren_tm; -- enable user-level access to time[h]
2477
              csr.rdata(2) <= csr.mcounteren_ir; -- enable user-level access to instret[h]
2478
              csr.rdata(csr.mcounteren_hpm'left+3 downto 3) <= csr.mcounteren_hpm; -- enable user-level access to hpmcounterx[h]
2479
            else
2480
              csr.rdata <= (others => '0');
2481
            end if;
2482 11 zero_gravi
 
2483
          -- machine trap handling --
2484 29 zero_gravi
          when csr_mscratch_c => -- R/W: mscratch - machine scratch register
2485 27 zero_gravi
            csr.rdata <= csr.mscratch;
2486 29 zero_gravi
          when csr_mepc_c => -- R/W: mepc - machine exception program counter
2487 27 zero_gravi
            csr.rdata <= csr.mepc(data_width_c-1 downto 1) & '0';
2488 35 zero_gravi
          when csr_mcause_c => -- R/W: mcause - machine trap cause
2489 49 zero_gravi
            csr.rdata(31) <= csr.mcause(csr.mcause'left);
2490
            csr.rdata(csr.mcause'left-1 downto 0) <= csr.mcause(csr.mcause'left-1 downto 0);
2491 29 zero_gravi
          when csr_mtval_c => -- R/W: mtval - machine bad address or instruction
2492 27 zero_gravi
            csr.rdata <= csr.mtval;
2493 29 zero_gravi
          when csr_mip_c => -- R/W: mip - machine interrupt pending
2494 40 zero_gravi
            csr.rdata(03) <= csr.mip_status(interrupt_msw_irq_c);
2495
            csr.rdata(07) <= csr.mip_status(interrupt_mtime_irq_c);
2496
            csr.rdata(11) <= csr.mip_status(interrupt_mext_irq_c);
2497 48 zero_gravi
            for i in 0 to 15 loop -- fast interrupt channels 0..15 pending
2498
              csr.rdata(16+i) <= csr.mip_status(interrupt_firq_0_c+i);
2499
            end loop; -- i
2500 11 zero_gravi
 
2501 37 zero_gravi
          -- physical memory protection - configuration --
2502 42 zero_gravi
          when csr_pmpcfg0_c  => csr.rdata <= csr.pmpcfg_rd(03) & csr.pmpcfg_rd(02) & csr.pmpcfg_rd(01) & csr.pmpcfg_rd(00); -- R/W: pmpcfg0
2503
          when csr_pmpcfg1_c  => csr.rdata <= csr.pmpcfg_rd(07) & csr.pmpcfg_rd(06) & csr.pmpcfg_rd(05) & csr.pmpcfg_rd(04); -- R/W: pmpcfg1
2504
          when csr_pmpcfg2_c  => csr.rdata <= csr.pmpcfg_rd(11) & csr.pmpcfg_rd(10) & csr.pmpcfg_rd(09) & csr.pmpcfg_rd(08); -- R/W: pmpcfg2
2505
          when csr_pmpcfg3_c  => csr.rdata <= csr.pmpcfg_rd(15) & csr.pmpcfg_rd(14) & csr.pmpcfg_rd(13) & csr.pmpcfg_rd(12); -- R/W: pmpcfg3
2506
          when csr_pmpcfg4_c  => csr.rdata <= csr.pmpcfg_rd(19) & csr.pmpcfg_rd(18) & csr.pmpcfg_rd(17) & csr.pmpcfg_rd(16); -- R/W: pmpcfg4
2507
          when csr_pmpcfg5_c  => csr.rdata <= csr.pmpcfg_rd(23) & csr.pmpcfg_rd(22) & csr.pmpcfg_rd(21) & csr.pmpcfg_rd(20); -- R/W: pmpcfg5
2508
          when csr_pmpcfg6_c  => csr.rdata <= csr.pmpcfg_rd(27) & csr.pmpcfg_rd(26) & csr.pmpcfg_rd(25) & csr.pmpcfg_rd(24); -- R/W: pmpcfg6
2509
          when csr_pmpcfg7_c  => csr.rdata <= csr.pmpcfg_rd(31) & csr.pmpcfg_rd(30) & csr.pmpcfg_rd(29) & csr.pmpcfg_rd(28); -- R/W: pmpcfg7
2510
          when csr_pmpcfg8_c  => csr.rdata <= csr.pmpcfg_rd(35) & csr.pmpcfg_rd(34) & csr.pmpcfg_rd(33) & csr.pmpcfg_rd(32); -- R/W: pmpcfg8
2511
          when csr_pmpcfg9_c  => csr.rdata <= csr.pmpcfg_rd(39) & csr.pmpcfg_rd(38) & csr.pmpcfg_rd(37) & csr.pmpcfg_rd(36); -- R/W: pmpcfg9
2512
          when csr_pmpcfg10_c => csr.rdata <= csr.pmpcfg_rd(43) & csr.pmpcfg_rd(42) & csr.pmpcfg_rd(41) & csr.pmpcfg_rd(40); -- R/W: pmpcfg10
2513
          when csr_pmpcfg11_c => csr.rdata <= csr.pmpcfg_rd(47) & csr.pmpcfg_rd(46) & csr.pmpcfg_rd(45) & csr.pmpcfg_rd(44); -- R/W: pmpcfg11
2514
          when csr_pmpcfg12_c => csr.rdata <= csr.pmpcfg_rd(51) & csr.pmpcfg_rd(50) & csr.pmpcfg_rd(49) & csr.pmpcfg_rd(48); -- R/W: pmpcfg12
2515
          when csr_pmpcfg13_c => csr.rdata <= csr.pmpcfg_rd(55) & csr.pmpcfg_rd(54) & csr.pmpcfg_rd(53) & csr.pmpcfg_rd(52); -- R/W: pmpcfg13
2516
          when csr_pmpcfg14_c => csr.rdata <= csr.pmpcfg_rd(59) & csr.pmpcfg_rd(58) & csr.pmpcfg_rd(57) & csr.pmpcfg_rd(56); -- R/W: pmpcfg14
2517
          when csr_pmpcfg15_c => csr.rdata <= csr.pmpcfg_rd(63) & csr.pmpcfg_rd(62) & csr.pmpcfg_rd(61) & csr.pmpcfg_rd(60); -- R/W: pmpcfg15
2518 15 zero_gravi
 
2519 37 zero_gravi
          -- physical memory protection - addresses --
2520 42 zero_gravi
          when csr_pmpaddr0_c  => csr.rdata <= csr.pmpaddr_rd(00); -- R/W: pmpaddr0
2521
          when csr_pmpaddr1_c  => csr.rdata <= csr.pmpaddr_rd(01); -- R/W: pmpaddr1
2522
          when csr_pmpaddr2_c  => csr.rdata <= csr.pmpaddr_rd(02); -- R/W: pmpaddr2
2523
          when csr_pmpaddr3_c  => csr.rdata <= csr.pmpaddr_rd(03); -- R/W: pmpaddr3
2524
          when csr_pmpaddr4_c  => csr.rdata <= csr.pmpaddr_rd(04); -- R/W: pmpaddr4
2525
          when csr_pmpaddr5_c  => csr.rdata <= csr.pmpaddr_rd(05); -- R/W: pmpaddr5
2526
          when csr_pmpaddr6_c  => csr.rdata <= csr.pmpaddr_rd(06); -- R/W: pmpaddr6
2527
          when csr_pmpaddr7_c  => csr.rdata <= csr.pmpaddr_rd(07); -- R/W: pmpaddr7
2528
          when csr_pmpaddr8_c  => csr.rdata <= csr.pmpaddr_rd(08); -- R/W: pmpaddr8
2529
          when csr_pmpaddr9_c  => csr.rdata <= csr.pmpaddr_rd(09); -- R/W: pmpaddr9
2530
          when csr_pmpaddr10_c => csr.rdata <= csr.pmpaddr_rd(10); -- R/W: pmpaddr10
2531
          when csr_pmpaddr11_c => csr.rdata <= csr.pmpaddr_rd(11); -- R/W: pmpaddr11
2532
          when csr_pmpaddr12_c => csr.rdata <= csr.pmpaddr_rd(12); -- R/W: pmpaddr12
2533
          when csr_pmpaddr13_c => csr.rdata <= csr.pmpaddr_rd(13); -- R/W: pmpaddr13
2534
          when csr_pmpaddr14_c => csr.rdata <= csr.pmpaddr_rd(14); -- R/W: pmpaddr14
2535
          when csr_pmpaddr15_c => csr.rdata <= csr.pmpaddr_rd(15); -- R/W: pmpaddr15
2536
          when csr_pmpaddr16_c => csr.rdata <= csr.pmpaddr_rd(16); -- R/W: pmpaddr16
2537
          when csr_pmpaddr17_c => csr.rdata <= csr.pmpaddr_rd(17); -- R/W: pmpaddr17
2538
          when csr_pmpaddr18_c => csr.rdata <= csr.pmpaddr_rd(18); -- R/W: pmpaddr18
2539
          when csr_pmpaddr19_c => csr.rdata <= csr.pmpaddr_rd(19); -- R/W: pmpaddr19
2540
          when csr_pmpaddr20_c => csr.rdata <= csr.pmpaddr_rd(20); -- R/W: pmpaddr20
2541
          when csr_pmpaddr21_c => csr.rdata <= csr.pmpaddr_rd(21); -- R/W: pmpaddr21
2542
          when csr_pmpaddr22_c => csr.rdata <= csr.pmpaddr_rd(22); -- R/W: pmpaddr22
2543
          when csr_pmpaddr23_c => csr.rdata <= csr.pmpaddr_rd(23); -- R/W: pmpaddr23
2544
          when csr_pmpaddr24_c => csr.rdata <= csr.pmpaddr_rd(24); -- R/W: pmpaddr24
2545
          when csr_pmpaddr25_c => csr.rdata <= csr.pmpaddr_rd(25); -- R/W: pmpaddr25
2546
          when csr_pmpaddr26_c => csr.rdata <= csr.pmpaddr_rd(26); -- R/W: pmpaddr26
2547
          when csr_pmpaddr27_c => csr.rdata <= csr.pmpaddr_rd(27); -- R/W: pmpaddr27
2548
          when csr_pmpaddr28_c => csr.rdata <= csr.pmpaddr_rd(28); -- R/W: pmpaddr28
2549
          when csr_pmpaddr29_c => csr.rdata <= csr.pmpaddr_rd(29); -- R/W: pmpaddr29
2550
          when csr_pmpaddr30_c => csr.rdata <= csr.pmpaddr_rd(30); -- R/W: pmpaddr30
2551
          when csr_pmpaddr31_c => csr.rdata <= csr.pmpaddr_rd(31); -- R/W: pmpaddr31
2552
          when csr_pmpaddr32_c => csr.rdata <= csr.pmpaddr_rd(32); -- R/W: pmpaddr32
2553
          when csr_pmpaddr33_c => csr.rdata <= csr.pmpaddr_rd(33); -- R/W: pmpaddr33
2554
          when csr_pmpaddr34_c => csr.rdata <= csr.pmpaddr_rd(34); -- R/W: pmpaddr34
2555
          when csr_pmpaddr35_c => csr.rdata <= csr.pmpaddr_rd(35); -- R/W: pmpaddr35
2556
          when csr_pmpaddr36_c => csr.rdata <= csr.pmpaddr_rd(36); -- R/W: pmpaddr36
2557
          when csr_pmpaddr37_c => csr.rdata <= csr.pmpaddr_rd(37); -- R/W: pmpaddr37
2558
          when csr_pmpaddr38_c => csr.rdata <= csr.pmpaddr_rd(38); -- R/W: pmpaddr38
2559
          when csr_pmpaddr39_c => csr.rdata <= csr.pmpaddr_rd(39); -- R/W: pmpaddr39
2560
          when csr_pmpaddr40_c => csr.rdata <= csr.pmpaddr_rd(40); -- R/W: pmpaddr40
2561
          when csr_pmpaddr41_c => csr.rdata <= csr.pmpaddr_rd(41); -- R/W: pmpaddr41
2562
          when csr_pmpaddr42_c => csr.rdata <= csr.pmpaddr_rd(42); -- R/W: pmpaddr42
2563
          when csr_pmpaddr43_c => csr.rdata <= csr.pmpaddr_rd(43); -- R/W: pmpaddr43
2564
          when csr_pmpaddr44_c => csr.rdata <= csr.pmpaddr_rd(44); -- R/W: pmpaddr44
2565
          when csr_pmpaddr45_c => csr.rdata <= csr.pmpaddr_rd(45); -- R/W: pmpaddr45
2566
          when csr_pmpaddr46_c => csr.rdata <= csr.pmpaddr_rd(46); -- R/W: pmpaddr46
2567
          when csr_pmpaddr47_c => csr.rdata <= csr.pmpaddr_rd(47); -- R/W: pmpaddr47
2568
          when csr_pmpaddr48_c => csr.rdata <= csr.pmpaddr_rd(48); -- R/W: pmpaddr48
2569
          when csr_pmpaddr49_c => csr.rdata <= csr.pmpaddr_rd(49); -- R/W: pmpaddr49
2570
          when csr_pmpaddr50_c => csr.rdata <= csr.pmpaddr_rd(50); -- R/W: pmpaddr50
2571
          when csr_pmpaddr51_c => csr.rdata <= csr.pmpaddr_rd(51); -- R/W: pmpaddr51
2572
          when csr_pmpaddr52_c => csr.rdata <= csr.pmpaddr_rd(52); -- R/W: pmpaddr52
2573
          when csr_pmpaddr53_c => csr.rdata <= csr.pmpaddr_rd(53); -- R/W: pmpaddr53
2574
          when csr_pmpaddr54_c => csr.rdata <= csr.pmpaddr_rd(54); -- R/W: pmpaddr54
2575
          when csr_pmpaddr55_c => csr.rdata <= csr.pmpaddr_rd(55); -- R/W: pmpaddr55
2576
          when csr_pmpaddr56_c => csr.rdata <= csr.pmpaddr_rd(56); -- R/W: pmpaddr56
2577
          when csr_pmpaddr57_c => csr.rdata <= csr.pmpaddr_rd(57); -- R/W: pmpaddr57
2578
          when csr_pmpaddr58_c => csr.rdata <= csr.pmpaddr_rd(58); -- R/W: pmpaddr58
2579
          when csr_pmpaddr59_c => csr.rdata <= csr.pmpaddr_rd(59); -- R/W: pmpaddr59
2580
          when csr_pmpaddr60_c => csr.rdata <= csr.pmpaddr_rd(60); -- R/W: pmpaddr60
2581
          when csr_pmpaddr61_c => csr.rdata <= csr.pmpaddr_rd(61); -- R/W: pmpaddr61
2582
          when csr_pmpaddr62_c => csr.rdata <= csr.pmpaddr_rd(62); -- R/W: pmpaddr62
2583
          when csr_pmpaddr63_c => csr.rdata <= csr.pmpaddr_rd(63); -- R/W: pmpaddr63
2584 15 zero_gravi
 
2585 41 zero_gravi
          -- machine counter setup --
2586
          -- --------------------------------------------------------------------
2587
          when csr_mcountinhibit_c => -- R/W: mcountinhibit - machine counter-inhibit register
2588
            csr.rdata(0) <= csr.mcountinhibit_cy; -- enable auto-increment of [m]cycle[h] counter
2589
            csr.rdata(2) <= csr.mcountinhibit_ir; -- enable auto-increment of [m]instret[h] counter
2590 42 zero_gravi
            csr.rdata(csr.mcountinhibit_hpm'left+3 downto 3) <= csr.mcountinhibit_hpm; -- enable auto-increment of [m]hpmcounterx[h] counter
2591 41 zero_gravi
 
2592 42 zero_gravi
          -- machine performance-monitoring event selector --
2593
          when csr_mhpmevent3_c  => csr.rdata(csr.mhpmevent_rd(00)'left downto 0) <= csr.mhpmevent_rd(00); -- R/W: mhpmevent3
2594
          when csr_mhpmevent4_c  => csr.rdata(csr.mhpmevent_rd(01)'left downto 0) <= csr.mhpmevent_rd(01); -- R/W: mhpmevent4
2595
          when csr_mhpmevent5_c  => csr.rdata(csr.mhpmevent_rd(02)'left downto 0) <= csr.mhpmevent_rd(02); -- R/W: mhpmevent5
2596
          when csr_mhpmevent6_c  => csr.rdata(csr.mhpmevent_rd(03)'left downto 0) <= csr.mhpmevent_rd(03); -- R/W: mhpmevent6
2597
          when csr_mhpmevent7_c  => csr.rdata(csr.mhpmevent_rd(04)'left downto 0) <= csr.mhpmevent_rd(04); -- R/W: mhpmevent7
2598
          when csr_mhpmevent8_c  => csr.rdata(csr.mhpmevent_rd(05)'left downto 0) <= csr.mhpmevent_rd(05); -- R/W: mhpmevent8
2599
          when csr_mhpmevent9_c  => csr.rdata(csr.mhpmevent_rd(06)'left downto 0) <= csr.mhpmevent_rd(06); -- R/W: mhpmevent9
2600
          when csr_mhpmevent10_c => csr.rdata(csr.mhpmevent_rd(07)'left downto 0) <= csr.mhpmevent_rd(07); -- R/W: mhpmevent10
2601
          when csr_mhpmevent11_c => csr.rdata(csr.mhpmevent_rd(08)'left downto 0) <= csr.mhpmevent_rd(08); -- R/W: mhpmevent11
2602
          when csr_mhpmevent12_c => csr.rdata(csr.mhpmevent_rd(09)'left downto 0) <= csr.mhpmevent_rd(09); -- R/W: mhpmevent12
2603
          when csr_mhpmevent13_c => csr.rdata(csr.mhpmevent_rd(10)'left downto 0) <= csr.mhpmevent_rd(10); -- R/W: mhpmevent13
2604
          when csr_mhpmevent14_c => csr.rdata(csr.mhpmevent_rd(11)'left downto 0) <= csr.mhpmevent_rd(11); -- R/W: mhpmevent14
2605
          when csr_mhpmevent15_c => csr.rdata(csr.mhpmevent_rd(12)'left downto 0) <= csr.mhpmevent_rd(12); -- R/W: mhpmevent15
2606
          when csr_mhpmevent16_c => csr.rdata(csr.mhpmevent_rd(13)'left downto 0) <= csr.mhpmevent_rd(13); -- R/W: mhpmevent16
2607
          when csr_mhpmevent17_c => csr.rdata(csr.mhpmevent_rd(14)'left downto 0) <= csr.mhpmevent_rd(14); -- R/W: mhpmevent17
2608
          when csr_mhpmevent18_c => csr.rdata(csr.mhpmevent_rd(15)'left downto 0) <= csr.mhpmevent_rd(15); -- R/W: mhpmevent18
2609
          when csr_mhpmevent19_c => csr.rdata(csr.mhpmevent_rd(16)'left downto 0) <= csr.mhpmevent_rd(16); -- R/W: mhpmevent19
2610
          when csr_mhpmevent20_c => csr.rdata(csr.mhpmevent_rd(17)'left downto 0) <= csr.mhpmevent_rd(17); -- R/W: mhpmevent20
2611
          when csr_mhpmevent21_c => csr.rdata(csr.mhpmevent_rd(18)'left downto 0) <= csr.mhpmevent_rd(18); -- R/W: mhpmevent21
2612
          when csr_mhpmevent22_c => csr.rdata(csr.mhpmevent_rd(19)'left downto 0) <= csr.mhpmevent_rd(19); -- R/W: mhpmevent22
2613
          when csr_mhpmevent23_c => csr.rdata(csr.mhpmevent_rd(20)'left downto 0) <= csr.mhpmevent_rd(20); -- R/W: mhpmevent23
2614
          when csr_mhpmevent24_c => csr.rdata(csr.mhpmevent_rd(21)'left downto 0) <= csr.mhpmevent_rd(21); -- R/W: mhpmevent24
2615
          when csr_mhpmevent25_c => csr.rdata(csr.mhpmevent_rd(22)'left downto 0) <= csr.mhpmevent_rd(22); -- R/W: mhpmevent25
2616
          when csr_mhpmevent26_c => csr.rdata(csr.mhpmevent_rd(23)'left downto 0) <= csr.mhpmevent_rd(23); -- R/W: mhpmevent26
2617
          when csr_mhpmevent27_c => csr.rdata(csr.mhpmevent_rd(24)'left downto 0) <= csr.mhpmevent_rd(24); -- R/W: mhpmevent27
2618
          when csr_mhpmevent28_c => csr.rdata(csr.mhpmevent_rd(25)'left downto 0) <= csr.mhpmevent_rd(25); -- R/W: mhpmevent28
2619
          when csr_mhpmevent29_c => csr.rdata(csr.mhpmevent_rd(26)'left downto 0) <= csr.mhpmevent_rd(26); -- R/W: mhpmevent29
2620
          when csr_mhpmevent30_c => csr.rdata(csr.mhpmevent_rd(27)'left downto 0) <= csr.mhpmevent_rd(27); -- R/W: mhpmevent30
2621
          when csr_mhpmevent31_c => csr.rdata(csr.mhpmevent_rd(28)'left downto 0) <= csr.mhpmevent_rd(28); -- R/W: mhpmevent31
2622
 
2623 29 zero_gravi
          -- counters and timers --
2624 42 zero_gravi
          when csr_cycle_c | csr_mcycle_c => -- (R)/(W): [m]cycle: Cycle counter LOW
2625 27 zero_gravi
            csr.rdata <= csr.mcycle(31 downto 0);
2626 42 zero_gravi
          when csr_time_c => -- (R)/-: time: System time LOW (from MTIME unit)
2627 27 zero_gravi
            csr.rdata <= time_i(31 downto 0);
2628 42 zero_gravi
          when csr_instret_c | csr_minstret_c => -- (R)/(W): [m]instret: Instructions-retired counter LOW
2629 27 zero_gravi
            csr.rdata <= csr.minstret(31 downto 0);
2630 42 zero_gravi
          when csr_cycleh_c | csr_mcycleh_c => -- (R)/(W): [m]cycleh: Cycle counter HIGH
2631 27 zero_gravi
            csr.rdata <= csr.mcycleh(31 downto 0);
2632 42 zero_gravi
          when csr_timeh_c => -- (R)/-: timeh: System time HIGH (from MTIME unit)
2633 27 zero_gravi
            csr.rdata <= time_i(63 downto 32);
2634 42 zero_gravi
          when csr_instreth_c | csr_minstreth_c => -- (R)/(W): [m]instreth: Instructions-retired counter HIGH
2635 27 zero_gravi
            csr.rdata <= csr.minstreth(31 downto 0);
2636 11 zero_gravi
 
2637 42 zero_gravi
          -- hardware performance counters --
2638
          when csr_hpmcounter3_c   | csr_mhpmcounter3_c   => csr.rdata <= csr.mhpmcounter_rd(00)(31 downto 0); -- (R)/(W): [m]hpmcounter3 - low
2639
          when csr_hpmcounter4_c   | csr_mhpmcounter4_c   => csr.rdata <= csr.mhpmcounter_rd(01)(31 downto 0); -- (R)/(W): [m]hpmcounter4 - low
2640
          when csr_hpmcounter5_c   | csr_mhpmcounter5_c   => csr.rdata <= csr.mhpmcounter_rd(02)(31 downto 0); -- (R)/(W): [m]hpmcounter5 - low
2641
          when csr_hpmcounter6_c   | csr_mhpmcounter6_c   => csr.rdata <= csr.mhpmcounter_rd(03)(31 downto 0); -- (R)/(W): [m]hpmcounter6 - low
2642
          when csr_hpmcounter7_c   | csr_mhpmcounter7_c   => csr.rdata <= csr.mhpmcounter_rd(04)(31 downto 0); -- (R)/(W): [m]hpmcounter7 - low
2643
          when csr_hpmcounter8_c   | csr_mhpmcounter8_c   => csr.rdata <= csr.mhpmcounter_rd(05)(31 downto 0); -- (R)/(W): [m]hpmcounter8 - low
2644
          when csr_hpmcounter9_c   | csr_mhpmcounter9_c   => csr.rdata <= csr.mhpmcounter_rd(06)(31 downto 0); -- (R)/(W): [m]hpmcounter9 - low
2645
          when csr_hpmcounter10_c  | csr_mhpmcounter10_c  => csr.rdata <= csr.mhpmcounter_rd(07)(31 downto 0); -- (R)/(W): [m]hpmcounter10 - low
2646
          when csr_hpmcounter11_c  | csr_mhpmcounter11_c  => csr.rdata <= csr.mhpmcounter_rd(08)(31 downto 0); -- (R)/(W): [m]hpmcounter11 - low
2647
          when csr_hpmcounter12_c  | csr_mhpmcounter12_c  => csr.rdata <= csr.mhpmcounter_rd(09)(31 downto 0); -- (R)/(W): [m]hpmcounter12 - low
2648
          when csr_hpmcounter13_c  | csr_mhpmcounter13_c  => csr.rdata <= csr.mhpmcounter_rd(10)(31 downto 0); -- (R)/(W): [m]hpmcounter13 - low
2649
          when csr_hpmcounter14_c  | csr_mhpmcounter14_c  => csr.rdata <= csr.mhpmcounter_rd(11)(31 downto 0); -- (R)/(W): [m]hpmcounter14 - low
2650
          when csr_hpmcounter15_c  | csr_mhpmcounter15_c  => csr.rdata <= csr.mhpmcounter_rd(12)(31 downto 0); -- (R)/(W): [m]hpmcounter15 - low
2651
          when csr_hpmcounter16_c  | csr_mhpmcounter16_c  => csr.rdata <= csr.mhpmcounter_rd(13)(31 downto 0); -- (R)/(W): [m]hpmcounter16 - low
2652
          when csr_hpmcounter17_c  | csr_mhpmcounter17_c  => csr.rdata <= csr.mhpmcounter_rd(14)(31 downto 0); -- (R)/(W): [m]hpmcounter17 - low
2653
          when csr_hpmcounter18_c  | csr_mhpmcounter18_c  => csr.rdata <= csr.mhpmcounter_rd(15)(31 downto 0); -- (R)/(W): [m]hpmcounter18 - low
2654
          when csr_hpmcounter19_c  | csr_mhpmcounter19_c  => csr.rdata <= csr.mhpmcounter_rd(16)(31 downto 0); -- (R)/(W): [m]hpmcounter19 - low
2655
          when csr_hpmcounter20_c  | csr_mhpmcounter20_c  => csr.rdata <= csr.mhpmcounter_rd(17)(31 downto 0); -- (R)/(W): [m]hpmcounter20 - low
2656
          when csr_hpmcounter21_c  | csr_mhpmcounter21_c  => csr.rdata <= csr.mhpmcounter_rd(18)(31 downto 0); -- (R)/(W): [m]hpmcounter21 - low
2657
          when csr_hpmcounter22_c  | csr_mhpmcounter22_c  => csr.rdata <= csr.mhpmcounter_rd(19)(31 downto 0); -- (R)/(W): [m]hpmcounter22 - low
2658
          when csr_hpmcounter23_c  | csr_mhpmcounter23_c  => csr.rdata <= csr.mhpmcounter_rd(20)(31 downto 0); -- (R)/(W): [m]hpmcounter23 - low
2659
          when csr_hpmcounter24_c  | csr_mhpmcounter24_c  => csr.rdata <= csr.mhpmcounter_rd(21)(31 downto 0); -- (R)/(W): [m]hpmcounter24 - low
2660
          when csr_hpmcounter25_c  | csr_mhpmcounter25_c  => csr.rdata <= csr.mhpmcounter_rd(22)(31 downto 0); -- (R)/(W): [m]hpmcounter25 - low
2661
          when csr_hpmcounter26_c  | csr_mhpmcounter26_c  => csr.rdata <= csr.mhpmcounter_rd(23)(31 downto 0); -- (R)/(W): [m]hpmcounter26 - low
2662
          when csr_hpmcounter27_c  | csr_mhpmcounter27_c  => csr.rdata <= csr.mhpmcounter_rd(24)(31 downto 0); -- (R)/(W): [m]hpmcounter27 - low
2663
          when csr_hpmcounter28_c  | csr_mhpmcounter28_c  => csr.rdata <= csr.mhpmcounter_rd(25)(31 downto 0); -- (R)/(W): [m]hpmcounter28 - low
2664
          when csr_hpmcounter29_c  | csr_mhpmcounter29_c  => csr.rdata <= csr.mhpmcounter_rd(26)(31 downto 0); -- (R)/(W): [m]hpmcounter29 - low
2665
          when csr_hpmcounter30_c  | csr_mhpmcounter30_c  => csr.rdata <= csr.mhpmcounter_rd(27)(31 downto 0); -- (R)/(W): [m]hpmcounter30 - low
2666
          when csr_hpmcounter31_c  | csr_mhpmcounter31_c  => csr.rdata <= csr.mhpmcounter_rd(28)(31 downto 0); -- (R)/(W): [m]hpmcounter31 - low
2667
 
2668
          when csr_hpmcounter3h_c  | csr_mhpmcounter3h_c  => csr.rdata <= csr.mhpmcounterh_rd(00)(31 downto 0); -- (R)/(W): [m]hpmcounter3h - high
2669
          when csr_hpmcounter4h_c  | csr_mhpmcounter4h_c  => csr.rdata <= csr.mhpmcounterh_rd(01)(31 downto 0); -- (R)/(W): [m]hpmcounter4h - high
2670
          when csr_hpmcounter5h_c  | csr_mhpmcounter5h_c  => csr.rdata <= csr.mhpmcounterh_rd(02)(31 downto 0); -- (R)/(W): [m]hpmcounter5h - high
2671
          when csr_hpmcounter6h_c  | csr_mhpmcounter6h_c  => csr.rdata <= csr.mhpmcounterh_rd(03)(31 downto 0); -- (R)/(W): [m]hpmcounter6h - high
2672
          when csr_hpmcounter7h_c  | csr_mhpmcounter7h_c  => csr.rdata <= csr.mhpmcounterh_rd(04)(31 downto 0); -- (R)/(W): [m]hpmcounter7h - high
2673
          when csr_hpmcounter8h_c  | csr_mhpmcounter8h_c  => csr.rdata <= csr.mhpmcounterh_rd(05)(31 downto 0); -- (R)/(W): [m]hpmcounter8h - high
2674
          when csr_hpmcounter9h_c  | csr_mhpmcounter9h_c  => csr.rdata <= csr.mhpmcounterh_rd(06)(31 downto 0); -- (R)/(W): [m]hpmcounter9h - high
2675
          when csr_hpmcounter10h_c | csr_mhpmcounter10h_c => csr.rdata <= csr.mhpmcounterh_rd(07)(31 downto 0); -- (R)/(W): [m]hpmcounter10h - high
2676
          when csr_hpmcounter11h_c | csr_mhpmcounter11h_c => csr.rdata <= csr.mhpmcounterh_rd(08)(31 downto 0); -- (R)/(W): [m]hpmcounter11h - high
2677
          when csr_hpmcounter12h_c | csr_mhpmcounter12h_c => csr.rdata <= csr.mhpmcounterh_rd(09)(31 downto 0); -- (R)/(W): [m]hpmcounter12h - high
2678
          when csr_hpmcounter13h_c | csr_mhpmcounter13h_c => csr.rdata <= csr.mhpmcounterh_rd(10)(31 downto 0); -- (R)/(W): [m]hpmcounter13h - high
2679
          when csr_hpmcounter14h_c | csr_mhpmcounter14h_c => csr.rdata <= csr.mhpmcounterh_rd(11)(31 downto 0); -- (R)/(W): [m]hpmcounter14h - high
2680
          when csr_hpmcounter15h_c | csr_mhpmcounter15h_c => csr.rdata <= csr.mhpmcounterh_rd(12)(31 downto 0); -- (R)/(W): [m]hpmcounter15h - high
2681
          when csr_hpmcounter16h_c | csr_mhpmcounter16h_c => csr.rdata <= csr.mhpmcounterh_rd(13)(31 downto 0); -- (R)/(W): [m]hpmcounter16h - high
2682
          when csr_hpmcounter17h_c | csr_mhpmcounter17h_c => csr.rdata <= csr.mhpmcounterh_rd(14)(31 downto 0); -- (R)/(W): [m]hpmcounter17h - high
2683
          when csr_hpmcounter18h_c | csr_mhpmcounter18h_c => csr.rdata <= csr.mhpmcounterh_rd(15)(31 downto 0); -- (R)/(W): [m]hpmcounter18h - high
2684
          when csr_hpmcounter19h_c | csr_mhpmcounter19h_c => csr.rdata <= csr.mhpmcounterh_rd(16)(31 downto 0); -- (R)/(W): [m]hpmcounter19h - high
2685
          when csr_hpmcounter20h_c | csr_mhpmcounter20h_c => csr.rdata <= csr.mhpmcounterh_rd(17)(31 downto 0); -- (R)/(W): [m]hpmcounter20h - high
2686
          when csr_hpmcounter21h_c | csr_mhpmcounter21h_c => csr.rdata <= csr.mhpmcounterh_rd(18)(31 downto 0); -- (R)/(W): [m]hpmcounter21h - high
2687
          when csr_hpmcounter22h_c | csr_mhpmcounter22h_c => csr.rdata <= csr.mhpmcounterh_rd(19)(31 downto 0); -- (R)/(W): [m]hpmcounter22h - high
2688
          when csr_hpmcounter23h_c | csr_mhpmcounter23h_c => csr.rdata <= csr.mhpmcounterh_rd(20)(31 downto 0); -- (R)/(W): [m]hpmcounter23h - high
2689
          when csr_hpmcounter24h_c | csr_mhpmcounter24h_c => csr.rdata <= csr.mhpmcounterh_rd(21)(31 downto 0); -- (R)/(W): [m]hpmcounter24h - high
2690
          when csr_hpmcounter25h_c | csr_mhpmcounter25h_c => csr.rdata <= csr.mhpmcounterh_rd(22)(31 downto 0); -- (R)/(W): [m]hpmcounter25h - high
2691
          when csr_hpmcounter26h_c | csr_mhpmcounter26h_c => csr.rdata <= csr.mhpmcounterh_rd(23)(31 downto 0); -- (R)/(W): [m]hpmcounter26h - high
2692
          when csr_hpmcounter27h_c | csr_mhpmcounter27h_c => csr.rdata <= csr.mhpmcounterh_rd(24)(31 downto 0); -- (R)/(W): [m]hpmcounter27h - high
2693
          when csr_hpmcounter28h_c | csr_mhpmcounter28h_c => csr.rdata <= csr.mhpmcounterh_rd(25)(31 downto 0); -- (R)/(W): [m]hpmcounter28h - high
2694
          when csr_hpmcounter29h_c | csr_mhpmcounter29h_c => csr.rdata <= csr.mhpmcounterh_rd(26)(31 downto 0); -- (R)/(W): [m]hpmcounter29h - high
2695
          when csr_hpmcounter30h_c | csr_mhpmcounter30h_c => csr.rdata <= csr.mhpmcounterh_rd(27)(31 downto 0); -- (R)/(W): [m]hpmcounter30h - high
2696
          when csr_hpmcounter31h_c | csr_mhpmcounter31h_c => csr.rdata <= csr.mhpmcounterh_rd(28)(31 downto 0); -- (R)/(W): [m]hpmcounter31h - high
2697
 
2698 11 zero_gravi
          -- machine information registers --
2699 29 zero_gravi
          when csr_mvendorid_c => -- R/-: mvendorid - vendor ID
2700 27 zero_gravi
            csr.rdata <= (others => '0');
2701 34 zero_gravi
          when csr_marchid_c => -- R/-: marchid - arch ID
2702
            csr.rdata(4 downto 0) <= "10011"; -- official RISC-V open-source arch ID
2703 32 zero_gravi
          when csr_mimpid_c => -- R/-: mimpid - implementation ID
2704
            csr.rdata <= hw_version_c; -- NEORV32 hardware version
2705 29 zero_gravi
          when csr_mhartid_c => -- R/-: mhartid - hardware thread ID
2706 49 zero_gravi
            csr.rdata <= std_ulogic_vector(to_unsigned(HW_THREAD_ID, 32));
2707 11 zero_gravi
 
2708 22 zero_gravi
          -- custom machine read-only CSRs --
2709 44 zero_gravi
          when csr_mzext_c => -- R/-: mzext - available RISC-V Z* extensions
2710
            csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr);    -- Zicsr
2711
            csr.rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Zifencei
2712 49 zero_gravi
            csr.rdata(2) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B);        -- Zbb
2713 51 zero_gravi
            csr.rdata(3) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B);        -- Zbs
2714 22 zero_gravi
 
2715 11 zero_gravi
          -- undefined/unavailable --
2716
          when others =>
2717 27 zero_gravi
            csr.rdata <= (others => '0'); -- not implemented
2718 11 zero_gravi
 
2719
        end case;
2720 2 zero_gravi
      end if;
2721
    end if;
2722
  end process csr_read_access;
2723
 
2724 27 zero_gravi
  -- CSR read data output --
2725
  csr_rdata_o <= csr.rdata;
2726
 
2727 12 zero_gravi
 
2728 2 zero_gravi
end neorv32_cpu_control_rtl;

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