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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_control.vhd] - Blame information for rev 68

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1 2 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - CPU Control >>                                                                   #
3
-- # ********************************************************************************************* #
4 31 zero_gravi
-- # CPU operation is split into a fetch engine (responsible for fetching instruction data), an    #
5
-- # issue engine (for recoding compressed instructions and for constructing 32-bit instruction    #
6
-- # words) and an execute engine (responsible for actually executing the instructions), a trap    #
7 44 zero_gravi
-- # handling controller and the RISC-V status and control register set (CSRs) including the       #
8
-- # hardware performance monitor counters.                                                        #
9 2 zero_gravi
-- # ********************************************************************************************* #
10
-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
12 42 zero_gravi
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
13 2 zero_gravi
-- #                                                                                               #
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-- # Redistribution and use in source and binary forms, with or without modification, are          #
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-- # permitted provided that the following conditions are met:                                     #
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-- #                                                                                               #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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-- #    conditions and the following disclaimer.                                                   #
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-- #                                                                                               #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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-- #    conditions and the following disclaimer in the documentation and/or other materials        #
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-- #    provided with the distribution.                                                            #
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-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
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-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
39
-- #################################################################################################
40
 
41
library ieee;
42
use ieee.std_logic_1164.all;
43
use ieee.numeric_std.all;
44
 
45
library neorv32;
46
use neorv32.neorv32_package.all;
47
 
48
entity neorv32_cpu_control is
49
  generic (
50
    -- General --
51 62 zero_gravi
    HW_THREAD_ID                 : natural; -- hardware thread id (32-bit)
52
    CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0); -- cpu boot address
53
    CPU_DEBUG_ADDR               : std_ulogic_vector(31 downto 0); -- cpu debug mode start address
54 2 zero_gravi
    -- RISC-V CPU Extensions --
55 62 zero_gravi
    CPU_EXTENSION_RISCV_A        : boolean; -- implement atomic extension?
56 66 zero_gravi
    CPU_EXTENSION_RISCV_B        : boolean; -- implement bit-manipulation extension?
57 62 zero_gravi
    CPU_EXTENSION_RISCV_C        : boolean; -- implement compressed extension?
58
    CPU_EXTENSION_RISCV_E        : boolean; -- implement embedded RF extension?
59 66 zero_gravi
    CPU_EXTENSION_RISCV_M        : boolean; -- implement mul/div extension?
60 62 zero_gravi
    CPU_EXTENSION_RISCV_U        : boolean; -- implement user mode extension?
61
    CPU_EXTENSION_RISCV_Zfinx    : boolean; -- implement 32-bit floating-point extension (using INT reg!)
62
    CPU_EXTENSION_RISCV_Zicsr    : boolean; -- implement CSR system?
63 66 zero_gravi
    CPU_EXTENSION_RISCV_Zicntr   : boolean; -- implement base counters?
64
    CPU_EXTENSION_RISCV_Zihpm    : boolean; -- implement hardware performance monitors?
65 62 zero_gravi
    CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
66
    CPU_EXTENSION_RISCV_Zmmul    : boolean; -- implement multiply-only M sub-extension?
67
    CPU_EXTENSION_RISCV_DEBUG    : boolean; -- implement CPU debug mode?
68 56 zero_gravi
    -- Extension Options --
69 62 zero_gravi
    CPU_CNT_WIDTH                : natural; -- total width of CPU cycle and instret counters (0..64)
70
    CPU_IPB_ENTRIES              : natural; -- entries is instruction prefetch buffer, has to be a power of 2
71 15 zero_gravi
    -- Physical memory protection (PMP) --
72 62 zero_gravi
    PMP_NUM_REGIONS              : natural; -- number of regions (0..64)
73
    PMP_MIN_GRANULARITY          : natural; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
74 42 zero_gravi
    -- Hardware Performance Monitors (HPM) --
75 62 zero_gravi
    HPM_NUM_CNTS                 : natural; -- number of implemented HPM counters (0..29)
76
    HPM_CNT_WIDTH                : natural  -- total size of HPM counters (0..64)
77 2 zero_gravi
  );
78
  port (
79
    -- global control --
80
    clk_i         : in  std_ulogic; -- global clock, rising edge
81
    rstn_i        : in  std_ulogic; -- global reset, low-active, async
82
    ctrl_o        : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
83
    -- status input --
84 61 zero_gravi
    alu_idone_i   : in  std_ulogic; -- ALU iterative operation done
85 12 zero_gravi
    bus_i_wait_i  : in  std_ulogic; -- wait for bus
86
    bus_d_wait_i  : in  std_ulogic; -- wait for bus
87 57 zero_gravi
    excl_state_i  : in  std_ulogic; -- atomic/exclusive access lock status
88 2 zero_gravi
    -- data input --
89
    instr_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- instruction
90
    cmp_i         : in  std_ulogic_vector(1 downto 0); -- comparator status
91 36 zero_gravi
    alu_add_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result
92
    rs1_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
93 2 zero_gravi
    -- data output --
94
    imm_o         : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
95 6 zero_gravi
    fetch_pc_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
96
    curr_pc_o     : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
97 68 zero_gravi
    next_pc_o     : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to next instruction)
98 2 zero_gravi
    csr_rdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
99 52 zero_gravi
    -- FPU interface --
100
    fpu_flags_i   : in  std_ulogic_vector(04 downto 0); -- exception flags
101 59 zero_gravi
    -- debug mode (halt) request --
102
    db_halt_req_i : in  std_ulogic;
103 14 zero_gravi
    -- interrupts (risc-v compliant) --
104
    msw_irq_i     : in  std_ulogic; -- machine software interrupt
105
    mext_irq_i    : in  std_ulogic; -- machine external interrupt
106 2 zero_gravi
    mtime_irq_i   : in  std_ulogic; -- machine timer interrupt
107 14 zero_gravi
    -- fast interrupts (custom) --
108 48 zero_gravi
    firq_i        : in  std_ulogic_vector(15 downto 0);
109 11 zero_gravi
    -- system time input from MTIME --
110
    time_i        : in  std_ulogic_vector(63 downto 0); -- current system time
111 15 zero_gravi
    -- physical memory protection --
112 23 zero_gravi
    pmp_addr_o    : out pmp_addr_if_t; -- addresses
113
    pmp_ctrl_o    : out pmp_ctrl_if_t; -- configs
114 2 zero_gravi
    -- bus access exceptions --
115 66 zero_gravi
    mar_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
116 2 zero_gravi
    ma_instr_i    : in  std_ulogic; -- misaligned instruction address
117
    ma_load_i     : in  std_ulogic; -- misaligned load data address
118
    ma_store_i    : in  std_ulogic; -- misaligned store data address
119
    be_instr_i    : in  std_ulogic; -- bus error on instruction access
120
    be_load_i     : in  std_ulogic; -- bus error on load data access
121 12 zero_gravi
    be_store_i    : in  std_ulogic  -- bus error on store data access
122 2 zero_gravi
  );
123
end neorv32_cpu_control;
124
 
125
architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
126
 
127 56 zero_gravi
  -- CPU core counter ([m]cycle, [m]instret) width - high/low parts --
128
  constant cpu_cnt_lo_width_c : natural := natural(cond_sel_int_f(boolean(CPU_CNT_WIDTH < 32), CPU_CNT_WIDTH, 32));
129
  constant cpu_cnt_hi_width_c : natural := natural(cond_sel_int_f(boolean(CPU_CNT_WIDTH > 32), CPU_CNT_WIDTH-32, 0));
130
 
131
  -- HPM counter width - high/low parts --
132
  constant hpm_cnt_lo_width_c : natural := natural(cond_sel_int_f(boolean(HPM_CNT_WIDTH < 32), HPM_CNT_WIDTH, 32));
133
  constant hpm_cnt_hi_width_c : natural := natural(cond_sel_int_f(boolean(HPM_CNT_WIDTH > 32), HPM_CNT_WIDTH-32, 0));
134
 
135 57 zero_gravi
  -- instruction fetch engine --
136
  type fetch_engine_state_t is (IFETCH_REQUEST, IFETCH_ISSUE);
137 6 zero_gravi
  type fetch_engine_t is record
138 31 zero_gravi
    state       : fetch_engine_state_t;
139
    state_nxt   : fetch_engine_state_t;
140 42 zero_gravi
    state_prev  : fetch_engine_state_t;
141 57 zero_gravi
    restart     : std_ulogic;
142
    restart_nxt : std_ulogic;
143 31 zero_gravi
    pc          : std_ulogic_vector(data_width_c-1 downto 0);
144
    pc_nxt      : std_ulogic_vector(data_width_c-1 downto 0);
145
    reset       : std_ulogic;
146
    bus_err_ack : std_ulogic;
147 6 zero_gravi
  end record;
148
  signal fetch_engine : fetch_engine_t;
149 2 zero_gravi
 
150 61 zero_gravi
  -- instruction prefetch buffer (FIFO) interface --
151 6 zero_gravi
  type ipb_t is record
152 31 zero_gravi
    wdata : std_ulogic_vector(2+31 downto 0); -- write status (bus_error, align_error) + 32-bit instruction data
153
    we    : std_ulogic; -- trigger write
154
    free  : std_ulogic; -- free entry available?
155
    clear : std_ulogic; -- clear all entries
156 20 zero_gravi
    --
157 31 zero_gravi
    rdata : std_ulogic_vector(2+31 downto 0); -- read data: status (bus_error, align_error) + 32-bit instruction data
158
    re    : std_ulogic; -- read enable
159
    avail : std_ulogic; -- data available?
160 6 zero_gravi
  end record;
161
  signal ipb : ipb_t;
162 2 zero_gravi
 
163 31 zero_gravi
  -- pre-decoder --
164
  signal ci_instr16 : std_ulogic_vector(15 downto 0);
165
  signal ci_instr32 : std_ulogic_vector(31 downto 0);
166
  signal ci_illegal : std_ulogic;
167
 
168 57 zero_gravi
  -- instruction issue engine --
169 31 zero_gravi
  type issue_engine_state_t is (ISSUE_ACTIVE, ISSUE_REALIGN);
170
  type issue_engine_t is record
171
    state     : issue_engine_state_t;
172
    state_nxt : issue_engine_state_t;
173
    align     : std_ulogic;
174
    align_nxt : std_ulogic;
175
    buf       : std_ulogic_vector(2+15 downto 0);
176
    buf_nxt   : std_ulogic_vector(2+15 downto 0);
177
  end record;
178
  signal issue_engine : issue_engine_t;
179
 
180 37 zero_gravi
  -- instruction issue interface --
181
  type cmd_issue_t is record
182
    data  : std_ulogic_vector(35 downto 0); -- 4-bit status + 32-bit instruction
183
    valid : std_ulogic; -- data word is valid when set
184 31 zero_gravi
  end record;
185 37 zero_gravi
  signal cmd_issue : cmd_issue_t;
186 31 zero_gravi
 
187 44 zero_gravi
  -- instruction decoding helper logic --
188
  type decode_aux_t is record
189 63 zero_gravi
    is_atomic_lr    : std_ulogic;
190
    is_atomic_sc    : std_ulogic;
191
    is_float_op     : std_ulogic;
192
    sys_env_cmd     : std_ulogic_vector(11 downto 0);
193
    is_m_mul        : std_ulogic;
194
    is_m_div        : std_ulogic;
195
    is_bitmanip_imm : std_ulogic;
196
    is_bitmanip_reg : std_ulogic;
197 68 zero_gravi
    rs1_zero        : std_ulogic;
198
    rs2_zero        : std_ulogic;
199
    rd_zero         : std_ulogic;
200 44 zero_gravi
  end record;
201
  signal decode_aux : decode_aux_t;
202
 
203 6 zero_gravi
  -- instruction execution engine --
204 66 zero_gravi
  type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP_ENTER, TRAP_EXIT, TRAP_EXECUTE, EXECUTE, ALU_WAIT,
205
                                  BRANCH, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, SYS_ENV, CSR_ACCESS);
206 6 zero_gravi
  type execute_engine_t is record
207
    state        : execute_engine_state_t;
208
    state_nxt    : execute_engine_state_t;
209 42 zero_gravi
    state_prev   : execute_engine_state_t;
210 39 zero_gravi
    --
211 6 zero_gravi
    i_reg        : std_ulogic_vector(31 downto 0);
212
    i_reg_nxt    : std_ulogic_vector(31 downto 0);
213 33 zero_gravi
    i_reg_last   : std_ulogic_vector(31 downto 0); -- last executed instruction
214 39 zero_gravi
    --
215 6 zero_gravi
    is_ci        : std_ulogic; -- current instruction is de-compressed instruction
216
    is_ci_nxt    : std_ulogic;
217 66 zero_gravi
    is_ici       : std_ulogic; -- current instruction is illegal de-compressed instruction
218
    is_ici_nxt   : std_ulogic;
219 39 zero_gravi
    --
220 57 zero_gravi
    branch_taken : std_ulogic; -- branch condition fulfilled
221 6 zero_gravi
    pc           : std_ulogic_vector(data_width_c-1 downto 0); -- actual PC, corresponding to current executed instruction
222 49 zero_gravi
    pc_mux_sel   : std_ulogic; -- source select for PC update
223 39 zero_gravi
    pc_we        : std_ulogic; -- PC update enabled
224 6 zero_gravi
    next_pc      : std_ulogic_vector(data_width_c-1 downto 0); -- next PC, corresponding to next instruction to be executed
225 49 zero_gravi
    next_pc_inc  : std_ulogic_vector(data_width_c-1 downto 0); -- increment to get next PC
226 6 zero_gravi
    last_pc      : std_ulogic_vector(data_width_c-1 downto 0); -- PC of last executed instruction
227 39 zero_gravi
    --
228 11 zero_gravi
    sleep        : std_ulogic; -- CPU in sleep mode
229 39 zero_gravi
    sleep_nxt    : std_ulogic;
230 49 zero_gravi
    branched     : std_ulogic; -- instruction fetch was reset
231
    branched_nxt : std_ulogic;
232 6 zero_gravi
  end record;
233
  signal execute_engine : execute_engine_t;
234 2 zero_gravi
 
235 6 zero_gravi
  -- trap controller --
236
  type trap_ctrl_t is record
237
    exc_buf       : std_ulogic_vector(exception_width_c-1 downto 0);
238
    exc_fire      : std_ulogic; -- set if there is a valid source in the exception buffer
239
    irq_buf       : std_ulogic_vector(interrupt_width_c-1 downto 0);
240
    irq_fire      : std_ulogic; -- set if there is a valid source in the interrupt buffer
241
    exc_ack       : std_ulogic; -- acknowledge all exceptions
242 59 zero_gravi
    cause         : std_ulogic_vector(6 downto 0); -- trap ID for mcause CSR
243
    cause_nxt     : std_ulogic_vector(6 downto 0);
244
    db_irq_fire   : std_ulogic; -- set if there is a valid IRQ source in the "enter debug mode" trap buffer
245 63 zero_gravi
    db_irq_en     : std_ulogic; -- set if IRQs are allowed in debug mode
246 6 zero_gravi
    --
247
    env_start     : std_ulogic; -- start trap handler env
248
    env_start_ack : std_ulogic; -- start of trap handler acknowledged
249
    env_end       : std_ulogic; -- end trap handler env
250
    --
251
    instr_be      : std_ulogic; -- instruction fetch bus error
252
    instr_ma      : std_ulogic; -- instruction fetch misaligned address
253
    instr_il      : std_ulogic; -- illegal instruction
254
    env_call      : std_ulogic;
255
    break_point   : std_ulogic;
256
  end record;
257
  signal trap_ctrl : trap_ctrl_t;
258
 
259 40 zero_gravi
  -- CPU main control bus --
260 6 zero_gravi
  signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
261 2 zero_gravi
 
262 40 zero_gravi
  -- fast instruction fetch access --
263 6 zero_gravi
  signal bus_fast_ir : std_ulogic;
264 2 zero_gravi
 
265 6 zero_gravi
  -- RISC-V control and status registers (CSRs) --
266 42 zero_gravi
  type pmp_ctrl_t     is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(7 downto 0);
267
  type pmp_addr_t     is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
268
  type pmp_ctrl_rd_t  is array (0 to 63) of std_ulogic_vector(7 downto 0);
269
  type mhpmevent_t    is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
270 61 zero_gravi
  type mhpmcnt_t      is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(31 downto 0);
271
  type mhpmcnt_nxt_t  is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(32 downto 0);
272
  type mhpmcnt_ovfl_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(0 downto 0);
273 56 zero_gravi
  type mhpmcnt_rd_t   is array (0 to 29) of std_ulogic_vector(31 downto 0);
274 6 zero_gravi
  type csr_t is record
275 42 zero_gravi
    addr              : std_ulogic_vector(11 downto 0); -- csr address
276
    we                : std_ulogic; -- csr write enable
277
    we_nxt            : std_ulogic;
278
    wdata             : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data
279
    rdata             : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
280 29 zero_gravi
    --
281 42 zero_gravi
    mstatus_mie       : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
282
    mstatus_mpie      : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/W)
283
    mstatus_mpp       : std_ulogic_vector(1 downto 0); -- mstatus.MPP: machine previous privilege mode
284 29 zero_gravi
    --
285 42 zero_gravi
    mie_msie          : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
286
    mie_meie          : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
287
    mie_mtie          : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)
288 48 zero_gravi
    mie_firqe         : std_ulogic_vector(15 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)
289 29 zero_gravi
    --
290 42 zero_gravi
    mcounteren_cy     : std_ulogic; -- mcounteren.cy: allow cycle[h] access from user-mode
291
    mcounteren_tm     : std_ulogic; -- mcounteren.tm: allow time[h] access from user-mode
292
    mcounteren_ir     : std_ulogic; -- mcounteren.ir: allow instret[h] access from user-mode
293 29 zero_gravi
    --
294 42 zero_gravi
    mcountinhibit_cy  : std_ulogic; -- mcounterinhibit.cy: enable auto-increment for [m]cycle[h]
295
    mcountinhibit_ir  : std_ulogic; -- mcounterinhibit.ir: enable auto-increment for [m]instret[h]
296
    mcountinhibit_hpm : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0); -- mcounterinhibit.hpm3: enable auto-increment for mhpmcounterx[h]
297 40 zero_gravi
    --
298 42 zero_gravi
    privilege         : std_ulogic_vector(1 downto 0); -- hart's current privilege mode
299 59 zero_gravi
    privilege_rd      : std_ulogic_vector(1 downto 0); -- hart's current privilege mode (effective)
300 42 zero_gravi
    priv_m_mode       : std_ulogic; -- CPU in M-mode
301
    priv_u_mode       : std_ulogic; -- CPU in u-mode
302 41 zero_gravi
    --
303 42 zero_gravi
    mepc              : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)
304 49 zero_gravi
    mcause            : std_ulogic_vector(5 downto 0); -- mcause: machine trap cause (R/W)
305 42 zero_gravi
    mtvec             : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00
306 49 zero_gravi
    mtval             : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or instruction (R/W)
307 42 zero_gravi
    --
308
    mhpmevent         : mhpmevent_t; -- mhpmevent*: machine performance-monitoring event selector (R/W)
309
    --
310
    mscratch          : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
311 56 zero_gravi
    --
312 61 zero_gravi
    mcycle            : std_ulogic_vector(31 downto 0); -- mcycle (R/W)
313
    mcycle_nxt        : std_ulogic_vector(32 downto 0);
314
    mcycle_ovfl       : std_ulogic_vector(00 downto 0); -- counter low-to-high-word overflow
315 60 zero_gravi
    mcycleh           : std_ulogic_vector(31 downto 0); -- mcycleh (R/W)
316 61 zero_gravi
    minstret          : std_ulogic_vector(31 downto 0); -- minstret (R/W)
317
    minstret_nxt      : std_ulogic_vector(32 downto 0);
318
    minstret_ovfl     : std_ulogic_vector(00 downto 0); -- counter low-to-high-word overflow
319 42 zero_gravi
    minstreth         : std_ulogic_vector(31 downto 0); -- minstreth (R/W)
320
    --
321
    mhpmcounter       : mhpmcnt_t; -- mhpmcounter* (R/W), plus carry bit
322 61 zero_gravi
    mhpmcounter_nxt   : mhpmcnt_nxt_t;
323
    mhpmcounter_ovfl  : mhpmcnt_ovfl_t; -- counter low-to-high-word overflow
324
    mhpmcounterh      : mhpmcnt_t; -- mhpmcounter*h (R/W)
325 42 zero_gravi
    mhpmcounter_rd    : mhpmcnt_rd_t; -- mhpmcounter* (R/W): actual read data
326 61 zero_gravi
    mhpmcounterh_rd   : mhpmcnt_rd_t; -- mhpmcounter*h (R/W): actual read data
327 42 zero_gravi
    --
328
    pmpcfg            : pmp_ctrl_t; -- physical memory protection - configuration registers
329
    pmpcfg_rd         : pmp_ctrl_rd_t; -- physical memory protection - actual read data
330
    pmpaddr           : pmp_addr_t; -- physical memory protection - address registers
331 52 zero_gravi
    --
332
    frm               : std_ulogic_vector(02 downto 0); -- frm (R/W): FPU rounding mode
333
    fflags            : std_ulogic_vector(04 downto 0); -- fflags (R/W): FPU exception flags
334 59 zero_gravi
    --
335
    dcsr_ebreakm      : std_ulogic; -- dcsr.ebreakm (R/W): behavior of ebreak instruction on m-mode
336
    dcsr_ebreaku      : std_ulogic; -- dcsr.ebreaku (R/W): behavior of ebreak instruction on u-mode
337
    dcsr_step         : std_ulogic; -- dcsr.step (R/W): single-step mode
338
    dcsr_prv          : std_ulogic_vector(01 downto 0); -- dcsr.prv (R/W): current privilege level when entering debug mode
339
    dcsr_cause        : std_ulogic_vector(02 downto 0); -- dcsr.cause (R/-): why was debug mode entered
340
    dcsr_rd           : std_ulogic_vector(data_width_c-1 downto 0); -- dcsr (R/(W)): debug mode control and status register
341
    dpc               : std_ulogic_vector(data_width_c-1 downto 0); -- dpc (R/W): debug mode program counter
342
    dscratch0         : std_ulogic_vector(data_width_c-1 downto 0); -- dscratch0 (R/W): debug mode scratch register 0
343 6 zero_gravi
  end record;
344
  signal csr : csr_t;
345 2 zero_gravi
 
346 59 zero_gravi
  -- debug mode controller --
347
  type debug_ctrl_state_t is (DEBUG_OFFLINE, DEBUG_PENDING, DEBUG_ONLINE, DEBUG_EXIT);
348
  type debug_ctrl_t is record
349
    state        : debug_ctrl_state_t;
350
    -- decoded state --
351
    running      : std_ulogic; -- debug mode active
352
    pending      : std_ulogic; -- waiting to start debug mode
353
    -- entering triggers --
354
    trig_break   : std_ulogic; -- ebreak instruction
355
    trig_halt    : std_ulogic; -- external request
356
    trig_step    : std_ulogic; -- single-stepping mode
357
    -- leave debug mode --
358
    dret         : std_ulogic; -- executed DRET instruction
359
    -- misc --
360 64 zero_gravi
    ext_halt_req : std_ulogic;
361 59 zero_gravi
  end record;
362
  signal debug_ctrl : debug_ctrl_t;
363
 
364 42 zero_gravi
  -- (hpm) counter events --
365 68 zero_gravi
  signal cnt_event      : std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
366
  signal hpmcnt_trigger : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0);
367 42 zero_gravi
 
368 6 zero_gravi
  -- illegal instruction check --
369 66 zero_gravi
  signal illegal_opcode_lsbs : std_ulogic; -- opcode != rv32
370 2 zero_gravi
  signal illegal_instruction : std_ulogic;
371 66 zero_gravi
  signal illegal_register    : std_ulogic; -- illegal register (>x15) - E-extension
372
  signal illegal_compressed  : std_ulogic; -- illegal compressed instruction - C-extension
373 2 zero_gravi
 
374 15 zero_gravi
  -- access (privilege) check --
375
  signal csr_acc_valid : std_ulogic; -- valid CSR access (implemented and valid access rights)
376
 
377 2 zero_gravi
begin
378
 
379 6 zero_gravi
-- ****************************************************************************************************************************
380 56 zero_gravi
-- Instruction Fetch (always fetch 32-bit-aligned 32-bit chunks of data)
381 6 zero_gravi
-- ****************************************************************************************************************************
382
 
383
  -- Fetch Engine FSM Sync ------------------------------------------------------------------
384
  -- -------------------------------------------------------------------------------------------
385 31 zero_gravi
  fetch_engine_fsm_sync: process(rstn_i, clk_i)
386 6 zero_gravi
  begin
387
    if (rstn_i = '0') then
388 57 zero_gravi
      fetch_engine.state      <= IFETCH_REQUEST;
389
      fetch_engine.state_prev <= IFETCH_REQUEST;
390
      fetch_engine.restart    <= '1';
391 56 zero_gravi
      fetch_engine.pc         <= (others => def_rst_val_c);
392 6 zero_gravi
    elsif rising_edge(clk_i) then
393 57 zero_gravi
      fetch_engine.state      <= fetch_engine.state_nxt;
394
      fetch_engine.state_prev <= fetch_engine.state;
395
      fetch_engine.restart    <= fetch_engine.restart_nxt;
396
      if (fetch_engine.restart = '1') then
397
        fetch_engine.pc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC
398 6 zero_gravi
      else
399 57 zero_gravi
        fetch_engine.pc <= fetch_engine.pc_nxt;
400 6 zero_gravi
      end if;
401
    end if;
402
  end process fetch_engine_fsm_sync;
403
 
404 12 zero_gravi
  -- PC output --
405 31 zero_gravi
  fetch_pc_o <= fetch_engine.pc(data_width_c-1 downto 1) & '0'; -- half-word aligned
406 6 zero_gravi
 
407 12 zero_gravi
 
408 6 zero_gravi
  -- Fetch Engine FSM Comb ------------------------------------------------------------------
409
  -- -------------------------------------------------------------------------------------------
410 31 zero_gravi
  fetch_engine_fsm_comb: process(fetch_engine, execute_engine, ipb, instr_i, bus_i_wait_i, be_instr_i, ma_instr_i)
411 6 zero_gravi
  begin
412
    -- arbiter defaults --
413 31 zero_gravi
    bus_fast_ir              <= '0';
414
    fetch_engine.state_nxt   <= fetch_engine.state;
415
    fetch_engine.pc_nxt      <= fetch_engine.pc;
416
    fetch_engine.bus_err_ack <= '0';
417 57 zero_gravi
    fetch_engine.restart_nxt <= fetch_engine.restart or fetch_engine.reset;
418 6 zero_gravi
 
419
    -- instruction prefetch buffer interface --
420
    ipb.we    <= '0';
421 31 zero_gravi
    ipb.wdata <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store exception info and instruction word
422 57 zero_gravi
    ipb.clear <= fetch_engine.restart;
423 6 zero_gravi
 
424
    -- state machine --
425
    case fetch_engine.state is
426
 
427 57 zero_gravi
      when IFETCH_REQUEST => -- request new 32-bit-aligned instruction word
428 6 zero_gravi
      -- ------------------------------------------------------------
429 57 zero_gravi
        if (ipb.free = '1') and (fetch_engine.restart = '0') then -- free entry in buffer AND no reset request?
430 31 zero_gravi
          bus_fast_ir            <= '1'; -- fast instruction fetch request
431
          fetch_engine.state_nxt <= IFETCH_ISSUE;
432
        end if;
433 57 zero_gravi
        if (fetch_engine.restart = '1') then -- reset request?
434
          fetch_engine.restart_nxt <= '0';
435
        end if;
436 6 zero_gravi
 
437 31 zero_gravi
      when IFETCH_ISSUE => -- store instruction data to prefetch buffer
438 6 zero_gravi
      -- ------------------------------------------------------------
439 41 zero_gravi
        fetch_engine.bus_err_ack <= be_instr_i or ma_instr_i; -- ACK bus/alignment errors
440 12 zero_gravi
        if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
441 57 zero_gravi
          fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4);
442
          ipb.we              <= not fetch_engine.restart; -- write to IPB if not being reset
443
          if (fetch_engine.restart = '1') then -- reset request?
444
            fetch_engine.restart_nxt <= '0';
445
          end if;
446 39 zero_gravi
          fetch_engine.state_nxt <= IFETCH_REQUEST;
447 6 zero_gravi
        end if;
448 11 zero_gravi
 
449 6 zero_gravi
      when others => -- undefined
450
      -- ------------------------------------------------------------
451 57 zero_gravi
        fetch_engine.state_nxt <= IFETCH_REQUEST;
452 6 zero_gravi
 
453
    end case;
454
  end process fetch_engine_fsm_comb;
455
 
456
 
457
-- ****************************************************************************************************************************
458
-- Instruction Prefetch Buffer
459
-- ****************************************************************************************************************************
460
 
461 20 zero_gravi
  -- Instruction Prefetch Buffer (FIFO) -----------------------------------------------------
462 6 zero_gravi
  -- -------------------------------------------------------------------------------------------
463 61 zero_gravi
  instr_prefetch_buffer: neorv32_fifo
464
  generic map (
465 62 zero_gravi
    FIFO_DEPTH => CPU_IPB_ENTRIES,  -- number of fifo entries; has to be a power of two; min 1
466 61 zero_gravi
    FIFO_WIDTH => ipb.wdata'length, -- size of data elements in fifo
467
    FIFO_RSYNC => false,            -- we NEED to read data asynchronously
468
    FIFO_SAFE  => false             -- no safe access required (ensured by FIFO-external control)
469
  )
470
  port map (
471
    -- control --
472
    clk_i   => clk_i,     -- clock, rising edge
473
    rstn_i  => '1',       -- async reset, low-active
474
    clear_i => ipb.clear, -- sync reset, high-active
475 65 zero_gravi
    level_o => open,
476
    half_o  => open,
477 61 zero_gravi
    -- write port --
478
    wdata_i => ipb.wdata, -- write data
479
    we_i    => ipb.we,    -- write enable
480
    free_o  => ipb.free,  -- at least one entry is free when set
481
    -- read port --
482
    re_i    => ipb.re,    -- read enable
483
    rdata_o => ipb.rdata, -- read data
484
    avail_o => ipb.avail  -- data available when set
485
  );
486 20 zero_gravi
 
487 56 zero_gravi
 
488 6 zero_gravi
-- ****************************************************************************************************************************
489 31 zero_gravi
-- Instruction Issue (recoding of compressed instructions and 32-bit instruction word construction)
490
-- ****************************************************************************************************************************
491
 
492
  -- Issue Engine FSM Sync ------------------------------------------------------------------
493
  -- -------------------------------------------------------------------------------------------
494
  issue_engine_fsm_sync: process(rstn_i, clk_i)
495
  begin
496
    if (rstn_i = '0') then
497
      issue_engine.state <= ISSUE_ACTIVE;
498 40 zero_gravi
      issue_engine.align <= CPU_BOOT_ADDR(1); -- 32- or 16-bit boundary
499 66 zero_gravi
      issue_engine.buf   <= (others => '0');
500 31 zero_gravi
    elsif rising_edge(clk_i) then
501
      if (ipb.clear = '1') then
502 68 zero_gravi
        if (CPU_EXTENSION_RISCV_C = true) and (execute_engine.pc(1) = '1') then -- branch to unaligned address?
503
          issue_engine.state <= ISSUE_REALIGN;
504
          issue_engine.align <= '1'; -- aligned on 16-bit boundary
505 31 zero_gravi
        else
506
          issue_engine.state <= issue_engine.state_nxt;
507
          issue_engine.align <= '0'; -- always aligned on 32-bit boundaries
508
        end if;
509
      else
510
        issue_engine.state <= issue_engine.state_nxt;
511
        issue_engine.align <= issue_engine.align_nxt;
512
      end if;
513
      issue_engine.buf <= issue_engine.buf_nxt;
514
    end if;
515
  end process issue_engine_fsm_sync;
516
 
517
 
518
  -- Issue Engine FSM Comb ------------------------------------------------------------------
519
  -- -------------------------------------------------------------------------------------------
520 37 zero_gravi
  issue_engine_fsm_comb: process(issue_engine, ipb, execute_engine, ci_illegal, ci_instr32)
521 31 zero_gravi
  begin
522
    -- arbiter defaults --
523
    issue_engine.state_nxt <= issue_engine.state;
524
    issue_engine.align_nxt <= issue_engine.align;
525
    issue_engine.buf_nxt   <= issue_engine.buf;
526
 
527
    -- instruction prefetch buffer interface defaults --
528
    ipb.re <= '0';
529
 
530 37 zero_gravi
    -- instruction issue interface defaults --
531
    -- cmd_issue.data = <illegal_compressed_instruction> & <bus_error & alignment_error> & <is_compressed_instrucion> & <32-bit_instruction_word>
532
    cmd_issue.data  <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);
533
    cmd_issue.valid <= '0';
534 31 zero_gravi
 
535
    -- state machine --
536
    case issue_engine.state is
537
 
538
      when ISSUE_ACTIVE => -- issue instruction if available
539
      -- ------------------------------------------------------------
540
        if (ipb.avail = '1') then -- instructions available?
541
 
542
          if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word
543 41 zero_gravi
            if (execute_engine.state = DISPATCH) then -- ready to issue new command?
544 39 zero_gravi
              cmd_issue.valid      <= '1';
545 31 zero_gravi
              issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction
546
              if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed and "aligned"
547 37 zero_gravi
                ipb.re <= '1';
548
                cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);
549 31 zero_gravi
              else -- compressed
550 37 zero_gravi
                ipb.re <= '1';
551
                cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
552 31 zero_gravi
                issue_engine.align_nxt <= '1';
553
              end if;
554
            end if;
555
 
556
          else -- begin check in HIGH instruction half-word
557 41 zero_gravi
            if (execute_engine.state = DISPATCH) then -- ready to issue new command?
558 39 zero_gravi
              cmd_issue.valid      <= '1';
559 31 zero_gravi
              issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction
560
              if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and "unaligned"
561 37 zero_gravi
                ipb.re <= '1';
562 66 zero_gravi
                cmd_issue.data <= '0' & (ipb.rdata(33 downto 32) or issue_engine.buf(17 downto 16)) & '0' & (ipb.rdata(15 downto 0) & issue_engine.buf(15 downto 0));
563 31 zero_gravi
              else -- compressed
564 36 zero_gravi
                -- do not read from ipb here!
565 37 zero_gravi
                cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
566 31 zero_gravi
                issue_engine.align_nxt <= '0';
567
              end if;
568
            end if;
569
          end if;
570
        end if;
571
 
572
      when ISSUE_REALIGN => -- re-align input fifos after a branch to an unaligned address
573
      -- ------------------------------------------------------------
574
        issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16);
575
        if (ipb.avail = '1') then -- instructions available?
576
          ipb.re <= '1';
577
          issue_engine.state_nxt <= ISSUE_ACTIVE;
578
        end if;
579
 
580
      when others => -- undefined
581
      -- ------------------------------------------------------------
582
        issue_engine.state_nxt <= ISSUE_ACTIVE;
583
 
584
    end case;
585
  end process issue_engine_fsm_comb;
586
 
587 41 zero_gravi
  -- 16-bit instructions: half-word select --
588 31 zero_gravi
  ci_instr16 <= ipb.rdata(15 downto 0) when (issue_engine.align = '0') else issue_engine.buf(15 downto 0);
589
 
590
 
591
  -- Compressed Instructions Recoding -------------------------------------------------------
592
  -- -------------------------------------------------------------------------------------------
593
  neorv32_cpu_decompressor_inst_true:
594
  if (CPU_EXTENSION_RISCV_C = true) generate
595
    neorv32_cpu_decompressor_inst: neorv32_cpu_decompressor
596
    port map (
597
      -- instruction input --
598
      ci_instr16_i => ci_instr16, -- compressed instruction input
599
      -- instruction output --
600
      ci_illegal_o => ci_illegal, -- is an illegal compressed instruction
601
      ci_instr32_o => ci_instr32  -- 32-bit decompressed instruction
602
    );
603
  end generate;
604
 
605
  neorv32_cpu_decompressor_inst_false:
606
  if (CPU_EXTENSION_RISCV_C = false) generate
607
    ci_instr32 <= (others => '0');
608
    ci_illegal <= '0';
609
  end generate;
610
 
611
 
612
-- ****************************************************************************************************************************
613 6 zero_gravi
-- Instruction Execution
614
-- ****************************************************************************************************************************
615
 
616 2 zero_gravi
  -- Immediate Generator --------------------------------------------------------------------
617
  -- -------------------------------------------------------------------------------------------
618 62 zero_gravi
  imm_gen: process(rstn_i, clk_i)
619 37 zero_gravi
    variable opcode_v : std_ulogic_vector(6 downto 0);
620 2 zero_gravi
  begin
621 56 zero_gravi
    if (rstn_i = '0') then
622
      imm_o <= (others => def_rst_val_c);
623
    elsif rising_edge(clk_i) then
624 68 zero_gravi
      -- default: I-immediate: ALU-immediate, loads, jump-and-link with registers
625
      imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
626
      imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
627
      imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
628
      imm_o(00)           <= execute_engine.i_reg(20);
629
 
630
      opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11";
631
      case opcode_v is -- save some bits here, the two LSBs are always "11" for rv32
632
        when opcode_store_c => -- S-immediate: store
633
          imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
634
          imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
635
          imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
636
          imm_o(00)           <= execute_engine.i_reg(07);
637
        when opcode_branch_c => -- B-immediate: conditional branches
638
          imm_o(31 downto 12) <= (others => execute_engine.i_reg(31)); -- sign extension
639
          imm_o(11)           <= execute_engine.i_reg(07);
640
          imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
641
          imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
642
          imm_o(00)           <= '0';
643
        when opcode_lui_c | opcode_auipc_c => -- U-immediate: lui, auipc
644
          imm_o(31 downto 20) <= execute_engine.i_reg(31 downto 20);
645
          imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);
646
          imm_o(11 downto 00) <= (others => '0');
647
        when opcode_jal_c => -- J-immediate: unconditional jumps
648
          imm_o(31 downto 20) <= (others => execute_engine.i_reg(31)); -- sign extension
649
          imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);
650
          imm_o(11)           <= execute_engine.i_reg(20);
651
          imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
652
          imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
653
          imm_o(00)           <= '0';
654
        when opcode_atomic_c => -- atomic memory access and everything else
655
          if (CPU_EXTENSION_RISCV_A = true) then
656
            imm_o <= (others => '0'); -- effective address is addr = reg + 0 = reg
657
          else
658
            NULL; -- use default
659
          end if;
660
        when others => -- I-immediate
661
          NULL; -- use default
662
      end case;
663 2 zero_gravi
    end if;
664
  end process imm_gen;
665
 
666
 
667
  -- Branch Condition Check -----------------------------------------------------------------
668
  -- -------------------------------------------------------------------------------------------
669 6 zero_gravi
  branch_check: process(execute_engine.i_reg, cmp_i)
670 2 zero_gravi
  begin
671 6 zero_gravi
    case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
672 2 zero_gravi
      when funct3_beq_c => -- branch if equal
673 47 zero_gravi
        execute_engine.branch_taken <= cmp_i(cmp_equal_c);
674 2 zero_gravi
      when funct3_bne_c => -- branch if not equal
675 47 zero_gravi
        execute_engine.branch_taken <= not cmp_i(cmp_equal_c);
676 2 zero_gravi
      when funct3_blt_c | funct3_bltu_c => -- branch if less (signed/unsigned)
677 47 zero_gravi
        execute_engine.branch_taken <= cmp_i(cmp_less_c);
678 2 zero_gravi
      when funct3_bge_c | funct3_bgeu_c => -- branch if greater or equal (signed/unsigned)
679 47 zero_gravi
        execute_engine.branch_taken <= not cmp_i(cmp_less_c);
680 66 zero_gravi
      when others => -- invalid
681 6 zero_gravi
        execute_engine.branch_taken <= '0';
682 2 zero_gravi
    end case;
683
  end process branch_check;
684
 
685
 
686 6 zero_gravi
  -- Execute Engine FSM Sync ----------------------------------------------------------------
687 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
688 56 zero_gravi
  execute_engine_fsm_sync: process(rstn_i, clk_i)
689 2 zero_gravi
  begin
690
    if (rstn_i = '0') then
691 56 zero_gravi
      -- registers that DO require a specific reset state --
692 68 zero_gravi
      execute_engine.pc         <= CPU_BOOT_ADDR(data_width_c-1 downto 2) & "00"; -- 32-bit aligned!
693
      execute_engine.state      <= SYS_WAIT;
694
      execute_engine.sleep      <= '0';
695
      execute_engine.branched   <= '1'; -- reset is a branch from "somewhere"
696 57 zero_gravi
      -- no dedicated RESET required --
697 62 zero_gravi
      execute_engine.state_prev <= SYS_WAIT; -- actual reset value is not relevant
698 56 zero_gravi
      execute_engine.i_reg      <= (others => def_rst_val_c);
699
      execute_engine.is_ci      <= def_rst_val_c;
700 66 zero_gravi
      execute_engine.is_ici     <= def_rst_val_c;
701 56 zero_gravi
      execute_engine.last_pc    <= (others => def_rst_val_c);
702
      execute_engine.i_reg_last <= (others => def_rst_val_c);
703
      execute_engine.next_pc    <= (others => def_rst_val_c);
704
      ctrl                      <= (others => def_rst_val_c);
705
      ctrl(ctrl_bus_rd_c)       <= '0';
706
      ctrl(ctrl_bus_wr_c)       <= '0';
707 2 zero_gravi
    elsif rising_edge(clk_i) then
708 39 zero_gravi
      -- PC update --
709
      if (execute_engine.pc_we = '1') then
710 49 zero_gravi
        if (execute_engine.pc_mux_sel = '0') then
711 58 zero_gravi
          execute_engine.pc <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- normal (linear) increment OR trap enter/exit
712 49 zero_gravi
        else
713
          execute_engine.pc <= alu_add_i(data_width_c-1 downto 1) & '0'; -- jump/taken_branch
714
        end if;
715 39 zero_gravi
      end if;
716 68 zero_gravi
 
717
      execute_engine.state      <= execute_engine.state_nxt;
718 42 zero_gravi
      execute_engine.state_prev <= execute_engine.state;
719 68 zero_gravi
      execute_engine.sleep      <= execute_engine.sleep_nxt;
720
      execute_engine.branched   <= execute_engine.branched_nxt;
721 42 zero_gravi
      execute_engine.i_reg      <= execute_engine.i_reg_nxt;
722
      execute_engine.is_ci      <= execute_engine.is_ci_nxt;
723 66 zero_gravi
      execute_engine.is_ici     <= execute_engine.is_ici_nxt;
724 59 zero_gravi
 
725 66 zero_gravi
      -- PC & IR of "last executed" instruction for trap handling --
726 40 zero_gravi
      if (execute_engine.state = EXECUTE) then
727
        execute_engine.last_pc    <= execute_engine.pc;
728 39 zero_gravi
        execute_engine.i_reg_last <= execute_engine.i_reg;
729
      end if;
730 59 zero_gravi
 
731 49 zero_gravi
      -- next PC --
732
      case execute_engine.state is
733 68 zero_gravi
        when TRAP_ENTER => -- ENTERING trap environment
734 59 zero_gravi
          if (CPU_EXTENSION_RISCV_DEBUG = false) then -- normal trapping
735
            execute_engine.next_pc <= csr.mtvec(data_width_c-1 downto 1) & '0'; -- trap enter
736
          else -- DEBUG MODE enabled
737
            if (trap_ctrl.cause(5) = '1') then -- trap cause: debug mode (re-)entry
738
              execute_engine.next_pc <= CPU_DEBUG_ADDR; -- debug mode enter; start at "parking loop" <normal_entry>
739
            elsif (debug_ctrl.running = '1') then -- any other exception INSIDE debug mode
740
              execute_engine.next_pc <= std_ulogic_vector(unsigned(CPU_DEBUG_ADDR) + 4); -- execute at "parking loop" <exception_entry>
741
            else -- normal trapping
742
              execute_engine.next_pc <= csr.mtvec(data_width_c-1 downto 1) & '0'; -- trap enter
743
            end if;
744
          end if;
745 68 zero_gravi
        when TRAP_EXIT => -- LEAVING trap environment
746 59 zero_gravi
          if (CPU_EXTENSION_RISCV_DEBUG = false) or (debug_ctrl.running = '0') then -- normal end of trap
747
            execute_engine.next_pc <= csr.mepc(data_width_c-1 downto 1) & '0'; -- trap exit
748
          else -- DEBUG MODE exiting
749
            execute_engine.next_pc <= csr.dpc(data_width_c-1 downto 1) & '0'; -- debug mode exit
750
          end if;
751 68 zero_gravi
        when EXECUTE => -- NORMAL pc increment
752 59 zero_gravi
          execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc) + unsigned(execute_engine.next_pc_inc)); -- next linear PC
753
        when others =>
754
          NULL;
755 49 zero_gravi
      end case;
756 59 zero_gravi
 
757 39 zero_gravi
      -- main control bus --
758 6 zero_gravi
      ctrl <= ctrl_nxt;
759 2 zero_gravi
    end if;
760 6 zero_gravi
  end process execute_engine_fsm_sync;
761 2 zero_gravi
 
762 56 zero_gravi
 
763 49 zero_gravi
  -- PC increment for next linear instruction (+2 for compressed instr., +4 otherwise) --
764
  execute_engine.next_pc_inc <= x"00000004" when ((execute_engine.is_ci = '0') or (CPU_EXTENSION_RISCV_C = false)) else x"00000002";
765 41 zero_gravi
 
766 20 zero_gravi
  -- PC output --
767 68 zero_gravi
  curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1)      & '0'; -- current PC for ALU ops
768
  next_pc_o <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- next PC for ALU ops
769 6 zero_gravi
 
770 49 zero_gravi
  -- CSR access address --
771
  csr.addr <= execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c);
772 20 zero_gravi
 
773 49 zero_gravi
 
774 6 zero_gravi
  -- CPU Control Bus Output -----------------------------------------------------------------
775
  -- -------------------------------------------------------------------------------------------
776 60 zero_gravi
  ctrl_output: process(ctrl, fetch_engine, trap_ctrl, bus_fast_ir, execute_engine, csr, debug_ctrl)
777 2 zero_gravi
  begin
778 36 zero_gravi
    -- signals from execute engine --
779 2 zero_gravi
    ctrl_o <= ctrl;
780 65 zero_gravi
    -- prevent commits if illegal instruction --
781
    ctrl_o(ctrl_rf_wb_en_c) <= ctrl(ctrl_rf_wb_en_c) and (not trap_ctrl.exc_buf(exception_iillegal_c));
782
    ctrl_o(ctrl_bus_rd_c)   <= ctrl(ctrl_bus_rd_c)   and (not trap_ctrl.exc_buf(exception_iillegal_c));
783
    ctrl_o(ctrl_bus_wr_c)   <= ctrl(ctrl_bus_wr_c)   and (not trap_ctrl.exc_buf(exception_iillegal_c));
784 36 zero_gravi
    -- current privilege level --
785 59 zero_gravi
    ctrl_o(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) <= csr.privilege_rd;
786 36 zero_gravi
    -- register addresses --
787 40 zero_gravi
    ctrl_o(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c);
788
    ctrl_o(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c);
789
    ctrl_o(ctrl_rf_rd_adr4_c  downto ctrl_rf_rd_adr0_c)  <= execute_engine.i_reg(instr_rd_msb_c  downto instr_rd_lsb_c);
790 12 zero_gravi
    -- fast bus access requests --
791 36 zero_gravi
    ctrl_o(ctrl_bus_if_c) <= bus_fast_ir;
792 12 zero_gravi
    -- bus error control --
793 47 zero_gravi
    ctrl_o(ctrl_bus_ierr_ack_c) <= fetch_engine.bus_err_ack; -- instruction fetch bus access error ACK
794
    ctrl_o(ctrl_bus_derr_ack_c) <= trap_ctrl.env_start_ack; -- data access bus error access ACK
795
    -- memory access size / sign --
796
    ctrl_o(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU)
797
    ctrl_o(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c); -- mem transfer size
798
    -- alu.shifter --
799
    ctrl_o(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction (left/right)
800
    ctrl_o(ctrl_alu_shift_ar_c)  <= execute_engine.i_reg(30); -- is arithmetic shift
801 36 zero_gravi
    -- instruction's function blocks (for co-processors) --
802 44 zero_gravi
    ctrl_o(ctrl_ir_opcode7_6_c  downto ctrl_ir_opcode7_0_c) <= execute_engine.i_reg(instr_opcode_msb_c  downto instr_opcode_lsb_c);
803 36 zero_gravi
    ctrl_o(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_0_c) <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c);
804
    ctrl_o(ctrl_ir_funct3_2_c   downto ctrl_ir_funct3_0_c)  <= execute_engine.i_reg(instr_funct3_msb_c  downto instr_funct3_lsb_c);
805 47 zero_gravi
    -- cpu status --
806 64 zero_gravi
    ctrl_o(ctrl_sleep_c)         <= execute_engine.sleep; -- cpu is in sleep mode
807
    ctrl_o(ctrl_trap_c)          <= trap_ctrl.env_start_ack; -- cpu is starting a trap handler
808
    ctrl_o(ctrl_debug_running_c) <= debug_ctrl.running; -- cpu is currently in debug mode
809 61 zero_gravi
    -- FPU rounding mode --
810
    ctrl_o(ctrl_alu_frm2_c downto ctrl_alu_frm0_c) <= csr.frm;
811 6 zero_gravi
  end process ctrl_output;
812 2 zero_gravi
 
813
 
814 44 zero_gravi
  -- Decoding Helper Logic ------------------------------------------------------------------
815
  -- -------------------------------------------------------------------------------------------
816
  decode_helper: process(execute_engine)
817 49 zero_gravi
    variable sys_env_cmd_mask_v : std_ulogic_vector(11 downto 0);
818 44 zero_gravi
  begin
819
    -- defaults --
820 63 zero_gravi
    decode_aux.is_atomic_lr    <= '0';
821
    decode_aux.is_atomic_sc    <= '0';
822
    decode_aux.is_float_op     <= '0';
823
    decode_aux.is_m_mul        <= '0';
824
    decode_aux.is_m_div        <= '0';
825
    decode_aux.is_bitmanip_imm <= '0';
826
    decode_aux.is_bitmanip_reg <= '0';
827 68 zero_gravi
    decode_aux.rs1_zero        <= '0';
828
    decode_aux.rs2_zero        <= '0';
829
    decode_aux.rd_zero         <= '0';
830 44 zero_gravi
 
831
    -- is atomic load-reservate/store-conditional? --
832 68 zero_gravi
    if (CPU_EXTENSION_RISCV_A = true) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') then -- valid atomic sub-opcode
833 44 zero_gravi
      decode_aux.is_atomic_lr <= not execute_engine.i_reg(instr_funct5_lsb_c);
834
      decode_aux.is_atomic_sc <=     execute_engine.i_reg(instr_funct5_lsb_c);
835
    end if;
836
 
837 63 zero_gravi
    -- is BITMANIP instruction? --
838
    -- pretty complex as we have to extract this from the ALU/ALUI instruction space --
839
    -- immediate operation --
840
    if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001") and
841
         (
842
          (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00000") or -- CLZ
843
          (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00001") or -- CTZ
844
          (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00010") or -- CPOP
845
          (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00100") or -- SEXT.B
846
          (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00101")    -- SEXT.H
847
         )
848
       ) or
849
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- RORI
850
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00111")) or -- ORCB
851
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "11000")) then -- REV8
852 68 zero_gravi
      decode_aux.is_bitmanip_imm <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- BITMANIP implemented at all?
853 63 zero_gravi
    end if;
854
    -- register operation --
855
    if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c-1 downto instr_funct3_lsb_c) = "01")) or -- ROR / ROL
856
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c) = '1')) or -- MIN[U] / MAX[U]
857
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100")) or -- ZEXTH
858
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100000") and
859
        (
860
         (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "111") or -- ANDN
861
         (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "110") or -- ORN
862
         (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100")    -- XORN
863
        )
864 66 zero_gravi
       ) or
865
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010000") and
866
        (
867
         (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010") or -- SH1ADD
868
         (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100") or -- SH2ADD
869
         (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "110")    -- SH3ADD
870
        )
871 63 zero_gravi
       ) then
872 68 zero_gravi
      decode_aux.is_bitmanip_reg <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- BITMANIP implemented at all?
873 63 zero_gravi
    end if;
874
 
875 53 zero_gravi
    -- floating-point operations (Zfinx) --
876
    if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+3) = "0000")) or -- FADD.S / FSUB.S
877 52 zero_gravi
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00010")) or -- FMUL.S
878 53 zero_gravi
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- FCLASS.S
879 52 zero_gravi
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00100") and (execute_engine.i_reg(instr_funct3_msb_c) = '0')) or -- FSGNJ[N/X].S
880
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_msb_c-1) = "00")) or -- FMIN.S / FMAX.S
881
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "10100") and (execute_engine.i_reg(instr_funct3_msb_c) = '0')) or -- FEQ.S / FLT.S / FLE.S
882 53 zero_gravi
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11010") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c+1) = "0000")) or -- FCVT.S.W*
883 52 zero_gravi
       ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11000") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c+1) = "0000")) then -- FCVT.W*.S
884 68 zero_gravi
      decode_aux.is_float_op <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- FPU implemented at all?
885 52 zero_gravi
    end if;
886
 
887 49 zero_gravi
    -- system/environment instructions --
888 59 zero_gravi
    sys_env_cmd_mask_v := funct12_ecall_c or funct12_ebreak_c or funct12_mret_c or funct12_wfi_c or funct12_dret_c; -- sum-up set bits
889 60 zero_gravi
    decode_aux.sys_env_cmd <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) and sys_env_cmd_mask_v; -- set unused bits to always-zero
890 61 zero_gravi
 
891
    -- integer MUL (M/Zmmul) / DIV (M) operation --
892
    if (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and
893
       (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then
894 68 zero_gravi
      decode_aux.is_m_mul <= (not execute_engine.i_reg(instr_funct3_msb_c)) and (bool_to_ulogic_f(CPU_EXTENSION_RISCV_M) or bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zmmul));
895
      decode_aux.is_m_div <= execute_engine.i_reg(instr_funct3_msb_c) and bool_to_ulogic_f(CPU_EXTENSION_RISCV_M);
896 61 zero_gravi
    end if;
897 68 zero_gravi
 
898
    -- register address checks --
899
    decode_aux.rs1_zero <= not or_reduce_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c));
900
    decode_aux.rs2_zero <= not or_reduce_f(execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c));
901
    decode_aux.rd_zero  <= not or_reduce_f(execute_engine.i_reg(instr_rd_msb_c  downto instr_rd_lsb_c));
902 44 zero_gravi
  end process decode_helper;
903
 
904
 
905 6 zero_gravi
  -- Execute Engine FSM Comb ----------------------------------------------------------------
906
  -- -------------------------------------------------------------------------------------------
907 61 zero_gravi
  execute_engine_fsm_comb: process(execute_engine, debug_ctrl, trap_ctrl, decode_aux, fetch_engine, cmd_issue,
908 65 zero_gravi
                                   csr, ctrl, alu_idone_i, bus_d_wait_i, excl_state_i)
909 44 zero_gravi
    variable opcode_v : std_ulogic_vector(6 downto 0);
910 2 zero_gravi
  begin
911
    -- arbiter defaults --
912 29 zero_gravi
    execute_engine.state_nxt    <= execute_engine.state;
913
    execute_engine.i_reg_nxt    <= execute_engine.i_reg;
914
    execute_engine.is_ci_nxt    <= execute_engine.is_ci;
915 66 zero_gravi
    execute_engine.is_ici_nxt   <= '0';
916 29 zero_gravi
    execute_engine.sleep_nxt    <= execute_engine.sleep;
917 49 zero_gravi
    execute_engine.branched_nxt <= execute_engine.branched;
918 39 zero_gravi
    --
919 49 zero_gravi
    execute_engine.pc_mux_sel   <= '0';
920 39 zero_gravi
    execute_engine.pc_we        <= '0';
921 2 zero_gravi
 
922 6 zero_gravi
    -- instruction dispatch --
923 37 zero_gravi
    fetch_engine.reset          <= '0';
924 2 zero_gravi
 
925 6 zero_gravi
    -- trap environment control --
926 37 zero_gravi
    trap_ctrl.env_start_ack     <= '0';
927
    trap_ctrl.env_end           <= '0';
928 6 zero_gravi
 
929 59 zero_gravi
    -- leave debug mode --
930
    debug_ctrl.dret             <= '0';
931
 
932 2 zero_gravi
    -- exception trigger --
933 37 zero_gravi
    trap_ctrl.instr_be          <= '0';
934
    trap_ctrl.instr_ma          <= '0';
935
    trap_ctrl.env_call          <= '0';
936
    trap_ctrl.break_point       <= '0';
937 2 zero_gravi
 
938 6 zero_gravi
    -- CSR access --
939 37 zero_gravi
    csr.we_nxt                  <= '0';
940 6 zero_gravi
 
941 39 zero_gravi
    -- CONTROL DEFAULTS --
942 36 zero_gravi
    ctrl_nxt <= (others => '0'); -- default: all off
943 47 zero_gravi
    -- ALU main control --
944 68 zero_gravi
    ctrl_nxt(ctrl_alu_op2_c   downto ctrl_alu_op0_c)   <= alu_op_add_c;    -- default ALU operation: ADD
945
    ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_core_c; -- default ALU operation: ADD
946 47 zero_gravi
    -- ALU sign control --
947 6 zero_gravi
    if (execute_engine.i_reg(instr_opcode_lsb_c+4) = '1') then -- ALU ops
948 36 zero_gravi
      ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation? (SLTIU, SLTU)
949 2 zero_gravi
    else -- branches
950 36 zero_gravi
      ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches? (BLTU, BGEU)
951 2 zero_gravi
    end if;
952 68 zero_gravi
    -- atomic store-conditional instruction (evaluate lock status) --
953
    ctrl_nxt(ctrl_bus_ch_lock_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A) and decode_aux.is_atomic_sc;
954 2 zero_gravi
 
955
 
956 6 zero_gravi
    -- state machine --
957
    case execute_engine.state is
958 2 zero_gravi
 
959 62 zero_gravi
      when SYS_WAIT => -- System delay cycle (to let side effects kick in)
960 2 zero_gravi
      -- ------------------------------------------------------------
961 6 zero_gravi
        execute_engine.state_nxt <= DISPATCH;
962 2 zero_gravi
 
963 39 zero_gravi
 
964 37 zero_gravi
      when DISPATCH => -- Get new command from instruction issue engine
965 25 zero_gravi
      -- ------------------------------------------------------------
966 49 zero_gravi
        -- PC update --
967
        execute_engine.pc_mux_sel <= '0'; -- linear next PC
968 40 zero_gravi
        -- IR update --
969 49 zero_gravi
        execute_engine.is_ci_nxt <= cmd_issue.data(32); -- flag to indicate a de-compressed instruction
970
        execute_engine.i_reg_nxt <= cmd_issue.data(31 downto 0);
971 40 zero_gravi
        --
972 37 zero_gravi
        if (cmd_issue.valid = '1') then -- instruction available?
973 49 zero_gravi
          -- PC update --
974
          execute_engine.branched_nxt <= '0';
975
          execute_engine.pc_we        <= not execute_engine.branched; -- update PC with linear next_pc if there was no actual branch
976 40 zero_gravi
          -- IR update - exceptions --
977 68 zero_gravi
          trap_ctrl.instr_ma        <= cmd_issue.data(33) and (not bool_to_ulogic_f(CPU_EXTENSION_RISCV_C)); -- misaligned instruction fetch address, if C disabled
978 66 zero_gravi
          trap_ctrl.instr_be        <= cmd_issue.data(34); -- bus access fault during instruction fetch
979
          execute_engine.is_ici_nxt <= cmd_issue.data(35); -- invalid decompressed instruction
980 40 zero_gravi
          -- any reason to go to trap state? --
981 68 zero_gravi
          if (execute_engine.sleep = '1') or -- enter sleep state
982 66 zero_gravi
             (trap_ctrl.exc_fire = '1') or -- exception during LAST instruction (illegal instruction)
983 61 zero_gravi
             (trap_ctrl.env_start = '1') or -- pending trap (IRQ or exception)
984 68 zero_gravi
             ((cmd_issue.data(33) = '1') and (CPU_EXTENSION_RISCV_C = false)) or -- misaligned instruction fetch address, if C disabled
985
             (cmd_issue.data(34) = '1') then -- bus access fault during instruction fetch
986 49 zero_gravi
            execute_engine.state_nxt <= TRAP_ENTER;
987 13 zero_gravi
          else
988 14 zero_gravi
            execute_engine.state_nxt <= EXECUTE;
989 13 zero_gravi
          end if;
990
        end if;
991 2 zero_gravi
 
992 39 zero_gravi
 
993 63 zero_gravi
      when TRAP_ENTER => -- Start trap environment - get xTVEC, stay here for sleep mode
994 2 zero_gravi
      -- ------------------------------------------------------------
995 34 zero_gravi
        if (trap_ctrl.env_start = '1') then -- trap triggered?
996 61 zero_gravi
          trap_ctrl.env_start_ack  <= '1';
997
          execute_engine.state_nxt <= TRAP_EXECUTE;
998 2 zero_gravi
        end if;
999
 
1000 68 zero_gravi
 
1001 63 zero_gravi
      when TRAP_EXIT => -- Return from trap environment - get xEPC
1002 49 zero_gravi
      -- ------------------------------------------------------------
1003
        trap_ctrl.env_end        <= '1';
1004
        execute_engine.state_nxt <= TRAP_EXECUTE;
1005 39 zero_gravi
 
1006 68 zero_gravi
 
1007
      when TRAP_EXECUTE => -- Process trap environment -> jump to xTVEC / return from trap environment -> jump to xEPC
1008 49 zero_gravi
      -- ------------------------------------------------------------
1009 60 zero_gravi
        execute_engine.pc_mux_sel <= '0'; -- next_PC
1010 49 zero_gravi
        fetch_engine.reset        <= '1';
1011
        execute_engine.pc_we      <= '1';
1012
        execute_engine.sleep_nxt  <= '0'; -- disable sleep mode
1013
        execute_engine.state_nxt  <= SYS_WAIT;
1014
 
1015
 
1016 60 zero_gravi
      when EXECUTE => -- Decode and execute instruction (control has to be here for exactly 1 cycle in any case!)
1017 2 zero_gravi
      -- ------------------------------------------------------------
1018 36 zero_gravi
        opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; -- save some bits here, LSBs are always 11 for rv32
1019
        case opcode_v is
1020 2 zero_gravi
 
1021 60 zero_gravi
          when opcode_alu_c | opcode_alui_c => -- (register/immediate) ALU operation
1022 2 zero_gravi
          -- ------------------------------------------------------------
1023 68 zero_gravi
            ctrl_nxt(ctrl_alu_opb_mux_c) <= not execute_engine.i_reg(instr_opcode_msb_c-1); -- use IMM as ALU.OPB for immediate operations
1024 25 zero_gravi
 
1025 68 zero_gravi
            -- ALU core operation --
1026 39 zero_gravi
            case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is -- actual ALU.logic operation (re-coding)
1027 68 zero_gravi
              when funct3_subadd_c => -- ADD(I)/SUB
1028
                if ((execute_engine.i_reg(instr_opcode_msb_c-1) = '1') and (execute_engine.i_reg(instr_funct7_msb_c-1) = '1')) then -- not an immediate op and funct7.6 set => SUB
1029
                  ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_sub_c;
1030
                else
1031
                  ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_add_c;
1032
                end if;
1033
              when funct3_slt_c | funct3_sltu_c => -- SLT(I), SLTU(I)
1034
                ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_slt_c;
1035
              when funct3_xor_c => -- XOR(I)
1036
                ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_xor_c;
1037
              when funct3_or_c => -- OR(I)
1038
                ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_or_c;
1039
              when others => -- AND(I), multi-cycle / co-processor operations
1040
                ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_and_c;
1041 39 zero_gravi
            end case;
1042
 
1043 68 zero_gravi
            -- Check if single-cycle or multi-cycle (co-processor) operation --
1044 44 zero_gravi
            -- co-processor MULDIV operation? --
1045 61 zero_gravi
            if ((CPU_EXTENSION_RISCV_M = true) and ((decode_aux.is_m_mul = '1') or (decode_aux.is_m_div = '1'))) or -- MUL/DIV
1046
               ((CPU_EXTENSION_RISCV_Zmmul = true) and (decode_aux.is_m_mul = '1')) then -- MUL
1047 44 zero_gravi
              ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- use MULDIV CP
1048 68 zero_gravi
              ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
1049
              execute_engine.state_nxt                           <= ALU_WAIT;
1050
            -- co-processor BIT-MANIPULATION operation? --
1051 66 zero_gravi
            elsif (CPU_EXTENSION_RISCV_B = true) and
1052 68 zero_gravi
                  (((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5))  and (decode_aux.is_bitmanip_reg = '1')) or -- register operation
1053
                   ((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_bitmanip_imm = '1'))) then -- immediate operation
1054 63 zero_gravi
              ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_bitmanip_c; -- use BITMANIP CP
1055 68 zero_gravi
              ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
1056
              execute_engine.state_nxt                           <= ALU_WAIT;
1057
            -- co-processor SHIFT operation? --
1058
            elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or
1059
                  (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) then
1060
              ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_shifter_c; -- use SHIFTER CP (only relevant for shift operations)
1061
              ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
1062
              execute_engine.state_nxt                           <= ALU_WAIT;
1063
            -- ALU core operations (single-cycle) --
1064 61 zero_gravi
            else
1065 68 zero_gravi
              ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_core_c;
1066
              ctrl_nxt(ctrl_rf_wb_en_c)                          <= '1'; -- valid RF write-back
1067
              execute_engine.state_nxt                           <= DISPATCH;
1068 39 zero_gravi
            end if;
1069
 
1070 2 zero_gravi
 
1071 25 zero_gravi
          when opcode_lui_c | opcode_auipc_c => -- load upper immediate / add upper immediate to PC
1072 2 zero_gravi
          -- ------------------------------------------------------------
1073 27 zero_gravi
            ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- ALU.OPA = PC (for AUIPC only)
1074
            ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB
1075 25 zero_gravi
            if (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_lui_c(5)) then -- LUI
1076 68 zero_gravi
              ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_movb_c; -- actual ALU operation = MOVB
1077 27 zero_gravi
            else -- AUIPC
1078 68 zero_gravi
              ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_add_c; -- actual ALU operation = ADD
1079 2 zero_gravi
            end if;
1080 68 zero_gravi
            ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
1081
            execute_engine.state_nxt  <= DISPATCH;
1082 2 zero_gravi
 
1083 68 zero_gravi
 
1084 53 zero_gravi
          when opcode_load_c | opcode_store_c | opcode_atomic_c => -- load/store / atomic memory access
1085 2 zero_gravi
          -- ------------------------------------------------------------
1086 66 zero_gravi
            ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB
1087
            ctrl_nxt(ctrl_bus_mo_we_c)   <= '1'; -- write to MAR and MDO (MDO only relevant for store)
1088 68 zero_gravi
            execute_engine.state_nxt     <= LOADSTORE_0;
1089 2 zero_gravi
 
1090 68 zero_gravi
 
1091 29 zero_gravi
          when opcode_branch_c | opcode_jal_c | opcode_jalr_c => -- branch / jump and link (with register)
1092 2 zero_gravi
          -- ------------------------------------------------------------
1093 29 zero_gravi
            if (execute_engine.i_reg(instr_opcode_lsb_c+3 downto instr_opcode_lsb_c+2) = opcode_jalr_c(3 downto 2)) then -- JALR
1094
              ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA (branch target address base)
1095 49 zero_gravi
            else -- JAL
1096 29 zero_gravi
              ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- use PC as ALU.OPA (branch target address base)
1097 2 zero_gravi
            end if;
1098 29 zero_gravi
            ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB (branch target address offset)
1099 49 zero_gravi
            execute_engine.state_nxt     <= BRANCH;
1100 2 zero_gravi
 
1101 68 zero_gravi
 
1102 8 zero_gravi
          when opcode_fence_c => -- fence operations
1103
          -- ------------------------------------------------------------
1104 68 zero_gravi
            if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
1105
              ctrl_nxt(ctrl_bus_fence_c)  <= '1';
1106
              execute_engine.state_nxt    <= SYS_WAIT;
1107
            elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true)  then -- FENCE.I
1108
              ctrl_nxt(ctrl_bus_fencei_c) <= '1';
1109
              execute_engine.branched_nxt <= '1'; -- this is an actual branch
1110
              execute_engine.state_nxt    <= TRAP_EXECUTE; -- use TRAP_EXECUTE to "modify" PC (PC <= PC)
1111
            else -- illegal fence instruction
1112
              execute_engine.state_nxt    <= SYS_WAIT;
1113 66 zero_gravi
            end if;
1114 8 zero_gravi
 
1115 68 zero_gravi
 
1116 2 zero_gravi
          when opcode_syscsr_c => -- system/csr access
1117
          -- ------------------------------------------------------------
1118 45 zero_gravi
            if (CPU_EXTENSION_RISCV_Zicsr = true) then
1119
              if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system/environment
1120
                execute_engine.state_nxt <= SYS_ENV;
1121
              else -- CSR access
1122
                execute_engine.state_nxt <= CSR_ACCESS;
1123
              end if;
1124
            else
1125
              execute_engine.state_nxt <= SYS_WAIT;
1126 2 zero_gravi
            end if;
1127
 
1128 68 zero_gravi
 
1129 53 zero_gravi
          when opcode_fop_c => -- floating-point operations
1130 52 zero_gravi
          -- ------------------------------------------------------------
1131 68 zero_gravi
            if (CPU_EXTENSION_RISCV_Zfinx = true) then
1132 61 zero_gravi
              ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_fpu_c; -- trigger FPU CP
1133 68 zero_gravi
              ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
1134
              execute_engine.state_nxt <= ALU_WAIT;
1135 53 zero_gravi
            else
1136
              execute_engine.state_nxt <= SYS_WAIT;
1137 52 zero_gravi
            end if;
1138
 
1139 68 zero_gravi
 
1140
          when others => -- illegal opcode
1141 2 zero_gravi
          -- ------------------------------------------------------------
1142 39 zero_gravi
            execute_engine.state_nxt <= SYS_WAIT;
1143 2 zero_gravi
 
1144
        end case;
1145
 
1146 39 zero_gravi
 
1147
      when SYS_ENV => -- system environment operation - execution
1148 2 zero_gravi
      -- ------------------------------------------------------------
1149 62 zero_gravi
        execute_engine.state_nxt <= SYS_WAIT; -- default
1150 68 zero_gravi
        if (trap_ctrl.exc_buf(exception_iillegal_c) = '0') then -- no illegal instruction
1151
          case decode_aux.sys_env_cmd is -- use a simplified input here (with hardwired zeros)
1152
            when funct12_ecall_c  => trap_ctrl.env_call       <= '1'; -- ECALL
1153
            when funct12_ebreak_c => trap_ctrl.break_point    <= '1'; -- EBREAK
1154
            when funct12_mret_c   => execute_engine.state_nxt <= TRAP_EXIT; -- MRET
1155
            when funct12_dret_c => -- DRET
1156
              if (CPU_EXTENSION_RISCV_DEBUG = true) then
1157
                execute_engine.state_nxt <= TRAP_EXIT;
1158
                debug_ctrl.dret <= '1';
1159
              else
1160
                NULL; -- executed as NOP (and raise illegal instruction exception)
1161
              end if;
1162
            when funct12_wfi_c => -- WFI
1163
              if (CPU_EXTENSION_RISCV_DEBUG = true) and
1164
                ((debug_ctrl.running = '1') or (csr.dcsr_step = '1')) then -- act as NOP when in debug-mode or during single-stepping
1165
                NULL; -- executed as NOP
1166
              else
1167
                execute_engine.sleep_nxt <= '1'; -- go to sleep mode
1168
              end if;
1169
            when others => NULL; -- undefined / execute as NOP
1170
          end case;
1171
        end if;
1172 39 zero_gravi
 
1173
 
1174
      when CSR_ACCESS => -- read & write status and control register (CSR)
1175
      -- ------------------------------------------------------------
1176 27 zero_gravi
        -- CSR write access --
1177 68 zero_gravi
        if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
1178
           (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then -- CSRRW(I)
1179
          csr.we_nxt <= '1'; -- always write CSR
1180
        else -- CSRRS(I) / CSRRC(I) [invalid CSR instruction are already checked by the illegal instruction logic]
1181
          csr.we_nxt <= not decode_aux.rs1_zero; -- write CSR if rs1/imm is not zero
1182
        end if;
1183 27 zero_gravi
        -- register file write back --
1184 68 zero_gravi
        ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_csrr_c;
1185
        ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
1186
        execute_engine.state_nxt  <= DISPATCH;
1187 2 zero_gravi
 
1188 39 zero_gravi
 
1189 61 zero_gravi
      when ALU_WAIT => -- wait for multi-cycle ALU operation (co-processor) to finish
1190 2 zero_gravi
      -- ------------------------------------------------------------
1191 68 zero_gravi
        ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
1192
        if (alu_idone_i = '1') or (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then -- completed or exception
1193 56 zero_gravi
          ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
1194
          execute_engine.state_nxt  <= DISPATCH;
1195 2 zero_gravi
        end if;
1196
 
1197 39 zero_gravi
 
1198 6 zero_gravi
      when BRANCH => -- update PC for taken branches and jumps
1199
      -- ------------------------------------------------------------
1200 39 zero_gravi
        -- get and store return address (only relevant for jump-and-link operations) --
1201 68 zero_gravi
        ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_nxpc_c; -- next PC
1202
        ctrl_nxt(ctrl_rf_wb_en_c) <= execute_engine.i_reg(instr_opcode_lsb_c+2); -- valid RF write-back? (is jump-and-link?)
1203 39 zero_gravi
        -- destination address --
1204 68 zero_gravi
        execute_engine.pc_mux_sel <= '1'; -- PC <= alu.add = branch/jump destination
1205 40 zero_gravi
        if (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') or (execute_engine.branch_taken = '1') then -- JAL/JALR or taken branch
1206 66 zero_gravi
          -- no need to check for illegal instructions here; the branch condition evaluation circuit will not set "branch_taken" if funct3 is invalid
1207 49 zero_gravi
          execute_engine.pc_we        <= '1'; -- update PC
1208
          execute_engine.branched_nxt <= '1'; -- this is an actual branch
1209
          fetch_engine.reset          <= '1'; -- trigger new instruction fetch from modified PC
1210
          execute_engine.state_nxt    <= SYS_WAIT;
1211 11 zero_gravi
        else
1212
          execute_engine.state_nxt <= DISPATCH;
1213 6 zero_gravi
        end if;
1214
 
1215 39 zero_gravi
 
1216 12 zero_gravi
      when LOADSTORE_0 => -- trigger memory request
1217 6 zero_gravi
      -- ------------------------------------------------------------
1218 57 zero_gravi
        ctrl_nxt(ctrl_bus_lock_c) <= decode_aux.is_atomic_lr; -- atomic.LR: set lock
1219 44 zero_gravi
        if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (decode_aux.is_atomic_lr = '1') then -- normal load or atomic load-reservate
1220 66 zero_gravi
          ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- read request
1221 39 zero_gravi
        else -- store
1222 68 zero_gravi
          if (decode_aux.is_atomic_sc = '0') or (CPU_EXTENSION_RISCV_A = false) then -- (normal) write request
1223
            ctrl_nxt(ctrl_bus_wr_c) <= '1';
1224
          else -- evaluate lock state
1225
            ctrl_nxt(ctrl_bus_wr_c) <= excl_state_i; -- write request if lock is still ok
1226 57 zero_gravi
          end if;
1227 12 zero_gravi
        end if;
1228
        execute_engine.state_nxt <= LOADSTORE_1;
1229 6 zero_gravi
 
1230 39 zero_gravi
 
1231 61 zero_gravi
      when LOADSTORE_1 => -- memory access latency
1232 6 zero_gravi
      -- ------------------------------------------------------------
1233 61 zero_gravi
        ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- write input data to MDI (only relevant for LOADs)
1234 57 zero_gravi
        execute_engine.state_nxt   <= LOADSTORE_2;
1235 6 zero_gravi
 
1236 39 zero_gravi
 
1237 12 zero_gravi
      when LOADSTORE_2 => -- wait for bus transaction to finish
1238 6 zero_gravi
      -- ------------------------------------------------------------
1239 57 zero_gravi
        ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for load (and SC.W) operations)
1240 53 zero_gravi
        ctrl_nxt(ctrl_rf_in_mux_c) <= '1'; -- RF input = memory input (only relevant for LOADs)
1241 68 zero_gravi
        -- wait for memory response --
1242
        if (trap_ctrl.env_start = '1') and (trap_ctrl.cause(6 downto 5) = "00") then -- abort if SYNC EXCEPTION (from bus or illegal cmd) / no IRQs and NOT DEBUG-MODE-related
1243
          execute_engine.state_nxt <= DISPATCH;
1244 26 zero_gravi
        elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction
1245 57 zero_gravi
          -- data write-back --
1246
          if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or -- normal load
1247
             (decode_aux.is_atomic_lr = '1') or -- atomic load-reservate
1248
             (decode_aux.is_atomic_sc = '1') then -- atomic store-conditional
1249 53 zero_gravi
            ctrl_nxt(ctrl_rf_wb_en_c) <= '1';
1250 6 zero_gravi
          end if;
1251 61 zero_gravi
          -- remove atomic lock if this is NOT the LR.W instruction used to SET the lock --
1252
          if (decode_aux.is_atomic_lr = '0') then -- execute and evaluate atomic store-conditional
1253
            ctrl_nxt(ctrl_bus_de_lock_c) <= '1';
1254
          end if;
1255 6 zero_gravi
          execute_engine.state_nxt <= DISPATCH;
1256
        end if;
1257
 
1258 39 zero_gravi
 
1259 2 zero_gravi
      when others => -- undefined
1260
      -- ------------------------------------------------------------
1261 7 zero_gravi
        execute_engine.state_nxt <= SYS_WAIT;
1262 2 zero_gravi
 
1263
    end case;
1264 6 zero_gravi
  end process execute_engine_fsm_comb;
1265 2 zero_gravi
 
1266
 
1267 15 zero_gravi
-- ****************************************************************************************************************************
1268
-- Invalid Instruction / CSR access check
1269
-- ****************************************************************************************************************************
1270
 
1271 49 zero_gravi
  -- CSR Access Check -----------------------------------------------------------------------
1272 15 zero_gravi
  -- -------------------------------------------------------------------------------------------
1273 68 zero_gravi
  csr_access_check: process(execute_engine.i_reg, decode_aux, csr, debug_ctrl)
1274
    variable csr_wacc_v : std_ulogic; -- actual CSR write
1275
--  variable csr_racc_v : std_ulogic; -- actual CSR read
1276 15 zero_gravi
  begin
1277 58 zero_gravi
    -- is this CSR instruction really going to write to a CSR? --
1278 30 zero_gravi
    if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
1279
       (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then
1280
      csr_wacc_v := '1'; -- always write CSR
1281 68 zero_gravi
--    csr_racc_v := or_reduce_f(execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c)); -- read if rd != 0
1282 58 zero_gravi
    else -- clear/set
1283 68 zero_gravi
      csr_wacc_v := not decode_aux.rs1_zero; -- write if rs1/uimm5 != 0
1284
--    csr_racc_v := '1'; -- always read CSR
1285 30 zero_gravi
    end if;
1286
 
1287 15 zero_gravi
    -- check CSR access --
1288 41 zero_gravi
    case csr.addr is
1289 56 zero_gravi
 
1290 58 zero_gravi
      -- floating-point CSRs --
1291 56 zero_gravi
      when csr_fflags_c | csr_frm_c | csr_fcsr_c =>
1292 65 zero_gravi
        csr_acc_valid <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- full access for everyone if FPU implemented
1293 56 zero_gravi
 
1294 68 zero_gravi
      -- machine trap setup/handling & counters --
1295 65 zero_gravi
      when csr_mstatus_c | csr_mstatush_c | csr_misa_c | csr_mie_c | csr_mtvec_c | csr_mscratch_c | csr_mepc_c | csr_mcause_c | csr_mip_c | csr_mtval_c |
1296
           csr_mcycle_c | csr_mcycleh_c | csr_minstret_c | csr_minstreth_c | csr_mcountinhibit_c =>
1297 64 zero_gravi
        -- NOTE: MISA, MIP and MTVAL are read-only in the NEORV32 but we do not cause an exception here for compatibility.
1298 65 zero_gravi
        -- Machine-level code should read-back those CSRs after writing them to realize they are read-only.
1299 64 zero_gravi
        csr_acc_valid <= csr.priv_m_mode; -- M-mode only 
1300 56 zero_gravi
 
1301 65 zero_gravi
      -- machine information registers, read-only --
1302
      when csr_mvendorid_c | csr_marchid_c | csr_mimpid_c | csr_mhartid_c | csr_mconfigptr_c =>
1303
        csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
1304
 
1305 68 zero_gravi
      -- user-mode registers --
1306
      when csr_mcounteren_c | csr_menvcfg_c | csr_menvcfgh_c =>
1307 64 zero_gravi
        csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(CPU_EXTENSION_RISCV_U);
1308
 
1309 63 zero_gravi
      -- physical memory protection (PMP) --
1310
      when csr_pmpaddr0_c  | csr_pmpaddr1_c  | csr_pmpaddr2_c  | csr_pmpaddr3_c  | csr_pmpaddr4_c  | csr_pmpaddr5_c  | csr_pmpaddr6_c  | csr_pmpaddr7_c  | -- address
1311 42 zero_gravi
           csr_pmpaddr8_c  | csr_pmpaddr9_c  | csr_pmpaddr10_c | csr_pmpaddr11_c | csr_pmpaddr12_c | csr_pmpaddr13_c | csr_pmpaddr14_c | csr_pmpaddr15_c |
1312
           csr_pmpaddr16_c | csr_pmpaddr17_c | csr_pmpaddr18_c | csr_pmpaddr19_c | csr_pmpaddr20_c | csr_pmpaddr21_c | csr_pmpaddr22_c | csr_pmpaddr23_c |
1313
           csr_pmpaddr24_c | csr_pmpaddr25_c | csr_pmpaddr26_c | csr_pmpaddr27_c | csr_pmpaddr28_c | csr_pmpaddr29_c | csr_pmpaddr30_c | csr_pmpaddr31_c |
1314
           csr_pmpaddr32_c | csr_pmpaddr33_c | csr_pmpaddr34_c | csr_pmpaddr35_c | csr_pmpaddr36_c | csr_pmpaddr37_c | csr_pmpaddr38_c | csr_pmpaddr39_c |
1315
           csr_pmpaddr40_c | csr_pmpaddr41_c | csr_pmpaddr42_c | csr_pmpaddr43_c | csr_pmpaddr44_c | csr_pmpaddr45_c | csr_pmpaddr46_c | csr_pmpaddr47_c |
1316
           csr_pmpaddr48_c | csr_pmpaddr49_c | csr_pmpaddr50_c | csr_pmpaddr51_c | csr_pmpaddr52_c | csr_pmpaddr53_c | csr_pmpaddr54_c | csr_pmpaddr55_c |
1317 60 zero_gravi
           csr_pmpaddr56_c | csr_pmpaddr57_c | csr_pmpaddr58_c | csr_pmpaddr59_c | csr_pmpaddr60_c | csr_pmpaddr61_c | csr_pmpaddr62_c | csr_pmpaddr63_c |
1318 63 zero_gravi
           csr_pmpcfg0_c   | csr_pmpcfg1_c   | csr_pmpcfg2_c   | csr_pmpcfg3_c   | csr_pmpcfg4_c   | csr_pmpcfg5_c   | csr_pmpcfg6_c   | csr_pmpcfg7_c   | -- configuration
1319 61 zero_gravi
           csr_pmpcfg8_c   | csr_pmpcfg9_c   | csr_pmpcfg10_c  | csr_pmpcfg11_c  | csr_pmpcfg12_c  | csr_pmpcfg13_c  | csr_pmpcfg14_c  | csr_pmpcfg15_c =>
1320 65 zero_gravi
        csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS > 0)); -- M-mode only
1321 56 zero_gravi
 
1322 61 zero_gravi
      -- hardware performance monitors (HPM) --
1323
      when csr_mhpmcounter3_c   | csr_mhpmcounter4_c   | csr_mhpmcounter5_c   | csr_mhpmcounter6_c   | csr_mhpmcounter7_c   | csr_mhpmcounter8_c   | -- counter LOW
1324 56 zero_gravi
           csr_mhpmcounter9_c   | csr_mhpmcounter10_c  | csr_mhpmcounter11_c  | csr_mhpmcounter12_c  | csr_mhpmcounter13_c  | csr_mhpmcounter14_c  |
1325
           csr_mhpmcounter15_c  | csr_mhpmcounter16_c  | csr_mhpmcounter17_c  | csr_mhpmcounter18_c  | csr_mhpmcounter19_c  | csr_mhpmcounter20_c  |
1326
           csr_mhpmcounter21_c  | csr_mhpmcounter22_c  | csr_mhpmcounter23_c  | csr_mhpmcounter24_c  | csr_mhpmcounter25_c  | csr_mhpmcounter26_c  |
1327
           csr_mhpmcounter27_c  | csr_mhpmcounter28_c  | csr_mhpmcounter29_c  | csr_mhpmcounter30_c  | csr_mhpmcounter31_c  |
1328 61 zero_gravi
           csr_mhpmcounter3h_c  | csr_mhpmcounter4h_c  | csr_mhpmcounter5h_c  | csr_mhpmcounter6h_c  | csr_mhpmcounter7h_c  | csr_mhpmcounter8h_c  | -- counter HIGH
1329 56 zero_gravi
           csr_mhpmcounter9h_c  | csr_mhpmcounter10h_c | csr_mhpmcounter11h_c | csr_mhpmcounter12h_c | csr_mhpmcounter13h_c | csr_mhpmcounter14h_c |
1330
           csr_mhpmcounter15h_c | csr_mhpmcounter16h_c | csr_mhpmcounter17h_c | csr_mhpmcounter18h_c | csr_mhpmcounter19h_c | csr_mhpmcounter20h_c |
1331
           csr_mhpmcounter21h_c | csr_mhpmcounter22h_c | csr_mhpmcounter23h_c | csr_mhpmcounter24h_c | csr_mhpmcounter25h_c | csr_mhpmcounter26h_c |
1332 61 zero_gravi
           csr_mhpmcounter27h_c | csr_mhpmcounter28h_c | csr_mhpmcounter29h_c | csr_mhpmcounter30h_c | csr_mhpmcounter31h_c |
1333
           csr_mhpmevent3_c     | csr_mhpmevent4_c     | csr_mhpmevent5_c     | csr_mhpmevent6_c     | csr_mhpmevent7_c     | csr_mhpmevent8_c     | -- event configuration
1334
           csr_mhpmevent9_c     | csr_mhpmevent10_c    | csr_mhpmevent11_c    | csr_mhpmevent12_c    | csr_mhpmevent13_c    | csr_mhpmevent14_c    |
1335
           csr_mhpmevent15_c    | csr_mhpmevent16_c    | csr_mhpmevent17_c    | csr_mhpmevent18_c    | csr_mhpmevent19_c    | csr_mhpmevent20_c    |
1336
           csr_mhpmevent21_c    | csr_mhpmevent22_c    | csr_mhpmevent23_c    | csr_mhpmevent24_c    | csr_mhpmevent25_c    | csr_mhpmevent26_c    |
1337
           csr_mhpmevent27_c    | csr_mhpmevent28_c    | csr_mhpmevent29_c    | csr_mhpmevent30_c    | csr_mhpmevent31_c =>
1338 66 zero_gravi
        csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zihpm); -- M-mode only
1339 56 zero_gravi
 
1340 68 zero_gravi
      -- user-level counters/timers (read-only) --
1341 65 zero_gravi
      when csr_cycle_c | csr_cycleh_c | csr_instret_c | csr_instreth_c | csr_time_c | csr_timeh_c =>
1342
        case csr.addr(1 downto 0) is
1343 66 zero_gravi
          when "00"   => csr_acc_valid <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr) and (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_cy); -- cyle[h]: M-mode, U-mode if authorized, implemented at all, read-only
1344
          when "01"   => csr_acc_valid <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr) and (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_tm); -- time[h]: M-mode, U-mode if authorized, implemented at all, read-only
1345
          when "10"   => csr_acc_valid <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr) and (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_ir); -- instret[h]: M-mode, U-mode if authorized, implemented at all read-only
1346 65 zero_gravi
          when others => csr_acc_valid <= '0';
1347
        end case;
1348 56 zero_gravi
 
1349 59 zero_gravi
      -- debug mode CSRs --
1350
      when csr_dcsr_c | csr_dpc_c | csr_dscratch0_c =>
1351 65 zero_gravi
        csr_acc_valid <= debug_ctrl.running and bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG); -- access only in debug-mode
1352 59 zero_gravi
 
1353 56 zero_gravi
      -- undefined / not implemented --
1354
      when others =>
1355 65 zero_gravi
        csr_acc_valid <= '0'; -- invalid access
1356 15 zero_gravi
    end case;
1357 49 zero_gravi
  end process csr_access_check;
1358 15 zero_gravi
 
1359
 
1360 2 zero_gravi
  -- Illegal Instruction Check --------------------------------------------------------------
1361
  -- -------------------------------------------------------------------------------------------
1362 62 zero_gravi
  illegal_instruction_check: process(execute_engine, decode_aux, csr, csr_acc_valid, debug_ctrl)
1363 36 zero_gravi
    variable opcode_v : std_ulogic_vector(6 downto 0);
1364 2 zero_gravi
  begin
1365 65 zero_gravi
    -- illegal instructions are checked in the EXECUTE state
1366 36 zero_gravi
    -- the execute engine should not commit any illegal instruction
1367 6 zero_gravi
    if (execute_engine.state = EXECUTE) then
1368 2 zero_gravi
      -- defaults --
1369
      illegal_instruction <= '0';
1370
      illegal_register    <= '0';
1371
 
1372 36 zero_gravi
      -- check opcode for rv32 --
1373
      if (execute_engine.i_reg(instr_opcode_lsb_c+1 downto instr_opcode_lsb_c) = "11") then
1374
        illegal_opcode_lsbs <= '0';
1375
      else
1376
        illegal_opcode_lsbs <= '1';
1377
      end if;
1378
 
1379 66 zero_gravi
      -- check for illegal compressed instruction --
1380
      if (CPU_EXTENSION_RISCV_C = true) then
1381
        illegal_compressed <= execute_engine.is_ici;
1382
      else
1383
        illegal_compressed <= '0';
1384
      end if;
1385
 
1386 2 zero_gravi
      -- check instructions --
1387 60 zero_gravi
      opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; -- save some bits here, LSBs are always 11 for rv32
1388 36 zero_gravi
      case opcode_v is
1389 2 zero_gravi
 
1390 59 zero_gravi
        when opcode_lui_c | opcode_auipc_c | opcode_jal_c => -- check sufficient LUI, UIPC, JAL (only check actual OPCODE)
1391 52 zero_gravi
        -- ------------------------------------------------------------
1392 2 zero_gravi
          illegal_instruction <= '0';
1393 23 zero_gravi
          -- illegal E-CPU register? --
1394 68 zero_gravi
          illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and execute_engine.i_reg(instr_rd_msb_c);
1395 2 zero_gravi
 
1396 44 zero_gravi
        when opcode_alu_c => -- check ALU.funct3 & ALU.funct7
1397 52 zero_gravi
        -- ------------------------------------------------------------
1398 68 zero_gravi
          if (((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c)) and
1399
              (execute_engine.i_reg(instr_funct7_msb_c-2 downto instr_funct7_lsb_c) = "00000") and (execute_engine.i_reg(instr_funct7_msb_c) = '0')) or
1400
             (((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or
1401
               (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or
1402
               (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) or
1403
               (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_xor_c) or
1404
               (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_or_c) or
1405
               (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_and_c)) and
1406
               (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000000")) then -- valid base ALUI instruction?
1407
            illegal_instruction <= '0';
1408
          elsif ((CPU_EXTENSION_RISCV_M = true) or (CPU_EXTENSION_RISCV_Zmmul = false)) and (decode_aux.is_m_mul = '1') then -- valid MUL instruction?
1409
            illegal_instruction <= '0';
1410
          elsif (CPU_EXTENSION_RISCV_M = true) and (decode_aux.is_m_div = '1') then -- valid DIV instruction?
1411
            illegal_instruction <= '0';
1412
          elsif (CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_bitmanip_reg = '1') then -- valid BITMANIP instruction?
1413
            illegal_instruction <= '0';
1414
          else
1415 44 zero_gravi
            illegal_instruction <= '1';
1416
          end if;
1417
          -- illegal E-CPU register? --
1418 68 zero_gravi
          illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rd_msb_c) or execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c));
1419 44 zero_gravi
 
1420
        when opcode_alui_c => -- check ALUI.funct7
1421 52 zero_gravi
        -- ------------------------------------------------------------
1422 68 zero_gravi
          if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or
1423
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or
1424
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) or
1425
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_xor_c) or
1426
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_or_c) or
1427
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_and_c) or
1428
             ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and -- shift logical left
1429
              (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000000")) or
1430
             ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and -- shift right
1431
              ((execute_engine.i_reg(instr_funct7_msb_c-2 downto instr_funct7_lsb_c) = "00000") and (execute_engine.i_reg(instr_funct7_msb_c) = '0'))) then -- valid base ALUI instruction?
1432
            illegal_instruction <= '0';
1433
          elsif (CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_bitmanip_imm = '1') then -- valid BITMANIP immediate instruction?
1434
            illegal_instruction <= '0';
1435
          else
1436 2 zero_gravi
            illegal_instruction <= '1';
1437
          end if;
1438 23 zero_gravi
          -- illegal E-CPU register? --
1439 68 zero_gravi
          illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
1440 39 zero_gravi
 
1441 44 zero_gravi
        when opcode_load_c => -- check LOAD.funct3
1442 52 zero_gravi
        -- ------------------------------------------------------------
1443 6 zero_gravi
          if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lb_c) or
1444
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lh_c) or
1445
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lw_c) or
1446
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lbu_c) or
1447
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lhu_c) then
1448 2 zero_gravi
            illegal_instruction <= '0';
1449
          else
1450
            illegal_instruction <= '1';
1451
          end if;
1452 23 zero_gravi
          -- illegal E-CPU register? --
1453 68 zero_gravi
          illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
1454 39 zero_gravi
 
1455 44 zero_gravi
        when opcode_store_c => -- check STORE.funct3
1456 52 zero_gravi
        -- ------------------------------------------------------------
1457 6 zero_gravi
          if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sb_c) or
1458
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sh_c) or
1459
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sw_c) then
1460 2 zero_gravi
            illegal_instruction <= '0';
1461
          else
1462
            illegal_instruction <= '1';
1463
          end if;
1464 23 zero_gravi
          -- illegal E-CPU register? --
1465 68 zero_gravi
          illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c));
1466
 
1467
        when opcode_atomic_c => -- atomic instructions
1468
        -- ------------------------------------------------------------
1469
          if (CPU_EXTENSION_RISCV_A = true) then
1470
            if (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = "00010") then -- LR
1471
              illegal_instruction <= '0';
1472
              -- illegal E-CPU register? --
1473
              illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
1474
            elsif (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = "00011") then -- SC
1475
              illegal_instruction <= '0';
1476
              -- illegal E-CPU register? --
1477
              illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
1478
            else
1479
              illegal_instruction <= '1';
1480
            end if;
1481
          else
1482
            illegal_instruction <= '1';
1483 23 zero_gravi
          end if;
1484 2 zero_gravi
 
1485 44 zero_gravi
        when opcode_branch_c => -- check BRANCH.funct3
1486 52 zero_gravi
        -- ------------------------------------------------------------
1487 6 zero_gravi
          if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_beq_c) or
1488
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bne_c) or
1489
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_blt_c) or
1490
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bge_c) or
1491
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bltu_c) or
1492
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bgeu_c) then
1493 2 zero_gravi
            illegal_instruction <= '0';
1494
          else
1495
            illegal_instruction <= '1';
1496
          end if;
1497 23 zero_gravi
          -- illegal E-CPU register? --
1498 68 zero_gravi
          illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c));
1499 2 zero_gravi
 
1500 44 zero_gravi
        when opcode_jalr_c => -- check JALR.funct3
1501 52 zero_gravi
        -- ------------------------------------------------------------
1502 6 zero_gravi
          if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") then
1503 2 zero_gravi
            illegal_instruction <= '0';
1504
          else
1505
            illegal_instruction <= '1';
1506
          end if;
1507 23 zero_gravi
          -- illegal E-CPU register? --
1508 68 zero_gravi
          illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
1509 2 zero_gravi
 
1510 68 zero_gravi
        when opcode_fence_c => -- check FENCE.funct3
1511 52 zero_gravi
        -- ------------------------------------------------------------
1512 64 zero_gravi
          if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true)) or -- FENCE.I
1513 61 zero_gravi
             (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
1514 8 zero_gravi
            illegal_instruction <= '0';
1515
          else
1516
            illegal_instruction <= '1';
1517
          end if;
1518 68 zero_gravi
          -- illegal E-CPU register? --
1519
          illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
1520 8 zero_gravi
 
1521 52 zero_gravi
        when opcode_syscsr_c => -- check system instructions
1522
        -- ------------------------------------------------------------
1523 2 zero_gravi
          -- CSR access --
1524 68 zero_gravi
          if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
1525
              (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrs_c) or
1526
              (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrc_c) or
1527
              (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) or
1528
              (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrsi_c) or
1529
              (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrci_c)) and
1530
             (csr_acc_valid = '1') then -- valid CSR access?
1531
            illegal_instruction <= '0';
1532 23 zero_gravi
            -- illegal E-CPU register? --
1533
            if (CPU_EXTENSION_RISCV_E = true) then
1534
              if (execute_engine.i_reg(instr_funct3_msb_c) = '0') then -- reg-reg CSR
1535
                illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
1536
              else -- reg-imm CSR
1537
                illegal_register <= execute_engine.i_reg(instr_rd_msb_c);
1538
              end if;
1539
            end if;
1540 60 zero_gravi
          -- ecall, ebreak, mret, wfi, dret --
1541 68 zero_gravi
          elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") and
1542
                (decode_aux.rs1_zero = '1') and (decode_aux.rd_zero = '1') and
1543
                ((execute_engine.i_reg(instr_funct12_msb_c  downto instr_funct12_lsb_c) = funct12_ecall_c)  or -- ECALL
1544
                 (execute_engine.i_reg(instr_funct12_msb_c  downto instr_funct12_lsb_c) = funct12_ebreak_c) or -- EBREAK 
1545
                 ((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_mret_c) and (csr.priv_m_mode = '1')) or -- MRET (only allowed in M-mode)
1546
                 ((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_dret_c) and (CPU_EXTENSION_RISCV_DEBUG = true) and (debug_ctrl.running = '1')) or -- DRET (only allowed in D-mode)
1547
                 (execute_engine.i_reg(instr_funct12_msb_c  downto instr_funct12_lsb_c) = funct12_wfi_c)) then -- WFI (always allowed to execute)
1548 39 zero_gravi
            illegal_instruction <= '0';
1549
          else
1550
            illegal_instruction <= '1';
1551
          end if;
1552
 
1553 53 zero_gravi
        when opcode_fop_c => -- floating point operations - single/dual operands
1554 52 zero_gravi
        -- ------------------------------------------------------------
1555 63 zero_gravi
          if (CPU_EXTENSION_RISCV_Zfinx = true) and -- F extension implemented
1556 53 zero_gravi
             (execute_engine.i_reg(instr_funct7_lsb_c+1 downto instr_funct7_lsb_c) = float_single_c) and -- single-precision operations only
1557
             (decode_aux.is_float_op = '1') then -- is correct/supported floating-point instruction
1558 52 zero_gravi
            illegal_instruction <= '0';
1559
          else
1560
            illegal_instruction <= '1';
1561
          end if;
1562 68 zero_gravi
          -- illegal E-CPU register? --
1563
          -- FIXME: rs2 is not checked!
1564
          illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
1565 52 zero_gravi
 
1566 36 zero_gravi
        when others => -- undefined instruction -> illegal!
1567 52 zero_gravi
        -- ------------------------------------------------------------
1568 36 zero_gravi
          illegal_instruction <= '1';
1569 2 zero_gravi
 
1570
      end case;
1571
    else
1572 36 zero_gravi
      illegal_opcode_lsbs <= '0';
1573 66 zero_gravi
      illegal_compressed  <= '0';
1574 2 zero_gravi
      illegal_instruction <= '0';
1575
      illegal_register    <= '0';
1576
    end if;
1577
  end process illegal_instruction_check;
1578
 
1579
  -- any illegal condition? --
1580 66 zero_gravi
  trap_ctrl.instr_il <= illegal_instruction or illegal_opcode_lsbs or illegal_register or illegal_compressed;
1581 2 zero_gravi
 
1582
 
1583 6 zero_gravi
-- ****************************************************************************************************************************
1584 38 zero_gravi
-- Exception and Interrupt (= Trap) Control
1585 6 zero_gravi
-- ****************************************************************************************************************************
1586 2 zero_gravi
 
1587 6 zero_gravi
  -- Trap Controller ------------------------------------------------------------------------
1588 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
1589 6 zero_gravi
  trap_controller: process(rstn_i, clk_i)
1590 40 zero_gravi
    variable mode_m_v, mode_u_v : std_ulogic;
1591 2 zero_gravi
  begin
1592
    if (rstn_i = '0') then
1593 6 zero_gravi
      trap_ctrl.exc_buf   <= (others => '0');
1594 64 zero_gravi
      trap_ctrl.irq_buf   <= (others => '0');
1595 6 zero_gravi
      trap_ctrl.exc_ack   <= '0';
1596 47 zero_gravi
      trap_ctrl.env_start <= '0';
1597 65 zero_gravi
      trap_ctrl.cause     <= (others => '0');
1598 2 zero_gravi
    elsif rising_edge(clk_i) then
1599
      if (CPU_EXTENSION_RISCV_Zicsr = true) then
1600 59 zero_gravi
 
1601 68 zero_gravi
        -- exception queue: misaligned load/store/instruction address --
1602 59 zero_gravi
        trap_ctrl.exc_buf(exception_lalign_c) <= (trap_ctrl.exc_buf(exception_lalign_c) or ma_load_i)          and (not trap_ctrl.exc_ack);
1603
        trap_ctrl.exc_buf(exception_salign_c) <= (trap_ctrl.exc_buf(exception_salign_c) or ma_store_i)         and (not trap_ctrl.exc_ack);
1604
        trap_ctrl.exc_buf(exception_ialign_c) <= (trap_ctrl.exc_buf(exception_ialign_c) or trap_ctrl.instr_ma) and (not trap_ctrl.exc_ack);
1605
 
1606 68 zero_gravi
        -- exception queue: load/store/instruction bus access error --
1607 59 zero_gravi
        trap_ctrl.exc_buf(exception_laccess_c) <= (trap_ctrl.exc_buf(exception_laccess_c) or be_load_i)          and (not trap_ctrl.exc_ack);
1608
        trap_ctrl.exc_buf(exception_saccess_c) <= (trap_ctrl.exc_buf(exception_saccess_c) or be_store_i)         and (not trap_ctrl.exc_ack);
1609
        trap_ctrl.exc_buf(exception_iaccess_c) <= (trap_ctrl.exc_buf(exception_iaccess_c) or trap_ctrl.instr_be) and (not trap_ctrl.exc_ack);
1610
 
1611 68 zero_gravi
        -- exception queue: illegal instruction / environment calls --
1612 40 zero_gravi
        trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or (trap_ctrl.env_call and csr.priv_m_mode)) and (not trap_ctrl.exc_ack);
1613
        trap_ctrl.exc_buf(exception_u_envcall_c) <= (trap_ctrl.exc_buf(exception_u_envcall_c) or (trap_ctrl.env_call and csr.priv_u_mode)) and (not trap_ctrl.exc_ack);
1614
        trap_ctrl.exc_buf(exception_iillegal_c)  <= (trap_ctrl.exc_buf(exception_iillegal_c)  or trap_ctrl.instr_il)                       and (not trap_ctrl.exc_ack);
1615 68 zero_gravi
 
1616
        -- exception queue: break point --
1617 59 zero_gravi
        if (CPU_EXTENSION_RISCV_DEBUG = true) then
1618 68 zero_gravi
          trap_ctrl.exc_buf(exception_break_c) <= (not trap_ctrl.exc_ack) and (trap_ctrl.exc_buf(exception_break_c) or
1619
            ((trap_ctrl.break_point and csr.priv_m_mode and (not csr.dcsr_ebreakm) and (not debug_ctrl.running)) or -- enable break to machine-trap-handler when in machine mode on "ebreak"
1620
             (trap_ctrl.break_point and csr.priv_u_mode and (not csr.dcsr_ebreaku) and (not debug_ctrl.running)))); -- enable break to machine-trap-handler when in user mode on "ebreak"
1621 59 zero_gravi
        else
1622
          trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack);
1623
        end if;
1624
 
1625 68 zero_gravi
        -- exception buffer: enter debug mode --
1626
        trap_ctrl.exc_buf(exception_db_break_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and (trap_ctrl.exc_buf(exception_db_break_c) or debug_ctrl.trig_break) and (not trap_ctrl.exc_ack);
1627
        trap_ctrl.irq_buf(interrupt_db_halt_c)  <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and debug_ctrl.trig_halt;
1628
        trap_ctrl.irq_buf(interrupt_db_step_c)  <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and debug_ctrl.trig_step;
1629 59 zero_gravi
 
1630 68 zero_gravi
        -- interrupt buffer: machine software/external/timer interrupt --
1631 64 zero_gravi
        trap_ctrl.irq_buf(interrupt_msw_irq_c)   <= csr.mie_msie and msw_irq_i;
1632
        trap_ctrl.irq_buf(interrupt_mext_irq_c)  <= csr.mie_meie and mext_irq_i;
1633
        trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and mtime_irq_i;
1634 59 zero_gravi
 
1635 68 zero_gravi
        -- interrupt buffer: NEORV32-specific fast interrupts (FIRQ) --
1636
        trap_ctrl.irq_buf(interrupt_firq_15_c downto interrupt_firq_0_c) <= csr.mie_firqe(15 downto 0) and firq_i(15 downto 0);
1637
 
1638
        -- trap environment control --
1639 6 zero_gravi
        if (trap_ctrl.env_start = '0') then -- no started trap handler
1640 68 zero_gravi
          if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception triggered!
1641 49 zero_gravi
             ((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP_ENTER))) then -- fire IRQs in EXECUTE or TRAP state only to continue execution even on permanent IRQ
1642 65 zero_gravi
            trap_ctrl.cause     <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr)
1643
            trap_ctrl.exc_ack   <= '1';                 -- clear exceptions (no ack mask: these have highest priority and are always evaluated first!)
1644
            trap_ctrl.env_start <= '1';                 -- now execute engine can start trap handler
1645 2 zero_gravi
          end if;
1646 6 zero_gravi
        else -- trap waiting to get started
1647
          if (trap_ctrl.env_start_ack = '1') then -- start of trap handler acknowledged by execution engine
1648
            trap_ctrl.exc_ack   <= '0';
1649
            trap_ctrl.env_start <= '0';
1650 2 zero_gravi
          end if;
1651
        end if;
1652
      end if;
1653
    end if;
1654 6 zero_gravi
  end process trap_controller;
1655 2 zero_gravi
 
1656
  -- any exception/interrupt? --
1657 60 zero_gravi
  trap_ctrl.exc_fire <= or_reduce_f(trap_ctrl.exc_buf); -- exceptions/faults CANNOT be masked
1658 64 zero_gravi
  trap_ctrl.irq_fire <= (or_reduce_f(trap_ctrl.irq_buf) and csr.mstatus_mie and trap_ctrl.db_irq_en) or trap_ctrl.db_irq_fire; -- interrupts CAN be masked (but not the DEBUG halt IRQ)
1659 2 zero_gravi
 
1660 59 zero_gravi
  -- debug mode (entry) interrupts --
1661 61 zero_gravi
  trap_ctrl.db_irq_en   <= '0' when (CPU_EXTENSION_RISCV_DEBUG = true) and ((debug_ctrl.running = '1') or (csr.dcsr_step = '1')) else '1'; -- no interrupts when IN debug mode or IN single-step mode
1662 59 zero_gravi
  trap_ctrl.db_irq_fire <= (trap_ctrl.irq_buf(interrupt_db_step_c) or trap_ctrl.irq_buf(interrupt_db_halt_c)) when (CPU_EXTENSION_RISCV_DEBUG = true) else '0'; -- "NMI" for debug mode entry
1663
 
1664 40 zero_gravi
 
1665 42 zero_gravi
  -- Trap Priority Encoder ------------------------------------------------------------------
1666 6 zero_gravi
  -- -------------------------------------------------------------------------------------------
1667
  trap_priority: process(trap_ctrl)
1668 2 zero_gravi
  begin
1669
    -- defaults --
1670 65 zero_gravi
    trap_ctrl.cause_nxt <= (others => '0');
1671 2 zero_gravi
 
1672 64 zero_gravi
    -- NOTE: Synchronous exceptions (from trap_ctrl.exc_buf) have higher priority than asynchronous
1673
    -- exceptions (from trap_ctrl.irq_buf).
1674
 
1675 58 zero_gravi
    -- ----------------------------------------------------------------------------------------
1676 68 zero_gravi
    -- the following traps are caused by *synchronous* exceptions; we do not need a
1677 64 zero_gravi
    -- specific acknowledge mask since only _one_ exception (the one with highest priority)
1678
    -- is allowed to kick in at once
1679 59 zero_gravi
    -- ----------------------------------------------------------------------------------------
1680
 
1681 64 zero_gravi
    -- exception: 0.0 instruction address misaligned --
1682
    if (trap_ctrl.exc_buf(exception_ialign_c) = '1') then
1683
      trap_ctrl.cause_nxt <= trap_ima_c;
1684
 
1685
    -- exception: 0.1 instruction access fault --
1686
    elsif (trap_ctrl.exc_buf(exception_iaccess_c) = '1') then
1687
      trap_ctrl.cause_nxt <= trap_iba_c;
1688
 
1689
    -- exception: 0.2 illegal instruction --
1690
    elsif (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then
1691
      trap_ctrl.cause_nxt <= trap_iil_c;
1692
 
1693
 
1694
    -- exception: 0.11 environment call from M-mode --
1695
    elsif (trap_ctrl.exc_buf(exception_m_envcall_c) = '1') then
1696
      trap_ctrl.cause_nxt <= trap_menv_c;
1697
 
1698
    -- exception: 0.8 environment call from U-mode --
1699
    elsif (trap_ctrl.exc_buf(exception_u_envcall_c) = '1') then
1700
      trap_ctrl.cause_nxt <= trap_uenv_c;
1701
 
1702
    -- exception: 0.3 breakpoint --
1703
    elsif (trap_ctrl.exc_buf(exception_break_c) = '1') then
1704
      trap_ctrl.cause_nxt <= trap_brk_c;
1705
 
1706
 
1707
    -- exception: 0.6 store address misaligned -
1708
    elsif (trap_ctrl.exc_buf(exception_salign_c) = '1') then
1709
      trap_ctrl.cause_nxt <= trap_sma_c;
1710
 
1711
    -- exception: 0.4 load address misaligned --
1712
    elsif (trap_ctrl.exc_buf(exception_lalign_c) = '1') then
1713
      trap_ctrl.cause_nxt <= trap_lma_c;
1714
 
1715
    -- exception: 0.7 store access fault --
1716
    elsif (trap_ctrl.exc_buf(exception_saccess_c) = '1') then
1717
      trap_ctrl.cause_nxt <= trap_sbe_c;
1718
 
1719
    -- exception: 0.5 load access fault --
1720
    elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then
1721
      trap_ctrl.cause_nxt <= trap_lbe_c;
1722
 
1723
 
1724
    -- ----------------------------------------------------------------------------------------
1725
    -- (re-)enter debug mode requests; basically, these are standard traps that have some
1726
    -- special handling - they have the highest INTERRUPT priority in order to go to debug when requested
1727
    -- even if other IRQs are pending right now
1728
    -- ----------------------------------------------------------------------------------------
1729
 
1730 59 zero_gravi
    -- break instruction --
1731 64 zero_gravi
    elsif (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.exc_buf(exception_db_break_c) = '1') then
1732 59 zero_gravi
      trap_ctrl.cause_nxt <= trap_db_break_c;
1733
 
1734
    -- external halt request --
1735
    elsif (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.irq_buf(interrupt_db_halt_c) = '1') then
1736
      trap_ctrl.cause_nxt <= trap_db_halt_c;
1737
 
1738 64 zero_gravi
    -- single stepping --
1739
    elsif (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.irq_buf(interrupt_db_step_c) = '1') then
1740
      trap_ctrl.cause_nxt <= trap_db_step_c;
1741 59 zero_gravi
 
1742 64 zero_gravi
 
1743 59 zero_gravi
    -- ----------------------------------------------------------------------------------------
1744 38 zero_gravi
    -- the following traps are caused by *asynchronous* exceptions (= interrupts)
1745 58 zero_gravi
    -- ----------------------------------------------------------------------------------------
1746 9 zero_gravi
 
1747 64 zero_gravi
    -- custom FAST interrupt requests --
1748 58 zero_gravi
 
1749 14 zero_gravi
    -- interrupt: 1.16 fast interrupt channel 0 --
1750
    elsif (trap_ctrl.irq_buf(interrupt_firq_0_c) = '1') then
1751
      trap_ctrl.cause_nxt <= trap_firq0_c;
1752
 
1753
    -- interrupt: 1.17 fast interrupt channel 1 --
1754
    elsif (trap_ctrl.irq_buf(interrupt_firq_1_c) = '1') then
1755
      trap_ctrl.cause_nxt <= trap_firq1_c;
1756
 
1757
    -- interrupt: 1.18 fast interrupt channel 2 --
1758
    elsif (trap_ctrl.irq_buf(interrupt_firq_2_c) = '1') then
1759
      trap_ctrl.cause_nxt <= trap_firq2_c;
1760
 
1761
    -- interrupt: 1.19 fast interrupt channel 3 --
1762
    elsif (trap_ctrl.irq_buf(interrupt_firq_3_c) = '1') then
1763
      trap_ctrl.cause_nxt <= trap_firq3_c;
1764
 
1765 47 zero_gravi
    -- interrupt: 1.20 fast interrupt channel 4 --
1766
    elsif (trap_ctrl.irq_buf(interrupt_firq_4_c) = '1') then
1767
      trap_ctrl.cause_nxt <= trap_firq4_c;
1768 14 zero_gravi
 
1769 47 zero_gravi
    -- interrupt: 1.21 fast interrupt channel 5 --
1770
    elsif (trap_ctrl.irq_buf(interrupt_firq_5_c) = '1') then
1771
      trap_ctrl.cause_nxt <= trap_firq5_c;
1772
 
1773
    -- interrupt: 1.22 fast interrupt channel 6 --
1774
    elsif (trap_ctrl.irq_buf(interrupt_firq_6_c) = '1') then
1775
      trap_ctrl.cause_nxt <= trap_firq6_c;
1776
 
1777
    -- interrupt: 1.23 fast interrupt channel 7 --
1778
    elsif (trap_ctrl.irq_buf(interrupt_firq_7_c) = '1') then
1779
      trap_ctrl.cause_nxt <= trap_firq7_c;
1780
 
1781 48 zero_gravi
    -- interrupt: 1.24 fast interrupt channel 8 --
1782
    elsif (trap_ctrl.irq_buf(interrupt_firq_8_c) = '1') then
1783
      trap_ctrl.cause_nxt <= trap_firq8_c;
1784 47 zero_gravi
 
1785 48 zero_gravi
    -- interrupt: 1.25 fast interrupt channel 9 --
1786
    elsif (trap_ctrl.irq_buf(interrupt_firq_9_c) = '1') then
1787
      trap_ctrl.cause_nxt <= trap_firq9_c;
1788
 
1789
    -- interrupt: 1.26 fast interrupt channel 10 --
1790
    elsif (trap_ctrl.irq_buf(interrupt_firq_10_c) = '1') then
1791
      trap_ctrl.cause_nxt <= trap_firq10_c;
1792
 
1793
    -- interrupt: 1.27 fast interrupt channel 11 --
1794
    elsif (trap_ctrl.irq_buf(interrupt_firq_11_c) = '1') then
1795
      trap_ctrl.cause_nxt <= trap_firq11_c;
1796
 
1797
    -- interrupt: 1.28 fast interrupt channel 12 --
1798
    elsif (trap_ctrl.irq_buf(interrupt_firq_12_c) = '1') then
1799
      trap_ctrl.cause_nxt <= trap_firq12_c;
1800
 
1801
    -- interrupt: 1.29 fast interrupt channel 13 --
1802
    elsif (trap_ctrl.irq_buf(interrupt_firq_13_c) = '1') then
1803
      trap_ctrl.cause_nxt <= trap_firq13_c;
1804
 
1805
    -- interrupt: 1.30 fast interrupt channel 14 --
1806
    elsif (trap_ctrl.irq_buf(interrupt_firq_14_c) = '1') then
1807
      trap_ctrl.cause_nxt <= trap_firq14_c;
1808
 
1809
    -- interrupt: 1.31 fast interrupt channel 15 --
1810
    elsif (trap_ctrl.irq_buf(interrupt_firq_15_c) = '1') then
1811
      trap_ctrl.cause_nxt <= trap_firq15_c;
1812
 
1813
 
1814 64 zero_gravi
    -- standard RISC-V interrupts --
1815 4 zero_gravi
 
1816 64 zero_gravi
    -- interrupt: 1.11 machine external interrupt --
1817
    elsif (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
1818
      trap_ctrl.cause_nxt <= trap_mei_c;
1819 2 zero_gravi
 
1820 64 zero_gravi
    -- interrupt: 1.3 machine SW interrupt --
1821
    elsif (trap_ctrl.irq_buf(interrupt_msw_irq_c) = '1') then
1822
      trap_ctrl.cause_nxt <= trap_msi_c;
1823 2 zero_gravi
 
1824 64 zero_gravi
    -- interrupt: 1.7 machine timer interrupt --
1825
    elsif (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then
1826
      trap_ctrl.cause_nxt <= trap_mti_c;
1827 2 zero_gravi
 
1828
    end if;
1829 6 zero_gravi
  end process trap_priority;
1830
 
1831 2 zero_gravi
 
1832 6 zero_gravi
-- ****************************************************************************************************************************
1833
-- Control and Status Registers (CSRs)
1834
-- ****************************************************************************************************************************
1835 2 zero_gravi
 
1836 27 zero_gravi
  -- Control and Status Registers Write Data ------------------------------------------------
1837
  -- -------------------------------------------------------------------------------------------
1838 36 zero_gravi
  csr_write_data: process(execute_engine.i_reg, csr.rdata, rs1_i)
1839
    variable csr_operand_v : std_ulogic_vector(data_width_c-1 downto 0);
1840 27 zero_gravi
  begin
1841 36 zero_gravi
    -- CSR operand source --
1842
    if (execute_engine.i_reg(instr_funct3_msb_c) = '1') then -- immediate
1843
      csr_operand_v := (others => '0');
1844 38 zero_gravi
      csr_operand_v(4 downto 0) := execute_engine.i_reg(19 downto 15); -- uimm5
1845 36 zero_gravi
    else -- register
1846
      csr_operand_v := rs1_i;
1847
    end if;
1848 40 zero_gravi
    -- tiny ALU for CSR write operations --
1849 27 zero_gravi
    case execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c) is
1850 36 zero_gravi
      when "10"   => csr.wdata <= csr.rdata or csr_operand_v; -- CSRRS(I)
1851
      when "11"   => csr.wdata <= csr.rdata and (not csr_operand_v); -- CSRRC(I)
1852
      when others => csr.wdata <= csr_operand_v; -- CSRRW(I)
1853 27 zero_gravi
    end case;
1854
  end process csr_write_data;
1855
 
1856
 
1857 52 zero_gravi
  -- Control and Status Registers - Write Access --------------------------------------------
1858 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
1859
  csr_write_access: process(rstn_i, clk_i)
1860 65 zero_gravi
    variable cause_v : std_ulogic_vector(6 downto 0);
1861 2 zero_gravi
  begin
1862 59 zero_gravi
    -- NOTE: If <dedicated_reset_c> = true then <def_rst_val_c> evaluates to '-'. Register that reset to <def_rst_val_c> do
1863
    -- NOT actually have a real reset by default (def_rst_val_c = '-') and have to be explicitly initialized by software!
1864 56 zero_gravi
    -- see: https://forums.xilinx.com/t5/General-Technical-Discussion/quot-Don-t-care-quot-reset-value/td-p/412845
1865 2 zero_gravi
    if (rstn_i = '0') then
1866 68 zero_gravi
      csr.we                <= '0';
1867 11 zero_gravi
      --
1868 68 zero_gravi
      csr.mstatus_mie       <= '0';
1869
      csr.mstatus_mpie      <= '0';
1870
      csr.mstatus_mpp       <= (others => '0');
1871
      csr.privilege         <= priv_mode_m_c; -- start in MACHINE mode
1872
      csr.mie_msie          <= def_rst_val_c;
1873
      csr.mie_meie          <= def_rst_val_c;
1874
      csr.mie_mtie          <= def_rst_val_c;
1875
      csr.mie_firqe         <= (others => def_rst_val_c);
1876
      csr.mtvec             <= (others => def_rst_val_c);
1877
      csr.mscratch          <= x"19880704";
1878
      csr.mepc              <= (others => def_rst_val_c);
1879
      csr.mcause            <= (others => def_rst_val_c);
1880
      csr.mtval             <= (others => def_rst_val_c);
1881 42 zero_gravi
      --
1882 68 zero_gravi
      csr.pmpcfg            <= (others => (others => '0'));
1883
      csr.pmpaddr           <= (others => (others => def_rst_val_c));
1884 34 zero_gravi
      --
1885 68 zero_gravi
      csr.mhpmevent         <= (others => (others => def_rst_val_c));
1886 41 zero_gravi
      --
1887 68 zero_gravi
      csr.mcounteren_cy     <= def_rst_val_c;
1888
      csr.mcounteren_tm     <= def_rst_val_c;
1889
      csr.mcounteren_ir     <= def_rst_val_c;
1890 42 zero_gravi
      --
1891 56 zero_gravi
      csr.mcountinhibit_cy  <= def_rst_val_c;
1892
      csr.mcountinhibit_ir  <= def_rst_val_c;
1893
      csr.mcountinhibit_hpm <= (others => def_rst_val_c);
1894 52 zero_gravi
      --
1895 68 zero_gravi
      csr.fflags            <= (others => def_rst_val_c);
1896
      csr.frm               <= (others => def_rst_val_c);
1897 59 zero_gravi
      --
1898 68 zero_gravi
      csr.dcsr_ebreakm      <= '0';
1899
      csr.dcsr_ebreaku      <= '0';
1900
      csr.dcsr_step         <= '0';
1901
      csr.dcsr_prv          <= (others => def_rst_val_c);
1902
      csr.dcsr_cause        <= (others => def_rst_val_c);
1903
      csr.dpc               <= (others => def_rst_val_c);
1904
      csr.dscratch0         <= (others => def_rst_val_c);
1905 49 zero_gravi
 
1906 2 zero_gravi
    elsif rising_edge(clk_i) then
1907 29 zero_gravi
      -- write access? --
1908
      csr.we <= csr.we_nxt;
1909 56 zero_gravi
 
1910 36 zero_gravi
      if (CPU_EXTENSION_RISCV_Zicsr = true) then
1911
        -- --------------------------------------------------------------------------------
1912
        -- CSR access by application software
1913
        -- --------------------------------------------------------------------------------
1914 68 zero_gravi
        if (csr.we = '1') and (trap_ctrl.exc_buf(exception_iillegal_c) = '0') then -- manual write access and not illegal instruction
1915 52 zero_gravi
 
1916
          -- user floating-point CSRs --
1917
          -- --------------------------------------------------------------------
1918 56 zero_gravi
          if (CPU_EXTENSION_RISCV_Zfinx = true) then -- floating point CSR class
1919 68 zero_gravi
            if (csr.addr(11 downto 2) = csr_class_float_c) then
1920
              if (csr.addr(1 downto 0) = "01") then -- R/W: fflags - floating-point (FPU) exception flags
1921
                csr.fflags <= csr.wdata(4 downto 0);
1922
              elsif (csr.addr(1 downto 0) = "10") then -- R/W: frm - floating-point (FPU) rounding mode
1923
                csr.frm    <= csr.wdata(2 downto 0);
1924
              elsif (csr.addr(1 downto 0) = "11") then -- R/W: fcsr - floating-point (FPU) control/status (frm + fflags)
1925
                csr.frm    <= csr.wdata(7 downto 5);
1926
                csr.fflags <= csr.wdata(4 downto 0);
1927
              end if;
1928 52 zero_gravi
            end if;
1929
          end if;
1930
 
1931
          -- machine trap setup --
1932
          -- --------------------------------------------------------------------
1933 63 zero_gravi
          if (csr.addr(11 downto 3) = csr_class_setup_c) then -- trap setup CSR class
1934 52 zero_gravi
            -- R/W: mstatus - machine status register --
1935 63 zero_gravi
            if (csr.addr(2 downto 0) = csr_mstatus_c(2 downto 0)) then
1936 36 zero_gravi
              csr.mstatus_mie  <= csr.wdata(03);
1937
              csr.mstatus_mpie <= csr.wdata(07);
1938
              if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
1939
                csr.mstatus_mpp(0) <= csr.wdata(11) or csr.wdata(12);
1940
                csr.mstatus_mpp(1) <= csr.wdata(11) or csr.wdata(12);
1941
              end if;
1942 52 zero_gravi
            end if;
1943
            -- R/W: mie - machine interrupt enable register --
1944 63 zero_gravi
            if (csr.addr(2 downto 0) = csr_mie_c(2 downto 0)) then
1945 29 zero_gravi
              csr.mie_msie <= csr.wdata(03); -- machine SW IRQ enable
1946
              csr.mie_mtie <= csr.wdata(07); -- machine TIMER IRQ enable
1947
              csr.mie_meie <= csr.wdata(11); -- machine EXT IRQ enable
1948 48 zero_gravi
              for i in 0 to 15 loop -- fast interrupt channels 0..15
1949
                csr.mie_firqe(i) <= csr.wdata(16+i);
1950
              end loop; -- i
1951 52 zero_gravi
            end if;
1952
            -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) --
1953 63 zero_gravi
            if (csr.addr(2 downto 0) = csr_mtvec_c(2 downto 0)) then
1954 29 zero_gravi
              csr.mtvec <= csr.wdata(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
1955 52 zero_gravi
            end if;
1956 66 zero_gravi
            -- R/W: mcounteren - machine counter enable register --
1957 56 zero_gravi
            if (CPU_EXTENSION_RISCV_U = true) then -- this CSR is hardwired to zero if user mode is not implemented
1958 63 zero_gravi
              if (csr.addr(2 downto 0) = csr_mcounteren_c(2 downto 0)) then
1959 61 zero_gravi
                csr.mcounteren_cy <= csr.wdata(0); -- enable user-level access to cycle[h]
1960
                csr.mcounteren_tm <= csr.wdata(1); -- enable user-level access to time[h]
1961
                csr.mcounteren_ir <= csr.wdata(2); -- enable user-level access to instret[h]
1962 51 zero_gravi
              end if;
1963 52 zero_gravi
            end if;
1964
          end if;
1965 29 zero_gravi
 
1966 52 zero_gravi
          -- machine trap handling --
1967
          -- --------------------------------------------------------------------
1968 68 zero_gravi
          if (csr.addr(11 downto 3) = csr_class_trap_c) then -- machine trap handling CSR class
1969 52 zero_gravi
            -- R/W: mscratch - machine scratch register --
1970 68 zero_gravi
            if (csr.addr(2 downto 0) = csr_mscratch_c(2 downto 0)) then
1971 36 zero_gravi
              csr.mscratch <= csr.wdata;
1972 52 zero_gravi
            end if;
1973
            -- R/W: mepc - machine exception program counter --
1974 68 zero_gravi
            if (csr.addr(2 downto 0) = csr_mepc_c(2 downto 0)) then
1975 64 zero_gravi
              csr.mepc <= csr.wdata;
1976 52 zero_gravi
            end if;
1977
            -- R/W: mcause - machine trap cause --
1978 68 zero_gravi
            if (csr.addr(2 downto 0) = csr_mcause_c(2 downto 0)) then
1979
              csr.mcause(csr.mcause'left) <= csr.wdata(31); -- 1: async/interrupt, 0: sync/exception
1980 36 zero_gravi
              csr.mcause(4 downto 0)      <= csr.wdata(4 downto 0); -- identifier
1981 52 zero_gravi
            end if;
1982
          end if;
1983 29 zero_gravi
 
1984 52 zero_gravi
          -- physical memory protection: R/W: pmpcfg* - PMP configuration registers --
1985
          -- --------------------------------------------------------------------
1986 56 zero_gravi
          if (PMP_NUM_REGIONS > 0) then
1987
            if (csr.addr(11 downto 4) = csr_class_pmpcfg_c) then -- pmp configuration CSR class
1988 52 zero_gravi
              for i in 0 to PMP_NUM_REGIONS-1 loop
1989
                if (csr.addr(3 downto 0) = std_ulogic_vector(to_unsigned(i, 4))) then
1990
                  if (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpcfg access
1991
                    csr.pmpcfg(i)(0) <= csr.wdata((i mod 4)*8+0); -- R (rights.read)
1992
                    csr.pmpcfg(i)(1) <= csr.wdata((i mod 4)*8+1); -- W (rights.write)
1993
                    csr.pmpcfg(i)(2) <= csr.wdata((i mod 4)*8+2); -- X (rights.execute)
1994
                    csr.pmpcfg(i)(3) <= csr.wdata((i mod 4)*8+3) and csr.wdata((i mod 4)*8+4); -- A_L
1995
                    csr.pmpcfg(i)(4) <= csr.wdata((i mod 4)*8+3) and csr.wdata((i mod 4)*8+4); -- A_H - NAPOT/OFF only
1996
                    csr.pmpcfg(i)(5) <= '0'; -- reserved
1997
                    csr.pmpcfg(i)(6) <= '0'; -- reserved
1998
                    csr.pmpcfg(i)(7) <= csr.wdata((i mod 4)*8+7); -- L (locked / rights also enforced in m-mode)
1999 36 zero_gravi
                  end if;
2000 52 zero_gravi
                end if;
2001
              end loop; -- i (PMP regions)
2002
            end if;
2003
          end if;
2004 4 zero_gravi
 
2005 52 zero_gravi
          -- physical memory protection: R/W: pmpaddr* - PMP address registers --
2006
          -- --------------------------------------------------------------------
2007 56 zero_gravi
          if (PMP_NUM_REGIONS > 0) then
2008
            if (csr.addr(11 downto 4) =  csr_pmpaddr0_c(11 downto 4)) or (csr.addr(11 downto 4) = csr_pmpaddr16_c(11 downto 4)) or
2009
               (csr.addr(11 downto 4) = csr_pmpaddr32_c(11 downto 4)) or (csr.addr(11 downto 4) = csr_pmpaddr48_c(11 downto 4)) then
2010 52 zero_gravi
              for i in 0 to PMP_NUM_REGIONS-1 loop
2011
                if (csr.addr(6 downto 0) = std_ulogic_vector(unsigned(csr_pmpaddr0_c(6 downto 0)) + i)) and (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpaddr access
2012
                  csr.pmpaddr(i) <= csr.wdata;
2013
                  csr.pmpaddr(i)(index_size_f(PMP_MIN_GRANULARITY)-4 downto 0) <= (others => '1');
2014
                end if;
2015
              end loop; -- i (PMP regions)
2016
            end if;
2017
          end if;
2018 2 zero_gravi
 
2019 52 zero_gravi
          -- machine counter setup --
2020
          -- --------------------------------------------------------------------
2021 56 zero_gravi
          if (csr.addr(11 downto 5) = csr_cnt_setup_c) then -- counter configuration CSR class
2022
            -- R/W: mcountinhibit - machine counter-inhibit register --
2023
            if (csr.addr(4 downto 0) = csr_mcountinhibit_c(4 downto 0)) then
2024 65 zero_gravi
              csr.mcountinhibit_cy <= csr.wdata(0); -- enable auto-increment of [m]cycle[h] counter
2025
              csr.mcountinhibit_ir <= csr.wdata(2); -- enable auto-increment of [m]instret[h] counter
2026 63 zero_gravi
              if (HPM_NUM_CNTS > 0) then -- any HPMs available?
2027
                csr.mcountinhibit_hpm <= csr.wdata(csr.mcountinhibit_hpm'left+3 downto 3); -- enable auto-increment of [m]hpmcounter*[h] counter
2028
              end if;
2029 56 zero_gravi
            end if;
2030 66 zero_gravi
            -- R/W: mhpmevent - machine performance-monitors event selector --
2031
            if (HPM_NUM_CNTS > 0) and (CPU_EXTENSION_RISCV_Zihpm = true) then
2032 52 zero_gravi
              for i in 0 to HPM_NUM_CNTS-1 loop
2033
                if (csr.addr(4 downto 0) = std_ulogic_vector(to_unsigned(i+3, 5))) then
2034
                  csr.mhpmevent(i) <= csr.wdata(csr.mhpmevent(i)'left downto 0);
2035
                end if;
2036 56 zero_gravi
                csr.mhpmevent(i)(hpmcnt_event_never_c) <= '0'; -- would be used for "TIME"
2037 52 zero_gravi
              end loop; -- i (CSRs)
2038
            end if;
2039
          end if;
2040 42 zero_gravi
 
2041 59 zero_gravi
          -- debug mode CSRs --
2042
          -- --------------------------------------------------------------------
2043
          if (CPU_EXTENSION_RISCV_DEBUG = true) then
2044
            if (csr.addr(11 downto 2) = csr_class_debug_c) then -- debug CSR class
2045
              -- R/W: dcsr - debug mode control and status register --
2046
              if (csr.addr(1 downto 0) = csr_dcsr_c(1 downto 0)) then
2047
                csr.dcsr_ebreakm <= csr.wdata(15);
2048
                csr.dcsr_step    <= csr.wdata(2);
2049
                if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
2050
                  csr.dcsr_ebreaku <= csr.wdata(12);
2051 65 zero_gravi
                  csr.dcsr_prv(0)  <= csr.wdata(1) or csr.wdata(0);
2052
                  csr.dcsr_prv(1)  <= csr.wdata(1) or csr.wdata(0);
2053 59 zero_gravi
                else -- only machine mode is available
2054
                  csr.dcsr_prv <= priv_mode_m_c;
2055
                end if;
2056
              end if;
2057
              -- R/W: dpc - debug mode program counter --
2058
              if (csr.addr(1 downto 0) = csr_dpc_c(1 downto 0)) then
2059 64 zero_gravi
                csr.dpc <= csr.wdata(data_width_c-1 downto 1) & '0';
2060 59 zero_gravi
              end if;
2061
              -- R/W: dscratch0 - debug mode scratch register 0 --
2062
              if (csr.addr(1 downto 0) = csr_dscratch0_c(1 downto 0)) then
2063
                csr.dscratch0 <= csr.wdata;
2064
              end if;
2065
            end if;
2066
          end if;
2067 29 zero_gravi
 
2068 59 zero_gravi
 
2069 36 zero_gravi
        -- --------------------------------------------------------------------------------
2070
        -- CSR access by hardware
2071
        -- --------------------------------------------------------------------------------
2072
        else
2073
 
2074 52 zero_gravi
          -- floating-point (FPU) exception flags --
2075
          -- --------------------------------------------------------------------
2076 68 zero_gravi
          if (CPU_EXTENSION_RISCV_Zfinx = true) and (trap_ctrl.exc_buf(exception_iillegal_c) = '0') then -- no illegal instruction
2077 52 zero_gravi
            csr.fflags <= csr.fflags or fpu_flags_i; -- accumulate flags ("accrued exception flags")
2078
          end if;
2079
 
2080 59 zero_gravi
          -- mcause, mepc, mtval: write machine trap cause, PC and trap value register --
2081 36 zero_gravi
          -- --------------------------------------------------------------------
2082
          if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
2083 66 zero_gravi
 
2084 59 zero_gravi
            if (CPU_EXTENSION_RISCV_DEBUG = false) or ((trap_ctrl.cause(5) = '0') and -- update mtval/mepc/mcause only when NOT ENTRY debug mode exception
2085
                                                       (debug_ctrl.running = '0')) then -- and NOT IN debug mode
2086
 
2087
              -- trap cause ID code --
2088
              csr.mcause(csr.mcause'left) <= trap_ctrl.cause(trap_ctrl.cause'left); -- 1: interrupt, 0: exception
2089
              csr.mcause(4 downto 0)      <= trap_ctrl.cause(4 downto 0); -- identifier
2090
 
2091
              -- trap PC --
2092
              if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS (async source)
2093
                csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
2094
              else -- for sync. EXCEPTIONS (sync source)
2095
                csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
2096
              end if;
2097
 
2098
              -- trap value --
2099 65 zero_gravi
              cause_v := trap_ctrl.cause;
2100
              cause_v(5) := '0'; -- bit 5 is always zero here (= normal trapping), so we do not need to check that again
2101
              case cause_v is
2102 59 zero_gravi
                when trap_ima_c | trap_iba_c => -- misaligned instruction address OR instruction access error
2103
                  csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
2104
                when trap_brk_c => -- breakpoint
2105 65 zero_gravi
                  csr.mtval <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- address of breakpoint instruction
2106 59 zero_gravi
                when trap_lma_c | trap_lbe_c | trap_sma_c | trap_sbe_c => -- misaligned load/store address OR load/store access error
2107
                  csr.mtval <= mar_i; -- faulting data access address
2108
                when trap_iil_c => -- illegal instruction
2109
                  csr.mtval <= execute_engine.i_reg_last; -- faulting instruction itself
2110
                when others => -- everything else including all interrupts
2111
                  csr.mtval <= (others => '0');
2112
              end case;
2113
 
2114 40 zero_gravi
            end if;
2115 59 zero_gravi
 
2116 61 zero_gravi
            -- DEBUG MODE (trap) enter: write dpc and dcsr --
2117 59 zero_gravi
            -- --------------------------------------------------------------------
2118
            if (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.cause(5) = '1') and (debug_ctrl.running = '0') then -- debug mode entry exception
2119
 
2120
              -- trap cause ID code --
2121
              csr.dcsr_cause <= trap_ctrl.cause(2 downto 0); -- why did we enter debug mode?
2122
              -- current privilege mode when debug mode was entered --
2123
              csr.dcsr_prv <= csr.privilege;
2124
 
2125
              -- trap PC --
2126
              if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS (async source)
2127
                csr.dpc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
2128
              else -- for sync. EXCEPTIONS (sync source)
2129
                csr.dpc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
2130
              end if;
2131
 
2132
            end if;
2133
 
2134 2 zero_gravi
          end if;
2135
 
2136 36 zero_gravi
          -- mstatus: context switch --
2137
          -- --------------------------------------------------------------------
2138 59 zero_gravi
          -- ENTER: trap handling starting?
2139 66 zero_gravi
          if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
2140
 
2141 59 zero_gravi
            if (CPU_EXTENSION_RISCV_DEBUG = false) or -- normal trapping (debug mode NOT implemented)
2142
               ((debug_ctrl.running = '0') and (trap_ctrl.cause(5) = '0')) then -- not IN debug mode and not ENTERING debug mode
2143
              csr.mstatus_mie  <= '0'; -- disable interrupts
2144
              csr.mstatus_mpie <= csr.mstatus_mie; -- buffer previous mie state
2145
              if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
2146
                csr.privilege   <= priv_mode_m_c; -- execute trap in machine mode
2147
                csr.mstatus_mpp <= csr.privilege; -- buffer previous privilege mode
2148
              end if;
2149 2 zero_gravi
            end if;
2150 59 zero_gravi
 
2151
          -- EXIT: return from exception
2152
          elsif (trap_ctrl.env_end = '1') then
2153
            if (CPU_EXTENSION_RISCV_DEBUG = true) and (debug_ctrl.running = '1') then -- return from debug mode
2154
              if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
2155
                csr.privilege <= csr.dcsr_prv;
2156
              end if;
2157
            else -- return from "normal trap"
2158
              csr.mstatus_mie  <= csr.mstatus_mpie; -- restore global IRQ enable flag
2159
              csr.mstatus_mpie <= '1';
2160
              if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
2161
                csr.privilege   <= csr.mstatus_mpp; -- go back to previous privilege mode
2162 60 zero_gravi
                csr.mstatus_mpp <= (others => '0');
2163 59 zero_gravi
              end if;
2164 30 zero_gravi
            end if;
2165 2 zero_gravi
          end if;
2166 59 zero_gravi
 
2167 52 zero_gravi
        end if; -- /hardware csr access
2168
      end if;
2169 29 zero_gravi
 
2170 52 zero_gravi
      -- --------------------------------------------------------------------------------
2171
      -- override write access for disabled functions
2172
      -- --------------------------------------------------------------------------------
2173
 
2174
      -- user mode disabled --
2175
      if (CPU_EXTENSION_RISCV_U = false) then
2176 61 zero_gravi
        csr.privilege     <= priv_mode_m_c;
2177
        csr.mstatus_mpp   <= priv_mode_m_c;
2178
        csr.mcounteren_cy <= '0';
2179
        csr.mcounteren_tm <= '0';
2180
        csr.mcounteren_ir <= '0';
2181
        csr.dcsr_ebreaku  <= '0';
2182
        csr.dcsr_prv      <= priv_mode_m_c;
2183 34 zero_gravi
      end if;
2184 52 zero_gravi
 
2185
      -- pmp disabled --
2186
      if (PMP_NUM_REGIONS = 0) then
2187
        csr.pmpcfg  <= (others => (others => '0'));
2188
        csr.pmpaddr <= (others => (others => '1'));
2189
      end if;
2190
 
2191
      -- hpms disabled --
2192
      if (HPM_NUM_CNTS = 0) then
2193
        csr.mhpmevent         <= (others => (others => '0'));
2194
        csr.mcountinhibit_hpm <= (others => '0');
2195
      end if;
2196
 
2197 56 zero_gravi
      -- cpu counters disabled --
2198
      if (CPU_CNT_WIDTH = 0) then
2199
        csr.mcounteren_cy    <= '0';
2200
        csr.mcounteren_ir    <= '0';
2201
        csr.mcountinhibit_cy <= '0';
2202
        csr.mcountinhibit_ir <= '0';
2203
      end if;
2204
 
2205 52 zero_gravi
      -- floating-point extension disabled --
2206 53 zero_gravi
      if (CPU_EXTENSION_RISCV_Zfinx = false) then
2207 63 zero_gravi
        csr.fflags <= (others => '0');
2208
        csr.frm    <= (others => '0');
2209 52 zero_gravi
      end if;
2210
 
2211 59 zero_gravi
      -- debug mode disabled --
2212
      if (CPU_EXTENSION_RISCV_DEBUG = false) then
2213
        csr.dcsr_ebreakm <= '0';
2214
        csr.dcsr_ebreaku <= '0';
2215
        csr.dcsr_step    <= '0';
2216
        csr.dcsr_cause   <= (others => '0');
2217
        csr.dpc          <= (others => '0');
2218
        csr.dscratch0    <= (others => '0');
2219
      end if;
2220
 
2221 2 zero_gravi
    end if;
2222
  end process csr_write_access;
2223
 
2224 56 zero_gravi
  -- decode current privilege mode --
2225 61 zero_gravi
  csr.privilege_rd <= priv_mode_m_c when (CPU_EXTENSION_RISCV_DEBUG = true) and (debug_ctrl.running = '1') else csr.privilege; -- effective privilege mode ("machine" when in debug mode)
2226 59 zero_gravi
  csr.priv_m_mode  <= '1' when (csr.privilege_rd = priv_mode_m_c) else '0';
2227
  csr.priv_u_mode  <= '1' when (csr.privilege_rd = priv_mode_u_c) and (CPU_EXTENSION_RISCV_U = true) else '0';
2228 40 zero_gravi
 
2229 36 zero_gravi
  -- PMP configuration output to bus unit --
2230 34 zero_gravi
  pmp_output: process(csr)
2231
  begin
2232
    pmp_addr_o <= (others => (others => '0'));
2233
    pmp_ctrl_o <= (others => (others => '0'));
2234 56 zero_gravi
    if (PMP_NUM_REGIONS /= 0) then
2235
      for i in 0 to PMP_NUM_REGIONS-1 loop
2236
        pmp_addr_o(i) <= csr.pmpaddr(i) & "11";
2237
        pmp_addr_o(i)(index_size_f(PMP_MIN_GRANULARITY)-4 downto 0) <= (others => '1');
2238
        pmp_ctrl_o(i) <= csr.pmpcfg(i);
2239
      end loop; -- i
2240
    end if;
2241 42 zero_gravi
  end process pmp_output;
2242
 
2243 58 zero_gravi
  -- PMP config read dummy --
2244 42 zero_gravi
  pmp_rd_dummy: process(csr)
2245
  begin
2246
    csr.pmpcfg_rd  <= (others => (others => '0'));
2247 56 zero_gravi
    if (PMP_NUM_REGIONS /= 0) then
2248
      for i in 0 to PMP_NUM_REGIONS-1 loop
2249
        csr.pmpcfg_rd(i)  <= csr.pmpcfg(i);
2250
      end loop; -- i
2251
    end if;
2252 42 zero_gravi
  end process pmp_rd_dummy;
2253
 
2254
 
2255
  -- Control and Status Registers - Counters ------------------------------------------------
2256
  -- -------------------------------------------------------------------------------------------
2257 56 zero_gravi
  csr_counters: process(rstn_i, clk_i)
2258 42 zero_gravi
  begin
2259 68 zero_gravi
    -- Counter CSRs (each counter is split into two 32-bit counters - coupled via an MSB overflow FF)
2260 56 zero_gravi
    if (rstn_i = '0') then
2261 61 zero_gravi
      csr.mcycle           <= (others => def_rst_val_c);
2262
      csr.mcycle_ovfl      <= (others => def_rst_val_c);
2263
      csr.mcycleh          <= (others => def_rst_val_c);
2264
      csr.minstret         <= (others => def_rst_val_c);
2265
      csr.minstret_ovfl    <= (others => def_rst_val_c);
2266
      csr.minstreth        <= (others => def_rst_val_c);
2267
      csr.mhpmcounter      <= (others => (others => def_rst_val_c));
2268
      csr.mhpmcounter_ovfl <= (others => (others => def_rst_val_c));
2269
      csr.mhpmcounterh     <= (others => (others => def_rst_val_c));
2270 56 zero_gravi
    elsif rising_edge(clk_i) then
2271 42 zero_gravi
 
2272
      -- [m]cycle --
2273 66 zero_gravi
      if (cpu_cnt_lo_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then
2274 68 zero_gravi
        csr.mcycle_ovfl(0) <= csr.mcycle_nxt(csr.mcycle_nxt'left) and (not csr.mcountinhibit_cy);
2275 60 zero_gravi
        if (csr.we = '1') and (csr.addr = csr_mcycle_c) then -- write access
2276 61 zero_gravi
          csr.mcycle(cpu_cnt_lo_width_c-1 downto 0) <= csr.wdata(cpu_cnt_lo_width_c-1 downto 0);
2277 60 zero_gravi
        elsif (csr.mcountinhibit_cy = '0') and (cnt_event(hpmcnt_event_cy_c) = '1') then -- non-inhibited automatic update
2278 61 zero_gravi
          csr.mcycle(cpu_cnt_lo_width_c-1 downto 0) <= csr.mcycle_nxt(cpu_cnt_lo_width_c-1 downto 0);
2279 60 zero_gravi
        end if;
2280
      else
2281 61 zero_gravi
        csr.mcycle <= (others => '-');
2282
        csr.mcycle_ovfl(0) <= '-';
2283 42 zero_gravi
      end if;
2284
 
2285
      -- [m]cycleh --
2286 66 zero_gravi
      if (cpu_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then
2287 60 zero_gravi
        if (csr.we = '1') and (csr.addr = csr_mcycleh_c) then -- write access
2288
          csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0) <= csr.wdata(cpu_cnt_hi_width_c-1 downto 0);
2289 68 zero_gravi
        else -- automatic update
2290 61 zero_gravi
          csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0)) + unsigned(csr.mcycle_ovfl));
2291 60 zero_gravi
        end if;
2292
      else
2293
        csr.mcycleh <= (others => '-');
2294 42 zero_gravi
      end if;
2295
 
2296 60 zero_gravi
 
2297 42 zero_gravi
      -- [m]instret --
2298 66 zero_gravi
      if (cpu_cnt_lo_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then
2299 68 zero_gravi
        csr.minstret_ovfl(0) <= csr.minstret_nxt(csr.minstret_nxt'left) and (not csr.mcountinhibit_ir);
2300 60 zero_gravi
        if (csr.we = '1') and (csr.addr = csr_minstret_c) then -- write access
2301 61 zero_gravi
          csr.minstret(cpu_cnt_lo_width_c-1 downto 0) <= csr.wdata(cpu_cnt_lo_width_c-1 downto 0);
2302 60 zero_gravi
        elsif (csr.mcountinhibit_ir = '0') and (cnt_event(hpmcnt_event_ir_c) = '1') then -- non-inhibited automatic update
2303 61 zero_gravi
          csr.minstret(cpu_cnt_lo_width_c-1 downto 0) <= csr.minstret_nxt(cpu_cnt_lo_width_c-1 downto 0);
2304 60 zero_gravi
        end if;
2305
      else
2306 61 zero_gravi
        csr.minstret <= (others => '-');
2307
        csr.minstret_ovfl(0) <= '-';
2308 42 zero_gravi
      end if;
2309
 
2310
      -- [m]instreth --
2311 66 zero_gravi
      if (cpu_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then
2312 60 zero_gravi
        if (csr.we = '1') and (csr.addr = csr_minstreth_c) then -- write access
2313
          csr.minstreth(cpu_cnt_hi_width_c-1 downto 0) <= csr.wdata(cpu_cnt_hi_width_c-1 downto 0);
2314 68 zero_gravi
        else -- automatic update
2315 61 zero_gravi
          csr.minstreth(cpu_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.minstreth(cpu_cnt_hi_width_c-1 downto 0)) + unsigned(csr.minstret_ovfl));
2316 60 zero_gravi
        end if;
2317
      else
2318
        csr.minstreth <= (others => '-');
2319 42 zero_gravi
      end if;
2320
 
2321 60 zero_gravi
 
2322 45 zero_gravi
      -- [machine] hardware performance monitors (counters) --
2323 42 zero_gravi
      for i in 0 to HPM_NUM_CNTS-1 loop
2324 60 zero_gravi
 
2325
        -- [m]hpmcounter* --
2326 66 zero_gravi
        if (hpm_cnt_lo_width_c > 0) and (CPU_EXTENSION_RISCV_Zihpm = true) then
2327 68 zero_gravi
          csr.mhpmcounter_ovfl(i)(0) <= csr.mhpmcounter_nxt(i)(csr.mhpmcounter_nxt(i)'left) and (not csr.mcountinhibit_hpm(i));
2328 56 zero_gravi
          if (csr.we = '1') and (csr.addr = std_ulogic_vector(unsigned(csr_mhpmcounter3_c) + i)) then -- write access
2329 61 zero_gravi
            csr.mhpmcounter(i)(hpm_cnt_lo_width_c-1 downto 0) <= csr.wdata(hpm_cnt_lo_width_c-1 downto 0);
2330 56 zero_gravi
          elsif (csr.mcountinhibit_hpm(i) = '0') and (hpmcnt_trigger(i) = '1') then -- non-inhibited automatic update
2331 61 zero_gravi
            csr.mhpmcounter(i)(hpm_cnt_lo_width_c-1 downto 0) <= csr.mhpmcounter_nxt(i)(hpm_cnt_lo_width_c-1 downto 0);
2332 56 zero_gravi
          end if;
2333 60 zero_gravi
        else
2334 61 zero_gravi
          csr.mhpmcounter(i) <= (others => '-');
2335
          csr.mhpmcounter_ovfl(i)(0) <= '-';
2336 42 zero_gravi
        end if;
2337
 
2338
        -- [m]hpmcounter*h --
2339 66 zero_gravi
        if (hpm_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zihpm = true) then
2340 56 zero_gravi
          if (csr.we = '1') and (csr.addr = std_ulogic_vector(unsigned(csr_mhpmcounter3h_c) + i)) then -- write access
2341
            csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0) <= csr.wdata(hpm_cnt_hi_width_c-1 downto 0);
2342 68 zero_gravi
          else -- automatic update
2343 61 zero_gravi
            csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0)) + unsigned(csr.mhpmcounter_ovfl(i)));
2344 56 zero_gravi
          end if;
2345 60 zero_gravi
        else
2346
          csr.mhpmcounterh(i) <= (others => '-');
2347 42 zero_gravi
        end if;
2348 60 zero_gravi
 
2349 34 zero_gravi
      end loop; -- i
2350 42 zero_gravi
 
2351 34 zero_gravi
    end if;
2352 42 zero_gravi
  end process csr_counters;
2353 34 zero_gravi
 
2354 60 zero_gravi
 
2355 61 zero_gravi
  -- mcycle & minstret increment LOW --
2356 68 zero_gravi
  csr.mcycle_nxt   <= std_ulogic_vector(unsigned('0' & csr.mcycle)   + 1);
2357 61 zero_gravi
  csr.minstret_nxt <= std_ulogic_vector(unsigned('0' & csr.minstret) + 1);
2358
 
2359
  -- hpm counter increment LOW --
2360
  hmp_cnt_lo_inc:
2361
  for i in 0 to HPM_NUM_CNTS-1 generate
2362
    csr.mhpmcounter_nxt(i) <= std_ulogic_vector(unsigned('0' & csr.mhpmcounter(i)) + 1);
2363
  end generate;
2364
 
2365
 
2366
  -- hpm counter read --
2367 42 zero_gravi
  hpm_rd_dummy: process(csr)
2368
  begin
2369
    csr.mhpmcounter_rd  <= (others => (others => '0'));
2370
    csr.mhpmcounterh_rd <= (others => (others => '0'));
2371 66 zero_gravi
    if (HPM_NUM_CNTS /= 0) and (CPU_EXTENSION_RISCV_Zihpm = true) then
2372 56 zero_gravi
      for i in 0 to HPM_NUM_CNTS-1 loop
2373
        if (hpm_cnt_lo_width_c > 0) then
2374 59 zero_gravi
          csr.mhpmcounter_rd(i)(hpm_cnt_lo_width_c-1 downto 0) <= csr.mhpmcounter(i)(hpm_cnt_lo_width_c-1 downto 0);
2375 56 zero_gravi
        end if;
2376
        if (hpm_cnt_hi_width_c > 0) then
2377
          csr.mhpmcounterh_rd(i)(hpm_cnt_hi_width_c-1 downto 0) <= csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0);
2378
        end if;
2379
      end loop; -- i
2380
    end if;
2381 42 zero_gravi
  end process hpm_rd_dummy;
2382 34 zero_gravi
 
2383 42 zero_gravi
 
2384 56 zero_gravi
  -- Hardware Performance Monitor - Counter Event Control -----------------------------------
2385 42 zero_gravi
  -- -------------------------------------------------------------------------------------------
2386 56 zero_gravi
  hpmcnt_ctrl: process(rstn_i, clk_i)
2387 42 zero_gravi
  begin
2388 56 zero_gravi
    if (rstn_i = '0') then
2389
      hpmcnt_trigger <= (others => def_rst_val_c);
2390
    elsif rising_edge(clk_i) then
2391 47 zero_gravi
      -- enable selected triggers by ANDing actual events and according CSR configuration bits --
2392
      -- OR everything to see if counter should increment --
2393 42 zero_gravi
      hpmcnt_trigger <= (others => '0'); -- default
2394 56 zero_gravi
      if (HPM_NUM_CNTS /= 0) then
2395
        for i in 0 to HPM_NUM_CNTS-1 loop
2396 60 zero_gravi
          hpmcnt_trigger(i) <= or_reduce_f(cnt_event and csr.mhpmevent(i)(cnt_event'left downto 0));
2397 56 zero_gravi
        end loop; -- i
2398
      end if;
2399 42 zero_gravi
    end if;
2400
  end process hpmcnt_ctrl;
2401
 
2402 56 zero_gravi
  -- counter event trigger - RISC-V-specific --
2403 68 zero_gravi
  cnt_event(hpmcnt_event_cy_c)      <= not execute_engine.sleep; -- active cycle
2404
  cnt_event(hpmcnt_event_never_c)   <= '0'; -- undefined (never)
2405
  cnt_event(hpmcnt_event_ir_c)      <= '1' when (execute_engine.state = EXECUTE) else '0'; -- retired instruction
2406 42 zero_gravi
 
2407
  -- counter event trigger - custom / NEORV32-specific --
2408 68 zero_gravi
  cnt_event(hpmcnt_event_cir_c)     <= '1' when (execute_engine.state = EXECUTE)      and (execute_engine.is_ci = '1')             else '0'; -- retired compressed instruction
2409
  cnt_event(hpmcnt_event_wait_if_c) <= '1' when (fetch_engine.state   = IFETCH_ISSUE) and (fetch_engine.state_prev = IFETCH_ISSUE) else '0'; -- instruction fetch memory wait cycle
2410
  cnt_event(hpmcnt_event_wait_ii_c) <= '1' when (execute_engine.state = DISPATCH)     and (execute_engine.state_prev = DISPATCH)   else '0'; -- instruction issue wait cycle
2411
  cnt_event(hpmcnt_event_wait_mc_c) <= '1' when (execute_engine.state = ALU_WAIT)                                                  else '0'; -- multi-cycle alu-operation wait cycle
2412 42 zero_gravi
 
2413 68 zero_gravi
  cnt_event(hpmcnt_event_load_c)    <= '1' when                                          (ctrl(ctrl_bus_rd_c) = '1')               else '0'; -- load operation
2414
  cnt_event(hpmcnt_event_store_c)   <= '1' when                                          (ctrl(ctrl_bus_wr_c) = '1')               else '0'; -- store operation
2415
  cnt_event(hpmcnt_event_wait_ls_c) <= '1' when (execute_engine.state = LOADSTORE_2) and (execute_engine.state_prev = LOADSTORE_2) else '0'; -- load/store memory wait cycle
2416 42 zero_gravi
 
2417 68 zero_gravi
  cnt_event(hpmcnt_event_jump_c)    <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') else '0'; -- jump (unconditional)
2418
  cnt_event(hpmcnt_event_branch_c)  <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') else '0'; -- branch (conditional, taken or not taken)
2419
  cnt_event(hpmcnt_event_tbranch_c) <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') and (execute_engine.branch_taken = '1') else '0'; -- taken branch (conditional)
2420 42 zero_gravi
 
2421 68 zero_gravi
  cnt_event(hpmcnt_event_trap_c)    <= '1' when (trap_ctrl.env_start_ack = '1')                                    else '0'; -- entered trap
2422
  cnt_event(hpmcnt_event_illegal_c) <= '1' when (trap_ctrl.env_start_ack = '1') and (trap_ctrl.cause = trap_iil_c) else '0'; -- illegal operation
2423 42 zero_gravi
 
2424
 
2425 52 zero_gravi
  -- Control and Status Registers - Read Access ---------------------------------------------
2426 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
2427 56 zero_gravi
  csr_read_access: process(rstn_i, clk_i)
2428 64 zero_gravi
    variable csr_addr_v : std_ulogic_vector(11 downto 0);
2429 2 zero_gravi
  begin
2430 61 zero_gravi
    if rising_edge(clk_i) then
2431 35 zero_gravi
      csr.rdata <= (others => '0'); -- default output
2432 65 zero_gravi
      if (CPU_EXTENSION_RISCV_Zicsr = true) then
2433 64 zero_gravi
        csr_addr_v(11 downto 10) := csr.addr(11 downto 10);
2434
        csr_addr_v(09 downto 08) := (others => csr.addr(8)); -- !!! WARNING: MACHINE (11) and USER (00) registers ONLY !!!
2435
        csr_addr_v(07 downto 00) := csr.addr(07 downto 00);
2436
        case csr_addr_v is
2437 11 zero_gravi
 
2438 58 zero_gravi
          -- floating-point CSRs --
2439 52 zero_gravi
          -- --------------------------------------------------------------------
2440 59 zero_gravi
          when csr_fflags_c => -- fflags (r/w): floating-point (FPU) exception flags
2441
            if (CPU_EXTENSION_RISCV_Zfinx = true) then csr.rdata(4 downto 0) <= csr.fflags; else NULL; end if;
2442
          when csr_frm_c => -- frm (r/w): floating-point (FPU) rounding mode
2443
            if (CPU_EXTENSION_RISCV_Zfinx = true) then csr.rdata(2 downto 0) <= csr.frm; else NULL; end if;
2444
          when csr_fcsr_c => -- fcsr (r/w): floating-point (FPU) control/status (frm + fflags)
2445
            if (CPU_EXTENSION_RISCV_Zfinx = true) then csr.rdata(7 downto 5) <= csr.frm; csr.rdata(4 downto 0) <= csr.fflags; else NULL; end if;
2446 52 zero_gravi
 
2447 11 zero_gravi
          -- machine trap setup --
2448 59 zero_gravi
          -- --------------------------------------------------------------------
2449
          when csr_mstatus_c => -- mstatus (r/w): machine status register
2450 41 zero_gravi
            csr.rdata(03) <= csr.mstatus_mie; -- MIE
2451 27 zero_gravi
            csr.rdata(07) <= csr.mstatus_mpie; -- MPIE
2452 29 zero_gravi
            csr.rdata(11) <= csr.mstatus_mpp(0); -- MPP: machine previous privilege mode low
2453
            csr.rdata(12) <= csr.mstatus_mpp(1); -- MPP: machine previous privilege mode high
2454 59 zero_gravi
          when csr_misa_c => -- misa (r/-): ISA and extensions
2455 39 zero_gravi
            csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A);     -- A CPU extension
2456 66 zero_gravi
            csr.rdata(01) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B);     -- B CPU extension
2457 27 zero_gravi
            csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C);     -- C CPU extension
2458
            csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E);     -- E CPU extension
2459
            csr.rdata(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
2460
            csr.rdata(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M);     -- M CPU extension
2461
            csr.rdata(20) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_U);     -- U CPU extension
2462
            csr.rdata(23) <= '1';                                         -- X CPU extension (non-std extensions)
2463
            csr.rdata(30) <= '1'; -- 32-bit architecture (MXL lo)
2464
            csr.rdata(31) <= '0'; -- 32-bit architecture (MXL hi)
2465 59 zero_gravi
          when csr_mie_c => -- mie (r/w): machine interrupt-enable register
2466 27 zero_gravi
            csr.rdata(03) <= csr.mie_msie; -- machine software IRQ enable
2467
            csr.rdata(07) <= csr.mie_mtie; -- machine timer IRQ enable
2468
            csr.rdata(11) <= csr.mie_meie; -- machine external IRQ enable
2469 48 zero_gravi
            for i in 0 to 15 loop -- fast interrupt channels 0..15 enable
2470
              csr.rdata(16+i) <= csr.mie_firqe(i);
2471
            end loop; -- i
2472 59 zero_gravi
          when csr_mtvec_c => -- mtvec (r/w): machine trap-handler base address (for ALL exceptions)
2473 27 zero_gravi
            csr.rdata <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
2474 59 zero_gravi
          when csr_mcounteren_c => -- mcounteren (r/w): machine counter enable register
2475 58 zero_gravi
            if (CPU_EXTENSION_RISCV_U = false) then -- this CSR is hardwired to zero if user mode is not implemented
2476
              NULL;
2477
            else
2478 51 zero_gravi
              csr.rdata(0) <= csr.mcounteren_cy; -- enable user-level access to cycle[h]
2479
              csr.rdata(1) <= csr.mcounteren_tm; -- enable user-level access to time[h]
2480
              csr.rdata(2) <= csr.mcounteren_ir; -- enable user-level access to instret[h]
2481
            end if;
2482 11 zero_gravi
 
2483
          -- machine trap handling --
2484 59 zero_gravi
          -- --------------------------------------------------------------------
2485
          when csr_mscratch_c => -- mscratch (r/w): machine scratch register
2486 27 zero_gravi
            csr.rdata <= csr.mscratch;
2487 59 zero_gravi
          when csr_mepc_c => -- mepc (r/w): machine exception program counter
2488 27 zero_gravi
            csr.rdata <= csr.mepc(data_width_c-1 downto 1) & '0';
2489 59 zero_gravi
          when csr_mcause_c => -- mcause (r/w): machine trap cause
2490 49 zero_gravi
            csr.rdata(31) <= csr.mcause(csr.mcause'left);
2491
            csr.rdata(csr.mcause'left-1 downto 0) <= csr.mcause(csr.mcause'left-1 downto 0);
2492 62 zero_gravi
          when csr_mtval_c => -- mtval (r/-): machine bad address or instruction
2493 27 zero_gravi
            csr.rdata <= csr.mtval;
2494 59 zero_gravi
          when csr_mip_c => -- mip (r/-): machine interrupt pending
2495 58 zero_gravi
            csr.rdata(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c);
2496
            csr.rdata(07) <= trap_ctrl.irq_buf(interrupt_mtime_irq_c);
2497
            csr.rdata(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c);
2498 48 zero_gravi
            for i in 0 to 15 loop -- fast interrupt channels 0..15 pending
2499 58 zero_gravi
              csr.rdata(16+i) <= trap_ctrl.irq_buf(interrupt_firq_0_c+i);
2500 48 zero_gravi
            end loop; -- i
2501 11 zero_gravi
 
2502 63 zero_gravi
          -- physical memory protection - configuration (r/w) --
2503 59 zero_gravi
          -- --------------------------------------------------------------------
2504 63 zero_gravi
          when csr_pmpcfg0_c  => if (PMP_NUM_REGIONS > 00) then csr.rdata <= csr.pmpcfg_rd(03) & csr.pmpcfg_rd(02) & csr.pmpcfg_rd(01) & csr.pmpcfg_rd(00); else NULL; end if;
2505
          when csr_pmpcfg1_c  => if (PMP_NUM_REGIONS > 03) then csr.rdata <= csr.pmpcfg_rd(07) & csr.pmpcfg_rd(06) & csr.pmpcfg_rd(05) & csr.pmpcfg_rd(04); else NULL; end if;
2506
          when csr_pmpcfg2_c  => if (PMP_NUM_REGIONS > 07) then csr.rdata <= csr.pmpcfg_rd(11) & csr.pmpcfg_rd(10) & csr.pmpcfg_rd(09) & csr.pmpcfg_rd(08); else NULL; end if;
2507
          when csr_pmpcfg3_c  => if (PMP_NUM_REGIONS > 11) then csr.rdata <= csr.pmpcfg_rd(15) & csr.pmpcfg_rd(14) & csr.pmpcfg_rd(13) & csr.pmpcfg_rd(12); else NULL; end if;
2508
          when csr_pmpcfg4_c  => if (PMP_NUM_REGIONS > 15) then csr.rdata <= csr.pmpcfg_rd(19) & csr.pmpcfg_rd(18) & csr.pmpcfg_rd(17) & csr.pmpcfg_rd(16); else NULL; end if;
2509
          when csr_pmpcfg5_c  => if (PMP_NUM_REGIONS > 19) then csr.rdata <= csr.pmpcfg_rd(23) & csr.pmpcfg_rd(22) & csr.pmpcfg_rd(21) & csr.pmpcfg_rd(20); else NULL; end if;
2510
          when csr_pmpcfg6_c  => if (PMP_NUM_REGIONS > 23) then csr.rdata <= csr.pmpcfg_rd(27) & csr.pmpcfg_rd(26) & csr.pmpcfg_rd(25) & csr.pmpcfg_rd(24); else NULL; end if;
2511
          when csr_pmpcfg7_c  => if (PMP_NUM_REGIONS > 27) then csr.rdata <= csr.pmpcfg_rd(31) & csr.pmpcfg_rd(30) & csr.pmpcfg_rd(29) & csr.pmpcfg_rd(28); else NULL; end if;
2512
          when csr_pmpcfg8_c  => if (PMP_NUM_REGIONS > 31) then csr.rdata <= csr.pmpcfg_rd(35) & csr.pmpcfg_rd(34) & csr.pmpcfg_rd(33) & csr.pmpcfg_rd(32); else NULL; end if;
2513
          when csr_pmpcfg9_c  => if (PMP_NUM_REGIONS > 35) then csr.rdata <= csr.pmpcfg_rd(39) & csr.pmpcfg_rd(38) & csr.pmpcfg_rd(37) & csr.pmpcfg_rd(36); else NULL; end if;
2514
          when csr_pmpcfg10_c => if (PMP_NUM_REGIONS > 39) then csr.rdata <= csr.pmpcfg_rd(43) & csr.pmpcfg_rd(42) & csr.pmpcfg_rd(41) & csr.pmpcfg_rd(40); else NULL; end if;
2515
          when csr_pmpcfg11_c => if (PMP_NUM_REGIONS > 43) then csr.rdata <= csr.pmpcfg_rd(47) & csr.pmpcfg_rd(46) & csr.pmpcfg_rd(45) & csr.pmpcfg_rd(44); else NULL; end if;
2516
          when csr_pmpcfg12_c => if (PMP_NUM_REGIONS > 47) then csr.rdata <= csr.pmpcfg_rd(51) & csr.pmpcfg_rd(50) & csr.pmpcfg_rd(49) & csr.pmpcfg_rd(48); else NULL; end if;
2517
          when csr_pmpcfg13_c => if (PMP_NUM_REGIONS > 51) then csr.rdata <= csr.pmpcfg_rd(55) & csr.pmpcfg_rd(54) & csr.pmpcfg_rd(53) & csr.pmpcfg_rd(52); else NULL; end if;
2518
          when csr_pmpcfg14_c => if (PMP_NUM_REGIONS > 55) then csr.rdata <= csr.pmpcfg_rd(59) & csr.pmpcfg_rd(58) & csr.pmpcfg_rd(57) & csr.pmpcfg_rd(56); else NULL; end if;
2519
          when csr_pmpcfg15_c => if (PMP_NUM_REGIONS > 59) then csr.rdata <= csr.pmpcfg_rd(63) & csr.pmpcfg_rd(62) & csr.pmpcfg_rd(61) & csr.pmpcfg_rd(60); else NULL; end if;
2520 15 zero_gravi
 
2521 63 zero_gravi
          -- physical memory protection - addresses (r/w) --
2522 59 zero_gravi
          -- --------------------------------------------------------------------
2523 63 zero_gravi
          when csr_pmpaddr0_c  => if (PMP_NUM_REGIONS > 00) then csr.rdata <= csr.pmpaddr(00); else NULL; end if;
2524
          when csr_pmpaddr1_c  => if (PMP_NUM_REGIONS > 01) then csr.rdata <= csr.pmpaddr(01); else NULL; end if;
2525
          when csr_pmpaddr2_c  => if (PMP_NUM_REGIONS > 02) then csr.rdata <= csr.pmpaddr(02); else NULL; end if;
2526
          when csr_pmpaddr3_c  => if (PMP_NUM_REGIONS > 03) then csr.rdata <= csr.pmpaddr(03); else NULL; end if;
2527
          when csr_pmpaddr4_c  => if (PMP_NUM_REGIONS > 04) then csr.rdata <= csr.pmpaddr(04); else NULL; end if;
2528
          when csr_pmpaddr5_c  => if (PMP_NUM_REGIONS > 05) then csr.rdata <= csr.pmpaddr(05); else NULL; end if;
2529
          when csr_pmpaddr6_c  => if (PMP_NUM_REGIONS > 06) then csr.rdata <= csr.pmpaddr(06); else NULL; end if;
2530
          when csr_pmpaddr7_c  => if (PMP_NUM_REGIONS > 07) then csr.rdata <= csr.pmpaddr(07); else NULL; end if;
2531
          when csr_pmpaddr8_c  => if (PMP_NUM_REGIONS > 08) then csr.rdata <= csr.pmpaddr(08); else NULL; end if;
2532
          when csr_pmpaddr9_c  => if (PMP_NUM_REGIONS > 09) then csr.rdata <= csr.pmpaddr(09); else NULL; end if;
2533
          when csr_pmpaddr10_c => if (PMP_NUM_REGIONS > 10) then csr.rdata <= csr.pmpaddr(10); else NULL; end if;
2534
          when csr_pmpaddr11_c => if (PMP_NUM_REGIONS > 11) then csr.rdata <= csr.pmpaddr(11); else NULL; end if;
2535
          when csr_pmpaddr12_c => if (PMP_NUM_REGIONS > 12) then csr.rdata <= csr.pmpaddr(12); else NULL; end if;
2536
          when csr_pmpaddr13_c => if (PMP_NUM_REGIONS > 13) then csr.rdata <= csr.pmpaddr(13); else NULL; end if;
2537
          when csr_pmpaddr14_c => if (PMP_NUM_REGIONS > 14) then csr.rdata <= csr.pmpaddr(14); else NULL; end if;
2538
          when csr_pmpaddr15_c => if (PMP_NUM_REGIONS > 15) then csr.rdata <= csr.pmpaddr(15); else NULL; end if;
2539
          when csr_pmpaddr16_c => if (PMP_NUM_REGIONS > 16) then csr.rdata <= csr.pmpaddr(16); else NULL; end if;
2540
          when csr_pmpaddr17_c => if (PMP_NUM_REGIONS > 17) then csr.rdata <= csr.pmpaddr(17); else NULL; end if;
2541
          when csr_pmpaddr18_c => if (PMP_NUM_REGIONS > 18) then csr.rdata <= csr.pmpaddr(18); else NULL; end if;
2542
          when csr_pmpaddr19_c => if (PMP_NUM_REGIONS > 19) then csr.rdata <= csr.pmpaddr(19); else NULL; end if;
2543
          when csr_pmpaddr20_c => if (PMP_NUM_REGIONS > 20) then csr.rdata <= csr.pmpaddr(20); else NULL; end if;
2544
          when csr_pmpaddr21_c => if (PMP_NUM_REGIONS > 21) then csr.rdata <= csr.pmpaddr(21); else NULL; end if;
2545
          when csr_pmpaddr22_c => if (PMP_NUM_REGIONS > 22) then csr.rdata <= csr.pmpaddr(22); else NULL; end if;
2546
          when csr_pmpaddr23_c => if (PMP_NUM_REGIONS > 23) then csr.rdata <= csr.pmpaddr(23); else NULL; end if;
2547
          when csr_pmpaddr24_c => if (PMP_NUM_REGIONS > 24) then csr.rdata <= csr.pmpaddr(24); else NULL; end if;
2548
          when csr_pmpaddr25_c => if (PMP_NUM_REGIONS > 25) then csr.rdata <= csr.pmpaddr(25); else NULL; end if;
2549
          when csr_pmpaddr26_c => if (PMP_NUM_REGIONS > 26) then csr.rdata <= csr.pmpaddr(26); else NULL; end if;
2550
          when csr_pmpaddr27_c => if (PMP_NUM_REGIONS > 27) then csr.rdata <= csr.pmpaddr(27); else NULL; end if;
2551
          when csr_pmpaddr28_c => if (PMP_NUM_REGIONS > 28) then csr.rdata <= csr.pmpaddr(28); else NULL; end if;
2552
          when csr_pmpaddr29_c => if (PMP_NUM_REGIONS > 29) then csr.rdata <= csr.pmpaddr(29); else NULL; end if;
2553
          when csr_pmpaddr30_c => if (PMP_NUM_REGIONS > 30) then csr.rdata <= csr.pmpaddr(30); else NULL; end if;
2554
          when csr_pmpaddr31_c => if (PMP_NUM_REGIONS > 31) then csr.rdata <= csr.pmpaddr(31); else NULL; end if;
2555
          when csr_pmpaddr32_c => if (PMP_NUM_REGIONS > 32) then csr.rdata <= csr.pmpaddr(32); else NULL; end if;
2556
          when csr_pmpaddr33_c => if (PMP_NUM_REGIONS > 33) then csr.rdata <= csr.pmpaddr(33); else NULL; end if;
2557
          when csr_pmpaddr34_c => if (PMP_NUM_REGIONS > 34) then csr.rdata <= csr.pmpaddr(34); else NULL; end if;
2558
          when csr_pmpaddr35_c => if (PMP_NUM_REGIONS > 35) then csr.rdata <= csr.pmpaddr(35); else NULL; end if;
2559
          when csr_pmpaddr36_c => if (PMP_NUM_REGIONS > 36) then csr.rdata <= csr.pmpaddr(36); else NULL; end if;
2560
          when csr_pmpaddr37_c => if (PMP_NUM_REGIONS > 37) then csr.rdata <= csr.pmpaddr(37); else NULL; end if;
2561
          when csr_pmpaddr38_c => if (PMP_NUM_REGIONS > 38) then csr.rdata <= csr.pmpaddr(38); else NULL; end if;
2562
          when csr_pmpaddr39_c => if (PMP_NUM_REGIONS > 39) then csr.rdata <= csr.pmpaddr(39); else NULL; end if;
2563
          when csr_pmpaddr40_c => if (PMP_NUM_REGIONS > 40) then csr.rdata <= csr.pmpaddr(40); else NULL; end if;
2564
          when csr_pmpaddr41_c => if (PMP_NUM_REGIONS > 41) then csr.rdata <= csr.pmpaddr(41); else NULL; end if;
2565
          when csr_pmpaddr42_c => if (PMP_NUM_REGIONS > 42) then csr.rdata <= csr.pmpaddr(42); else NULL; end if;
2566
          when csr_pmpaddr43_c => if (PMP_NUM_REGIONS > 43) then csr.rdata <= csr.pmpaddr(43); else NULL; end if;
2567
          when csr_pmpaddr44_c => if (PMP_NUM_REGIONS > 44) then csr.rdata <= csr.pmpaddr(44); else NULL; end if;
2568
          when csr_pmpaddr45_c => if (PMP_NUM_REGIONS > 45) then csr.rdata <= csr.pmpaddr(45); else NULL; end if;
2569
          when csr_pmpaddr46_c => if (PMP_NUM_REGIONS > 46) then csr.rdata <= csr.pmpaddr(46); else NULL; end if;
2570
          when csr_pmpaddr47_c => if (PMP_NUM_REGIONS > 47) then csr.rdata <= csr.pmpaddr(47); else NULL; end if;
2571
          when csr_pmpaddr48_c => if (PMP_NUM_REGIONS > 48) then csr.rdata <= csr.pmpaddr(48); else NULL; end if;
2572
          when csr_pmpaddr49_c => if (PMP_NUM_REGIONS > 49) then csr.rdata <= csr.pmpaddr(49); else NULL; end if;
2573
          when csr_pmpaddr50_c => if (PMP_NUM_REGIONS > 50) then csr.rdata <= csr.pmpaddr(50); else NULL; end if;
2574
          when csr_pmpaddr51_c => if (PMP_NUM_REGIONS > 51) then csr.rdata <= csr.pmpaddr(51); else NULL; end if;
2575
          when csr_pmpaddr52_c => if (PMP_NUM_REGIONS > 52) then csr.rdata <= csr.pmpaddr(52); else NULL; end if;
2576
          when csr_pmpaddr53_c => if (PMP_NUM_REGIONS > 53) then csr.rdata <= csr.pmpaddr(53); else NULL; end if;
2577
          when csr_pmpaddr54_c => if (PMP_NUM_REGIONS > 54) then csr.rdata <= csr.pmpaddr(54); else NULL; end if;
2578
          when csr_pmpaddr55_c => if (PMP_NUM_REGIONS > 55) then csr.rdata <= csr.pmpaddr(55); else NULL; end if;
2579
          when csr_pmpaddr56_c => if (PMP_NUM_REGIONS > 56) then csr.rdata <= csr.pmpaddr(56); else NULL; end if;
2580
          when csr_pmpaddr57_c => if (PMP_NUM_REGIONS > 57) then csr.rdata <= csr.pmpaddr(57); else NULL; end if;
2581
          when csr_pmpaddr58_c => if (PMP_NUM_REGIONS > 58) then csr.rdata <= csr.pmpaddr(58); else NULL; end if;
2582
          when csr_pmpaddr59_c => if (PMP_NUM_REGIONS > 59) then csr.rdata <= csr.pmpaddr(59); else NULL; end if;
2583
          when csr_pmpaddr60_c => if (PMP_NUM_REGIONS > 60) then csr.rdata <= csr.pmpaddr(60); else NULL; end if;
2584
          when csr_pmpaddr61_c => if (PMP_NUM_REGIONS > 61) then csr.rdata <= csr.pmpaddr(61); else NULL; end if;
2585
          when csr_pmpaddr62_c => if (PMP_NUM_REGIONS > 62) then csr.rdata <= csr.pmpaddr(62); else NULL; end if;
2586
          when csr_pmpaddr63_c => if (PMP_NUM_REGIONS > 63) then csr.rdata <= csr.pmpaddr(63); else NULL; end if;
2587 15 zero_gravi
 
2588 41 zero_gravi
          -- machine counter setup --
2589
          -- --------------------------------------------------------------------
2590 59 zero_gravi
          when csr_mcountinhibit_c => -- mcountinhibit (r/w): machine counter-inhibit register
2591 41 zero_gravi
            csr.rdata(0) <= csr.mcountinhibit_cy; -- enable auto-increment of [m]cycle[h] counter
2592
            csr.rdata(2) <= csr.mcountinhibit_ir; -- enable auto-increment of [m]instret[h] counter
2593 63 zero_gravi
            if (HPM_NUM_CNTS > 0) then -- any HPMs available?
2594
              csr.rdata(csr.mcountinhibit_hpm'left+3 downto 3) <= csr.mcountinhibit_hpm; -- enable auto-increment of [m]hpmcounterx[h] counter
2595
            end if;
2596 41 zero_gravi
 
2597 63 zero_gravi
          -- machine performance-monitoring event selector (r/w) --
2598 59 zero_gravi
          -- --------------------------------------------------------------------
2599 66 zero_gravi
          when csr_mhpmevent3_c  => if (HPM_NUM_CNTS > 00) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(00); else NULL; end if;
2600
          when csr_mhpmevent4_c  => if (HPM_NUM_CNTS > 01) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(01); else NULL; end if;
2601
          when csr_mhpmevent5_c  => if (HPM_NUM_CNTS > 02) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(02); else NULL; end if;
2602
          when csr_mhpmevent6_c  => if (HPM_NUM_CNTS > 03) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(03); else NULL; end if;
2603
          when csr_mhpmevent7_c  => if (HPM_NUM_CNTS > 04) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(04); else NULL; end if;
2604
          when csr_mhpmevent8_c  => if (HPM_NUM_CNTS > 05) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(05); else NULL; end if;
2605
          when csr_mhpmevent9_c  => if (HPM_NUM_CNTS > 06) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(06); else NULL; end if;
2606
          when csr_mhpmevent10_c => if (HPM_NUM_CNTS > 07) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(07); else NULL; end if;
2607
          when csr_mhpmevent11_c => if (HPM_NUM_CNTS > 08) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(08); else NULL; end if;
2608
          when csr_mhpmevent12_c => if (HPM_NUM_CNTS > 09) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(09); else NULL; end if;
2609
          when csr_mhpmevent13_c => if (HPM_NUM_CNTS > 10) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(10); else NULL; end if;
2610
          when csr_mhpmevent14_c => if (HPM_NUM_CNTS > 11) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(11); else NULL; end if;
2611
          when csr_mhpmevent15_c => if (HPM_NUM_CNTS > 12) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(12); else NULL; end if;
2612
          when csr_mhpmevent16_c => if (HPM_NUM_CNTS > 13) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(13); else NULL; end if;
2613
          when csr_mhpmevent17_c => if (HPM_NUM_CNTS > 14) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(14); else NULL; end if;
2614
          when csr_mhpmevent18_c => if (HPM_NUM_CNTS > 15) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(15); else NULL; end if;
2615
          when csr_mhpmevent19_c => if (HPM_NUM_CNTS > 16) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(16); else NULL; end if;
2616
          when csr_mhpmevent20_c => if (HPM_NUM_CNTS > 17) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(17); else NULL; end if;
2617
          when csr_mhpmevent21_c => if (HPM_NUM_CNTS > 18) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(18); else NULL; end if;
2618
          when csr_mhpmevent22_c => if (HPM_NUM_CNTS > 19) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(19); else NULL; end if;
2619
          when csr_mhpmevent23_c => if (HPM_NUM_CNTS > 20) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(20); else NULL; end if;
2620
          when csr_mhpmevent24_c => if (HPM_NUM_CNTS > 21) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(21); else NULL; end if;
2621
          when csr_mhpmevent25_c => if (HPM_NUM_CNTS > 22) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(22); else NULL; end if;
2622
          when csr_mhpmevent26_c => if (HPM_NUM_CNTS > 23) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(23); else NULL; end if;
2623
          when csr_mhpmevent27_c => if (HPM_NUM_CNTS > 24) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(24); else NULL; end if;
2624
          when csr_mhpmevent28_c => if (HPM_NUM_CNTS > 25) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(25); else NULL; end if;
2625
          when csr_mhpmevent29_c => if (HPM_NUM_CNTS > 26) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(26); else NULL; end if;
2626
          when csr_mhpmevent30_c => if (HPM_NUM_CNTS > 27) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(27); else NULL; end if;
2627
          when csr_mhpmevent31_c => if (HPM_NUM_CNTS > 28) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(28); else NULL; end if;
2628 42 zero_gravi
 
2629 29 zero_gravi
          -- counters and timers --
2630 59 zero_gravi
          -- --------------------------------------------------------------------
2631
          when csr_cycle_c | csr_mcycle_c => -- [m]cycle (r/w): Cycle counter LOW
2632 66 zero_gravi
            if (cpu_cnt_lo_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then csr.rdata(cpu_cnt_lo_width_c-1 downto 0) <= csr.mcycle(cpu_cnt_lo_width_c-1 downto 0); else NULL; end if;
2633 59 zero_gravi
          when csr_cycleh_c | csr_mcycleh_c => -- [m]cycleh (r/w): Cycle counter HIGH
2634 66 zero_gravi
            if (cpu_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then csr.rdata(cpu_cnt_hi_width_c-1 downto 0) <= csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0); else NULL; end if;
2635 58 zero_gravi
 
2636 59 zero_gravi
          when csr_instret_c | csr_minstret_c => -- [m]instret (r/w): Instructions-retired counter LOW
2637 66 zero_gravi
            if (cpu_cnt_lo_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then csr.rdata(cpu_cnt_lo_width_c-1 downto 0) <= csr.minstret(cpu_cnt_lo_width_c-1 downto 0); else NULL; end if;
2638 59 zero_gravi
          when csr_instreth_c | csr_minstreth_c => -- [m]instreth (r/w): Instructions-retired counter HIGH
2639 66 zero_gravi
            if (cpu_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then csr.rdata(cpu_cnt_hi_width_c-1 downto 0) <= csr.minstreth(cpu_cnt_hi_width_c-1 downto 0); else NULL; end if;
2640 58 zero_gravi
 
2641 66 zero_gravi
          when csr_time_c => -- time (r/-): System time LOW (from MTIME unit)
2642
            if (CPU_EXTENSION_RISCV_Zicntr = true) then csr.rdata <= time_i(31 downto 00); else NULL; end if;
2643
          when csr_timeh_c => -- timeh (r/-): System time HIGH (from MTIME unit)
2644
            if (CPU_EXTENSION_RISCV_Zicntr = true) then csr.rdata <= time_i(63 downto 32); else NULL; end if;
2645 11 zero_gravi
 
2646 42 zero_gravi
          -- hardware performance counters --
2647 59 zero_gravi
          -- --------------------------------------------------------------------
2648 63 zero_gravi
          -- low word (r/w) --
2649 66 zero_gravi
          when csr_mhpmcounter3_c   => if (HPM_NUM_CNTS > 00) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(00); else NULL; end if;
2650
          when csr_mhpmcounter4_c   => if (HPM_NUM_CNTS > 01) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(01); else NULL; end if;
2651
          when csr_mhpmcounter5_c   => if (HPM_NUM_CNTS > 02) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(02); else NULL; end if;
2652
          when csr_mhpmcounter6_c   => if (HPM_NUM_CNTS > 03) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(03); else NULL; end if;
2653
          when csr_mhpmcounter7_c   => if (HPM_NUM_CNTS > 04) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(04); else NULL; end if;
2654
          when csr_mhpmcounter8_c   => if (HPM_NUM_CNTS > 05) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(05); else NULL; end if;
2655
          when csr_mhpmcounter9_c   => if (HPM_NUM_CNTS > 06) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(06); else NULL; end if;
2656
          when csr_mhpmcounter10_c  => if (HPM_NUM_CNTS > 07) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(07); else NULL; end if;
2657
          when csr_mhpmcounter11_c  => if (HPM_NUM_CNTS > 08) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(08); else NULL; end if;
2658
          when csr_mhpmcounter12_c  => if (HPM_NUM_CNTS > 09) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(09); else NULL; end if;
2659
          when csr_mhpmcounter13_c  => if (HPM_NUM_CNTS > 10) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(10); else NULL; end if;
2660
          when csr_mhpmcounter14_c  => if (HPM_NUM_CNTS > 11) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(11); else NULL; end if;
2661
          when csr_mhpmcounter15_c  => if (HPM_NUM_CNTS > 12) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(12); else NULL; end if;
2662
          when csr_mhpmcounter16_c  => if (HPM_NUM_CNTS > 13) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(13); else NULL; end if;
2663
          when csr_mhpmcounter17_c  => if (HPM_NUM_CNTS > 14) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(14); else NULL; end if;
2664
          when csr_mhpmcounter18_c  => if (HPM_NUM_CNTS > 15) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(15); else NULL; end if;
2665
          when csr_mhpmcounter19_c  => if (HPM_NUM_CNTS > 16) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(16); else NULL; end if;
2666
          when csr_mhpmcounter20_c  => if (HPM_NUM_CNTS > 17) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(17); else NULL; end if;
2667
          when csr_mhpmcounter21_c  => if (HPM_NUM_CNTS > 18) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(18); else NULL; end if;
2668
          when csr_mhpmcounter22_c  => if (HPM_NUM_CNTS > 19) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(19); else NULL; end if;
2669
          when csr_mhpmcounter23_c  => if (HPM_NUM_CNTS > 20) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(20); else NULL; end if;
2670
          when csr_mhpmcounter24_c  => if (HPM_NUM_CNTS > 21) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(21); else NULL; end if;
2671
          when csr_mhpmcounter25_c  => if (HPM_NUM_CNTS > 22) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(22); else NULL; end if;
2672
          when csr_mhpmcounter26_c  => if (HPM_NUM_CNTS > 23) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(23); else NULL; end if;
2673
          when csr_mhpmcounter27_c  => if (HPM_NUM_CNTS > 24) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(24); else NULL; end if;
2674
          when csr_mhpmcounter28_c  => if (HPM_NUM_CNTS > 25) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(25); else NULL; end if;
2675
          when csr_mhpmcounter29_c  => if (HPM_NUM_CNTS > 26) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(26); else NULL; end if;
2676
          when csr_mhpmcounter30_c  => if (HPM_NUM_CNTS > 27) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(27); else NULL; end if;
2677
          when csr_mhpmcounter31_c  => if (HPM_NUM_CNTS > 28) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(28); else NULL; end if;
2678 63 zero_gravi
          -- high word (r/w) --
2679 66 zero_gravi
          when csr_mhpmcounter3h_c  => if (HPM_NUM_CNTS > 00) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(00); else NULL; end if;
2680
          when csr_mhpmcounter4h_c  => if (HPM_NUM_CNTS > 01) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(01); else NULL; end if;
2681
          when csr_mhpmcounter5h_c  => if (HPM_NUM_CNTS > 02) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(02); else NULL; end if;
2682
          when csr_mhpmcounter6h_c  => if (HPM_NUM_CNTS > 03) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(03); else NULL; end if;
2683
          when csr_mhpmcounter7h_c  => if (HPM_NUM_CNTS > 04) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(04); else NULL; end if;
2684
          when csr_mhpmcounter8h_c  => if (HPM_NUM_CNTS > 05) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(05); else NULL; end if;
2685
          when csr_mhpmcounter9h_c  => if (HPM_NUM_CNTS > 06) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(06); else NULL; end if;
2686
          when csr_mhpmcounter10h_c => if (HPM_NUM_CNTS > 07) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(07); else NULL; end if;
2687
          when csr_mhpmcounter11h_c => if (HPM_NUM_CNTS > 08) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(08); else NULL; end if;
2688
          when csr_mhpmcounter12h_c => if (HPM_NUM_CNTS > 09) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(09); else NULL; end if;
2689
          when csr_mhpmcounter13h_c => if (HPM_NUM_CNTS > 10) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(10); else NULL; end if;
2690
          when csr_mhpmcounter14h_c => if (HPM_NUM_CNTS > 11) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(11); else NULL; end if;
2691
          when csr_mhpmcounter15h_c => if (HPM_NUM_CNTS > 12) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(12); else NULL; end if;
2692
          when csr_mhpmcounter16h_c => if (HPM_NUM_CNTS > 13) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(13); else NULL; end if;
2693
          when csr_mhpmcounter17h_c => if (HPM_NUM_CNTS > 14) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(14); else NULL; end if;
2694
          when csr_mhpmcounter18h_c => if (HPM_NUM_CNTS > 15) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(15); else NULL; end if;
2695
          when csr_mhpmcounter19h_c => if (HPM_NUM_CNTS > 16) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(16); else NULL; end if;
2696
          when csr_mhpmcounter20h_c => if (HPM_NUM_CNTS > 17) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(17); else NULL; end if;
2697
          when csr_mhpmcounter21h_c => if (HPM_NUM_CNTS > 18) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(18); else NULL; end if;
2698
          when csr_mhpmcounter22h_c => if (HPM_NUM_CNTS > 19) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(19); else NULL; end if;
2699
          when csr_mhpmcounter23h_c => if (HPM_NUM_CNTS > 20) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(20); else NULL; end if;
2700
          when csr_mhpmcounter24h_c => if (HPM_NUM_CNTS > 21) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(21); else NULL; end if;
2701
          when csr_mhpmcounter25h_c => if (HPM_NUM_CNTS > 22) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(22); else NULL; end if;
2702
          when csr_mhpmcounter26h_c => if (HPM_NUM_CNTS > 23) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(23); else NULL; end if;
2703
          when csr_mhpmcounter27h_c => if (HPM_NUM_CNTS > 24) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(24); else NULL; end if;
2704
          when csr_mhpmcounter28h_c => if (HPM_NUM_CNTS > 25) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(25); else NULL; end if;
2705
          when csr_mhpmcounter29h_c => if (HPM_NUM_CNTS > 26) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(26); else NULL; end if;
2706
          when csr_mhpmcounter30h_c => if (HPM_NUM_CNTS > 27) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(27); else NULL; end if;
2707
          when csr_mhpmcounter31h_c => if (HPM_NUM_CNTS > 28) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(28); else NULL; end if;
2708 42 zero_gravi
 
2709 11 zero_gravi
          -- machine information registers --
2710 59 zero_gravi
          -- --------------------------------------------------------------------
2711 63 zero_gravi
--        when csr_mvendorid_c  => NULL; -- mvendorid (r/-): vendor ID, implemented but always zero
2712 62 zero_gravi
          when csr_marchid_c    => csr.rdata(4 downto 0) <= "10011"; -- marchid (r/-): arch ID - official RISC-V open-source arch ID
2713
          when csr_mimpid_c     => csr.rdata <= hw_version_c; -- mimpid (r/-): implementation ID -- NEORV32 hardware version
2714
          when csr_mhartid_c    => csr.rdata <= std_ulogic_vector(to_unsigned(HW_THREAD_ID, 32)); -- mhartid (r/-): hardware thread ID
2715 65 zero_gravi
--        when csr_mconfigptr_c => NULL; -- mconfigptr (r/-): machine configuration pointer register, implemented but always zero
2716 11 zero_gravi
 
2717 59 zero_gravi
          -- debug mode CSRs --
2718
          -- --------------------------------------------------------------------
2719
          when csr_dcsr_c      => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= csr.dcsr_rd;   else NULL; end if; -- dcsr (r/w): debug mode control and status
2720
          when csr_dpc_c       => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= csr.dpc;       else NULL; end if; -- dpc (r/w): debug mode program counter
2721
          when csr_dscratch0_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= csr.dscratch0; else NULL; end if; -- dscratch0 (r/w): debug mode scratch register 0
2722
 
2723 11 zero_gravi
          -- undefined/unavailable --
2724 59 zero_gravi
          -- --------------------------------------------------------------------
2725 11 zero_gravi
          when others =>
2726 65 zero_gravi
            NULL; -- not implemented, read as zero
2727 11 zero_gravi
 
2728
        end case;
2729 2 zero_gravi
      end if;
2730
    end if;
2731
  end process csr_read_access;
2732
 
2733 27 zero_gravi
  -- CSR read data output --
2734
  csr_rdata_o <= csr.rdata;
2735
 
2736 12 zero_gravi
 
2737 59 zero_gravi
  -- Debug Control --------------------------------------------------------------------------
2738
  -- -------------------------------------------------------------------------------------------
2739
  debug_control: process(rstn_i, clk_i)
2740
  begin
2741
    if (rstn_i = '0') then
2742 68 zero_gravi
      debug_ctrl.state <= DEBUG_OFFLINE;
2743 64 zero_gravi
      debug_ctrl.ext_halt_req <= '0';
2744 59 zero_gravi
    elsif rising_edge(clk_i) then
2745
      if (CPU_EXTENSION_RISCV_DEBUG = true) then
2746
 
2747 68 zero_gravi
        -- external halt request (from Debug Module) --
2748 64 zero_gravi
        debug_ctrl.ext_halt_req <= db_halt_req_i;
2749 59 zero_gravi
 
2750
        -- state machine --
2751
        case debug_ctrl.state is
2752
 
2753
          when DEBUG_OFFLINE => -- not in debug mode, waiting for entering request
2754
            if (debug_ctrl.trig_halt = '1') or -- external request (from DM)
2755
               (debug_ctrl.trig_break = '1') or -- ebreak instruction
2756
               (debug_ctrl.trig_step = '1') then -- single-stepping mode
2757
              debug_ctrl.state <= DEBUG_PENDING;
2758
            end if;
2759
 
2760
          when DEBUG_PENDING => -- waiting to start debug mode
2761
            if (trap_ctrl.env_start_ack = '1') and (trap_ctrl.cause(5) = '1') then -- processing trap entry into debug mode
2762
              debug_ctrl.state <= DEBUG_ONLINE;
2763
            end if;
2764
 
2765
          when DEBUG_ONLINE => -- we are in debug mode
2766
            if (debug_ctrl.dret = '1') then -- DRET instruction
2767
              debug_ctrl.state <= DEBUG_EXIT;
2768
            end if;
2769
 
2770
          when DEBUG_EXIT => -- leaving debug mode
2771
            if (execute_engine.state = TRAP_EXECUTE) then -- processing trap exit
2772
              debug_ctrl.state <= DEBUG_OFFLINE;
2773
            end if;
2774
 
2775
          when others => -- undefined
2776
            debug_ctrl.state <= DEBUG_OFFLINE;
2777
 
2778
        end case;
2779
      else -- debug mode NOT implemented
2780 68 zero_gravi
        debug_ctrl.state <= DEBUG_OFFLINE;
2781 64 zero_gravi
        debug_ctrl.ext_halt_req <= '0';
2782 59 zero_gravi
      end if;
2783
    end if;
2784
  end process debug_control;
2785
 
2786
  -- state decoding --
2787
  debug_ctrl.pending <= '1' when (debug_ctrl.state = DEBUG_PENDING) and (CPU_EXTENSION_RISCV_DEBUG = true) else '0';
2788
  debug_ctrl.running <= '1' when ((debug_ctrl.state = DEBUG_ONLINE) or (debug_ctrl.state = DEBUG_EXIT)) and (CPU_EXTENSION_RISCV_DEBUG = true) else '0';
2789
 
2790
  -- entry debug mode triggers --
2791
  debug_ctrl.trig_break <= trap_ctrl.break_point and (debug_ctrl.running or -- we are in debug mode: re-enter debug mode
2792 60 zero_gravi
                           (csr.priv_m_mode and csr.dcsr_ebreakm and (not debug_ctrl.running)) or -- enabled goto-debug-mode in machine mode on "ebreak"
2793
                           (csr.priv_u_mode and csr.dcsr_ebreaku and (not debug_ctrl.running))); -- enabled goto-debug-mode in user mode on "ebreak"
2794 64 zero_gravi
  debug_ctrl.trig_halt <= debug_ctrl.ext_halt_req and (not debug_ctrl.running); -- external halt request (if not halted already)
2795 59 zero_gravi
  debug_ctrl.trig_step <= csr.dcsr_step and (not debug_ctrl.running); -- single-step mode (trigger when NOT CURRENTLY in debug mode)
2796
 
2797
 
2798
  -- Debug Control and Status Register (dcsr) - Read-Back -----------------------------------
2799
  -- -------------------------------------------------------------------------------------------
2800
  dcsr_readback_false:
2801
  if (CPU_EXTENSION_RISCV_DEBUG = false) generate
2802 60 zero_gravi
    csr.dcsr_rd <= (others => '-');
2803 59 zero_gravi
  end generate;
2804
 
2805
  dcsr_readback_true:
2806
  if (CPU_EXTENSION_RISCV_DEBUG = true) generate
2807
    csr.dcsr_rd(31 downto 28) <= "0100"; -- xdebugver: external debug support compatible to spec
2808
    csr.dcsr_rd(27 downto 16) <= (others => '0'); -- reserved
2809
    csr.dcsr_rd(15) <= csr.dcsr_ebreakm; -- ebreakm: what happens on ebreak in m-mode? (normal trap OR debug-enter)
2810 68 zero_gravi
    csr.dcsr_rd(14) <= '0'; -- ebreakh: hypervisor mode not implemented
2811
    csr.dcsr_rd(13) <= '0'; -- ebreaks: supervisor mode not implemented
2812 59 zero_gravi
    csr.dcsr_rd(12) <= csr.dcsr_ebreaku when (CPU_EXTENSION_RISCV_U = true) else '0'; -- ebreaku: what happens on ebreak in u-mode? (normal trap OR debug-enter)
2813 60 zero_gravi
    csr.dcsr_rd(11) <= '0'; -- stepie: interrupts are disabled during single-stepping
2814 59 zero_gravi
    csr.dcsr_rd(10) <= '0'; -- stopcount: counters increment as usual FIXME ???
2815 60 zero_gravi
    csr.dcsr_rd(09) <= '0'; -- stoptime: timers increment as usual
2816
    csr.dcsr_rd(08 downto 06) <= csr.dcsr_cause; -- debug mode entry cause
2817 59 zero_gravi
    csr.dcsr_rd(05) <= '0'; -- reserved
2818
    csr.dcsr_rd(04) <= '0'; -- mprven: mstatus.mprv is ignored in debug mode
2819 64 zero_gravi
    csr.dcsr_rd(03) <= '0'; -- nmip: pending non-maskable interrupt
2820 59 zero_gravi
    csr.dcsr_rd(02) <= csr.dcsr_step; -- step: single-step mode
2821
    csr.dcsr_rd(01 downto 00) <= csr.dcsr_prv; -- prv: privilege mode when debug mode was entered
2822
  end generate;
2823
 
2824
 
2825 2 zero_gravi
end neorv32_cpu_control_rtl;

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