Subversion Repositories neorv32

-- #################################################################################################

-- # << NEORV32 - CPU Co-Processor: Single-Prec. Floating Point Unit (RISC-V "Zfinx" Extension) >> #

-- # ********************************************************************************************* #

-- # The Zfinx floating-point extension uses the integer register file (x) for all FP operations.  #

-- # See the official RISC-V specs (https://github.com/riscv/riscv-zfinx) for more information.    #

-- #                                                                                               #

-- # Design Notes:                                                                                 #

-- # * This FPU is based on a multi-cycle architecture and is NOT suited for pipelined operations. #

-- # * The hardware design goal was SIZE (performance comes second). All shift operations are done #

-- #   using an iterative approach (one bit per clock cycle, no barrel shifters!).                 #

-- # * Multiplication (FMUL instruction) will infer DSP blocks (if available).                     #

-- # * Subnormal numbers are not supported yet - they are "flushed to zero" before entering the    #

-- #   actual FPU core.                                                                            #

-- # * Division and sqare root operations (FDIV, FSQRT) and fused multiply-accumulate operations   #

-- #   (F[N]MADD) are not supported yet - they will raise an illegal instruction exception.        #

-- # * Rounding mode <100> ("round to nearest, ties to max magnitude") is not supported yet.       #

-- # * Signaling NaNs (sNaN) will not be generated by the hardware at all. However, if inserted by #

-- #   the programmer they are handled correctly.                                                  #

-- # ********************************************************************************************* #

-- # BSD 3-Clause License                                                                          #

-- #                                                                                               #

-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #

-- #                                                                                               #

-- # Redistribution and use in source and binary forms, with or without modification, are          #

-- # permitted provided that the following conditions are met:                                     #

-- #                                                                                               #

-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #

-- #    conditions and the following disclaimer.                                                   #

-- #                                                                                               #

-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #

-- #    conditions and the following disclaimer in the documentation and/or other materials        #

-- #    provided with the distribution.                                                            #

-- #                                                                                               #

-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #

-- #    endorse or promote products derived from this software without specific prior written      #

-- #    permission.                                                                                #

-- #                                                                                               #

-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #

-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #

-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #

-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #

-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #

-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #

-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #

-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #

-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #

-- # ********************************************************************************************* #

-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #

-- #################################################################################################

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

library neorv32;

use neorv32.neorv32_package.all;

entity neorv32_cpu_cp_fpu is

  port (

    -- global control --

    clk_i    : in  std_ulogic; -- global clock, rising edge

    rstn_i   : in  std_ulogic; -- global reset, low-active, async

    ctrl_i   : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus

    start_i  : in  std_ulogic; -- trigger operation

    -- data input --

    frm_i    : in  std_ulogic_vector(2 downto 0); -- rounding mode

    rs1_i    : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1

    rs2_i    : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2

    -- result and status --

    res_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result

    fflags_o : out std_ulogic_vector(4 downto 0); -- exception flags

    valid_o  : out std_ulogic -- data output valid

  );

end neorv32_cpu_cp_fpu;

architecture neorv32_cpu_cp_fpu_rtl of neorv32_cpu_cp_fpu is

  -- FPU core functions --

  constant op_class_c  : std_ulogic_vector(2 downto 0) := "000";

  constant op_comp_c   : std_ulogic_vector(2 downto 0) := "001";

  constant op_i2f_c    : std_ulogic_vector(2 downto 0) := "010";

  constant op_f2i_c    : std_ulogic_vector(2 downto 0) := "011";

  constant op_sgnj_c   : std_ulogic_vector(2 downto 0) := "100";

  constant op_minmax_c : std_ulogic_vector(2 downto 0) := "101";

  constant op_addsub_c : std_ulogic_vector(2 downto 0) := "110";

  constant op_mul_c    : std_ulogic_vector(2 downto 0) := "111";

  -- float-to-integer unit --

  component neorv32_cpu_cp_fpu_f2i

  port (

    -- control --

    clk_i      : in  std_ulogic; -- global clock, rising edge

    rstn_i     : in  std_ulogic; -- global reset, low-active, async

    start_i    : in  std_ulogic; -- trigger operation

    rmode_i    : in  std_ulogic_vector(02 downto 0); -- rounding mode

    funct_i    : in  std_ulogic; -- 0=signed, 1=unsigned

    -- input --

    sign_i     : in  std_ulogic; -- sign

    exponent_i : in  std_ulogic_vector(07 downto 0); -- exponent

    mantissa_i : in  std_ulogic_vector(22 downto 0); -- mantissa

    class_i    : in  std_ulogic_vector(09 downto 0); -- operand class

    -- output --

    result_o   : out std_ulogic_vector(31 downto 0); -- integer result

    flags_o    : out std_ulogic_vector(04 downto 0); -- exception flags

    done_o     : out std_ulogic -- operation done

  );

  end component;

  -- normalizer + rounding unit --

  component neorv32_cpu_cp_fpu_normalizer

  port (

    -- control --

    clk_i      : in  std_ulogic; -- global clock, rising edge

    rstn_i     : in  std_ulogic; -- global reset, low-active, async

    start_i    : in  std_ulogic; -- trigger operation

    rmode_i    : in  std_ulogic_vector(02 downto 0); -- rounding mode

    funct_i    : in  std_ulogic; -- operating mode (0=norm&round, 1=int-to-float)

    -- input --

    sign_i     : in  std_ulogic; -- sign

    exponent_i : in  std_ulogic_vector(08 downto 0); -- extended exponent

    mantissa_i : in  std_ulogic_vector(47 downto 0); -- extended mantissa

    integer_i  : in  std_ulogic_vector(31 downto 0); -- integer input

    class_i    : in  std_ulogic_vector(09 downto 0); -- input number class

    flags_i    : in  std_ulogic_vector(04 downto 0); -- exception flags input

    -- output --

    result_o   : out std_ulogic_vector(31 downto 0); -- result (float or int)

    flags_o    : out std_ulogic_vector(04 downto 0); -- exception flags

    done_o     : out std_ulogic -- operation done

  );

  end component;

  -- commands (one-hot) --

  type cmd_t is record

    instr_class  : std_ulogic;

    instr_sgnj   : std_ulogic;

    instr_comp   : std_ulogic;

    instr_i2f    : std_ulogic;

    instr_f2i    : std_ulogic;

    instr_minmax : std_ulogic;

    instr_addsub : std_ulogic;

    instr_mul    : std_ulogic;

    funct        : std_ulogic_vector(2 downto 0);

  end record;

  signal cmd : cmd_t;

  signal funct_ff : std_ulogic_vector(2 downto 0);

  -- co-processor control engine --

  type ctrl_state_t is (S_IDLE, S_BUSY);

  type ctrl_engine_t is record

    state : ctrl_state_t;

    start : std_ulogic;

    valid : std_ulogic;

  end record;

  signal ctrl_engine : ctrl_engine_t;

  -- floating-point operands --

  type op_data_t  is array (0 to 1) of std_ulogic_vector(31 downto 0);

  type op_class_t is array (0 to 1) of std_ulogic_vector(09 downto 0);

  type fpu_operands_t is record

    rs1       : std_ulogic_vector(31 downto 0); -- operand 1

    rs1_class : std_ulogic_vector(09 downto 0); -- operand 1 number class

    rs2       : std_ulogic_vector(31 downto 0); -- operand 2

    rs2_class : std_ulogic_vector(09 downto 0); -- operand 2 number class

    frm       : std_ulogic_vector(02 downto 0); -- rounding mode

  end record;

  signal op_data      : op_data_t;

  signal op_class     : op_class_t;

  signal fpu_operands : fpu_operands_t;

  -- floating-point comparator --

  signal comp_equal_ff : std_ulogic;

  signal comp_less_ff  : std_ulogic;

  signal comp_less     : std_ulogic;

  -- functional units interface --

  type fu_interface_t is record

    result : std_ulogic_vector(31 downto 0);

    flags  : std_ulogic_vector(04 downto 0);

    start  : std_ulogic;

    done   : std_ulogic;

  end record;

  signal fu_classify    : fu_interface_t;

  signal fu_compare     : fu_interface_t;

  signal fu_sign_inject : fu_interface_t;

  signal fu_min_max     : fu_interface_t;

  signal fu_conv_f2i    : fu_interface_t;

  signal fu_addsub      : fu_interface_t;

  signal fu_mul         : fu_interface_t;

  signal fu_core_done   : std_ulogic; -- FU operation completed

  -- integer-to-float --

  type fu_i2f_interface_t is record

    result : std_ulogic_vector(31 downto 0);

    sign   : std_ulogic;

    start  : std_ulogic;

    done   : std_ulogic;

  end record;

  signal fu_conv_i2f : fu_i2f_interface_t; -- float result

  -- multiplier unit --

  type multiplier_t is record

    opa       : unsigned(23 downto 0); -- mantissa A plus hidden one

    opb       : unsigned(23 downto 0); -- mantissa B plus hidden one

    buf_ff    : unsigned(47 downto 0); -- product buffer

    sign      : std_ulogic; -- resulting sign

    product   : std_ulogic_vector(47 downto 0); -- product

    exp_sum   : std_ulogic_vector(08 downto 0); -- incl 1x overflow/underflow bit

    exp_res   : std_ulogic_vector(09 downto 0); -- resulting exponent incl 2x overflow/underflow bit

    --

    res_class : std_ulogic_vector(09 downto 0);

    flags     : std_ulogic_vector(04 downto 0); -- exception flags

    --

    start     : std_ulogic;

    latency   : std_ulogic_vector(02 downto 0); -- unit latency

    done      : std_ulogic;

  end record;

  signal multiplier : multiplier_t;

  -- adder/subtractor unit --

  type addsub_t is record

    -- input comparison --

    exp_comp  : std_ulogic_vector(01 downto 0); -- equal & less

    small_exp : std_ulogic_vector(07 downto 0);

    small_man : std_ulogic_vector(23 downto 0); -- mantissa + hiden one

    large_exp : std_ulogic_vector(07 downto 0);

    large_man : std_ulogic_vector(23 downto 0); -- mantissa + hiden one

    -- smaller mantissa alginment --

    man_sreg  : std_ulogic_vector(23 downto 0); -- mantissa + hidden one

    man_g_ext : std_ulogic;

    man_r_ext : std_ulogic;

    man_s_ext : std_ulogic;

    exp_cnt   : std_ulogic_vector(08 downto 0);

    -- adder/subtractor stage --

    man_comp  : std_ulogic;

    man_s     : std_ulogic_vector(26 downto 0); -- mantissa + hiden one + GRS

    man_l     : std_ulogic_vector(26 downto 0); -- mantissa + hiden one + GRS

    add_stage : std_ulogic_vector(27 downto 0); -- adder result incl. overflow

    -- result --

    res_sign  : std_ulogic;

    res_sum   : std_ulogic_vector(27 downto 0); -- mantissa sum (+1 bit) + GRS bits (for rounding)

    res_class : std_ulogic_vector(09 downto 0);

    flags     : std_ulogic_vector(04 downto 0); -- exception flags

    -- arbitration --

    start     : std_ulogic;

    latency   : std_ulogic_vector(04 downto 0); -- unit latency

    done      : std_ulogic;

  end record;

  signal addsub : addsub_t;

  -- normalizer interface (normalization & rounding and int-to-float) --

  type normalizer_t is record

    start     : std_ulogic;

    mode      : std_ulogic;

    sign      : std_ulogic;

    xexp      : std_ulogic_vector(08 downto 0);

    xmantissa : std_ulogic_vector(47 downto 0);

    result    : std_ulogic_vector(31 downto 0);

    class     : std_ulogic_vector(09 downto 0);

    flags_in  : std_ulogic_vector(04 downto 0);

    flags_out : std_ulogic_vector(04 downto 0);

    done      : std_ulogic;

  end record;

  signal normalizer : normalizer_t;

begin

-- ****************************************************************************************************************************

-- Control

-- ****************************************************************************************************************************

  -- Instruction Decoding -------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- one-hot re-encoding --

  cmd.instr_class  <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "11100") else '0';

  cmd.instr_comp   <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "10100") else '0';

  cmd.instr_i2f    <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "11010") else '0';

  cmd.instr_f2i    <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "11000") else '0';

  cmd.instr_sgnj   <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "00100") else '0';

  cmd.instr_minmax <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "00101") else '0';

  cmd.instr_addsub <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_8_c) = "0000")  else '0';

  cmd.instr_mul    <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "00010") else '0';

  -- binary re-encoding --

  cmd.funct <= op_mul_c     when (cmd.instr_mul    = '1') else

               op_addsub_c  when (cmd.instr_addsub = '1') else

               op_minmax_c  when (cmd.instr_minmax = '1') else

               op_sgnj_c    when (cmd.instr_sgnj   = '1') else

               op_f2i_c     when (cmd.instr_f2i    = '1') else

               op_i2f_c     when (cmd.instr_i2f    = '1') else

               op_comp_c    when (cmd.instr_comp   = '1') else

               op_class_c;--when (cmd.instr_class  = '1') else (others => '-');

  -- Input Operands: Check for subnormal numbers (flush to zero) ----------------------------

  -- -------------------------------------------------------------------------------------------

  -- Subnormal numbers are not supported and are "flushed to zero"! FIXME / TODO

  -- rs1 --

  op_data(0)(31)           <= rs1_i(31);

  op_data(0)(30 downto 23) <= rs1_i(30 downto 23);

  op_data(0)(22 downto 00) <= (others => '0') when (rs1_i(30 downto 23) = "00000000") else rs1_i(22 downto 0); -- flush mantissa to zero if subnormal

  -- rs2 --

  op_data(1)(31)           <= rs2_i(31);

  op_data(1)(30 downto 23) <= rs2_i(30 downto 23);

  op_data(1)(22 downto 00) <= (others => '0') when (rs2_i(30 downto 23) = "00000000") else rs2_i(22 downto 0); -- flush mantissa to zero if subnormal

  -- Number Classifier ----------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  number_classifier: process(op_data)

    variable op_m_all_zero_v, op_e_all_zero_v, op_e_all_one_v       : std_ulogic;

    variable op_is_zero_v, op_is_inf_v, op_is_denorm_v, op_is_nan_v : std_ulogic;

  begin

    for i in 0 to 1 loop -- for rs1 and rs2 inputs

      -- check for all-zero/all-one --

      op_m_all_zero_v := not or_all_f(op_data(i)(22 downto 00));

      op_e_all_zero_v := not or_all_f(op_data(i)(30 downto 23));

      op_e_all_one_v  := and_all_f(op_data(i)(30 downto 23));

      -- check special cases --

      op_is_zero_v   := op_e_all_zero_v and      op_m_all_zero_v;  -- zero

      op_is_inf_v    := op_e_all_one_v  and      op_m_all_zero_v;  -- infinity

      op_is_denorm_v := '0'; -- FIXME / TODO op_e_all_zero_v and (not op_m_all_zero_v); -- subnormal

      op_is_nan_v    := op_e_all_one_v  and (not op_m_all_zero_v); -- NaN

      -- actual attributes --

      op_class(i)(fp_class_neg_inf_c)    <= op_data(i)(31) and op_is_inf_v; -- negative infinity

      op_class(i)(fp_class_neg_norm_c)   <= op_data(i)(31) and (not op_is_denorm_v) and (not op_is_nan_v) and (not op_is_inf_v) and (not op_is_zero_v); -- negative normal number

      op_class(i)(fp_class_neg_denorm_c) <= op_data(i)(31) and op_is_denorm_v; -- negative subnormal number

      op_class(i)(fp_class_neg_zero_c)   <= op_data(i)(31) and op_is_zero_v; -- negative zero

      op_class(i)(fp_class_pos_zero_c)   <= (not op_data(i)(31)) and op_is_zero_v; -- positive zero

      op_class(i)(fp_class_pos_denorm_c) <= (not op_data(i)(31)) and op_is_denorm_v; -- positive subnormal number

      op_class(i)(fp_class_pos_norm_c)   <= (not op_data(i)(31)) and (not op_is_denorm_v) and (not op_is_nan_v) and (not op_is_inf_v) and (not op_is_zero_v); -- positive normal number

      op_class(i)(fp_class_pos_inf_c)    <= (not op_data(i)(31)) and op_is_inf_v; -- positive infinity

      op_class(i)(fp_class_snan_c)       <= op_is_nan_v and (not op_data(i)(22)); -- signaling NaN

      op_class(i)(fp_class_qnan_c)       <= op_is_nan_v and (    op_data(i)(22)); -- quiet NaN

    end loop; -- i

  end process number_classifier;

  -- Co-Processor Control Engine ------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  control_engine_fsm: process(rstn_i, clk_i)

  begin

    if (rstn_i = '0') then

      ctrl_engine.state      <= S_IDLE;

      ctrl_engine.start      <= '0';

      fpu_operands.frm       <= (others => '0');

      fpu_operands.rs1       <= (others => '0');

      fpu_operands.rs1_class <= (others => '0');

      fpu_operands.rs2       <= (others => '0');

      fpu_operands.rs2_class <= (others => '0');

      funct_ff               <= (others => '0');

    elsif rising_edge(clk_i) then

      -- arbiter defaults --

      ctrl_engine.valid <= '0';

      ctrl_engine.start <= '0';

      -- state machine --

      case ctrl_engine.state is

        when S_IDLE => -- waiting for operation trigger

        -- ------------------------------------------------------------

          funct_ff <= cmd.funct; -- actual operation to execute

          -- rounding mode --

          -- TODO / FIXME "round to nearest, ties to max magnitude" (0b100) is not supported yet

          if (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "111") then

            fpu_operands.frm <= '0' & frm_i(1 downto 0);

          else

            fpu_operands.frm <= '0' & ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c);

          end if;

          --

          if (start_i = '1') then

            -- operand data --

            fpu_operands.rs1       <= op_data(0);

            fpu_operands.rs1_class <= op_class(0);

            fpu_operands.rs2       <= op_data(1);

            fpu_operands.rs2_class <= op_class(1);

            -- execute! --

            ctrl_engine.start <= '1';

            ctrl_engine.state <= S_BUSY;

          end if;

        when S_BUSY => -- operation in progress (multi-cycle)

        -- -----------------------------------------------------------

          if (fu_core_done = '1') then -- processing done?

            ctrl_engine.valid <= '1';

            ctrl_engine.state <= S_IDLE;

          end if;

        when others => -- undefined

        -- ------------------------------------------------------------

          ctrl_engine.state <= S_IDLE;

      end case;

    end if;

  end process control_engine_fsm;

  -- operation done / valid output --

  valid_o <= ctrl_engine.valid;

  -- Functional Unit Interface (operation-start trigger) ------------------------------------

  -- -------------------------------------------------------------------------------------------

  fu_classify.start    <= ctrl_engine.start and cmd.instr_class;

  fu_compare.start     <= ctrl_engine.start and cmd.instr_comp;

  fu_sign_inject.start <= ctrl_engine.start and cmd.instr_sgnj;

  fu_min_max.start     <= ctrl_engine.start and cmd.instr_minmax;

  fu_conv_i2f.start    <= ctrl_engine.start and cmd.instr_i2f;

  fu_conv_f2i.start    <= ctrl_engine.start and cmd.instr_f2i;

  fu_addsub.start      <= ctrl_engine.start and cmd.instr_addsub;

  fu_mul.start         <= ctrl_engine.start and cmd.instr_mul;

-- ****************************************************************************************************************************

-- FPU Core - Functional Units

-- ****************************************************************************************************************************

  -- Number Classifier (FCLASS) -------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  fu_classify.flags <= (others => '0'); -- does not generate flags at all

  fu_classify.result(31 downto 10) <= (others => '0');

  fu_classify.result(09 downto 00) <= fpu_operands.rs1_class;

  fu_classify.done <= fu_classify.start;

  -- Floating-Point Comparator --------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  float_comparator: process(clk_i)

    variable cond_v : std_ulogic_vector(1 downto 0);

  begin

    if rising_edge(clk_i) then

      -- equal --

      if ((fpu_operands.rs1_class(fp_class_pos_inf_c)   = '1') and (fpu_operands.rs2_class(fp_class_pos_inf_c) = '1')) or -- +inf == +inf

         ((fpu_operands.rs1_class(fp_class_neg_inf_c)   = '1') and (fpu_operands.rs2_class(fp_class_neg_inf_c) = '1')) or -- -inf == -inf

         (((fpu_operands.rs1_class(fp_class_pos_zero_c) = '1') or (fpu_operands.rs1_class(fp_class_neg_zero_c) = '1')) and

          ((fpu_operands.rs2_class(fp_class_pos_zero_c) = '1') or (fpu_operands.rs2_class(fp_class_neg_zero_c) = '1'))) or  -- +/-zero == +/-zero

         (fpu_operands.rs1 = fpu_operands.rs2) then -- identical in every way

        comp_equal_ff <= '1';

      else

        comp_equal_ff <= '0';

      end if;

      -- less than --

      if ((fpu_operands.rs1_class(fp_class_pos_inf_c)  = '1') and (fpu_operands.rs2_class(fp_class_pos_inf_c) = '1')) or -- +inf !< +inf

         ((fpu_operands.rs1_class(fp_class_neg_inf_c)  = '1') and (fpu_operands.rs2_class(fp_class_neg_inf_c) = '1')) or -- -inf !< -inf

         (((fpu_operands.rs1_class(fp_class_pos_zero_c) = '1') or (fpu_operands.rs1_class(fp_class_neg_zero_c) = '1')) and

          ((fpu_operands.rs2_class(fp_class_pos_zero_c) = '1') or (fpu_operands.rs2_class(fp_class_neg_zero_c) = '1'))) then  -- +/-zero !< +/-zero

        comp_less_ff <= '0';

      else

        cond_v := fpu_operands.rs1(31) & fpu_operands.rs2(31);

        case cond_v is

          when "10"   => comp_less_ff <= '1'; -- rs1 negative, rs2 positive

          when "01"   => comp_less_ff <= '0'; -- rs1 positive, rs2 negative

          when "00"   => comp_less_ff <= comp_less; -- both positive

          when "11"   => comp_less_ff <= not comp_less; -- both negative

          when others => comp_less_ff <= '0'; -- undefined

        end case;

      end if;

      -- comparator latency --

      fu_compare.done <= fu_compare.start; -- for actual comparison operation

      fu_min_max.done <= fu_min_max.start; -- for min/max operations

    end if;

  end process float_comparator;

  -- less than - only compare the "magnitude" part - sign bit has to be handled separately --

  comp_less <= '1' when (unsigned(fpu_operands.rs1(30 downto 0)) < unsigned(fpu_operands.rs2(30 downto 0))) else '0';

  -- Comparison (FEQ/FLT/FLE) ---------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  float_comparison: process(fpu_operands, ctrl_i, comp_equal_ff, comp_less_ff)

    variable snan_v : std_ulogic; -- at least one input is sNaN

    variable qnan_v : std_ulogic; -- at least one input is qNaN

  begin

    -- check for NaN --

    snan_v := fpu_operands.rs1_class(fp_class_snan_c) or fpu_operands.rs2_class(fp_class_snan_c);

    qnan_v := fpu_operands.rs1_class(fp_class_qnan_c) or fpu_operands.rs2_class(fp_class_qnan_c);

    -- condition evaluation --

    fu_compare.result <= (others => '0');

    case ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) is

      when "00" => -- FLE: less than or equal

        fu_compare.result(0) <= (comp_less_ff or comp_equal_ff) and (not (snan_v or qnan_v)); -- result is zero if either input is NaN

      when "01" => -- FLT: less than

        fu_compare.result(0) <= comp_less_ff and (not (snan_v or qnan_v)); -- result is zero if either input is NaN

      when "10" => -- FEQ: equal

        fu_compare.result(0) <= comp_equal_ff and (not (snan_v or qnan_v)); -- result is zero if either input is NaN

      when others => -- undefined

        fu_compare.result(0) <= '0';

    end case;

  end process float_comparison;

  -- latency --

  -- -> done in "float_comparator"

  -- exceptions --

  fu_compare.flags <= (others => '0'); -- does not generate exceptions here, but normalizer can generate exceptions

  -- Min/Max Select (FMIN/FMAX) -------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  min_max_select: process(fpu_operands, comp_less_ff, fpu_operands, fu_compare, ctrl_i)

    variable cond_v : std_ulogic_vector(2 downto 0);

  begin

    -- comparison restul - check for special cases: -0 is less than +0

    if ((fpu_operands.rs1_class(fp_class_neg_zero_c) = '1') and (fpu_operands.rs2_class(fp_class_pos_zero_c) = '1')) then

      cond_v(0) := ctrl_i(ctrl_ir_funct3_0_c);

    elsif ((fpu_operands.rs1_class(fp_class_pos_zero_c) = '1') and (fpu_operands.rs2_class(fp_class_neg_zero_c) = '1')) then

      cond_v(0) := not ctrl_i(ctrl_ir_funct3_0_c);

    else -- "normal= comparison

      cond_v(0) := comp_less_ff xnor ctrl_i(ctrl_ir_funct3_0_c); -- min/max select

    end if;

    -- nmumber NaN check --

    cond_v(2) := fpu_operands.rs1_class(fp_class_snan_c) or fpu_operands.rs1_class(fp_class_qnan_c);

    cond_v(1) := fpu_operands.rs2_class(fp_class_snan_c) or fpu_operands.rs2_class(fp_class_qnan_c);

    -- data output --

    case cond_v is

      when "000"         => fu_min_max.result <= fpu_operands.rs1;

      when "001"         => fu_min_max.result <= fpu_operands.rs2;

      when "010" | "011" => fu_min_max.result <= fpu_operands.rs1; -- if one input is NaN output the non-NaN one

      when "100" | "101" => fu_min_max.result <= fpu_operands.rs2; -- if one input is NaN output the non-NaN one

      when others        => fu_min_max.result <= fp_single_qnan_c; -- output quiet NaN if both inputs are NaN

    end case;

  end process min_max_select;

  -- latency --

  -- -> done in "float_comparator"

  -- exceptions --

  fu_min_max.flags <= (others => '0'); -- does not generate exceptions here, but normalizer can generate exceptions

  -- Convert: Float to [unsigned] Integer (FCVT.S.W) ----------------------------------------

  -- -------------------------------------------------------------------------------------------

  neorv32_cpu_cp_fpu_f2i_inst: neorv32_cpu_cp_fpu_f2i

  port map (

    -- control --

    clk_i      => clk_i,                          -- global clock, rising edge

    rstn_i     => rstn_i,                         -- global reset, low-active, async

    start_i    => fu_conv_f2i.start,              -- trigger operation

    rmode_i    => fpu_operands.frm,               -- rounding mode

    funct_i    => ctrl_i(ctrl_ir_funct12_0_c),    -- 0=signed, 1=unsigned

    -- input --

    sign_i     => fpu_operands.rs1(31),           -- sign

    exponent_i => fpu_operands.rs1(30 downto 23), -- exponent

    mantissa_i => fpu_operands.rs1(22 downto 00), -- mantissa

    class_i    => fpu_operands.rs1_class,         -- operand class

    -- output --

    result_o   => fu_conv_f2i.result,             -- integer result

    flags_o    => fu_conv_f2i.flags,              -- exception flags

    done_o     => fu_conv_f2i.done                -- operation done

  );

  -- Sign-Injection (FSGNJ) -----------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  sign_injector: process(ctrl_i, fpu_operands)

  begin

    case ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) is

      when "00"   => fu_sign_inject.result(31) <= fpu_operands.rs2(31); -- FSGNJ

      when "01"   => fu_sign_inject.result(31) <= not fpu_operands.rs2(31); -- FSGNJN

      when "10"   => fu_sign_inject.result(31) <= fpu_operands.rs1(31) xor fpu_operands.rs2(31); -- FSGNJX

      when others => fu_sign_inject.result(31) <= fpu_operands.rs2(31); -- undefined

    end case;

    fu_sign_inject.result(30 downto 0) <= fpu_operands.rs1(30 downto 0);

    fu_sign_inject.flags <= (others => '0'); -- does not generate flags

  end process sign_injector;

  -- latency --

  fu_sign_inject.done <= fu_sign_inject.start;

  -- Convert: [unsigned] Integer to Float (FCVT.W.S) ----------------------------------------

  -- -------------------------------------------------------------------------------------------