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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_cp_muldiv.vhd] - Blame information for rev 2

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-- #################################################################################################
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-- # << NEORV32 - CPU Co-Processor: MULDIV unit >>                                                 #
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-- # ********************************************************************************************* #
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-- # Multiplier and Divider unit. Implements the RISC-V RV32-M CPU extension.                      #
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-- # Multiplier core (signed/unsigned) uses serial algorithm. -> 32+8 cycles latency               #
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-- # Divider core (unsigned) uses serial algorithm. -> 32+8 cycles latency                         #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
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-- #                                                                                               #
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-- # Redistribution and use in source and binary forms, with or without modification, are          #
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-- # permitted provided that the following conditions are met:                                     #
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-- #                                                                                               #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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-- #    conditions and the following disclaimer.                                                   #
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-- #                                                                                               #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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-- #    conditions and the following disclaimer in the documentation and/or other materials        #
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-- #    provided with the distribution.                                                            #
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-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
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-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_cp_muldiv is
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  port (
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    -- global control --
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    clk_i   : in  std_ulogic; -- global clock, rising edge
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    rstn_i  : in  std_ulogic; -- global reset, low-active, async
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    ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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    -- data input --
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    rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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    rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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    -- result and status --
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    res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
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    valid_o : out std_ulogic -- data output valid
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  );
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end neorv32_cpu_cp_muldiv;
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architecture neorv32_cpu_cp_muldiv_rtl of neorv32_cpu_cp_muldiv is
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  -- controller --
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  type state_t is (IDLE, DECODE, INIT_OPX, INIT_OPY, PROCESSING, FINALIZE, COMPLETED);
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  signal state         : state_t;
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  signal cnt           : std_ulogic_vector(4 downto 0);
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  signal cp_op         : std_ulogic_vector(2 downto 0); -- operation to execute
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  signal start         : std_ulogic;
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  signal operation     : std_ulogic;
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  signal opx, opy      : std_ulogic_vector(data_width_c-1 downto 0); -- input operands
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  signal opx_is_signed : std_ulogic;
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  signal opy_is_signed : std_ulogic;
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  signal div_res_corr  : std_ulogic;
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  -- divider core --
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  signal remainder        : std_ulogic_vector(data_width_c-1 downto 0);
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  signal quotient         : std_ulogic_vector(data_width_c-1 downto 0);
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  signal div_sub          : std_ulogic_vector(data_width_c   downto 0);
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  signal div_sign_comp_in : std_ulogic_vector(data_width_c-1 downto 0);
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  signal div_sign_comp    : std_ulogic_vector(data_width_c-1 downto 0);
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  signal div_res          : std_ulogic_vector(data_width_c-1 downto 0);
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  -- multiplier core --
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  signal mul_product    : std_ulogic_vector(63 downto 0);
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  signal mul_do_add     : std_ulogic_vector(32 downto 0);
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  signal mul_sign_cycle : std_ulogic;
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  signal mul_p_sext     : std_ulogic;
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begin
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  -- Co-Processor Controller ----------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  coprocessor_ctrl: process(rstn_i, clk_i)
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  begin
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    if (rstn_i = '0') then
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      state        <= IDLE;
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      cp_op        <= (others => '0');
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      opx          <= (others => '-');
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      opy          <= (others => '-');
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      cnt          <= (others => '-');
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      start        <= '-';
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      valid_o      <= '0';
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      div_res_corr <= '-';
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    elsif rising_edge(clk_i) then
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      -- defaults --
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      start   <= '0';
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      valid_o <= '0';
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      -- FSM --
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      case state is
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        when IDLE =>
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          opx   <= rs1_i;
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          opy   <= rs2_i;
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          if (ctrl_i(ctrl_cp_use_c) = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = cp_sel_muldiv_c) then
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            cp_op <= ctrl_i(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c);
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            state <= DECODE;
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          end if;
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        when DECODE =>
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          if (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) then -- result sign compensation for div?
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            div_res_corr <= opx(opx'left) xor opy(opy'left);
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          else
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            div_res_corr <= '0';
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          end if;
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          cnt <= "11111";
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          if (operation = '1') then -- division
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            state <= INIT_OPX;
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          else -- multiplication
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            start <= '1';
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            state <= PROCESSING;
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          end if;
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        when INIT_OPX =>
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          if ((opx(opx'left) and opx_is_signed) = '1') then -- signed division?
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            opx <= div_sign_comp; -- make positive
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          end if;
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          state <= INIT_OPY;
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        when INIT_OPY =>
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          start <= '1';
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          if ((opy(opy'left) and opy_is_signed) = '1') then -- signed division?
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            opy <= div_sign_comp; -- make positive
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          end if;
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          state <= PROCESSING;
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        when PROCESSING =>
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          cnt <= std_ulogic_vector(unsigned(cnt) - 1);
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          if (cnt = "00000") then
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            state <= FINALIZE;
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          end if;
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        when FINALIZE =>
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          state <= COMPLETED;
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        when COMPLETED =>
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          valid_o <= '1';
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          state   <= IDLE;
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      end case;
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    end if;
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  end process coprocessor_ctrl;
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  -- operation --
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  operation <= '1' when (cp_op = cp_op_div_c) or (cp_op = cp_op_divu_c) or (cp_op = cp_op_rem_c) or (cp_op = cp_op_remu_c) else '0';
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  -- opx (rs1) signed? --
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  opx_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_mulhsu_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0';
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  -- opy (rs2) signed? --
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  opy_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0';
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  -- Multiplier Core ------------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  multiplier_core: process(clk_i)
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  begin
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    if rising_edge(clk_i) then
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      if (start = '1') then -- start new multiplication
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        mul_product(63 downto 32) <= (others => (opy(opy'left) and opy_is_signed)); -- sign extension
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        mul_product(31 downto 00) <= opy;
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      elsif ((state = PROCESSING) or (state = FINALIZE)) and (operation = '0') then
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        mul_product(63 downto 31) <= mul_do_add(32 downto 0);
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        mul_product(30 downto 00) <= mul_product(31 downto 1);
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      end if;
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    end if;
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  end process multiplier_core;
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  -- MUL: do another addition --
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  mul_update: process(mul_product, mul_sign_cycle, mul_p_sext, opy_is_signed, opx)
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  begin
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    if (mul_product(0) = '1') then
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      if (mul_sign_cycle = '1') then -- for signed operation only: take care of negative weighted MSB
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        mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) - unsigned((opx(opy'left) and opx_is_signed) & opx));
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      else
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        mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) + unsigned((opx(opy'left) and opx_is_signed) & opx));
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      end if;
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    else
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      mul_do_add <= mul_p_sext & mul_product(63 downto 32);
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    end if;
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  end process mul_update;
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  -- sign control --
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  mul_sign_cycle <= opy_is_signed when (state = FINALIZE) else '0';
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  mul_p_sext     <= mul_product(mul_product'left) and opx_is_signed;
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  -- Divider Core ---------------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  divider_core: process(clk_i)
209
  begin
210
    if rising_edge(clk_i) then
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      if (start = '1') then -- start new division
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        quotient  <= opx;
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        remainder <= (others => '0');
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      elsif ((state = PROCESSING) or (state = FINALIZE)) and (operation = '1') then -- running?
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        quotient <= quotient(30 downto 0) & (not div_sub(32));
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        if (div_sub(32) = '0') then -- still overflowing
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          remainder <= div_sub(31 downto 0);
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        else -- underflow
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          remainder <= remainder(30 downto 0) & quotient(31);
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        end if;
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      end if;
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    end if;
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  end process divider_core;
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  -- DIV: try another subtraction --
226
  div_sub <= std_ulogic_vector(unsigned('0' & remainder(30 downto 0) & quotient(31)) - unsigned('0' & opy));
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  -- Div sign compensation --
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  div_sign_comp_in <= opx when (state = INIT_OPX) else
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                      opy when (state = INIT_OPY) else
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                      quotient when ((cp_op = cp_op_div_c) or (cp_op = cp_op_divu_c)) else remainder;
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  div_sign_comp <= std_ulogic_vector(0 - unsigned(div_sign_comp_in));
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  -- result sign correction --
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  div_res <= div_sign_comp when (div_res_corr = '1') else div_sign_comp_in;
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238
  -- Data Output ----------------------------------------------------------------------------
239
  -- -------------------------------------------------------------------------------------------
240
  operation_result: process(clk_i)
241
  begin
242
    if rising_edge(clk_i) then
243
      case cp_op is
244
        when cp_op_mul_c =>
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          res_o <= mul_product(31 downto 00);
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        when cp_op_mulh_c | cp_op_mulhsu_c | cp_op_mulhu_c =>
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          res_o <= mul_product(63 downto 32);
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        when cp_op_div_c =>
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          res_o <= div_res;
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        when cp_op_divu_c =>
251
          res_o <= quotient;
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        when cp_op_rem_c =>
253
          res_o <= div_res;
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        when cp_op_remu_c =>
255
          res_o <= remainder;
256
        when others => -- undefined
257
          res_o <= (others => '-');
258
      end case;
259
    end if;
260
  end process operation_result;
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end neorv32_cpu_cp_muldiv_rtl;

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