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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_cp_muldiv.vhd] - Blame information for rev 22

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1 2 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - CPU Co-Processor: MULDIV unit >>                                                 #
3
-- # ********************************************************************************************* #
4
-- # Multiplier and Divider unit. Implements the RISC-V RV32-M CPU extension.                      #
5 6 zero_gravi
-- # Multiplier core (signed/unsigned) uses serial algorithm. -> 32+4 cycles latency               #
6
-- # Divider core (unsigned) uses serial algorithm. -> 32+6 cycles latency                         #
7 2 zero_gravi
-- # ********************************************************************************************* #
8
-- # BSD 3-Clause License                                                                          #
9
-- #                                                                                               #
10
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
11
-- #                                                                                               #
12
-- # Redistribution and use in source and binary forms, with or without modification, are          #
13
-- # permitted provided that the following conditions are met:                                     #
14
-- #                                                                                               #
15
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
16
-- #    conditions and the following disclaimer.                                                   #
17
-- #                                                                                               #
18
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
19
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
20
-- #    provided with the distribution.                                                            #
21
-- #                                                                                               #
22
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
23
-- #    endorse or promote products derived from this software without specific prior written      #
24
-- #    permission.                                                                                #
25
-- #                                                                                               #
26
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
27
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
28
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
29
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
30
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
31
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
32
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
33
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
34
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
36
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
37
-- #################################################################################################
38
 
39
library ieee;
40
use ieee.std_logic_1164.all;
41
use ieee.numeric_std.all;
42
 
43
library neorv32;
44
use neorv32.neorv32_package.all;
45
 
46
entity neorv32_cpu_cp_muldiv is
47 19 zero_gravi
  generic (
48
    FAST_MUL_EN : boolean := false -- use DSPs for faster multiplication
49
  );
50 2 zero_gravi
  port (
51
    -- global control --
52
    clk_i   : in  std_ulogic; -- global clock, rising edge
53
    rstn_i  : in  std_ulogic; -- global reset, low-active, async
54
    ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
55
    -- data input --
56 19 zero_gravi
    start_i : in  std_ulogic; -- trigger operation
57 2 zero_gravi
    rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
58
    rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
59
    -- result and status --
60
    res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
61
    valid_o : out std_ulogic -- data output valid
62
  );
63
end neorv32_cpu_cp_muldiv;
64
 
65
architecture neorv32_cpu_cp_muldiv_rtl of neorv32_cpu_cp_muldiv is
66
 
67 19 zero_gravi
  -- advanced configuration --
68
  constant dsp_add_reg_stage_c : boolean := false; -- add another register stage to DSP-based multiplication for timing-closure
69 6 zero_gravi
 
70 2 zero_gravi
  -- controller --
71 22 zero_gravi
  type state_t is (IDLE, DECODE, INIT_OPX, INIT_OPY, PROCESSING, FINALIZE, COMPLETED, FAST_MUL);
72 2 zero_gravi
  signal state         : state_t;
73
  signal cnt           : std_ulogic_vector(4 downto 0);
74
  signal cp_op         : std_ulogic_vector(2 downto 0); -- operation to execute
75
  signal start         : std_ulogic;
76
  signal operation     : std_ulogic;
77
  signal opx, opy      : std_ulogic_vector(data_width_c-1 downto 0); -- input operands
78
  signal opx_is_signed : std_ulogic;
79
  signal opy_is_signed : std_ulogic;
80 6 zero_gravi
  signal opy_is_zero   : std_ulogic;
81 2 zero_gravi
  signal div_res_corr  : std_ulogic;
82
 
83
  -- divider core --
84
  signal remainder        : std_ulogic_vector(data_width_c-1 downto 0);
85
  signal quotient         : std_ulogic_vector(data_width_c-1 downto 0);
86
  signal div_sub          : std_ulogic_vector(data_width_c   downto 0);
87
  signal div_sign_comp_in : std_ulogic_vector(data_width_c-1 downto 0);
88
  signal div_sign_comp    : std_ulogic_vector(data_width_c-1 downto 0);
89
  signal div_res          : std_ulogic_vector(data_width_c-1 downto 0);
90
 
91
  -- multiplier core --
92
  signal mul_product    : std_ulogic_vector(63 downto 0);
93 12 zero_gravi
  signal mul_do_add     : std_ulogic_vector(data_width_c downto 0);
94 2 zero_gravi
  signal mul_sign_cycle : std_ulogic;
95
  signal mul_p_sext     : std_ulogic;
96 19 zero_gravi
  signal mul_op_x       : signed(32 downto 0); -- for using DSPs
97
  signal mul_op_y       : signed(32 downto 0); -- for using DSPs
98
  signal mul_buf_ff     : signed(65 downto 0); -- for using DSPs
99
  signal mul_buf2_ff    : signed(65 downto 0); -- for using DSPs
100 2 zero_gravi
 
101
begin
102
 
103
  -- Co-Processor Controller ----------------------------------------------------------------
104
  -- -------------------------------------------------------------------------------------------
105
  coprocessor_ctrl: process(rstn_i, clk_i)
106
  begin
107
    if (rstn_i = '0') then
108
      state        <= IDLE;
109
      cp_op        <= (others => '0');
110 3 zero_gravi
      opx          <= (others => '0');
111
      opy          <= (others => '0');
112
      cnt          <= (others => '0');
113
      start        <= '0';
114 2 zero_gravi
      valid_o      <= '0';
115 3 zero_gravi
      div_res_corr <= '0';
116 6 zero_gravi
      opy_is_zero  <= '0';
117 2 zero_gravi
    elsif rising_edge(clk_i) then
118
      -- defaults --
119
      start   <= '0';
120
      valid_o <= '0';
121
 
122
      -- FSM --
123
      case state is
124
        when IDLE =>
125 19 zero_gravi
          opx <= rs1_i;
126
          opy <= rs2_i;
127
          if (start_i = '1') then
128
            cp_op <= ctrl_i(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c);
129 2 zero_gravi
            state <= DECODE;
130
          end if;
131
 
132
        when DECODE =>
133 12 zero_gravi
          --
134 6 zero_gravi
          if (cp_op = cp_op_div_c) then -- result sign compensation for div?
135 2 zero_gravi
            div_res_corr <= opx(opx'left) xor opy(opy'left);
136 6 zero_gravi
          elsif (cp_op = cp_op_rem_c) then -- result sign compensation for rem?
137
            div_res_corr <= opx(opx'left);
138 2 zero_gravi
          else
139
            div_res_corr <= '0';
140
          end if;
141 12 zero_gravi
          --
142
          if (or_all_f(opy) = '0') then -- *divide* by 0?
143 6 zero_gravi
            opy_is_zero <= '1';
144
          else
145
            opy_is_zero <= '0';
146
          end if;
147 12 zero_gravi
          --
148 22 zero_gravi
          cnt   <= "11111";
149 2 zero_gravi
          if (operation = '1') then -- division
150
            state <= INIT_OPX;
151
          else -- multiplication
152 22 zero_gravi
            start <= '1';
153
            if (FAST_MUL_EN = true) then
154
              state <= FAST_MUL;
155 12 zero_gravi
            else
156 22 zero_gravi
              state <= PROCESSING;
157 12 zero_gravi
            end if;
158 2 zero_gravi
          end if;
159
 
160
        when INIT_OPX =>
161
          if ((opx(opx'left) and opx_is_signed) = '1') then -- signed division?
162
            opx <= div_sign_comp; -- make positive
163
          end if;
164
          state <= INIT_OPY;
165
 
166
        when INIT_OPY =>
167
          start <= '1';
168
          if ((opy(opy'left) and opy_is_signed) = '1') then -- signed division?
169
            opy <= div_sign_comp; -- make positive
170
          end if;
171
          state <= PROCESSING;
172
 
173
        when PROCESSING =>
174
          cnt <= std_ulogic_vector(unsigned(cnt) - 1);
175
          if (cnt = "00000") then
176
            state <= FINALIZE;
177
          end if;
178
 
179 22 zero_gravi
        when FAST_MUL =>
180
          state <= FINALIZE;
181
 
182 2 zero_gravi
        when FINALIZE =>
183
          state <= COMPLETED;
184
 
185
        when COMPLETED =>
186
          valid_o <= '1';
187
          state   <= IDLE;
188
      end case;
189
    end if;
190
  end process coprocessor_ctrl;
191
 
192
  -- operation --
193
  operation <= '1' when (cp_op = cp_op_div_c) or (cp_op = cp_op_divu_c) or (cp_op = cp_op_rem_c) or (cp_op = cp_op_remu_c) else '0';
194
 
195
  -- opx (rs1) signed? --
196
  opx_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_mulhsu_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0';
197
 
198
  -- opy (rs2) signed? --
199
  opy_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0';
200
 
201
 
202 12 zero_gravi
  -- Multiplier Core (signed) ---------------------------------------------------------------
203 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
204
  multiplier_core: process(clk_i)
205
  begin
206
    if rising_edge(clk_i) then
207 12 zero_gravi
      if (FAST_MUL_EN = false) then -- use small iterative computation
208
        if (start = '1') then -- start new multiplication
209
          mul_product(63 downto 32) <= (others => '0');
210
          mul_product(31 downto 00) <= opy;
211
        elsif ((state = PROCESSING) or (state = FINALIZE)) and (operation = '0') then
212
          mul_product(63 downto 31) <= mul_do_add(32 downto 0);
213
          mul_product(30 downto 00) <= mul_product(31 downto 1);
214
        end if;
215
      else -- use direct approach using (several!) DSP blocks
216
        if (start = '1') then
217 19 zero_gravi
          mul_op_x <= signed((opx(opx'left) and opx_is_signed) & opx);
218
          mul_op_y <= signed((opy(opy'left) and opy_is_signed) & opy);
219 12 zero_gravi
        end if;
220 19 zero_gravi
        mul_buf_ff <= mul_op_x * mul_op_y;
221
        if (dsp_add_reg_stage_c = true) then -- add another reg stage?
222
          mul_buf2_ff <= mul_buf_ff;
223
          mul_product <= std_ulogic_vector(mul_buf2_ff(63 downto 0)); -- let the register balancing do the magic here
224
        else
225
          mul_product <= std_ulogic_vector(mul_buf_ff(63 downto 0)); -- let the register balancing do the magic here
226
        end if;
227 2 zero_gravi
      end if;
228
    end if;
229
  end process multiplier_core;
230
 
231
  -- MUL: do another addition --
232 4 zero_gravi
  mul_update: process(mul_product, mul_sign_cycle, mul_p_sext, opx_is_signed, opx)
233 2 zero_gravi
  begin
234 12 zero_gravi
    -- current bit of opy to take care of --
235
    if (mul_product(0) = '1') then -- multiply with 1
236
      if (mul_sign_cycle = '1') then -- for signed operations only: take care of negative weighted MSB -> multiply with -1
237 6 zero_gravi
        mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) - unsigned((opx(opx'left) and opx_is_signed) & opx));
238 12 zero_gravi
      else -- multiply with +1
239 6 zero_gravi
        mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) + unsigned((opx(opx'left) and opx_is_signed) & opx));
240 2 zero_gravi
      end if;
241 12 zero_gravi
    else -- multiply with 0
242 2 zero_gravi
      mul_do_add <= mul_p_sext & mul_product(63 downto 32);
243
    end if;
244
  end process mul_update;
245
 
246
  -- sign control --
247
  mul_sign_cycle <= opy_is_signed when (state = FINALIZE) else '0';
248
  mul_p_sext     <= mul_product(mul_product'left) and opx_is_signed;
249
 
250
 
251 12 zero_gravi
  -- Divider Core (unsigned) ----------------------------------------------------------------
252 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
253
  divider_core: process(clk_i)
254
  begin
255
    if rising_edge(clk_i) then
256
      if (start = '1') then -- start new division
257
        quotient  <= opx;
258
        remainder <= (others => '0');
259
      elsif ((state = PROCESSING) or (state = FINALIZE)) and (operation = '1') then -- running?
260
        quotient <= quotient(30 downto 0) & (not div_sub(32));
261
        if (div_sub(32) = '0') then -- still overflowing
262
          remainder <= div_sub(31 downto 0);
263
        else -- underflow
264
          remainder <= remainder(30 downto 0) & quotient(31);
265
        end if;
266
      end if;
267
    end if;
268
  end process divider_core;
269
 
270
  -- DIV: try another subtraction --
271
  div_sub <= std_ulogic_vector(unsigned('0' & remainder(30 downto 0) & quotient(31)) - unsigned('0' & opy));
272
 
273
  -- Div sign compensation --
274
  div_sign_comp_in <= opx when (state = INIT_OPX) else
275
                      opy when (state = INIT_OPY) else
276
                      quotient when ((cp_op = cp_op_div_c) or (cp_op = cp_op_divu_c)) else remainder;
277
  div_sign_comp <= std_ulogic_vector(0 - unsigned(div_sign_comp_in));
278
 
279
  -- result sign correction --
280 6 zero_gravi
  div_res <= div_sign_comp when (div_res_corr = '1') and (opy_is_zero = '0') else div_sign_comp_in;
281 2 zero_gravi
 
282
 
283
  -- Data Output ----------------------------------------------------------------------------
284
  -- -------------------------------------------------------------------------------------------
285
  operation_result: process(clk_i)
286
  begin
287
    if rising_edge(clk_i) then
288 6 zero_gravi
      res_o <= (others => '0'); -- default
289 2 zero_gravi
      case cp_op is
290
        when cp_op_mul_c =>
291
          res_o <= mul_product(31 downto 00);
292
        when cp_op_mulh_c | cp_op_mulhsu_c | cp_op_mulhu_c =>
293
          res_o <= mul_product(63 downto 32);
294
        when cp_op_div_c =>
295
          res_o <= div_res;
296
        when cp_op_divu_c =>
297
          res_o <= quotient;
298
        when cp_op_rem_c =>
299 6 zero_gravi
          if (opy_is_zero = '0') then
300
            res_o <= div_res;
301
          else
302
            res_o <= opx;
303
          end if;
304 2 zero_gravi
        when cp_op_remu_c =>
305
          res_o <= remainder;
306
        when others => -- undefined
307 3 zero_gravi
          res_o <= (others => '0');
308 2 zero_gravi
      end case;
309
    end if;
310
  end process operation_result;
311
 
312
 
313
end neorv32_cpu_cp_muldiv_rtl;

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