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zero_gravi |
-- #################################################################################################
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49 |
zero_gravi |
-- # << NEORV32 - CPU: Compressed Instructions Decoder (RISC-V "C" Extension) >> #
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2 |
zero_gravi |
-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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zero_gravi |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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2 |
zero_gravi |
-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_decompressor is
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73 |
zero_gravi |
generic (
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FPU_ENABLE : boolean -- floating-point instruction enabled
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);
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2 |
zero_gravi |
port (
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-- instruction input --
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ci_instr16_i : in std_ulogic_vector(15 downto 0); -- compressed instruction input
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-- instruction output --
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ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
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ci_instr32_o : out std_ulogic_vector(31 downto 0) -- 32-bit decompressed instruction
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);
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end neorv32_cpu_decompressor;
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architecture neorv32_cpu_decompressor_rtl of neorv32_cpu_decompressor is
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-- compressed instruction layout --
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constant ci_opcode_lsb_c : natural := 0;
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constant ci_opcode_msb_c : natural := 1;
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constant ci_rd_3_lsb_c : natural := 2;
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constant ci_rd_3_msb_c : natural := 4;
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constant ci_rd_5_lsb_c : natural := 7;
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constant ci_rd_5_msb_c : natural := 11;
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constant ci_rs1_3_lsb_c : natural := 7;
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constant ci_rs1_3_msb_c : natural := 9;
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constant ci_rs1_5_lsb_c : natural := 7;
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constant ci_rs1_5_msb_c : natural := 11;
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constant ci_rs2_3_lsb_c : natural := 2;
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constant ci_rs2_3_msb_c : natural := 4;
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constant ci_rs2_5_lsb_c : natural := 2;
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constant ci_rs2_5_msb_c : natural := 6;
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constant ci_funct3_lsb_c : natural := 13;
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constant ci_funct3_msb_c : natural := 15;
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begin
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-- Compressed Instruction Decoder ---------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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decompressor: process(ci_instr16_i)
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variable imm20_v : std_ulogic_vector(20 downto 0);
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variable imm12_v : std_ulogic_vector(12 downto 0);
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begin
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-- defaults --
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ci_illegal_o <= '0';
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ci_instr32_o <= (others => '0');
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58 |
zero_gravi |
-- helper: 22-bit sign-extended immediate for J/JAL --
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2 |
zero_gravi |
imm20_v := (others => ci_instr16_i(12)); -- sign extension
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imm20_v(00):= '0';
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imm20_v(01):= ci_instr16_i(3);
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imm20_v(02):= ci_instr16_i(4);
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imm20_v(03):= ci_instr16_i(5);
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imm20_v(04):= ci_instr16_i(11);
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imm20_v(05):= ci_instr16_i(2);
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imm20_v(06):= ci_instr16_i(7);
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imm20_v(07):= ci_instr16_i(6);
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imm20_v(08):= ci_instr16_i(9);
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imm20_v(09):= ci_instr16_i(10);
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imm20_v(10):= ci_instr16_i(8);
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imm20_v(11):= ci_instr16_i(12);
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58 |
zero_gravi |
-- helper: 12-bit sign-extended immediate for branches --
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2 |
zero_gravi |
imm12_v := (others => ci_instr16_i(12)); -- sign extension
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imm12_v(00):= '0';
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imm12_v(01):= ci_instr16_i(3);
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imm12_v(02):= ci_instr16_i(4);
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imm12_v(03):= ci_instr16_i(10);
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imm12_v(04):= ci_instr16_i(11);
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imm12_v(05):= ci_instr16_i(2);
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imm12_v(06):= ci_instr16_i(5);
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imm12_v(07):= ci_instr16_i(6);
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imm12_v(08):= ci_instr16_i(12);
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-- actual decoder --
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case ci_instr16_i(ci_opcode_msb_c downto ci_opcode_lsb_c) is
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when "00" => -- C0: Register-Based Loads and Stores
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case ci_instr16_i(ci_funct3_msb_c downto ci_funct3_lsb_c) is
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when "000" => -- Illegal_instruction, C.ADDI4SPN
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-- ----------------------------------------------------------------------------------------------------------
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65 |
zero_gravi |
-- C.ADDI4SPN
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ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c;
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ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00010"; -- stack pointer
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ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "01" & ci_instr16_i(ci_rd_3_msb_c downto ci_rd_3_lsb_c);
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ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_subadd_c;
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ci_instr32_o(instr_imm12_msb_c downto instr_imm12_lsb_c) <= (others => '0'); -- zero extend
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ci_instr32_o(instr_imm12_lsb_c + 0) <= '0';
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ci_instr32_o(instr_imm12_lsb_c + 1) <= '0';
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ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(6);
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ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5);
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ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(11);
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ci_instr32_o(instr_imm12_lsb_c + 5) <= ci_instr16_i(12);
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ci_instr32_o(instr_imm12_lsb_c + 6) <= ci_instr16_i(7);
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ci_instr32_o(instr_imm12_lsb_c + 7) <= ci_instr16_i(8);
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ci_instr32_o(instr_imm12_lsb_c + 8) <= ci_instr16_i(9);
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ci_instr32_o(instr_imm12_lsb_c + 9) <= ci_instr16_i(10);
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--
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73 |
zero_gravi |
if (ci_instr16_i(12 downto 2) = "00000000000") then -- 12:2 = "00000000000" is official illegal instruction
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ci_illegal_o <= '1';
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end if;
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2 |
zero_gravi |
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52 |
zero_gravi |
when "010" | "011" => -- C.LW / C.FLW
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2 |
zero_gravi |
-- ----------------------------------------------------------------------------------------------------------
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53 |
zero_gravi |
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_load_c;
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2 |
zero_gravi |
ci_instr32_o(21 downto 20) <= "00";
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ci_instr32_o(22) <= ci_instr16_i(6);
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ci_instr32_o(23) <= ci_instr16_i(10);
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ci_instr32_o(24) <= ci_instr16_i(11);
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ci_instr32_o(25) <= ci_instr16_i(12);
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ci_instr32_o(26) <= ci_instr16_i(5);
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6 |
zero_gravi |
ci_instr32_o(31 downto 27) <= (others => '0');
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2 |
zero_gravi |
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_lw_c;
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ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "01" & ci_instr16_i(ci_rs1_3_msb_c downto ci_rs1_3_lsb_c); -- x8 - x15
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ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "01" & ci_instr16_i(ci_rd_3_msb_c downto ci_rd_3_lsb_c); -- x8 - x15
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73 |
zero_gravi |
if (ci_instr16_i(ci_funct3_lsb_c) = '1') and (FPU_ENABLE = false) then -- C.FLW
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53 |
zero_gravi |
ci_illegal_o <= '1';
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end if;
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2 |
zero_gravi |
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| 160 |
52 |
zero_gravi |
when "110" | "111" => -- C.SW / C.FSW
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2 |
zero_gravi |
-- ----------------------------------------------------------------------------------------------------------
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53 |
zero_gravi |
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_store_c;
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2 |
zero_gravi |
ci_instr32_o(08 downto 07) <= "00";
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ci_instr32_o(09) <= ci_instr16_i(6);
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| 165 |
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ci_instr32_o(10) <= ci_instr16_i(10);
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| 166 |
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ci_instr32_o(11) <= ci_instr16_i(11);
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| 167 |
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ci_instr32_o(25) <= ci_instr16_i(12);
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| 168 |
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ci_instr32_o(26) <= ci_instr16_i(5);
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| 169 |
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ci_instr32_o(31 downto 27) <= (others => '0');
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| 170 |
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ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_sw_c;
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| 171 |
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ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "01" & ci_instr16_i(ci_rs1_3_msb_c downto ci_rs1_3_lsb_c); -- x8 - x15
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| 172 |
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ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= "01" & ci_instr16_i(ci_rs2_3_msb_c downto ci_rs2_3_lsb_c); -- x8 - x15
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73 |
zero_gravi |
if (ci_instr16_i(ci_funct3_lsb_c) = '1') and (FPU_ENABLE = false) then -- C.FSW
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| 174 |
53 |
zero_gravi |
ci_illegal_o <= '1';
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| 175 |
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end if;
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| 176 |
2 |
zero_gravi |
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| 177 |
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when others => -- undefined
|
| 178 |
49 |
zero_gravi |
-- ----------------------------------------------------------------------------------------------------------
|
| 179 |
65 |
zero_gravi |
ci_instr32_o <= (others => '-');
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| 180 |
2 |
zero_gravi |
ci_illegal_o <= '1';
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| 181 |
49 |
zero_gravi |
|
| 182 |
2 |
zero_gravi |
end case;
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| 183 |
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| 184 |
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when "01" => -- C1: Control Transfer Instructions, Integer Constant-Generation Instructions
|
| 185 |
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| 186 |
|
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case ci_instr16_i(ci_funct3_msb_c downto ci_funct3_lsb_c) is
|
| 187 |
|
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when "101" => -- C.J
|
| 188 |
|
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-- ----------------------------------------------------------------------------------------------------------
|
| 189 |
|
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ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_jal_c;
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| 190 |
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ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "00000"; -- discard return address
|
| 191 |
|
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ci_instr32_o(19 downto 12) <= imm20_v(19 downto 12);
|
| 192 |
|
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ci_instr32_o(20) <= imm20_v(11);
|
| 193 |
|
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ci_instr32_o(30 downto 21) <= imm20_v(10 downto 01);
|
| 194 |
|
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ci_instr32_o(31) <= imm20_v(20);
|
| 195 |
|
|
|
| 196 |
|
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when "001" => -- C.JAL
|
| 197 |
|
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-- ----------------------------------------------------------------------------------------------------------
|
| 198 |
|
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ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_jal_c;
|
| 199 |
|
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ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "00001"; -- save return address to link register
|
| 200 |
|
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ci_instr32_o(19 downto 12) <= imm20_v(19 downto 12);
|
| 201 |
|
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ci_instr32_o(20) <= imm20_v(11);
|
| 202 |
|
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ci_instr32_o(30 downto 21) <= imm20_v(10 downto 01);
|
| 203 |
|
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ci_instr32_o(31) <= imm20_v(20);
|
| 204 |
|
|
|
| 205 |
|
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when "110" => -- C.BEQ
|
| 206 |
|
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-- ----------------------------------------------------------------------------------------------------------
|
| 207 |
|
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ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_branch_c;
|
| 208 |
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_beq_c;
|
| 209 |
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "01" & ci_instr16_i(ci_rs1_3_msb_c downto ci_rs1_3_lsb_c);
|
| 210 |
|
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ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= "00000"; -- x0
|
| 211 |
|
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ci_instr32_o(07) <= imm12_v(11);
|
| 212 |
|
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ci_instr32_o(11 downto 08) <= imm12_v(04 downto 01);
|
| 213 |
|
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ci_instr32_o(30 downto 25) <= imm12_v(10 downto 05);
|
| 214 |
|
|
ci_instr32_o(31) <= imm12_v(12);
|
| 215 |
|
|
|
| 216 |
|
|
when "111" => -- C.BNEZ
|
| 217 |
|
|
-- ----------------------------------------------------------------------------------------------------------
|
| 218 |
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_branch_c;
|
| 219 |
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_bne_c;
|
| 220 |
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "01" & ci_instr16_i(ci_rs1_3_msb_c downto ci_rs1_3_lsb_c);
|
| 221 |
|
|
ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= "00000"; -- x0
|
| 222 |
|
|
ci_instr32_o(07) <= imm12_v(11);
|
| 223 |
|
|
ci_instr32_o(11 downto 08) <= imm12_v(04 downto 01);
|
| 224 |
|
|
ci_instr32_o(30 downto 25) <= imm12_v(10 downto 05);
|
| 225 |
|
|
ci_instr32_o(31) <= imm12_v(12);
|
| 226 |
|
|
|
| 227 |
|
|
when "010" => -- C.LI
|
| 228 |
|
|
-- ----------------------------------------------------------------------------------------------------------
|
| 229 |
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c;
|
| 230 |
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_subadd_c;
|
| 231 |
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00000"; -- x0
|
| 232 |
|
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c);
|
| 233 |
|
|
ci_instr32_o(instr_imm12_msb_c downto instr_imm12_lsb_c) <= (others => ci_instr16_i(12)); -- sign extend
|
| 234 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 0) <= ci_instr16_i(2);
|
| 235 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 1) <= ci_instr16_i(3);
|
| 236 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(4);
|
| 237 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5);
|
| 238 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6);
|
| 239 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 5) <= ci_instr16_i(12);
|
| 240 |
|
|
|
| 241 |
|
|
when "011" => -- C.LUI / C.ADDI16SP
|
| 242 |
|
|
-- ----------------------------------------------------------------------------------------------------------
|
| 243 |
|
|
if (ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c) = "00010") then -- C.ADDI16SP
|
| 244 |
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c;
|
| 245 |
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_subadd_c;
|
| 246 |
|
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c);
|
| 247 |
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00010"; -- stack pointer
|
| 248 |
|
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "00010"; -- stack pointer
|
| 249 |
|
|
ci_instr32_o(instr_imm12_msb_c downto instr_imm12_lsb_c) <= (others => ci_instr16_i(12)); -- sign extend
|
| 250 |
41 |
zero_gravi |
ci_instr32_o(instr_imm12_lsb_c + 0) <= '0';
|
| 251 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 1) <= '0';
|
| 252 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 2) <= '0';
|
| 253 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 3) <= '0';
|
| 254 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6);
|
| 255 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 5) <= ci_instr16_i(2);
|
| 256 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 6) <= ci_instr16_i(5);
|
| 257 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 7) <= ci_instr16_i(3);
|
| 258 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 8) <= ci_instr16_i(4);
|
| 259 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 9) <= ci_instr16_i(12);
|
| 260 |
2 |
zero_gravi |
else -- C.LUI
|
| 261 |
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_lui_c;
|
| 262 |
|
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c);
|
| 263 |
|
|
ci_instr32_o(instr_imm20_msb_c downto instr_imm20_lsb_c) <= (others => ci_instr16_i(12)); -- sign extend
|
| 264 |
|
|
ci_instr32_o(instr_imm20_lsb_c + 0) <= ci_instr16_i(2);
|
| 265 |
|
|
ci_instr32_o(instr_imm20_lsb_c + 1) <= ci_instr16_i(3);
|
| 266 |
|
|
ci_instr32_o(instr_imm20_lsb_c + 2) <= ci_instr16_i(4);
|
| 267 |
|
|
ci_instr32_o(instr_imm20_lsb_c + 3) <= ci_instr16_i(5);
|
| 268 |
|
|
ci_instr32_o(instr_imm20_lsb_c + 4) <= ci_instr16_i(6);
|
| 269 |
|
|
ci_instr32_o(instr_imm20_lsb_c + 5) <= ci_instr16_i(12);
|
| 270 |
|
|
end if;
|
| 271 |
|
|
if (ci_instr16_i(6 downto 2) = "00000") and (ci_instr16_i(12) = '0') then -- reserved
|
| 272 |
|
|
ci_illegal_o <= '1';
|
| 273 |
|
|
end if;
|
| 274 |
|
|
|
| 275 |
|
|
when "000" => -- C.NOP (rd=0) / C.ADDI
|
| 276 |
|
|
-- ----------------------------------------------------------------------------------------------------------
|
| 277 |
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c;
|
| 278 |
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_subadd_c;
|
| 279 |
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= ci_instr16_i(ci_rs1_5_msb_c downto ci_rs1_5_lsb_c);
|
| 280 |
|
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c);
|
| 281 |
|
|
ci_instr32_o(instr_imm12_msb_c downto instr_imm12_lsb_c) <= (others => ci_instr16_i(12)); -- sign extend
|
| 282 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 0) <= ci_instr16_i(2);
|
| 283 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 1) <= ci_instr16_i(3);
|
| 284 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(4);
|
| 285 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5);
|
| 286 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6);
|
| 287 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 5) <= ci_instr16_i(12);
|
| 288 |
|
|
|
| 289 |
|
|
when "100" => -- C.SRLI, C.SRAI, C.ANDI, C.SUB, C.XOR, C.OR, C.AND, reserved
|
| 290 |
|
|
-- ----------------------------------------------------------------------------------------------------------
|
| 291 |
73 |
zero_gravi |
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "01" & ci_instr16_i(ci_rs1_3_msb_c downto ci_rs1_3_lsb_c);
|
| 292 |
2 |
zero_gravi |
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "01" & ci_instr16_i(ci_rs1_3_msb_c downto ci_rs1_3_lsb_c);
|
| 293 |
73 |
zero_gravi |
ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= "01" & ci_instr16_i(ci_rs2_3_msb_c downto ci_rs2_3_lsb_c);
|
| 294 |
|
|
case ci_instr16_i(11 downto 10) is
|
| 295 |
|
|
when "00" => -- C.SRLI
|
| 296 |
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c;
|
| 297 |
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_sr_c;
|
| 298 |
|
|
ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0000000";
|
| 299 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 0) <= ci_instr16_i(2);
|
| 300 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 1) <= ci_instr16_i(3);
|
| 301 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(4);
|
| 302 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5);
|
| 303 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6);
|
| 304 |
|
|
if (ci_instr16_i(12) = '1') then
|
| 305 |
|
|
ci_illegal_o <= '1';
|
| 306 |
|
|
end if;
|
| 307 |
|
|
when "01" => -- C.SRAI
|
| 308 |
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c;
|
| 309 |
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_sr_c;
|
| 310 |
|
|
ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0100000";
|
| 311 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 0) <= ci_instr16_i(2);
|
| 312 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 1) <= ci_instr16_i(3);
|
| 313 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(4);
|
| 314 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5);
|
| 315 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6);
|
| 316 |
|
|
if (ci_instr16_i(12) = '1') then
|
| 317 |
|
|
ci_illegal_o <= '1';
|
| 318 |
|
|
end if;
|
| 319 |
|
|
when "10" => -- C.ANDI
|
| 320 |
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c;
|
| 321 |
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_and_c;
|
| 322 |
|
|
ci_instr32_o(instr_imm12_msb_c downto instr_imm12_lsb_c) <= (others => ci_instr16_i(12)); -- sign extend
|
| 323 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 0) <= ci_instr16_i(2);
|
| 324 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 1) <= ci_instr16_i(3);
|
| 325 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(4);
|
| 326 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5);
|
| 327 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6);
|
| 328 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 5) <= ci_instr16_i(12);
|
| 329 |
|
|
when others => -- "11" = register-register operation
|
| 330 |
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alu_c;
|
| 331 |
|
|
case ci_instr16_i(6 downto 5) is
|
| 332 |
|
|
when "00" => -- C.SUB
|
| 333 |
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_subadd_c;
|
| 334 |
|
|
ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0100000";
|
| 335 |
|
|
when "01" => -- C.XOR
|
| 336 |
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_xor_c;
|
| 337 |
|
|
ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0000000";
|
| 338 |
|
|
when "10" => -- C.OR
|
| 339 |
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_or_c;
|
| 340 |
|
|
ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0000000";
|
| 341 |
|
|
when others => -- C.AND
|
| 342 |
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_and_c;
|
| 343 |
|
|
ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0000000";
|
| 344 |
|
|
end case;
|
| 345 |
|
|
end case;
|
| 346 |
2 |
zero_gravi |
|
| 347 |
|
|
when others => -- undefined
|
| 348 |
49 |
zero_gravi |
-- ----------------------------------------------------------------------------------------------------------
|
| 349 |
65 |
zero_gravi |
ci_instr32_o <= (others => '-');
|
| 350 |
2 |
zero_gravi |
ci_illegal_o <= '1';
|
| 351 |
49 |
zero_gravi |
|
| 352 |
2 |
zero_gravi |
end case;
|
| 353 |
|
|
|
| 354 |
|
|
when "10" => -- C2: Stack-Pointer-Based Loads and Stores, Control Transfer Instructions
|
| 355 |
|
|
case ci_instr16_i(ci_funct3_msb_c downto ci_funct3_lsb_c) is
|
| 356 |
|
|
|
| 357 |
|
|
when "000" => -- C.SLLI
|
| 358 |
|
|
-- ----------------------------------------------------------------------------------------------------------
|
| 359 |
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c;
|
| 360 |
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= ci_instr16_i(ci_rs1_5_msb_c downto ci_rs1_5_lsb_c);
|
| 361 |
|
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rs1_5_msb_c downto ci_rs1_5_lsb_c);
|
| 362 |
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_sll_c;
|
| 363 |
|
|
ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0000000";
|
| 364 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 0) <= ci_instr16_i(2);
|
| 365 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 1) <= ci_instr16_i(3);
|
| 366 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(4);
|
| 367 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5);
|
| 368 |
|
|
ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6);
|
| 369 |
73 |
zero_gravi |
if (ci_instr16_i(12) = '1') then
|
| 370 |
|
|
ci_illegal_o <= ci_instr16_i(12);
|
| 371 |
|
|
end if;
|
| 372 |
2 |
zero_gravi |
|
| 373 |
52 |
zero_gravi |
when "010" | "011" => -- C.LWSP / C.FLWSP
|
| 374 |
2 |
zero_gravi |
-- ----------------------------------------------------------------------------------------------------------
|
| 375 |
53 |
zero_gravi |
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_load_c;
|
| 376 |
2 |
zero_gravi |
ci_instr32_o(21 downto 20) <= "00";
|
| 377 |
|
|
ci_instr32_o(22) <= ci_instr16_i(4);
|
| 378 |
|
|
ci_instr32_o(23) <= ci_instr16_i(5);
|
| 379 |
|
|
ci_instr32_o(24) <= ci_instr16_i(6);
|
| 380 |
|
|
ci_instr32_o(25) <= ci_instr16_i(12);
|
| 381 |
|
|
ci_instr32_o(26) <= ci_instr16_i(2);
|
| 382 |
|
|
ci_instr32_o(27) <= ci_instr16_i(3);
|
| 383 |
|
|
ci_instr32_o(31 downto 28) <= (others => '0');
|
| 384 |
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_lw_c;
|
| 385 |
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00010"; -- stack pointer
|
| 386 |
|
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c);
|
| 387 |
73 |
zero_gravi |
if (ci_instr16_i(ci_funct3_lsb_c) = '1') and (FPU_ENABLE = false) then -- C.FLWSP
|
| 388 |
53 |
zero_gravi |
ci_illegal_o <= '1';
|
| 389 |
|
|
end if;
|
| 390 |
2 |
zero_gravi |
|
| 391 |
52 |
zero_gravi |
when "110" | "111" => -- C.SWSP / C.FSWSP
|
| 392 |
2 |
zero_gravi |
-- ----------------------------------------------------------------------------------------------------------
|
| 393 |
53 |
zero_gravi |
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_store_c;
|
| 394 |
2 |
zero_gravi |
ci_instr32_o(08 downto 07) <= "00";
|
| 395 |
|
|
ci_instr32_o(09) <= ci_instr16_i(9);
|
| 396 |
|
|
ci_instr32_o(10) <= ci_instr16_i(10);
|
| 397 |
|
|
ci_instr32_o(11) <= ci_instr16_i(11);
|
| 398 |
|
|
ci_instr32_o(25) <= ci_instr16_i(12);
|
| 399 |
|
|
ci_instr32_o(26) <= ci_instr16_i(7);
|
| 400 |
|
|
ci_instr32_o(27) <= ci_instr16_i(8);
|
| 401 |
|
|
ci_instr32_o(31 downto 28) <= (others => '0');
|
| 402 |
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_sw_c;
|
| 403 |
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00010"; -- stack pointer
|
| 404 |
|
|
ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= ci_instr16_i(ci_rs2_5_msb_c downto ci_rs2_5_lsb_c);
|
| 405 |
73 |
zero_gravi |
if (ci_instr16_i(ci_funct3_lsb_c) = '1') and (FPU_ENABLE = false) then -- C.FSWSP
|
| 406 |
53 |
zero_gravi |
ci_illegal_o <= '1';
|
| 407 |
|
|
end if;
|
| 408 |
2 |
zero_gravi |
|
| 409 |
|
|
when "100" => -- C.JR, C.JALR, C.MV, C.EBREAK, C.ADD
|
| 410 |
|
|
-- ----------------------------------------------------------------------------------------------------------
|
| 411 |
|
|
if (ci_instr16_i(12) = '0') then -- C.JR, C.MV
|
| 412 |
|
|
if (ci_instr16_i(6 downto 2) = "00000") then -- C.JR
|
| 413 |
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_jalr_c;
|
| 414 |
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= ci_instr16_i(ci_rs1_5_msb_c downto ci_rs1_5_lsb_c);
|
| 415 |
|
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "00000"; -- discard return address
|
| 416 |
|
|
else -- C.MV
|
| 417 |
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alu_c;
|
| 418 |
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= "000";
|
| 419 |
|
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c);
|
| 420 |
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00000"; -- x0
|
| 421 |
|
|
ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= ci_instr16_i(ci_rs2_5_msb_c downto ci_rs2_5_lsb_c);
|
| 422 |
|
|
end if;
|
| 423 |
|
|
else -- C.EBREAK, C.JALR, C.ADD
|
| 424 |
|
|
if (ci_instr16_i(6 downto 2) = "00000") then -- C.EBREAK, C.JALR
|
| 425 |
|
|
if (ci_instr16_i(11 downto 7) = "00000") then -- C.EBREAK
|
| 426 |
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_syscsr_c;
|
| 427 |
|
|
ci_instr32_o(instr_funct12_msb_c downto instr_funct12_lsb_c) <= "000000000001";
|
| 428 |
|
|
else -- C.JALR
|
| 429 |
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_jalr_c;
|
| 430 |
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= ci_instr16_i(ci_rs1_5_msb_c downto ci_rs1_5_lsb_c);
|
| 431 |
|
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "00001"; -- save return address to link register
|
| 432 |
|
|
end if;
|
| 433 |
|
|
else -- C.ADD
|
| 434 |
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alu_c;
|
| 435 |
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= "000";
|
| 436 |
|
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c);
|
| 437 |
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c);
|
| 438 |
|
|
ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= ci_instr16_i(ci_rs2_5_msb_c downto ci_rs2_5_lsb_c);
|
| 439 |
|
|
end if;
|
| 440 |
|
|
end if;
|
| 441 |
|
|
|
| 442 |
|
|
when others => -- undefined
|
| 443 |
49 |
zero_gravi |
-- ----------------------------------------------------------------------------------------------------------
|
| 444 |
65 |
zero_gravi |
ci_instr32_o <= (others => '-');
|
| 445 |
2 |
zero_gravi |
ci_illegal_o <= '1';
|
| 446 |
49 |
zero_gravi |
|
| 447 |
2 |
zero_gravi |
end case;
|
| 448 |
|
|
|
| 449 |
|
|
when others => -- not a compressed instruction
|
| 450 |
49 |
zero_gravi |
-- ----------------------------------------------------------------------------------------------------------
|
| 451 |
65 |
zero_gravi |
ci_instr32_o <= (others => '-');
|
| 452 |
|
|
ci_illegal_o <= '0';
|
| 453 |
2 |
zero_gravi |
|
| 454 |
|
|
end case;
|
| 455 |
|
|
end process decompressor;
|
| 456 |
|
|
|
| 457 |
|
|
|
| 458 |
|
|
end neorv32_cpu_decompressor_rtl;
|
