OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_regfile.vhd] - Blame information for rev 45

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 zero_gravi
-- #################################################################################################
2 45 zero_gravi
-- # << NEORV32 - CPU General Purpose Data Register File >>                                        #
3 2 zero_gravi
-- # ********************************************************************************************* #
4 45 zero_gravi
-- # General purpose data register file. 32 entries (= 1024 bit) for normal mode (RV32I),          #
5
-- # 16 entries (= 512 bit) for embedded mode (RV32E) when RISC-V "E" extension is enabled.        #
6
-- #                                                                                               #
7
-- # Register zero (r0/x0) is a "normal" physical reg that has to be initialized to zero by the    #
8
-- # CPU control system. For normal operations register zero cannot be written.                    #
9
-- #                                                                                               #
10
-- # The register file uses synchronous read accesses and a *single* (multiplexed) address port    #
11
-- # for writing and reading rs1 and a single read-only port for rs2. Therefore, the whole         #
12
-- # register file can be mapped to a single true dual-port block RAM.                             #
13 2 zero_gravi
-- # ********************************************************************************************* #
14
-- # BSD 3-Clause License                                                                          #
15
-- #                                                                                               #
16 45 zero_gravi
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
17 2 zero_gravi
-- #                                                                                               #
18
-- # Redistribution and use in source and binary forms, with or without modification, are          #
19
-- # permitted provided that the following conditions are met:                                     #
20
-- #                                                                                               #
21
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
22
-- #    conditions and the following disclaimer.                                                   #
23
-- #                                                                                               #
24
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
25
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
26
-- #    provided with the distribution.                                                            #
27
-- #                                                                                               #
28
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
29
-- #    endorse or promote products derived from this software without specific prior written      #
30
-- #    permission.                                                                                #
31
-- #                                                                                               #
32
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
33
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
34
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
35
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
36
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
37
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
38
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
39
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
40
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
41
-- # ********************************************************************************************* #
42
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
43
-- #################################################################################################
44
 
45
library ieee;
46
use ieee.std_logic_1164.all;
47
use ieee.numeric_std.all;
48
 
49
library neorv32;
50
use neorv32.neorv32_package.all;
51
 
52
entity neorv32_cpu_regfile is
53
  generic (
54
    CPU_EXTENSION_RISCV_E : boolean := false -- implement embedded RF extension?
55
  );
56
  port (
57
    -- global control --
58
    clk_i  : in  std_ulogic; -- global clock, rising edge
59
    ctrl_i : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
60
    -- data input --
61
    mem_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
62
    alu_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
63
    csr_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
64
    -- data output --
65
    rs1_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
66
    rs2_o  : out std_ulogic_vector(data_width_c-1 downto 0)  -- operand 2
67
  );
68
end neorv32_cpu_regfile;
69
 
70
architecture neorv32_cpu_regfile_rtl of neorv32_cpu_regfile is
71
 
72
  -- register file --
73
  type   reg_file_t is array (31 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
74
  type   reg_file_emb_t is array (15 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
75
  signal reg_file      : reg_file_t;
76
  signal reg_file_emb  : reg_file_emb_t;
77 39 zero_gravi
  signal rf_mux_data   : std_ulogic_vector(data_width_c-1 downto 0);
78 2 zero_gravi
  signal rf_write_data : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data
79 36 zero_gravi
  signal rd_is_r0      : std_ulogic; -- writing to r0?
80
  signal rf_we         : std_ulogic;
81
  signal dst_addr      : std_ulogic_vector(4 downto 0); -- destination address
82 45 zero_gravi
  signal opa_addr      : std_ulogic_vector(4 downto 0); -- rs1/dst address
83
  signal opb_addr      : std_ulogic_vector(4 downto 0); -- rs2 address
84 2 zero_gravi
 
85
begin
86
 
87 45 zero_gravi
  -- Data Input Mux -------------------------------------------------------------------------
88 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
89 45 zero_gravi
  rf_mux_data   <= mem_i when (ctrl_i(ctrl_rf_in_mux_lsb_c) = '0') else csr_i;
90
  rf_write_data <= alu_i when (ctrl_i(ctrl_rf_in_mux_msb_c) = '0') else rf_mux_data;
91
 
92
 
93
  -- Register File Access -------------------------------------------------------------------
94
  -- -------------------------------------------------------------------------------------------
95 2 zero_gravi
  rf_access: process(clk_i)
96
  begin
97 9 zero_gravi
    if rising_edge(clk_i) then -- sync read and write
98 2 zero_gravi
      if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries
99 36 zero_gravi
        if (rf_we = '1') then
100 45 zero_gravi
          reg_file(to_integer(unsigned(opa_addr(4 downto 0)))) <= rf_write_data;
101 2 zero_gravi
        end if;
102 45 zero_gravi
        rs1_o <= reg_file(to_integer(unsigned(opa_addr(4 downto 0))));
103
        rs2_o <= reg_file(to_integer(unsigned(opb_addr(4 downto 0))));
104 2 zero_gravi
      else -- embedded register file with 16 entries
105 36 zero_gravi
        if (rf_we = '1') then
106 45 zero_gravi
          reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0)))) <= rf_write_data;
107 2 zero_gravi
        end if;
108 45 zero_gravi
        rs1_o <= reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0))));
109
        rs2_o <= reg_file_emb(to_integer(unsigned(opb_addr(3 downto 0))));
110 2 zero_gravi
      end if;
111
    end if;
112
  end process rf_access;
113
 
114 39 zero_gravi
  -- check if we are writing to x0 --
115
  rd_is_r0 <= not or_all_f(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)) when (CPU_EXTENSION_RISCV_E = false) else
116
              not or_all_f(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c));
117
 
118 45 zero_gravi
  -- valid RF write access? --
119 39 zero_gravi
  rf_we <= (ctrl_i(ctrl_rf_wb_en_c) and (not rd_is_r0)) or ctrl_i(ctrl_rf_r0_we_c);
120
 
121
  -- destination address --
122
  dst_addr <= ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) when (ctrl_i(ctrl_rf_r0_we_c) = '0') else (others => '0'); -- force dst=r0?
123
 
124 45 zero_gravi
  -- access addresses --
125
  opa_addr <= dst_addr when (rf_we = '1') else ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- rd/rs1
126
  opb_addr <= ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c); -- rs2
127 39 zero_gravi
 
128
 
129 2 zero_gravi
end neorv32_cpu_regfile_rtl;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.