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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_debug_dtm.vhd] - Blame information for rev 68

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1 59 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - RISC-V Debug Transport Module (DTM) >>                                           #
3
-- # ********************************************************************************************* #
4
-- # Provides a JTAG-compatible TAP to access the DMI register interface.                          #
5
-- # Compatible to the RISC-V debug specification.                                                 #
6
-- # ********************************************************************************************* #
7
-- # BSD 3-Clause License                                                                          #
8
-- #                                                                                               #
9
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
10
-- #                                                                                               #
11
-- # Redistribution and use in source and binary forms, with or without modification, are          #
12
-- # permitted provided that the following conditions are met:                                     #
13
-- #                                                                                               #
14
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
15
-- #    conditions and the following disclaimer.                                                   #
16
-- #                                                                                               #
17
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
18
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
19
-- #    provided with the distribution.                                                            #
20
-- #                                                                                               #
21
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
22
-- #    endorse or promote products derived from this software without specific prior written      #
23
-- #    permission.                                                                                #
24
-- #                                                                                               #
25
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
26
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
27
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
28
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
29
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
30
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
31
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
32
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
33
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
34
-- # ********************************************************************************************* #
35
-- # https://github.com/stnolting/riscv-debug-dtm                              (c) Stephan Nolting #
36
-- #################################################################################################
37
 
38
library ieee;
39
use ieee.std_logic_1164.all;
40
 
41
entity neorv32_debug_dtm is
42
  generic (
43 62 zero_gravi
    IDCODE_VERSION : std_ulogic_vector(03 downto 0); -- version
44
    IDCODE_PARTID  : std_ulogic_vector(15 downto 0); -- part number
45
    IDCODE_MANID   : std_ulogic_vector(10 downto 0)  -- manufacturer id
46 59 zero_gravi
  );
47
  port (
48
    -- global control --
49
    clk_i            : in  std_ulogic; -- global clock line
50
    rstn_i           : in  std_ulogic; -- global reset line, low-active
51
    -- jtag connection --
52
    jtag_trst_i      : in  std_ulogic;
53
    jtag_tck_i       : in  std_ulogic;
54
    jtag_tdi_i       : in  std_ulogic;
55
    jtag_tdo_o       : out std_ulogic;
56
    jtag_tms_i       : in  std_ulogic;
57
    -- debug module interface (DMI) --
58
    dmi_rstn_o       : out std_ulogic;
59
    dmi_req_valid_o  : out std_ulogic;
60
    dmi_req_ready_i  : in  std_ulogic; -- DMI is allowed to make new requests when set
61
    dmi_req_addr_o   : out std_ulogic_vector(06 downto 0);
62
    dmi_req_op_o     : out std_ulogic; -- 0=read, 1=write
63
    dmi_req_data_o   : out std_ulogic_vector(31 downto 0);
64
    dmi_resp_valid_i : in  std_ulogic; -- response valid when set
65
    dmi_resp_ready_o : out std_ulogic; -- ready to receive respond
66
    dmi_resp_data_i  : in  std_ulogic_vector(31 downto 0);
67
    dmi_resp_err_i   : in  std_ulogic -- 0=ok, 1=error
68
  );
69
end neorv32_debug_dtm;
70
 
71
architecture neorv32_debug_dtm_rtl of neorv32_debug_dtm is
72
 
73
  -- DMI Configuration (fixed!) --
74 68 zero_gravi
  constant dmi_idle_c    : std_ulogic_vector(02 downto 0) := "000"; -- no idle cycles required
75 59 zero_gravi
  constant dmi_version_c : std_ulogic_vector(03 downto 0) := "0001"; -- version (0.13)
76
  constant dmi_abits_c   : std_ulogic_vector(05 downto 0) := "000111"; -- number of DMI address bits (7)
77
 
78 68 zero_gravi
  -- tap JTAG signal synchronizer --
79
  type tap_sync_t is record
80
    -- internal --
81
    trst_ff     : std_ulogic_vector(2 downto 0);
82
    tck_ff      : std_ulogic_vector(2 downto 0);
83
    tdi_ff      : std_ulogic_vector(2 downto 0);
84
    tms_ff      : std_ulogic_vector(2 downto 0);
85
    -- external --
86
    trst        : std_ulogic;
87
    tck_rising  : std_ulogic;
88
    tck_falling : std_ulogic;
89
    tdi         : std_ulogic;
90
    tdo         : std_ulogic;
91
    tms         : std_ulogic;
92
  end record;
93
  signal tap_sync : tap_sync_t;
94
 
95 59 zero_gravi
  -- tap controller - fsm --
96
  type tap_ctrl_state_t is (LOGIC_RESET, DR_SCAN, DR_CAPTURE, DR_SHIFT, DR_EXIT1, DR_PAUSE, DR_EXIT2, DR_UPDATE,
97
                               RUN_IDLE, IR_SCAN, IR_CAPTURE, IR_SHIFT, IR_EXIT1, IR_PAUSE, IR_EXIT2, IR_UPDATE);
98
  type tap_ctrl_t is record
99
    state      : tap_ctrl_state_t;
100
    state_prev : tap_ctrl_state_t;
101
  end record;
102
  signal tap_ctrl : tap_ctrl_t;
103
 
104
  -- tap registers --
105
  type tap_reg_t is record
106
    ireg             : std_ulogic_vector(04 downto 0);
107
    bypass           : std_ulogic;
108
    idcode           : std_ulogic_vector(31 downto 0);
109
    dtmcs, dtmcs_nxt : std_ulogic_vector(31 downto 0);
110
    dmi,   dmi_nxt   : std_ulogic_vector((7+32+2)-1 downto 0); -- 7-bit address + 32-bit data + 2-bit operation
111
  end record;
112
  signal tap_reg : tap_reg_t;
113
 
114
  -- debug module interface --
115
  type dmi_ctrl_state_t is (DMI_IDLE, DMI_READ_WAIT, DMI_READ, DMI_READ_BUSY,
116
                            DMI_WRITE_WAIT, DMI_WRITE, DMI_WRITE_BUSY);
117
  type dmi_ctrl_t is record
118
    state        : dmi_ctrl_state_t;
119
    --
120
    dmihardreset : std_ulogic;
121
    dmireset     : std_ulogic;
122
    --
123
    err          : std_ulogic; -- sticky error
124
    rdata        : std_ulogic_vector(31 downto 0);
125
    wdata        : std_ulogic_vector(31 downto 0);
126
    addr         : std_ulogic_vector(06 downto 0);
127
  end record;
128
  signal dmi_ctrl : dmi_ctrl_t;
129
 
130
begin
131
 
132 68 zero_gravi
  -- JTAG Signal Synchronizer ---------------------------------------------------------------
133
  -- -------------------------------------------------------------------------------------------
134
  tap_synchronizer: process(rstn_i, clk_i)
135
  begin
136
    if rising_edge(clk_i) then
137
      tap_sync.trst_ff <= tap_sync.trst_ff(1 downto 0) & jtag_trst_i;
138
      tap_sync.tck_ff  <= tap_sync.tck_ff( 1 downto 0) & jtag_tck_i;
139
      tap_sync.tdi_ff  <= tap_sync.tdi_ff( 1 downto 0) & jtag_tdi_i;
140
      tap_sync.tms_ff  <= tap_sync.tms_ff( 1 downto 0) & jtag_tms_i;
141
      if (tap_sync.tck_falling = '1') then -- update output data TDO on falling edge of TCK
142
        jtag_tdo_o <= tap_sync.tdo;
143
      end if;
144
    end if;
145
  end process tap_synchronizer;
146
 
147
  -- JTAG reset --
148
  tap_sync.trst <= '0' when (tap_sync.trst_ff(2 downto 1) = "00") else '1';
149
 
150
  -- JTAG clock edge --
151
  tap_sync.tck_rising  <= '1' when (tap_sync.tck_ff(2 downto 1) = "01") else '0';
152
  tap_sync.tck_falling <= '1' when (tap_sync.tck_ff(2 downto 1) = "10") else '0';
153
 
154
  -- JTAG test mode select --
155
  tap_sync.tms <= tap_sync.tms_ff(2);
156
 
157
  -- JTAG serial data input --
158
  tap_sync.tdi <= tap_sync.tdi_ff(2);
159
 
160
 
161 59 zero_gravi
  -- Tap Control FSM ------------------------------------------------------------------------
162
  -- -------------------------------------------------------------------------------------------
163
  tap_control: process(rstn_i, clk_i)
164
  begin
165
    if (rstn_i = '0') then
166
      tap_ctrl.state      <= LOGIC_RESET;
167
      tap_ctrl.state_prev <= LOGIC_RESET;
168
    elsif rising_edge(clk_i) then
169
      tap_ctrl.state_prev <= tap_ctrl.state;
170 68 zero_gravi
      if (tap_sync.trst = '0') then -- reset
171 59 zero_gravi
        tap_ctrl.state <= LOGIC_RESET;
172 68 zero_gravi
      elsif (tap_sync.tck_rising = '1') then -- clock pulse (evaluate TMS on the rising edge of TCK)
173 59 zero_gravi
        case tap_ctrl.state is -- JTAG state machine
174 68 zero_gravi
          when LOGIC_RESET => if (tap_sync.tms = '0') then tap_ctrl.state <= RUN_IDLE;   else tap_ctrl.state <= LOGIC_RESET; end if;
175
          when RUN_IDLE    => if (tap_sync.tms = '0') then tap_ctrl.state <= RUN_IDLE;   else tap_ctrl.state <= DR_SCAN;     end if;
176
          when DR_SCAN     => if (tap_sync.tms = '0') then tap_ctrl.state <= DR_CAPTURE; else tap_ctrl.state <= IR_SCAN;     end if;
177
          when DR_CAPTURE  => if (tap_sync.tms = '0') then tap_ctrl.state <= DR_SHIFT;   else tap_ctrl.state <= DR_EXIT1;    end if;
178
          when DR_SHIFT    => if (tap_sync.tms = '0') then tap_ctrl.state <= DR_SHIFT;   else tap_ctrl.state <= DR_EXIT1;    end if;
179
          when DR_EXIT1    => if (tap_sync.tms = '0') then tap_ctrl.state <= DR_PAUSE;   else tap_ctrl.state <= DR_UPDATE;   end if;
180
          when DR_PAUSE    => if (tap_sync.tms = '0') then tap_ctrl.state <= DR_PAUSE;   else tap_ctrl.state <= DR_EXIT2;    end if;
181
          when DR_EXIT2    => if (tap_sync.tms = '0') then tap_ctrl.state <= DR_SHIFT;   else tap_ctrl.state <= DR_UPDATE;   end if;
182
          when DR_UPDATE   => if (tap_sync.tms = '0') then tap_ctrl.state <= RUN_IDLE;   else tap_ctrl.state <= DR_SCAN;     end if;
183
          when IR_SCAN     => if (tap_sync.tms = '0') then tap_ctrl.state <= IR_CAPTURE; else tap_ctrl.state <= LOGIC_RESET; end if;
184
          when IR_CAPTURE  => if (tap_sync.tms = '0') then tap_ctrl.state <= IR_SHIFT;   else tap_ctrl.state <= IR_EXIT1;    end if;
185
          when IR_SHIFT    => if (tap_sync.tms = '0') then tap_ctrl.state <= IR_SHIFT;   else tap_ctrl.state <= IR_EXIT1;    end if;
186
          when IR_EXIT1    => if (tap_sync.tms = '0') then tap_ctrl.state <= IR_PAUSE;   else tap_ctrl.state <= IR_UPDATE;   end if;
187
          when IR_PAUSE    => if (tap_sync.tms = '0') then tap_ctrl.state <= IR_PAUSE;   else tap_ctrl.state <= IR_EXIT2;    end if;
188
          when IR_EXIT2    => if (tap_sync.tms = '0') then tap_ctrl.state <= IR_SHIFT;   else tap_ctrl.state <= IR_UPDATE;   end if;
189
          when IR_UPDATE   => if (tap_sync.tms = '0') then tap_ctrl.state <= RUN_IDLE;   else tap_ctrl.state <= DR_SCAN;     end if;
190 59 zero_gravi
          when others      => tap_ctrl.state <= LOGIC_RESET;
191
        end case;
192
      end if;
193
    end if;
194
  end process tap_control;
195
 
196
 
197
  -- Tap Register Access --------------------------------------------------------------------
198
  -- -------------------------------------------------------------------------------------------
199
  reg_access: process(clk_i)
200
  begin
201
    if rising_edge(clk_i) then
202 68 zero_gravi
      -- serial data input --
203
      if (tap_sync.tck_rising = '1') then -- clock pulse (evaluate TDI on rising edge of TCK)
204 59 zero_gravi
 
205
        -- instruction register --
206 68 zero_gravi
        if (tap_ctrl.state = LOGIC_RESET) or (tap_ctrl.state = IR_CAPTURE) then -- reset or preload phase
207 59 zero_gravi
          tap_reg.ireg <= "00001"; -- IDCODE
208
        elsif (tap_ctrl.state = IR_SHIFT) then -- access phase
209 68 zero_gravi
          tap_reg.ireg <= tap_sync.tdi & tap_reg.ireg(tap_reg.ireg'left downto 1);
210 59 zero_gravi
        end if;
211
 
212
        -- data register --
213
        if (tap_ctrl.state = DR_CAPTURE) then -- preload phase
214
          case tap_reg.ireg is
215 68 zero_gravi
            when "00001" => tap_reg.idcode <= IDCODE_VERSION & IDCODE_PARTID & IDCODE_MANID & '1'; -- IDCODE (LSB has to be always set!)
216 59 zero_gravi
            when "10000" => tap_reg.dtmcs  <= tap_reg.dtmcs_nxt;-- dtmcs
217
            when "10001" => tap_reg.dmi    <= tap_reg.dmi_nxt; -- dmi
218
            when others  => tap_reg.bypass <= '0'; -- BYPASS
219
          end case;
220
        elsif (tap_ctrl.state = DR_SHIFT) then -- access phase
221
          case tap_reg.ireg is
222 68 zero_gravi
            when "00001" => tap_reg.idcode <= tap_sync.tdi & tap_reg.idcode(tap_reg.idcode'left downto 1); -- IDCODE
223
            when "10000" => tap_reg.dtmcs  <= tap_sync.tdi & tap_reg.dtmcs(tap_reg.dtmcs'left downto 1); -- dtmcs
224
            when "10001" => tap_reg.dmi    <= tap_sync.tdi & tap_reg.dmi(tap_reg.dmi'left downto 1); -- dmi
225
            when others  => tap_reg.bypass <= tap_sync.tdi; -- BYPASS
226 59 zero_gravi
          end case;
227
        end if;
228
      end if;
229
 
230
      -- serial data output --
231
      if (tap_ctrl.state = IR_SHIFT) then
232 68 zero_gravi
        tap_sync.tdo <= tap_reg.ireg(0);
233 59 zero_gravi
      else
234
        case tap_reg.ireg is
235 68 zero_gravi
          when "00001" => tap_sync.tdo <= tap_reg.idcode(0); -- IDCODE
236
          when "10000" => tap_sync.tdo <= tap_reg.dtmcs(0); -- dtmcs
237
          when "10001" => tap_sync.tdo <= tap_reg.dmi(0); -- dmi
238
          when others  => tap_sync.tdo <= tap_reg.bypass; -- BYPASS
239 59 zero_gravi
        end case;
240
      end if;
241
    end if;
242
  end process reg_access;
243
 
244
 
245
  -- Debug Module Interface -----------------------------------------------------------------
246
  -- -------------------------------------------------------------------------------------------
247
  dmi_controller: process(rstn_i, clk_i)
248
  begin
249
    if (rstn_i = '0') then
250
      dmi_ctrl.state        <= DMI_IDLE;
251
      dmi_ctrl.dmihardreset <= '1';
252
      dmi_ctrl.dmireset     <= '1';
253
      dmi_ctrl.err          <= '0';
254
      dmi_ctrl.rdata        <= (others => '-');
255
      dmi_ctrl.wdata        <= (others => '-');
256
      dmi_ctrl.addr         <= (others => '-');
257
    elsif rising_edge(clk_i) then
258
 
259
      -- DMI status and control --
260
      dmi_ctrl.dmihardreset <= '0'; -- default
261
      dmi_ctrl.dmireset     <= '0'; -- default
262
      if (tap_ctrl.state = DR_UPDATE) and (tap_ctrl.state_prev /= DR_UPDATE) and (tap_reg.ireg = "10000") then
263
        dmi_ctrl.dmireset     <= tap_reg.dtmcs(16);
264
        dmi_ctrl.dmihardreset <= tap_reg.dtmcs(17);
265
      end if;
266
 
267
      -- DMI interface arbiter --
268
      if (dmi_ctrl.dmihardreset = '1') then -- DMI hard reset
269
        dmi_ctrl.state <= DMI_IDLE;
270
        dmi_ctrl.err   <= '0';
271
      else
272
        case dmi_ctrl.state is
273
 
274
          when DMI_IDLE => -- waiting for new request
275
            if (tap_ctrl.state = DR_UPDATE) and (tap_ctrl.state_prev /= DR_UPDATE) and (tap_reg.ireg = "10001") then -- update <dmi>
276 68 zero_gravi
              if (tap_reg.dmi(1 downto 0) = "01") then -- read
277
                dmi_ctrl.state <= DMI_READ_WAIT;
278
              elsif (tap_reg.dmi(1 downto 0) = "10") then -- write
279
                dmi_ctrl.state <= DMI_WRITE_WAIT;
280
              end if;
281
              dmi_ctrl.addr  <= tap_reg.dmi(40 downto 34);
282
              dmi_ctrl.wdata <= tap_reg.dmi(33 downto 02);
283 59 zero_gravi
            end if;
284
 
285 68 zero_gravi
 
286 59 zero_gravi
          when DMI_READ_WAIT => -- wait for DMI to become ready
287
            if (dmi_req_ready_i = '1') then
288
              dmi_ctrl.state <= DMI_READ;
289
            end if;
290
 
291
          when DMI_READ => -- start read access
292
            dmi_ctrl.state <= DMI_READ_BUSY;
293
 
294
          when DMI_READ_BUSY => -- pending read access
295
            if (dmi_resp_valid_i = '1') then
296
              dmi_ctrl.rdata <= dmi_resp_data_i;
297
              dmi_ctrl.err   <= dmi_ctrl.err or dmi_resp_err_i; -- sticky error
298
              dmi_ctrl.state <= DMI_IDLE;
299
            end if;
300
 
301 68 zero_gravi
 
302 59 zero_gravi
          when DMI_WRITE_WAIT => -- wait for DMI to become ready
303
            if (dmi_req_ready_i = '1') then
304
              dmi_ctrl.state <= DMI_WRITE;
305
            end if;
306
 
307
          when DMI_WRITE => -- start write access
308
            dmi_ctrl.state <= DMI_WRITE_BUSY;
309
 
310
          when DMI_WRITE_BUSY => -- pending write access
311
            if (dmi_resp_valid_i = '1') then
312
              dmi_ctrl.err   <= dmi_ctrl.err or dmi_resp_err_i; -- sticky error
313
              dmi_ctrl.state <= DMI_IDLE;
314
            end if;
315
 
316 68 zero_gravi
 
317 59 zero_gravi
          when others => -- undefined
318
            dmi_ctrl.state <= DMI_IDLE;
319
 
320
        end case;
321 68 zero_gravi
        -- clear sticky error flag --
322 59 zero_gravi
        if (dmi_ctrl.dmireset = '1') then
323
          dmi_ctrl.err <= '0';
324
        end if;
325
      end if;
326
    end if;
327
  end process dmi_controller;
328
 
329 68 zero_gravi
  -- DTM Control and Status Register (dtmcs) --
330
  tap_reg.dtmcs_nxt(31 downto 18) <= (others => '0'); -- unused
331
  tap_reg.dtmcs_nxt(17)           <= '0'; -- dmihardreset, always reads as zero
332
  tap_reg.dtmcs_nxt(16)           <= '0'; -- dmireset, always reads as zero
333
  tap_reg.dtmcs_nxt(15)           <= '0'; -- unused
334
  tap_reg.dtmcs_nxt(14 downto 12) <= dmi_idle_c; -- minimum number of idle cycles
335
  tap_reg.dtmcs_nxt(11 downto 10) <= tap_reg.dmi_nxt(1 downto 0); -- dmistat
336
  tap_reg.dtmcs_nxt(09 downto 04) <= dmi_abits_c; -- number of DMI address bits
337
  tap_reg.dtmcs_nxt(03 downto 00) <= dmi_version_c; -- version
338
 
339 59 zero_gravi
  -- DMI register read access --
340
  tap_reg.dmi_nxt(40 downto 34) <= dmi_ctrl.addr; -- address
341
  tap_reg.dmi_nxt(33 downto 02) <= dmi_ctrl.rdata; -- read data
342
  tap_reg.dmi_nxt(01 downto 00) <= "11" when (dmi_ctrl.state /= DMI_IDLE) else (dmi_ctrl.err & '0'); -- status
343
 
344
  -- direct DMI output --
345
  dmi_rstn_o       <= '0' when (dmi_ctrl.dmihardreset = '1') else '1';
346
  dmi_req_valid_o  <= '1' when (dmi_ctrl.state = DMI_READ) or (dmi_ctrl.state = DMI_WRITE) else '0';
347
  dmi_req_op_o     <= '1' when (dmi_ctrl.state = DMI_WRITE) or (dmi_ctrl.state = DMI_WRITE_BUSY) else '0';
348
  dmi_resp_ready_o <= '1' when (dmi_ctrl.state = DMI_READ_BUSY) or (dmi_ctrl.state = DMI_WRITE_BUSY) else '0';
349
  dmi_req_addr_o   <= dmi_ctrl.addr;
350
  dmi_req_data_o   <= dmi_ctrl.wdata;
351
 
352
 
353
end neorv32_debug_dtm_rtl;

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