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zero_gravi |
-- #################################################################################################
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-- # << NEORV32 - RISC-V Debug Transport Module (DTM) >> #
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-- # ********************************************************************************************* #
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-- # Provides a JTAG-compatible TAP to access the DMI register interface. #
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-- # Compatible to the RISC-V debug specification. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # https://github.com/stnolting/riscv-debug-dtm (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity neorv32_debug_dtm is
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generic (
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zero_gravi |
IDCODE_VERSION : std_ulogic_vector(03 downto 0); -- version
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IDCODE_PARTID : std_ulogic_vector(15 downto 0); -- part number
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IDCODE_MANID : std_ulogic_vector(10 downto 0) -- manufacturer id
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zero_gravi |
);
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port (
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-- global control --
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active
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-- jtag connection --
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jtag_trst_i : in std_ulogic;
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jtag_tck_i : in std_ulogic;
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jtag_tdi_i : in std_ulogic;
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jtag_tdo_o : out std_ulogic;
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jtag_tms_i : in std_ulogic;
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-- debug module interface (DMI) --
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dmi_rstn_o : out std_ulogic;
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dmi_req_valid_o : out std_ulogic;
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dmi_req_ready_i : in std_ulogic; -- DMI is allowed to make new requests when set
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dmi_req_addr_o : out std_ulogic_vector(06 downto 0);
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dmi_req_op_o : out std_ulogic; -- 0=read, 1=write
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dmi_req_data_o : out std_ulogic_vector(31 downto 0);
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dmi_resp_valid_i : in std_ulogic; -- response valid when set
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dmi_resp_ready_o : out std_ulogic; -- ready to receive respond
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dmi_resp_data_i : in std_ulogic_vector(31 downto 0);
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dmi_resp_err_i : in std_ulogic -- 0=ok, 1=error
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);
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end neorv32_debug_dtm;
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architecture neorv32_debug_dtm_rtl of neorv32_debug_dtm is
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-- DMI Configuration (fixed!) --
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constant dmi_idle_c : std_ulogic_vector(02 downto 0) := "010"; -- minimum number if idle cycles
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constant dmi_version_c : std_ulogic_vector(03 downto 0) := "0001"; -- version (0.13)
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constant dmi_abits_c : std_ulogic_vector(05 downto 0) := "000111"; -- number of DMI address bits (7)
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-- tap controller - fsm --
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type tap_ctrl_state_t is (LOGIC_RESET, DR_SCAN, DR_CAPTURE, DR_SHIFT, DR_EXIT1, DR_PAUSE, DR_EXIT2, DR_UPDATE,
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RUN_IDLE, IR_SCAN, IR_CAPTURE, IR_SHIFT, IR_EXIT1, IR_PAUSE, IR_EXIT2, IR_UPDATE);
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type tap_ctrl_t is record
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state : tap_ctrl_state_t;
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state_prev : tap_ctrl_state_t;
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trst_sync : std_ulogic_vector(01 downto 0);
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tck_sync : std_ulogic_vector(02 downto 0);
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tdi_sync : std_ulogic_vector(01 downto 0);
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tdo_sync : std_ulogic;
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tms_sync : std_ulogic_vector(01 downto 0);
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end record;
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signal tap_ctrl : tap_ctrl_t;
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-- tap registers --
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type tap_reg_t is record
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ireg : std_ulogic_vector(04 downto 0);
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bypass : std_ulogic;
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idcode : std_ulogic_vector(31 downto 0);
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dtmcs, dtmcs_nxt : std_ulogic_vector(31 downto 0);
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dmi, dmi_nxt : std_ulogic_vector((7+32+2)-1 downto 0); -- 7-bit address + 32-bit data + 2-bit operation
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end record;
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signal tap_reg : tap_reg_t;
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-- debug module interface --
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type dmi_ctrl_state_t is (DMI_IDLE, DMI_READ_WAIT, DMI_READ, DMI_READ_BUSY,
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DMI_WRITE_WAIT, DMI_WRITE, DMI_WRITE_BUSY);
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type dmi_ctrl_t is record
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state : dmi_ctrl_state_t;
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--
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dmihardreset : std_ulogic;
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dmireset : std_ulogic;
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--
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err : std_ulogic; -- sticky error
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rdata : std_ulogic_vector(31 downto 0);
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wdata : std_ulogic_vector(31 downto 0);
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addr : std_ulogic_vector(06 downto 0);
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end record;
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signal dmi_ctrl : dmi_ctrl_t;
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begin
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-- Tap Control FSM ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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tap_control: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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tap_ctrl.trst_sync <= (others => '0');
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tap_ctrl.tck_sync <= (others => '0');
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tap_ctrl.tdi_sync <= (others => '0');
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tap_ctrl.tms_sync <= (others => '0');
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jtag_tdo_o <= '0';
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--
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tap_ctrl.state <= LOGIC_RESET;
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tap_ctrl.state_prev <= LOGIC_RESET;
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elsif rising_edge(clk_i) then
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-- synchronizer --
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tap_ctrl.trst_sync <= tap_ctrl.trst_sync(0) & jtag_trst_i;
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tap_ctrl.tck_sync <= tap_ctrl.tck_sync(1 downto 0) & jtag_tck_i;
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tap_ctrl.tdi_sync <= tap_ctrl.tdi_sync(0) & jtag_tdi_i;
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tap_ctrl.tms_sync <= tap_ctrl.tms_sync(0) & jtag_tms_i;
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jtag_tdo_o <= tap_ctrl.tdo_sync;
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-- state machine --
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tap_ctrl.state_prev <= tap_ctrl.state;
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if (tap_ctrl.trst_sync(1) = '0') then -- reset
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tap_ctrl.state <= LOGIC_RESET;
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elsif (tap_ctrl.tck_sync(2) = '0') and (tap_ctrl.tck_sync(1) = '1') then -- clock pulse (trigger on rising edge)
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case tap_ctrl.state is -- JTAG state machine
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when LOGIC_RESET => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= RUN_IDLE; else tap_ctrl.state <= LOGIC_RESET; end if;
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when RUN_IDLE => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= RUN_IDLE; else tap_ctrl.state <= DR_SCAN; end if;
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when DR_SCAN => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= DR_CAPTURE; else tap_ctrl.state <= IR_SCAN; end if;
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when DR_CAPTURE => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= DR_SHIFT; else tap_ctrl.state <= DR_EXIT1; end if;
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when DR_SHIFT => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= DR_SHIFT; else tap_ctrl.state <= DR_EXIT1; end if;
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when DR_EXIT1 => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= DR_PAUSE; else tap_ctrl.state <= DR_UPDATE; end if;
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when DR_PAUSE => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= DR_PAUSE; else tap_ctrl.state <= DR_EXIT2; end if;
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when DR_EXIT2 => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= DR_SHIFT; else tap_ctrl.state <= DR_UPDATE; end if;
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when DR_UPDATE => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= RUN_IDLE; else tap_ctrl.state <= DR_SCAN; end if;
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when IR_SCAN => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= IR_CAPTURE; else tap_ctrl.state <= LOGIC_RESET; end if;
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when IR_CAPTURE => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= IR_SHIFT; else tap_ctrl.state <= IR_EXIT1; end if;
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when IR_SHIFT => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= IR_SHIFT; else tap_ctrl.state <= IR_EXIT1; end if;
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when IR_EXIT1 => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= IR_PAUSE; else tap_ctrl.state <= IR_UPDATE; end if;
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when IR_PAUSE => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= IR_PAUSE; else tap_ctrl.state <= IR_EXIT2; end if;
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when IR_EXIT2 => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= IR_SHIFT; else tap_ctrl.state <= IR_UPDATE; end if;
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when IR_UPDATE => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= RUN_IDLE; else tap_ctrl.state <= DR_SCAN; end if;
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when others => tap_ctrl.state <= LOGIC_RESET;
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end case;
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end if;
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end if;
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end process tap_control;
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-- Tap Register Access --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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reg_access: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if (tap_ctrl.trst_sync(1) = '0') then -- reset
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tap_reg.ireg <= "00001"; -- IDCODE
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elsif (tap_ctrl.tck_sync(2) = '0') and (tap_ctrl.tck_sync(1) = '1') then -- clock pulse (trigger on rising edge)
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-- instruction register --
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if (tap_ctrl.state = LOGIC_RESET) then -- reset
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tap_reg.ireg <= "00001"; -- IDCODE
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elsif (tap_ctrl.state = IR_CAPTURE) then -- preload phase
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tap_reg.ireg <= "00001"; -- IDCODE
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elsif (tap_ctrl.state = IR_SHIFT) then -- access phase
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tap_reg.ireg <= tap_ctrl.tdi_sync(1) & tap_reg.ireg(tap_reg.ireg'left downto 1);
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end if;
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-- data register --
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if (tap_ctrl.state = DR_CAPTURE) then -- preload phase
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case tap_reg.ireg is
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when "00001" => tap_reg.idcode <= IDCODE_VERSION & IDCODE_PARTID & IDCODE_MANID & '1'; -- IDCODE (LBS has to be always set!)
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when "10000" => tap_reg.dtmcs <= tap_reg.dtmcs_nxt;-- dtmcs
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when "10001" => tap_reg.dmi <= tap_reg.dmi_nxt; -- dmi
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when others => tap_reg.bypass <= '0'; -- BYPASS
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end case;
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elsif (tap_ctrl.state = DR_SHIFT) then -- access phase
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case tap_reg.ireg is
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when "00001" => tap_reg.idcode <= tap_ctrl.tdi_sync(1) & tap_reg.idcode(tap_reg.idcode'left downto 1); -- IDCODE
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when "10000" => tap_reg.dtmcs <= tap_ctrl.tdi_sync(1) & tap_reg.dtmcs(tap_reg.dtmcs'left downto 1); -- dtmcs
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when "10001" => tap_reg.dmi <= tap_ctrl.tdi_sync(1) & tap_reg.dmi(tap_reg.dmi'left downto 1); -- dmi
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when others => tap_reg.bypass <= tap_ctrl.tdi_sync(1); -- BYPASS
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end case;
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end if;
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end if;
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-- serial data output --
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if (tap_ctrl.state = IR_SHIFT) then
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tap_ctrl.tdo_sync <= tap_reg.ireg(0);
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else
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case tap_reg.ireg is
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when "00001" => tap_ctrl.tdo_sync <= tap_reg.idcode(0); -- IDCODE
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when "10000" => tap_ctrl.tdo_sync <= tap_reg.dtmcs(0); -- dtmcs
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when "10001" => tap_ctrl.tdo_sync <= tap_reg.dmi(0); -- dmi
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when others => tap_ctrl.tdo_sync <= tap_reg.bypass; -- BYPASS
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end case;
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end if;
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end if;
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end process reg_access;
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221 |
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-- Debug Module Interface -----------------------------------------------------------------
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223 |
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-- -------------------------------------------------------------------------------------------
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224 |
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225 |
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-- DTM Control and Status Register (dtmcs) --
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226 |
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tap_reg.dtmcs_nxt(31 downto 18) <= (others => '0'); -- unused
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227 |
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tap_reg.dtmcs_nxt(17) <= '0'; -- dmihardreset, always reads as zero
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228 |
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tap_reg.dtmcs_nxt(16) <= '0'; -- dmireset, always reads as zero
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tap_reg.dtmcs_nxt(15) <= '0'; -- unused
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tap_reg.dtmcs_nxt(14 downto 12) <= dmi_idle_c; -- minimum number if idle cycles
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tap_reg.dtmcs_nxt(11 downto 10) <= tap_reg.dmi_nxt(1 downto 0); -- dmistat
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232 |
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tap_reg.dtmcs_nxt(09 downto 04) <= dmi_abits_c; -- number of DMI address bits
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tap_reg.dtmcs_nxt(03 downto 00) <= dmi_version_c; -- version
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234 |
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235 |
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236 |
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-- Debug Module Interface Access Register (dmi) --
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237 |
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dmi_controller: process(rstn_i, clk_i)
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238 |
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begin
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239 |
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if (rstn_i = '0') then
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240 |
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dmi_ctrl.state <= DMI_IDLE;
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dmi_ctrl.dmihardreset <= '1';
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242 |
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dmi_ctrl.dmireset <= '1';
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dmi_ctrl.err <= '0';
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dmi_ctrl.rdata <= (others => '-');
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dmi_ctrl.wdata <= (others => '-');
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dmi_ctrl.addr <= (others => '-');
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247 |
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elsif rising_edge(clk_i) then
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248 |
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249 |
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-- DMI status and control --
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250 |
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dmi_ctrl.dmihardreset <= '0'; -- default
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251 |
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dmi_ctrl.dmireset <= '0'; -- default
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if (tap_ctrl.state = DR_UPDATE) and (tap_ctrl.state_prev /= DR_UPDATE) and (tap_reg.ireg = "10000") then
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dmi_ctrl.dmireset <= tap_reg.dtmcs(16);
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dmi_ctrl.dmihardreset <= tap_reg.dtmcs(17);
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end if;
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256 |
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257 |
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-- DMI interface arbiter --
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258 |
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if (dmi_ctrl.dmihardreset = '1') then -- DMI hard reset
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259 |
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dmi_ctrl.state <= DMI_IDLE;
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260 |
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dmi_ctrl.err <= '0';
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261 |
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else
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262 |
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case dmi_ctrl.state is
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263 |
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264 |
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when DMI_IDLE => -- waiting for new request
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265 |
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if (tap_ctrl.state = DR_UPDATE) and (tap_ctrl.state_prev /= DR_UPDATE) and (tap_reg.ireg = "10001") then -- update <dmi>
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266 |
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case tap_reg.dmi(1 downto 0) is -- op field
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267 |
|
|
when "01" => dmi_ctrl.state <= DMI_READ_WAIT; -- read
|
268 |
|
|
when "10" => dmi_ctrl.state <= DMI_WRITE_WAIT; -- write
|
269 |
|
|
when others => NULL;
|
270 |
|
|
end case;
|
271 |
|
|
dmi_ctrl.addr <= tap_reg.dmi(40 downto 34);
|
272 |
|
|
dmi_ctrl.wdata <= tap_reg.dmi(33 downto 02);
|
273 |
|
|
end if;
|
274 |
|
|
|
275 |
|
|
when DMI_READ_WAIT => -- wait for DMI to become ready
|
276 |
|
|
if (dmi_req_ready_i = '1') then
|
277 |
|
|
dmi_ctrl.state <= DMI_READ;
|
278 |
|
|
end if;
|
279 |
|
|
|
280 |
|
|
when DMI_READ => -- start read access
|
281 |
|
|
dmi_ctrl.state <= DMI_READ_BUSY;
|
282 |
|
|
|
283 |
|
|
when DMI_READ_BUSY => -- pending read access
|
284 |
|
|
if (dmi_resp_valid_i = '1') then
|
285 |
|
|
dmi_ctrl.rdata <= dmi_resp_data_i;
|
286 |
|
|
dmi_ctrl.err <= dmi_ctrl.err or dmi_resp_err_i; -- sticky error
|
287 |
|
|
dmi_ctrl.state <= DMI_IDLE;
|
288 |
|
|
end if;
|
289 |
|
|
|
290 |
|
|
when DMI_WRITE_WAIT => -- wait for DMI to become ready
|
291 |
|
|
if (dmi_req_ready_i = '1') then
|
292 |
|
|
dmi_ctrl.state <= DMI_WRITE;
|
293 |
|
|
end if;
|
294 |
|
|
|
295 |
|
|
when DMI_WRITE => -- start write access
|
296 |
|
|
dmi_ctrl.state <= DMI_WRITE_BUSY;
|
297 |
|
|
|
298 |
|
|
when DMI_WRITE_BUSY => -- pending write access
|
299 |
|
|
if (dmi_resp_valid_i = '1') then
|
300 |
|
|
dmi_ctrl.err <= dmi_ctrl.err or dmi_resp_err_i; -- sticky error
|
301 |
|
|
dmi_ctrl.state <= DMI_IDLE;
|
302 |
|
|
end if;
|
303 |
|
|
|
304 |
|
|
when others => -- undefined
|
305 |
|
|
dmi_ctrl.state <= DMI_IDLE;
|
306 |
|
|
|
307 |
|
|
end case;
|
308 |
|
|
-- override sticky error flag --
|
309 |
|
|
if (dmi_ctrl.dmireset = '1') then
|
310 |
|
|
dmi_ctrl.err <= '0';
|
311 |
|
|
end if;
|
312 |
|
|
end if;
|
313 |
|
|
end if;
|
314 |
|
|
end process dmi_controller;
|
315 |
|
|
|
316 |
|
|
-- DMI register read access --
|
317 |
|
|
tap_reg.dmi_nxt(40 downto 34) <= dmi_ctrl.addr; -- address
|
318 |
|
|
tap_reg.dmi_nxt(33 downto 02) <= dmi_ctrl.rdata; -- read data
|
319 |
|
|
tap_reg.dmi_nxt(01 downto 00) <= "11" when (dmi_ctrl.state /= DMI_IDLE) else (dmi_ctrl.err & '0'); -- status
|
320 |
|
|
|
321 |
|
|
-- direct DMI output --
|
322 |
|
|
dmi_rstn_o <= '0' when (dmi_ctrl.dmihardreset = '1') else '1';
|
323 |
|
|
dmi_req_valid_o <= '1' when (dmi_ctrl.state = DMI_READ) or (dmi_ctrl.state = DMI_WRITE) else '0';
|
324 |
|
|
dmi_req_op_o <= '1' when (dmi_ctrl.state = DMI_WRITE) or (dmi_ctrl.state = DMI_WRITE_BUSY) else '0';
|
325 |
|
|
dmi_resp_ready_o <= '1' when (dmi_ctrl.state = DMI_READ_BUSY) or (dmi_ctrl.state = DMI_WRITE_BUSY) else '0';
|
326 |
|
|
dmi_req_addr_o <= dmi_ctrl.addr;
|
327 |
|
|
dmi_req_data_o <= dmi_ctrl.wdata;
|
328 |
|
|
|
329 |
|
|
|
330 |
|
|
end neorv32_debug_dtm_rtl;
|