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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_gpio.vhd] - Blame information for rev 47

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-- #################################################################################################
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-- # << NEORV32 - General Purpose Parallel Input/Output Port (GPIO) >>                             #
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-- # ********************************************************************************************* #
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-- # 32-bit parallel input & output unit. Any pin change (HI->LO or LO->HI) of an enabled input    #
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-- # pin (via irq_en register) triggers an IRQ.                                                    #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
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-- #                                                                                               #
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-- # Redistribution and use in source and binary forms, with or without modification, are          #
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-- # permitted provided that the following conditions are met:                                     #
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-- #                                                                                               #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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-- #    conditions and the following disclaimer.                                                   #
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-- #                                                                                               #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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-- #    conditions and the following disclaimer in the documentation and/or other materials        #
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-- #    provided with the distribution.                                                            #
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-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
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-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_gpio is
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  port (
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    -- host access --
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    clk_i  : in  std_ulogic; -- global clock line
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    addr_i : in  std_ulogic_vector(31 downto 0); -- address
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    rden_i : in  std_ulogic; -- read enable
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    wren_i : in  std_ulogic; -- write enable
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    data_i : in  std_ulogic_vector(31 downto 0); -- data in
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    data_o : out std_ulogic_vector(31 downto 0); -- data out
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    ack_o  : out std_ulogic; -- transfer acknowledge
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    -- parallel io --
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    gpio_o : out std_ulogic_vector(31 downto 0);
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    gpio_i : in  std_ulogic_vector(31 downto 0);
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    -- interrupt --
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    irq_o  : out std_ulogic
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  );
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end neorv32_gpio;
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architecture neorv32_gpio_rtl of neorv32_gpio is
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  -- IO space: module base address --
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  constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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  constant lo_abb_c : natural := index_size_f(gpio_size_c); -- low address boundary bit
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  -- access control --
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  signal acc_en : std_ulogic; -- module access enable
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  signal addr   : std_ulogic_vector(31 downto 0); -- access address
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  -- accessible regs --
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  signal din    : std_ulogic_vector(31 downto 0); -- r/-
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  signal dout   : std_ulogic_vector(31 downto 0); -- r/w
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  signal irq_en : std_ulogic_vector(31 downto 0); -- -/w, uses the same address as data_in
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  -- misc --
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  signal in_buf : std_ulogic_vector(31 downto 0);
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begin
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  -- Access Control -------------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = gpio_base_c(hi_abb_c downto lo_abb_c)) else '0';
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  addr   <= gpio_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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  -- Read/Write Access ----------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  rw_access: process(clk_i)
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  begin
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    if rising_edge(clk_i) then
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      ack_o <= acc_en and (rden_i or wren_i);
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      -- write access --
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      if ((acc_en and wren_i) = '1') then
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        if (addr = gpio_in_addr_c) then
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          irq_en <= data_i; -- pin change IRQ enable
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        else -- gpio_out_addr_c
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          dout <= data_i; -- data output port
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        end if;
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      end if;
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      -- read access --
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      data_o <= (others => '0');
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      if ((acc_en and rden_i) = '1') then
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        if (addr = gpio_in_addr_c) then
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          data_o <= din; -- data input port
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        else -- gpio_out_addr_c
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          data_o <= dout; -- data output port
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        end if;
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      end if;
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    end if;
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  end process rw_access;
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  -- output --
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  gpio_o <= dout;
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  -- IRQ Detector ------------------------------------------------------------
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  -- -----------------------------------------------------------------------------
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  irq_detector: process(clk_i)
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  begin
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    if rising_edge(clk_i) then
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      -- input synchronizer --
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      in_buf <= gpio_i;
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      din    <= in_buf;
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      -- IRQ --
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      irq_o <= or_all_f((in_buf xor din) and irq_en); -- any enabled pin transition triggers an interrupt
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    end if;
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  end process irq_detector;
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end neorv32_gpio_rtl;

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