Subversion Repositories neorv32

-- #################################################################################################

-- # << NEORV32 - General Purpose Parallel Input/Output Port (GPIO) >>                             #

-- # ********************************************************************************************* #

-- # 64-bit general purpose parallel input & output port unit.                                     #

-- # ********************************************************************************************* #

-- # BSD 3-Clause License                                                                          #

-- #                                                                                               #

-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #

-- #                                                                                               #

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-- # permitted provided that the following conditions are met:                                     #

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-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #

-- #    conditions and the following disclaimer.                                                   #

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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #

-- #    conditions and the following disclaimer in the documentation and/or other materials        #

-- #    provided with the distribution.                                                            #

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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #

-- #    endorse or promote products derived from this software without specific prior written      #

-- #    permission.                                                                                #

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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #

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-- # ********************************************************************************************* #

-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #

-- #################################################################################################

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

library neorv32;

use neorv32.neorv32_package.all;

entity neorv32_gpio is

  port (

    -- host access --

    clk_i  : in  std_ulogic; -- global clock line

    addr_i : in  std_ulogic_vector(31 downto 0); -- address

    rden_i : in  std_ulogic; -- read enable

    wren_i : in  std_ulogic; -- write enable

    data_i : in  std_ulogic_vector(31 downto 0); -- data in

    data_o : out std_ulogic_vector(31 downto 0); -- data out

    ack_o  : out std_ulogic; -- transfer acknowledge

    -- parallel io --

    gpio_o : out std_ulogic_vector(63 downto 0);

    gpio_i : in  std_ulogic_vector(63 downto 0)

  );

end neorv32_gpio;

architecture neorv32_gpio_rtl of neorv32_gpio is

  -- IO space: module base address --

  constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit

  constant lo_abb_c : natural := index_size_f(gpio_size_c); -- low address boundary bit

  -- access control --

  signal acc_en : std_ulogic; -- module access enable

  signal addr   : std_ulogic_vector(31 downto 0); -- access address

  -- accessible regs --

  signal din_lo,  din_hi  : std_ulogic_vector(31 downto 0); -- r/-

  signal dout_lo, dout_hi : std_ulogic_vector(31 downto 0); -- r/w

begin

  -- Access Control -------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = gpio_base_c(hi_abb_c downto lo_abb_c)) else '0';

  addr   <= gpio_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned

  -- Read/Write Access ----------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  rw_access: process(clk_i)

  begin

    if rising_edge(clk_i) then

      -- bus handshake --

      ack_o <= acc_en and (rden_i or wren_i);

      -- write access --

      if ((acc_en and wren_i) = '1') then

        if (addr = gpio_out_lo_addr_c) then

          dout_lo <= data_i;

        end if;

        if (addr = gpio_out_hi_addr_c) then

          dout_hi <= data_i;

        end if;

      end if;

      -- input buffer --

      din_lo <= gpio_i(31 downto 00);

      din_hi <= gpio_i(63 downto 32);

      -- read access --

      data_o <= (others => '0');

      if ((acc_en and rden_i) = '1') then

        case addr is

          when gpio_in_lo_addr_c  => data_o <= din_lo;

          when gpio_in_hi_addr_c  => data_o <= din_hi;

          when gpio_out_lo_addr_c => data_o <= dout_lo;

          when gpio_out_hi_addr_c => data_o <= dout_hi;

          when others             => data_o <= (others => '0');

        end case;

      end if;

    end if;

  end process rw_access;

  -- output --

  gpio_o <= dout_hi & dout_lo;

end neorv32_gpio_rtl;