OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_icache.vhd] - Blame information for rev 61

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 45 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - Processor-Internal Instruction Cache >>                                          #
3
-- # ********************************************************************************************* #
4 47 zero_gravi
-- # Direct mapped (ICACHE_NUM_SETS = 1) or 2-way set-associative (ICACHE_NUM_SETS = 2).           #
5
-- # Least recently used replacement policy (if ICACHE_NUM_SETS > 1).                              #
6 45 zero_gravi
-- # ********************************************************************************************* #
7
-- # BSD 3-Clause License                                                                          #
8
-- #                                                                                               #
9 53 zero_gravi
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
10 45 zero_gravi
-- #                                                                                               #
11
-- # Redistribution and use in source and binary forms, with or without modification, are          #
12
-- # permitted provided that the following conditions are met:                                     #
13
-- #                                                                                               #
14
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
15
-- #    conditions and the following disclaimer.                                                   #
16
-- #                                                                                               #
17
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
18
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
19
-- #    provided with the distribution.                                                            #
20
-- #                                                                                               #
21
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
22
-- #    endorse or promote products derived from this software without specific prior written      #
23
-- #    permission.                                                                                #
24
-- #                                                                                               #
25
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
26
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
27
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
28
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
29
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
30
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
31
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
32
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
33
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
34
-- # ********************************************************************************************* #
35
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
36
-- #################################################################################################
37
 
38
library ieee;
39
use ieee.std_logic_1164.all;
40
use ieee.numeric_std.all;
41
 
42
library neorv32;
43
use neorv32.neorv32_package.all;
44
 
45
entity neorv32_icache is
46
  generic (
47 47 zero_gravi
    ICACHE_NUM_BLOCKS : natural := 4;  -- number of blocks (min 1), has to be a power of 2
48
    ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2
49
    ICACHE_NUM_SETS   : natural := 1   -- associativity / number of sets (1=direct_mapped), has to be a power of 2
50 45 zero_gravi
  );
51
  port (
52
    -- global control --
53
    clk_i         : in  std_ulogic; -- global clock, rising edge
54
    rstn_i        : in  std_ulogic; -- global reset, low-active, async
55
    clear_i       : in  std_ulogic; -- cache clear
56
    -- host controller interface --
57
    host_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
58
    host_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
59
    host_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
60
    host_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
61
    host_we_i     : in  std_ulogic; -- write enable
62
    host_re_i     : in  std_ulogic; -- read enable
63
    host_ack_o    : out std_ulogic; -- bus transfer acknowledge
64
    host_err_o    : out std_ulogic; -- bus transfer error
65
    -- peripheral bus interface --
66
    bus_addr_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
67
    bus_rdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
68
    bus_wdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
69
    bus_ben_o     : out std_ulogic_vector(03 downto 0); -- byte enable
70
    bus_we_o      : out std_ulogic; -- write enable
71
    bus_re_o      : out std_ulogic; -- read enable
72
    bus_ack_i     : in  std_ulogic; -- bus transfer acknowledge
73
    bus_err_i     : in  std_ulogic  -- bus transfer error
74
  );
75
end neorv32_icache;
76
 
77
architecture neorv32_icache_rtl of neorv32_icache is
78
 
79
  -- cache layout --
80 47 zero_gravi
  constant cache_offset_size_c : natural := index_size_f(ICACHE_BLOCK_SIZE/4); -- offset addresses full 32-bit words
81
  constant cache_index_size_c  : natural := index_size_f(ICACHE_NUM_BLOCKS);
82 45 zero_gravi
  constant cache_tag_size_c    : natural := 32 - (cache_offset_size_c + cache_index_size_c + 2); -- 2 additonal bits for byte offset
83
 
84
  -- cache memory --
85
  component neorv32_icache_memory
86
  generic (
87 47 zero_gravi
    ICACHE_NUM_BLOCKS : natural := 4;  -- number of blocks (min 1), has to be a power of 2
88
    ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2
89
    ICACHE_NUM_SETS   : natural := 1   -- associativity; 0=direct-mapped, 1=2-way set-associative
90 45 zero_gravi
  );
91
  port (
92
    -- global control --
93
    clk_i          : in  std_ulogic; -- global clock, rising edge
94
    invalidate_i   : in  std_ulogic; -- invalidate whole cache
95
    -- host cache access (read-only) --
96
    host_addr_i    : in  std_ulogic_vector(31 downto 0); -- access address
97
    host_re_i      : in  std_ulogic; -- read enable
98
    host_rdata_o   : out std_ulogic_vector(31 downto 0); -- read data
99
    -- access status (1 cycle delay to access) --
100
    hit_o          : out std_ulogic; -- hit access
101
    -- ctrl cache access (write-only) --
102
    ctrl_en_i      : in  std_ulogic; -- control interface enable
103
    ctrl_addr_i    : in  std_ulogic_vector(31 downto 0); -- access address
104
    ctrl_we_i      : in  std_ulogic; -- write enable (full-word)
105
    ctrl_wdata_i   : in  std_ulogic_vector(31 downto 0); -- write data
106
    ctrl_tag_we_i  : in  std_ulogic; -- write tag to selected block
107
    ctrl_valid_i   : in  std_ulogic; -- make selected block valid
108
    ctrl_invalid_i : in  std_ulogic  -- make selected block invalid
109
  );
110
  end component;
111
 
112
  -- cache interface --
113
  type cache_if_t is record
114
    clear           : std_ulogic; -- cache clear
115
    --
116
    host_addr       : std_ulogic_vector(31 downto 0); -- cpu access address
117
    host_rdata      : std_ulogic_vector(31 downto 0); -- cpu read data
118
    --
119
    hit             : std_ulogic; -- hit access
120
    --
121
    ctrl_en         : std_ulogic; -- control access enable
122
    ctrl_addr       : std_ulogic_vector(31 downto 0); -- control access address
123
    ctrl_we         : std_ulogic; -- control write enable
124
    ctrl_wdata      : std_ulogic_vector(31 downto 0); -- control write data
125
    ctrl_tag_we     : std_ulogic; -- control tag write enabled
126
    ctrl_valid_we   : std_ulogic; -- control valid flag set
127
    ctrl_invalid_we : std_ulogic; -- control valid flag clear
128
  end record;
129
  signal cache : cache_if_t;
130
 
131
  -- control engine --
132
  type ctrl_engine_state_t is (S_IDLE, S_CACHE_CLEAR, S_CACHE_CHECK, S_CACHE_MISS, S_BUS_DOWNLOAD_REQ, S_BUS_DOWNLOAD_GET,
133 57 zero_gravi
                               S_CACHE_RESYNC_0, S_CACHE_RESYNC_1, S_BUS_ERROR);
134 45 zero_gravi
  type ctrl_t is record
135 61 zero_gravi
    state         : ctrl_engine_state_t; -- current state
136
    state_nxt     : ctrl_engine_state_t; -- next state
137
    addr_reg      : std_ulogic_vector(31 downto 0); -- address register for block download
138
    addr_reg_nxt  : std_ulogic_vector(31 downto 0);
139 45 zero_gravi
    --
140 61 zero_gravi
    re_buf        : std_ulogic; -- read request buffer
141
    re_buf_nxt    : std_ulogic;
142
    --
143
    clear_buf     : std_ulogic; -- clear request buffer
144
    clear_buf_nxt : std_ulogic;
145 45 zero_gravi
  end record;
146
  signal ctrl : ctrl_t;
147
 
148
begin
149
 
150
  -- Sanity Checks --------------------------------------------------------------------------
151
  -- -------------------------------------------------------------------------------------------
152
  -- configuration --
153 47 zero_gravi
  assert not (is_power_of_two_f(ICACHE_NUM_BLOCKS) = false) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache number of blocks <ICACHE_NUM_BLOCKS> has to be a power of 2." severity error;
154
  assert not (is_power_of_two_f(ICACHE_BLOCK_SIZE) = false) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache block size <ICACHE_BLOCK_SIZE> has to be a power of 2." severity error;
155
  assert not ((is_power_of_two_f(ICACHE_NUM_SETS) = false)) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache associativity <ICACHE_NUM_SETS> has to be a power of 2." severity error;
156
  assert not (ICACHE_NUM_BLOCKS < 1) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache number of blocks <ICACHE_NUM_BLOCKS> has to be >= 1." severity error;
157
  assert not (ICACHE_BLOCK_SIZE < 4) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache block size <ICACHE_BLOCK_SIZE> has to be >= 4." severity error;
158
  assert not ((ICACHE_NUM_SETS = 0) or (ICACHE_NUM_SETS > 2)) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache associativity <ICACHE_NUM_SETS> has to be 1 (direct-mapped) or 2 (2-way set-associative)." severity error;
159 45 zero_gravi
 
160
 
161
  -- Control Engine FSM Sync ----------------------------------------------------------------
162
  -- -------------------------------------------------------------------------------------------
163
  -- registers that REQUIRE a specific reset state --
164
  ctrl_engine_fsm_sync_rst: process(rstn_i, clk_i)
165
  begin
166
    if (rstn_i = '0') then
167 61 zero_gravi
      ctrl.state     <= S_CACHE_CLEAR;
168
      ctrl.re_buf    <= '0';
169
      ctrl.clear_buf <= '0';
170 45 zero_gravi
    elsif rising_edge(clk_i) then
171 61 zero_gravi
      ctrl.state     <= ctrl.state_nxt;
172
      ctrl.re_buf    <= ctrl.re_buf_nxt;
173
      ctrl.clear_buf <= ctrl.clear_buf_nxt;
174 45 zero_gravi
    end if;
175
  end process ctrl_engine_fsm_sync_rst;
176
 
177
  -- registers that do not require a specific reset state --
178
  ctrl_engine_fsm_sync: process(clk_i)
179
  begin
180
    if rising_edge(clk_i) then
181
      ctrl.addr_reg <= ctrl.addr_reg_nxt;
182
    end if;
183
  end process ctrl_engine_fsm_sync;
184
 
185
 
186
  -- Control Engine FSM Comb ----------------------------------------------------------------
187
  -- -------------------------------------------------------------------------------------------
188 57 zero_gravi
  ctrl_engine_fsm_comb: process(ctrl, cache, clear_i, host_addr_i, host_re_i, bus_rdata_i, bus_ack_i, bus_err_i)
189 45 zero_gravi
  begin
190
    -- control defaults --
191
    ctrl.state_nxt        <= ctrl.state;
192
    ctrl.addr_reg_nxt     <= ctrl.addr_reg;
193 57 zero_gravi
    ctrl.re_buf_nxt       <= ctrl.re_buf or host_re_i;
194 61 zero_gravi
    ctrl.clear_buf_nxt    <= ctrl.clear_buf or clear_i; -- buffer clear request from CPU
195 45 zero_gravi
 
196
    -- cache defaults --
197
    cache.clear           <= '0';
198
    cache.host_addr       <= host_addr_i;
199
    cache.ctrl_en         <= '0';
200
    cache.ctrl_addr       <= ctrl.addr_reg;
201
    cache.ctrl_we         <= '0';
202
    cache.ctrl_wdata      <= bus_rdata_i;
203
    cache.ctrl_tag_we     <= '0';
204
    cache.ctrl_valid_we   <= '0';
205
    cache.ctrl_invalid_we <= '0';
206
 
207
    -- host interface defaults --
208
    host_ack_o            <= '0';
209
    host_err_o            <= '0';
210
    host_rdata_o          <= cache.host_rdata;
211
 
212
    -- peripheral bus interface defaults --
213
    bus_addr_o            <= ctrl.addr_reg;
214
    bus_wdata_o           <= (others => '0'); -- cache is read-only
215
    bus_ben_o             <= (others => '0'); -- cache is read-only
216
    bus_we_o              <= '0'; -- cache is read-only
217
    bus_re_o              <= '0';
218
 
219
    -- fsm --
220
    case ctrl.state is
221
 
222
      when S_IDLE => -- wait for host access request or cache control operation
223
      -- ------------------------------------------------------------
224 61 zero_gravi
        if (ctrl.clear_buf = '1') then -- cache control operation?
225 45 zero_gravi
          ctrl.state_nxt <= S_CACHE_CLEAR;
226
        elsif (host_re_i = '1') or (ctrl.re_buf = '1') then -- cache access
227 57 zero_gravi
          ctrl.re_buf_nxt <= '0';
228
          ctrl.state_nxt  <= S_CACHE_CHECK;
229 45 zero_gravi
        end if;
230
 
231
      when S_CACHE_CLEAR => -- invalidate all cache entries
232
      -- ------------------------------------------------------------
233 61 zero_gravi
        ctrl.clear_buf_nxt <= '0';
234
        cache.clear        <= '1';
235
        ctrl.state_nxt     <= S_IDLE;
236 45 zero_gravi
 
237
      when S_CACHE_CHECK => -- finalize host access if cache hit
238
      -- ------------------------------------------------------------
239
        if (cache.hit = '1') then -- cache HIT
240 57 zero_gravi
          host_ack_o     <= '1';
241 45 zero_gravi
          ctrl.state_nxt <= S_IDLE;
242
        else -- cache MISS
243
          ctrl.state_nxt <= S_CACHE_MISS;
244
        end if;
245
 
246
      when S_CACHE_MISS => -- 
247
      -- ------------------------------------------------------------
248
        -- compute block base address --
249
        ctrl.addr_reg_nxt <= host_addr_i;
250
        ctrl.addr_reg_nxt((2+cache_offset_size_c)-1 downto 2) <= (others => '0'); -- block-aligned
251
        ctrl.addr_reg_nxt(1 downto 0) <= "00"; -- word-aligned
252
        --
253 57 zero_gravi
        ctrl.state_nxt <= S_BUS_DOWNLOAD_REQ;
254 45 zero_gravi
 
255
      when S_BUS_DOWNLOAD_REQ => -- download new cache block: request new word
256
      -- ------------------------------------------------------------
257 57 zero_gravi
        cache.ctrl_en  <= '1'; -- we are in cache control mode
258 45 zero_gravi
        bus_re_o       <= '1'; -- request new read transfer
259
        ctrl.state_nxt <= S_BUS_DOWNLOAD_GET;
260
 
261
      when S_BUS_DOWNLOAD_GET => -- download new cache block: wait for bus response
262
      -- ------------------------------------------------------------
263
        cache.ctrl_en <= '1'; -- we are in cache control mode
264
        --
265
        if (bus_err_i = '1') then -- bus error
266
          ctrl.state_nxt <= S_BUS_ERROR;
267
        elsif (bus_ack_i = '1') then -- ACK = write to cache and get next word
268
          cache.ctrl_we <= '1'; -- write to cache
269 60 zero_gravi
          if (and_reduce_f(ctrl.addr_reg((2+cache_offset_size_c)-1 downto 2)) = '1') then -- block complete?
270 45 zero_gravi
            cache.ctrl_tag_we   <= '1'; -- current block is valid now
271
            cache.ctrl_valid_we <= '1'; -- write tag of current address
272
            ctrl.state_nxt      <= S_CACHE_RESYNC_0;
273
          else -- get next word
274
            ctrl.addr_reg_nxt <= std_ulogic_vector(unsigned(ctrl.addr_reg) + 4);
275
            ctrl.state_nxt    <= S_BUS_DOWNLOAD_REQ;
276
          end if;
277
        end if;
278
 
279
      when S_CACHE_RESYNC_0 => -- re-sync host/cache access: cache read-latency
280
      -- ------------------------------------------------------------
281
        ctrl.state_nxt <= S_CACHE_RESYNC_1;
282
 
283
      when S_CACHE_RESYNC_1 => -- re-sync host/cache access: finalize CPU request
284
      -- ------------------------------------------------------------
285 57 zero_gravi
        host_ack_o     <= '1';
286 45 zero_gravi
        ctrl.state_nxt <= S_IDLE;
287
 
288
      when S_BUS_ERROR => -- bus error during download
289
      -- ------------------------------------------------------------
290
        host_err_o     <= '1';
291 57 zero_gravi
        ctrl.state_nxt <= S_IDLE;
292 45 zero_gravi
 
293
      when others => -- undefined
294
      -- ------------------------------------------------------------
295
        ctrl.state_nxt <= S_IDLE;
296
 
297
    end case;
298
  end process ctrl_engine_fsm_comb;
299
 
300
 
301
        -- Cache Memory ---------------------------------------------------------------------------
302
  -- -------------------------------------------------------------------------------------------
303
  neorv32_icache_memory_inst: neorv32_icache_memory
304
  generic map (
305 47 zero_gravi
    ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS,     -- number of blocks (min 1), has to be a power of 2
306
    ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE,     -- block size in bytes (min 4), has to be a power of 2
307
    ICACHE_NUM_SETS   => ICACHE_NUM_SETS        -- associativity; 0=direct-mapped, 1=2-way set-associative
308 45 zero_gravi
  )
309
  port map (
310
    -- global control --
311
    clk_i            => clk_i,                -- global clock, rising edge
312
    invalidate_i     => cache.clear,          -- invalidate whole cache
313
    -- host cache access (read-only)          --
314
    host_addr_i      => cache.host_addr,      -- access address
315
    host_re_i        => host_re_i,            -- read enable
316
    host_rdata_o     => cache.host_rdata,     -- read data
317
    -- access status (1 cycle delay to access) --
318
    hit_o            => cache.hit,            -- hit access
319
    -- ctrl cache access (write-only) --
320
    ctrl_en_i        => cache.ctrl_en,        -- control interface enable
321
    ctrl_addr_i      => cache.ctrl_addr,      -- access address
322
    ctrl_we_i        => cache.ctrl_we,        -- write enable (full-word)
323
    ctrl_wdata_i     => cache.ctrl_wdata,     -- write data
324
    ctrl_tag_we_i    => cache.ctrl_tag_we,    -- write tag to selected block
325
    ctrl_valid_i     => cache.ctrl_valid_we,  -- make selected block valid
326
    ctrl_invalid_i   => cache.ctrl_invalid_we -- make selected block invalid
327
  );
328
 
329
end neorv32_icache_rtl;
330
 
331
 
332
-- ###########################################################################################################################################
333
-- ###########################################################################################################################################
334
 
335
 
336
-- #################################################################################################
337
-- # << NEORV32 - Cache Memory >>                                                                  #
338
-- # ********************************************************************************************* #
339 47 zero_gravi
-- # Direct mapped (ICACHE_NUM_SETS = 1) or 2-way set-associative (ICACHE_NUM_SETS = 2).           #
340
-- # Least recently used replacement policy (if ICACHE_NUM_SETS > 1).                              #
341 45 zero_gravi
-- # Read-only for host, write-only for control. All output signals have one cycle latency.        #
342
-- #                                                                                               #
343
-- # Cache sets are mapped to individual memory components - no multi-dimensional memory arrays    #
344
-- # are used as some synthesis tools have problems to map these to actual BRAM primitives.        #
345
-- # ********************************************************************************************* #
346
-- # BSD 3-Clause License                                                                          #
347
-- #                                                                                               #
348
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
349
-- #                                                                                               #
350
-- # Redistribution and use in source and binary forms, with or without modification, are          #
351
-- # permitted provided that the following conditions are met:                                     #
352
-- #                                                                                               #
353
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
354
-- #    conditions and the following disclaimer.                                                   #
355
-- #                                                                                               #
356
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
357
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
358
-- #    provided with the distribution.                                                            #
359
-- #                                                                                               #
360
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
361
-- #    endorse or promote products derived from this software without specific prior written      #
362
-- #    permission.                                                                                #
363
-- #                                                                                               #
364
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
365
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
366
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
367
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
368
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
369
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
370
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
371
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
372
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
373
-- # ********************************************************************************************* #
374
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
375
-- #################################################################################################
376
 
377
library ieee;
378
use ieee.std_logic_1164.all;
379
use ieee.numeric_std.all;
380
 
381
library neorv32;
382
use neorv32.neorv32_package.all;
383
 
384
entity neorv32_icache_memory is
385
  generic (
386 47 zero_gravi
    ICACHE_NUM_BLOCKS : natural := 4;  -- number of blocks (min 1), has to be a power of 2
387
    ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2
388
    ICACHE_NUM_SETS   : natural := 1   -- associativity; 1=direct-mapped, 2=2-way set-associative
389 45 zero_gravi
  );
390
  port (
391
    -- global control --
392
    clk_i            : in  std_ulogic; -- global clock, rising edge
393
    invalidate_i     : in  std_ulogic; -- invalidate whole cache
394
    -- host cache access (read-only) --
395
    host_addr_i      : in  std_ulogic_vector(31 downto 0); -- access address
396
    host_re_i        : in  std_ulogic; -- read enable
397
    host_rdata_o     : out std_ulogic_vector(31 downto 0); -- read data
398
    -- access status (1 cycle delay to access) --
399
    hit_o            : out std_ulogic; -- hit access
400
    -- ctrl cache access (write-only) --
401
    ctrl_en_i        : in  std_ulogic; -- control interface enable
402
    ctrl_addr_i      : in  std_ulogic_vector(31 downto 0); -- access address
403
    ctrl_we_i        : in  std_ulogic; -- write enable (full-word)
404
    ctrl_wdata_i     : in  std_ulogic_vector(31 downto 0); -- write data
405
    ctrl_tag_we_i    : in  std_ulogic; -- write tag to selected block
406
    ctrl_valid_i     : in  std_ulogic; -- make selected block valid
407
    ctrl_invalid_i   : in  std_ulogic  -- make selected block invalid
408
  );
409
end neorv32_icache_memory;
410
 
411
architecture neorv32_icache_memory_rtl of neorv32_icache_memory is
412
 
413
  -- cache layout --
414 47 zero_gravi
  constant cache_offset_size_c : natural := index_size_f(ICACHE_BLOCK_SIZE/4); -- offset addresses full 32-bit words
415
  constant cache_index_size_c  : natural := index_size_f(ICACHE_NUM_BLOCKS);
416 45 zero_gravi
  constant cache_tag_size_c    : natural := 32 - (cache_offset_size_c + cache_index_size_c + 2); -- 2 additonal bits for byte offset
417 47 zero_gravi
  constant cache_entries_c     : natural := ICACHE_NUM_BLOCKS * (ICACHE_BLOCK_SIZE/4); -- number of 32-bit entries (per set)
418 45 zero_gravi
 
419
  -- status flag memory --
420 47 zero_gravi
  signal valid_flag_s0 : std_ulogic_vector(ICACHE_NUM_BLOCKS-1 downto 0);
421
  signal valid_flag_s1 : std_ulogic_vector(ICACHE_NUM_BLOCKS-1 downto 0);
422 45 zero_gravi
  signal valid         : std_ulogic_vector(1 downto 0); -- valid flag read data
423
 
424
  -- tag memory --
425 47 zero_gravi
  type tag_mem_t is array (0 to ICACHE_NUM_BLOCKS-1) of std_ulogic_vector(cache_tag_size_c-1 downto 0);
426 45 zero_gravi
  signal tag_mem_s0 : tag_mem_t;
427
  signal tag_mem_s1 : tag_mem_t;
428
  type tag_rd_t is array (0 to 1) of std_ulogic_vector(cache_tag_size_c-1 downto 0);
429
  signal tag : tag_rd_t; -- tag read data
430
 
431
  -- access status --
432
  signal hit : std_ulogic_vector(1 downto 0);
433
 
434
  -- access address decomposition --
435
  type acc_addr_t is record
436
    tag    : std_ulogic_vector(cache_tag_size_c-1 downto 0);
437
    index  : std_ulogic_vector(cache_index_size_c-1 downto 0);
438
    offset : std_ulogic_vector(cache_offset_size_c-1 downto 0);
439
  end record;
440
  signal host_acc_addr, ctrl_acc_addr : acc_addr_t;
441
 
442
  -- cache data memory --
443
  type cache_mem_t is array (0 to cache_entries_c-1) of std_ulogic_vector(31 downto 0);
444
  signal cache_data_memory_s0 : cache_mem_t; -- set 0
445
  signal cache_data_memory_s1 : cache_mem_t; -- set 1
446
 
447
  -- cache data memory access --
448
  type cache_rdata_t is array (0 to 1) of std_ulogic_vector(31 downto 0);
449
  signal cache_rdata  : cache_rdata_t;
450
  signal cache_index  : std_ulogic_vector(cache_index_size_c-1 downto 0);
451
  signal cache_offset : std_ulogic_vector(cache_offset_size_c-1 downto 0);
452
  signal cache_addr   : std_ulogic_vector((cache_index_size_c+cache_offset_size_c)-1 downto 0); -- index & offset
453
  signal cache_we     : std_ulogic; -- write enable (full-word)
454
  signal set_select   : std_ulogic;
455
 
456
  -- access history --
457
  type history_t is record
458
    re_ff          : std_ulogic;
459 47 zero_gravi
    last_used_set  : std_ulogic_vector(ICACHE_NUM_BLOCKS-1 downto 0);
460 45 zero_gravi
    to_be_replaced : std_ulogic;
461
  end record;
462
  signal history : history_t;
463
 
464
begin
465
 
466
        -- Access Address Decomposition -----------------------------------------------------------
467
  -- -------------------------------------------------------------------------------------------
468
  host_acc_addr.tag    <= host_addr_i(31 downto 31-(cache_tag_size_c-1));
469
  host_acc_addr.index  <= host_addr_i(31-cache_tag_size_c downto 2+cache_offset_size_c);
470
  host_acc_addr.offset <= host_addr_i(2+(cache_offset_size_c-1) downto 2); -- discard byte offset
471
 
472
  ctrl_acc_addr.tag    <= ctrl_addr_i(31 downto 31-(cache_tag_size_c-1));
473
  ctrl_acc_addr.index  <= ctrl_addr_i(31-cache_tag_size_c downto 2+cache_offset_size_c);
474
  ctrl_acc_addr.offset <= ctrl_addr_i(2+(cache_offset_size_c-1) downto 2); -- discard byte offset
475
 
476
 
477
        -- Cache Access History -------------------------------------------------------------------
478
  -- -------------------------------------------------------------------------------------------
479
  access_history: process(clk_i)
480
  begin
481
    if rising_edge(clk_i) then
482
      history.re_ff <= host_re_i;
483
      if (invalidate_i = '1') then -- invalidate whole cache
484
        history.last_used_set <= (others => '1');
485 60 zero_gravi
      elsif (history.re_ff = '1') and (or_reduce_f(hit) = '1') and (ctrl_en_i = '0') then -- store last accessed set that caused a hit
486 45 zero_gravi
        history.last_used_set(to_integer(unsigned(cache_index))) <= not hit(0);
487
      end if;
488
      history.to_be_replaced <= history.last_used_set(to_integer(unsigned(cache_index)));
489
    end if;
490
  end process access_history;
491
 
492
  -- which set is going to be replaced? -> opposite of last used set = least recently used set --
493 47 zero_gravi
  set_select <= '0' when (ICACHE_NUM_SETS = 1) else (not history.to_be_replaced);
494 45 zero_gravi
 
495
 
496
        -- Status flag memory ---------------------------------------------------------------------
497
  -- -------------------------------------------------------------------------------------------
498
  status_memory: process(clk_i)
499
  begin
500
    if rising_edge(clk_i) then
501
      -- write access --
502
      if (invalidate_i = '1') then -- invalidate whole cache
503
        valid_flag_s0 <= (others => '0');
504
        valid_flag_s1 <= (others => '0');
505
      elsif (ctrl_en_i = '1') then
506
        if (ctrl_invalid_i = '1') then -- make current block invalid
507
          if (set_select = '0') then
508
            valid_flag_s0(to_integer(unsigned(cache_index))) <= '0';
509
          else
510
            valid_flag_s1(to_integer(unsigned(cache_index))) <= '0';
511
          end if;
512
        elsif (ctrl_valid_i = '1') then -- make current block valid
513
          if (set_select = '0') then
514
            valid_flag_s0(to_integer(unsigned(cache_index))) <= '1';
515
          else
516
            valid_flag_s1(to_integer(unsigned(cache_index))) <= '1';
517
          end if;
518
        end if;
519
      end if;
520
      -- read access (sync) --
521
      valid(0) <= valid_flag_s0(to_integer(unsigned(cache_index)));
522
      valid(1) <= valid_flag_s1(to_integer(unsigned(cache_index)));
523
    end if;
524
  end process status_memory;
525
 
526
 
527
        -- Tag memory -----------------------------------------------------------------------------
528
  -- -------------------------------------------------------------------------------------------
529
  tag_memory: process(clk_i)
530
  begin
531
    if rising_edge(clk_i) then
532
      if (ctrl_en_i = '1') and (ctrl_tag_we_i = '1') then -- write access
533
        if (set_select = '0') then
534
          tag_mem_s0(to_integer(unsigned(cache_index))) <= ctrl_acc_addr.tag;
535
        else
536
          tag_mem_s1(to_integer(unsigned(cache_index))) <= ctrl_acc_addr.tag;
537
        end if;
538
      end if;
539 56 zero_gravi
      tag(0) <= tag_mem_s0(to_integer(unsigned(cache_index)));
540
      tag(1) <= tag_mem_s1(to_integer(unsigned(cache_index)));
541 45 zero_gravi
    end if;
542
  end process tag_memory;
543
 
544
  -- comparator --
545
  comparator: process(host_acc_addr, tag, valid)
546
  begin
547
    hit <= (others => '0');
548 47 zero_gravi
    for i in 0 to ICACHE_NUM_SETS-1 loop
549 45 zero_gravi
      if (host_acc_addr.tag = tag(i)) and (valid(i) = '1') then
550
        hit(i) <= '1';
551
      end if;
552
    end loop; -- i
553
  end process comparator;
554
 
555
  -- global hit --
556 60 zero_gravi
  hit_o <= or_reduce_f(hit);
557 45 zero_gravi
 
558
 
559
        -- Cache Data Memory ----------------------------------------------------------------------
560
  -- -------------------------------------------------------------------------------------------
561
  cache_mem_access: process(clk_i)
562
  begin
563
    if rising_edge(clk_i) then
564
      if (cache_we = '1') then -- write access from control (full-word)
565 56 zero_gravi
        if (set_select = '0') or (ICACHE_NUM_SETS = 1) then
566 45 zero_gravi
          cache_data_memory_s0(to_integer(unsigned(cache_addr))) <= ctrl_wdata_i;
567
        else
568
          cache_data_memory_s1(to_integer(unsigned(cache_addr))) <= ctrl_wdata_i;
569
        end if;
570
      end if;
571 56 zero_gravi
      -- read access from host (full-word) --
572
      cache_rdata(0) <= cache_data_memory_s0(to_integer(unsigned(cache_addr)));
573
      cache_rdata(1) <= cache_data_memory_s1(to_integer(unsigned(cache_addr)));
574 45 zero_gravi
    end if;
575
  end process cache_mem_access;
576
 
577
  -- data output --
578 47 zero_gravi
  host_rdata_o <= cache_rdata(0) when (hit(0) = '1') or (ICACHE_NUM_SETS = 1) else cache_rdata(1);
579 45 zero_gravi
 
580
  -- cache block ram access address --
581
  cache_addr <= cache_index & cache_offset;
582
 
583
  -- cache access select --
584
  cache_index  <= host_acc_addr.index  when (ctrl_en_i = '0') else ctrl_acc_addr.index;
585
  cache_offset <= host_acc_addr.offset when (ctrl_en_i = '0') else ctrl_acc_addr.offset;
586
  cache_we     <= '0'                  when (ctrl_en_i = '0') else ctrl_we_i;
587
 
588
 
589
end neorv32_icache_memory_rtl;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.