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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_icache.vhd] - Blame information for rev 73

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1 45 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - Processor-Internal Instruction Cache >>                                          #
3
-- # ********************************************************************************************* #
4 47 zero_gravi
-- # Direct mapped (ICACHE_NUM_SETS = 1) or 2-way set-associative (ICACHE_NUM_SETS = 2).           #
5
-- # Least recently used replacement policy (if ICACHE_NUM_SETS > 1).                              #
6 45 zero_gravi
-- # ********************************************************************************************* #
7
-- # BSD 3-Clause License                                                                          #
8
-- #                                                                                               #
9 70 zero_gravi
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved.                                     #
10 45 zero_gravi
-- #                                                                                               #
11
-- # Redistribution and use in source and binary forms, with or without modification, are          #
12
-- # permitted provided that the following conditions are met:                                     #
13
-- #                                                                                               #
14
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
15
-- #    conditions and the following disclaimer.                                                   #
16
-- #                                                                                               #
17
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
18
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
19
-- #    provided with the distribution.                                                            #
20
-- #                                                                                               #
21
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
22
-- #    endorse or promote products derived from this software without specific prior written      #
23
-- #    permission.                                                                                #
24
-- #                                                                                               #
25
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
26
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
27
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
28
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
29
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
30
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
31
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
32
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
33
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
34
-- # ********************************************************************************************* #
35
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
36
-- #################################################################################################
37
 
38
library ieee;
39
use ieee.std_logic_1164.all;
40
use ieee.numeric_std.all;
41
 
42
library neorv32;
43
use neorv32.neorv32_package.all;
44
 
45
entity neorv32_icache is
46
  generic (
47 62 zero_gravi
    ICACHE_NUM_BLOCKS : natural; -- number of blocks (min 1), has to be a power of 2
48
    ICACHE_BLOCK_SIZE : natural; -- block size in bytes (min 4), has to be a power of 2
49
    ICACHE_NUM_SETS   : natural  -- associativity / number of sets (1=direct_mapped), has to be a power of 2
50 45 zero_gravi
  );
51
  port (
52
    -- global control --
53 70 zero_gravi
    clk_i        : in  std_ulogic; -- global clock, rising edge
54
    rstn_i       : in  std_ulogic; -- global reset, low-active, async
55
    clear_i      : in  std_ulogic; -- cache clear
56 73 zero_gravi
    miss_o       : out std_ulogic; -- cache miss
57 45 zero_gravi
    -- host controller interface --
58 70 zero_gravi
    host_addr_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
59
    host_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
60
    host_wdata_i : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
61
    host_ben_i   : in  std_ulogic_vector(03 downto 0); -- byte enable
62
    host_we_i    : in  std_ulogic; -- write enable
63
    host_re_i    : in  std_ulogic; -- read enable
64
    host_ack_o   : out std_ulogic; -- bus transfer acknowledge
65
    host_err_o   : out std_ulogic; -- bus transfer error
66 45 zero_gravi
    -- peripheral bus interface --
67 70 zero_gravi
    bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
68
    bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
69
    bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
70
    bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
71
    bus_we_o     : out std_ulogic; -- write enable
72
    bus_re_o     : out std_ulogic; -- read enable
73
    bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
74
    bus_err_i    : in  std_ulogic  -- bus transfer error
75 45 zero_gravi
  );
76
end neorv32_icache;
77
 
78
architecture neorv32_icache_rtl of neorv32_icache is
79
 
80
  -- cache layout --
81 47 zero_gravi
  constant cache_offset_size_c : natural := index_size_f(ICACHE_BLOCK_SIZE/4); -- offset addresses full 32-bit words
82
  constant cache_index_size_c  : natural := index_size_f(ICACHE_NUM_BLOCKS);
83 45 zero_gravi
  constant cache_tag_size_c    : natural := 32 - (cache_offset_size_c + cache_index_size_c + 2); -- 2 additonal bits for byte offset
84
 
85
  -- cache memory --
86
  component neorv32_icache_memory
87
  generic (
88 47 zero_gravi
    ICACHE_NUM_BLOCKS : natural := 4;  -- number of blocks (min 1), has to be a power of 2
89
    ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2
90
    ICACHE_NUM_SETS   : natural := 1   -- associativity; 0=direct-mapped, 1=2-way set-associative
91 45 zero_gravi
  );
92
  port (
93
    -- global control --
94
    clk_i          : in  std_ulogic; -- global clock, rising edge
95
    invalidate_i   : in  std_ulogic; -- invalidate whole cache
96
    -- host cache access (read-only) --
97
    host_addr_i    : in  std_ulogic_vector(31 downto 0); -- access address
98
    host_re_i      : in  std_ulogic; -- read enable
99
    host_rdata_o   : out std_ulogic_vector(31 downto 0); -- read data
100
    -- access status (1 cycle delay to access) --
101
    hit_o          : out std_ulogic; -- hit access
102
    -- ctrl cache access (write-only) --
103
    ctrl_en_i      : in  std_ulogic; -- control interface enable
104
    ctrl_addr_i    : in  std_ulogic_vector(31 downto 0); -- access address
105
    ctrl_we_i      : in  std_ulogic; -- write enable (full-word)
106
    ctrl_wdata_i   : in  std_ulogic_vector(31 downto 0); -- write data
107
    ctrl_tag_we_i  : in  std_ulogic; -- write tag to selected block
108
    ctrl_valid_i   : in  std_ulogic; -- make selected block valid
109
    ctrl_invalid_i : in  std_ulogic  -- make selected block invalid
110
  );
111
  end component;
112
 
113
  -- cache interface --
114
  type cache_if_t is record
115
    clear           : std_ulogic; -- cache clear
116
    host_addr       : std_ulogic_vector(31 downto 0); -- cpu access address
117
    host_rdata      : std_ulogic_vector(31 downto 0); -- cpu read data
118
    hit             : std_ulogic; -- hit access
119
    ctrl_en         : std_ulogic; -- control access enable
120
    ctrl_addr       : std_ulogic_vector(31 downto 0); -- control access address
121
    ctrl_we         : std_ulogic; -- control write enable
122
    ctrl_wdata      : std_ulogic_vector(31 downto 0); -- control write data
123
    ctrl_tag_we     : std_ulogic; -- control tag write enabled
124
    ctrl_valid_we   : std_ulogic; -- control valid flag set
125
    ctrl_invalid_we : std_ulogic; -- control valid flag clear
126
  end record;
127
  signal cache : cache_if_t;
128
 
129
  -- control engine --
130
  type ctrl_engine_state_t is (S_IDLE, S_CACHE_CLEAR, S_CACHE_CHECK, S_CACHE_MISS, S_BUS_DOWNLOAD_REQ, S_BUS_DOWNLOAD_GET,
131 57 zero_gravi
                               S_CACHE_RESYNC_0, S_CACHE_RESYNC_1, S_BUS_ERROR);
132 45 zero_gravi
  type ctrl_t is record
133 61 zero_gravi
    state         : ctrl_engine_state_t; -- current state
134
    state_nxt     : ctrl_engine_state_t; -- next state
135
    addr_reg      : std_ulogic_vector(31 downto 0); -- address register for block download
136
    addr_reg_nxt  : std_ulogic_vector(31 downto 0);
137
    re_buf        : std_ulogic; -- read request buffer
138
    re_buf_nxt    : std_ulogic;
139
    clear_buf     : std_ulogic; -- clear request buffer
140
    clear_buf_nxt : std_ulogic;
141 45 zero_gravi
  end record;
142
  signal ctrl : ctrl_t;
143
 
144
begin
145
 
146
  -- Sanity Checks --------------------------------------------------------------------------
147
  -- -------------------------------------------------------------------------------------------
148
  -- configuration --
149 47 zero_gravi
  assert not (is_power_of_two_f(ICACHE_NUM_BLOCKS) = false) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache number of blocks <ICACHE_NUM_BLOCKS> has to be a power of 2." severity error;
150
  assert not (is_power_of_two_f(ICACHE_BLOCK_SIZE) = false) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache block size <ICACHE_BLOCK_SIZE> has to be a power of 2." severity error;
151
  assert not ((is_power_of_two_f(ICACHE_NUM_SETS) = false)) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache associativity <ICACHE_NUM_SETS> has to be a power of 2." severity error;
152
  assert not (ICACHE_NUM_BLOCKS < 1) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache number of blocks <ICACHE_NUM_BLOCKS> has to be >= 1." severity error;
153
  assert not (ICACHE_BLOCK_SIZE < 4) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache block size <ICACHE_BLOCK_SIZE> has to be >= 4." severity error;
154
  assert not ((ICACHE_NUM_SETS = 0) or (ICACHE_NUM_SETS > 2)) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache associativity <ICACHE_NUM_SETS> has to be 1 (direct-mapped) or 2 (2-way set-associative)." severity error;
155 45 zero_gravi
 
156
 
157
  -- Control Engine FSM Sync ----------------------------------------------------------------
158
  -- -------------------------------------------------------------------------------------------
159 70 zero_gravi
  ctrl_engine_fsm_sync: process(rstn_i, clk_i)
160 45 zero_gravi
  begin
161
    if (rstn_i = '0') then
162 61 zero_gravi
      ctrl.state     <= S_CACHE_CLEAR;
163
      ctrl.re_buf    <= '0';
164
      ctrl.clear_buf <= '0';
165 70 zero_gravi
      ctrl.addr_reg  <= (others => '-');
166 45 zero_gravi
    elsif rising_edge(clk_i) then
167 61 zero_gravi
      ctrl.state     <= ctrl.state_nxt;
168
      ctrl.re_buf    <= ctrl.re_buf_nxt;
169
      ctrl.clear_buf <= ctrl.clear_buf_nxt;
170 70 zero_gravi
      ctrl.addr_reg  <= ctrl.addr_reg_nxt;
171 45 zero_gravi
    end if;
172
  end process ctrl_engine_fsm_sync;
173
 
174
 
175
  -- Control Engine FSM Comb ----------------------------------------------------------------
176
  -- -------------------------------------------------------------------------------------------
177 57 zero_gravi
  ctrl_engine_fsm_comb: process(ctrl, cache, clear_i, host_addr_i, host_re_i, bus_rdata_i, bus_ack_i, bus_err_i)
178 45 zero_gravi
  begin
179
    -- control defaults --
180
    ctrl.state_nxt        <= ctrl.state;
181
    ctrl.addr_reg_nxt     <= ctrl.addr_reg;
182 57 zero_gravi
    ctrl.re_buf_nxt       <= ctrl.re_buf or host_re_i;
183 61 zero_gravi
    ctrl.clear_buf_nxt    <= ctrl.clear_buf or clear_i; -- buffer clear request from CPU
184 45 zero_gravi
 
185
    -- cache defaults --
186
    cache.clear           <= '0';
187
    cache.host_addr       <= host_addr_i;
188
    cache.ctrl_en         <= '0';
189
    cache.ctrl_addr       <= ctrl.addr_reg;
190
    cache.ctrl_we         <= '0';
191
    cache.ctrl_wdata      <= bus_rdata_i;
192
    cache.ctrl_tag_we     <= '0';
193
    cache.ctrl_valid_we   <= '0';
194
    cache.ctrl_invalid_we <= '0';
195
 
196
    -- host interface defaults --
197
    host_ack_o            <= '0';
198
    host_err_o            <= '0';
199
    host_rdata_o          <= cache.host_rdata;
200
 
201
    -- peripheral bus interface defaults --
202
    bus_addr_o            <= ctrl.addr_reg;
203
    bus_wdata_o           <= (others => '0'); -- cache is read-only
204
    bus_ben_o             <= (others => '0'); -- cache is read-only
205
    bus_we_o              <= '0'; -- cache is read-only
206
    bus_re_o              <= '0';
207
 
208
    -- fsm --
209
    case ctrl.state is
210
 
211
      when S_IDLE => -- wait for host access request or cache control operation
212
      -- ------------------------------------------------------------
213 61 zero_gravi
        if (ctrl.clear_buf = '1') then -- cache control operation?
214 45 zero_gravi
          ctrl.state_nxt <= S_CACHE_CLEAR;
215
        elsif (host_re_i = '1') or (ctrl.re_buf = '1') then -- cache access
216 57 zero_gravi
          ctrl.re_buf_nxt <= '0';
217
          ctrl.state_nxt  <= S_CACHE_CHECK;
218 45 zero_gravi
        end if;
219
 
220
      when S_CACHE_CLEAR => -- invalidate all cache entries
221
      -- ------------------------------------------------------------
222 61 zero_gravi
        ctrl.clear_buf_nxt <= '0';
223
        cache.clear        <= '1';
224
        ctrl.state_nxt     <= S_IDLE;
225 45 zero_gravi
 
226
      when S_CACHE_CHECK => -- finalize host access if cache hit
227
      -- ------------------------------------------------------------
228
        if (cache.hit = '1') then -- cache HIT
229 57 zero_gravi
          host_ack_o     <= '1';
230 45 zero_gravi
          ctrl.state_nxt <= S_IDLE;
231
        else -- cache MISS
232
          ctrl.state_nxt <= S_CACHE_MISS;
233
        end if;
234
 
235
      when S_CACHE_MISS => -- 
236
      -- ------------------------------------------------------------
237
        -- compute block base address --
238
        ctrl.addr_reg_nxt <= host_addr_i;
239
        ctrl.addr_reg_nxt((2+cache_offset_size_c)-1 downto 2) <= (others => '0'); -- block-aligned
240
        ctrl.addr_reg_nxt(1 downto 0) <= "00"; -- word-aligned
241
        --
242 57 zero_gravi
        ctrl.state_nxt <= S_BUS_DOWNLOAD_REQ;
243 45 zero_gravi
 
244
      when S_BUS_DOWNLOAD_REQ => -- download new cache block: request new word
245
      -- ------------------------------------------------------------
246 57 zero_gravi
        cache.ctrl_en  <= '1'; -- we are in cache control mode
247 45 zero_gravi
        bus_re_o       <= '1'; -- request new read transfer
248
        ctrl.state_nxt <= S_BUS_DOWNLOAD_GET;
249
 
250
      when S_BUS_DOWNLOAD_GET => -- download new cache block: wait for bus response
251
      -- ------------------------------------------------------------
252
        cache.ctrl_en <= '1'; -- we are in cache control mode
253
        --
254
        if (bus_err_i = '1') then -- bus error
255
          ctrl.state_nxt <= S_BUS_ERROR;
256
        elsif (bus_ack_i = '1') then -- ACK = write to cache and get next word
257
          cache.ctrl_we <= '1'; -- write to cache
258 60 zero_gravi
          if (and_reduce_f(ctrl.addr_reg((2+cache_offset_size_c)-1 downto 2)) = '1') then -- block complete?
259 45 zero_gravi
            cache.ctrl_tag_we   <= '1'; -- current block is valid now
260
            cache.ctrl_valid_we <= '1'; -- write tag of current address
261
            ctrl.state_nxt      <= S_CACHE_RESYNC_0;
262
          else -- get next word
263
            ctrl.addr_reg_nxt <= std_ulogic_vector(unsigned(ctrl.addr_reg) + 4);
264
            ctrl.state_nxt    <= S_BUS_DOWNLOAD_REQ;
265
          end if;
266
        end if;
267
 
268
      when S_CACHE_RESYNC_0 => -- re-sync host/cache access: cache read-latency
269
      -- ------------------------------------------------------------
270
        ctrl.state_nxt <= S_CACHE_RESYNC_1;
271
 
272
      when S_CACHE_RESYNC_1 => -- re-sync host/cache access: finalize CPU request
273
      -- ------------------------------------------------------------
274 57 zero_gravi
        host_ack_o     <= '1';
275 45 zero_gravi
        ctrl.state_nxt <= S_IDLE;
276
 
277
      when S_BUS_ERROR => -- bus error during download
278
      -- ------------------------------------------------------------
279
        host_err_o     <= '1';
280 57 zero_gravi
        ctrl.state_nxt <= S_IDLE;
281 45 zero_gravi
 
282
      when others => -- undefined
283
      -- ------------------------------------------------------------
284
        ctrl.state_nxt <= S_IDLE;
285
 
286
    end case;
287
  end process ctrl_engine_fsm_comb;
288
 
289 73 zero_gravi
  -- signal cache miss to CPU --
290
  miss_o <= '1' when (ctrl.state = S_CACHE_MISS) else '0';
291 45 zero_gravi
 
292 73 zero_gravi
 
293 45 zero_gravi
        -- Cache Memory ---------------------------------------------------------------------------
294
  -- -------------------------------------------------------------------------------------------
295
  neorv32_icache_memory_inst: neorv32_icache_memory
296
  generic map (
297 70 zero_gravi
    ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- number of blocks (min 1), has to be a power of 2
298
    ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- block size in bytes (min 4), has to be a power of 2
299
    ICACHE_NUM_SETS   => ICACHE_NUM_SETS    -- associativity; 0=direct-mapped, 1=2-way set-associative
300 45 zero_gravi
  )
301
  port map (
302
    -- global control --
303 70 zero_gravi
    clk_i          => clk_i,                -- global clock, rising edge
304
    invalidate_i   => cache.clear,          -- invalidate whole cache
305
    -- host cache access (read-only) --
306
    host_addr_i    => cache.host_addr,      -- access address
307
    host_re_i      => host_re_i,            -- read enable
308
    host_rdata_o   => cache.host_rdata,     -- read data
309 45 zero_gravi
    -- access status (1 cycle delay to access) --
310 70 zero_gravi
    hit_o          => cache.hit,            -- hit access
311 45 zero_gravi
    -- ctrl cache access (write-only) --
312 70 zero_gravi
    ctrl_en_i      => cache.ctrl_en,        -- control interface enable
313
    ctrl_addr_i    => cache.ctrl_addr,      -- access address
314
    ctrl_we_i      => cache.ctrl_we,        -- write enable (full-word)
315
    ctrl_wdata_i   => cache.ctrl_wdata,     -- write data
316
    ctrl_tag_we_i  => cache.ctrl_tag_we,    -- write tag to selected block
317
    ctrl_valid_i   => cache.ctrl_valid_we,  -- make selected block valid
318
    ctrl_invalid_i => cache.ctrl_invalid_we -- make selected block invalid
319 45 zero_gravi
  );
320
 
321
end neorv32_icache_rtl;
322
 
323
 
324
-- ###########################################################################################################################################
325
-- ###########################################################################################################################################
326
 
327
 
328
-- #################################################################################################
329
-- # << NEORV32 - Cache Memory >>                                                                  #
330
-- # ********************************************************************************************* #
331 47 zero_gravi
-- # Direct mapped (ICACHE_NUM_SETS = 1) or 2-way set-associative (ICACHE_NUM_SETS = 2).           #
332
-- # Least recently used replacement policy (if ICACHE_NUM_SETS > 1).                              #
333 45 zero_gravi
-- # Read-only for host, write-only for control. All output signals have one cycle latency.        #
334
-- #                                                                                               #
335
-- # Cache sets are mapped to individual memory components - no multi-dimensional memory arrays    #
336
-- # are used as some synthesis tools have problems to map these to actual BRAM primitives.        #
337
-- # ********************************************************************************************* #
338
-- # BSD 3-Clause License                                                                          #
339
-- #                                                                                               #
340 70 zero_gravi
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved.                                     #
341 45 zero_gravi
-- #                                                                                               #
342
-- # Redistribution and use in source and binary forms, with or without modification, are          #
343
-- # permitted provided that the following conditions are met:                                     #
344
-- #                                                                                               #
345
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
346
-- #    conditions and the following disclaimer.                                                   #
347
-- #                                                                                               #
348
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
349
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
350
-- #    provided with the distribution.                                                            #
351
-- #                                                                                               #
352
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
353
-- #    endorse or promote products derived from this software without specific prior written      #
354
-- #    permission.                                                                                #
355
-- #                                                                                               #
356
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
357
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
358
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
359
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
360
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
361
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
362
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
363
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
364
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
365
-- # ********************************************************************************************* #
366
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
367
-- #################################################################################################
368
 
369
library ieee;
370
use ieee.std_logic_1164.all;
371
use ieee.numeric_std.all;
372
 
373
library neorv32;
374
use neorv32.neorv32_package.all;
375
 
376
entity neorv32_icache_memory is
377
  generic (
378 47 zero_gravi
    ICACHE_NUM_BLOCKS : natural := 4;  -- number of blocks (min 1), has to be a power of 2
379
    ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2
380
    ICACHE_NUM_SETS   : natural := 1   -- associativity; 1=direct-mapped, 2=2-way set-associative
381 45 zero_gravi
  );
382
  port (
383
    -- global control --
384 70 zero_gravi
    clk_i          : in  std_ulogic; -- global clock, rising edge
385
    invalidate_i   : in  std_ulogic; -- invalidate whole cache
386 45 zero_gravi
    -- host cache access (read-only) --
387 70 zero_gravi
    host_addr_i    : in  std_ulogic_vector(31 downto 0); -- access address
388
    host_re_i      : in  std_ulogic; -- read enable
389
    host_rdata_o   : out std_ulogic_vector(31 downto 0); -- read data
390 45 zero_gravi
    -- access status (1 cycle delay to access) --
391 70 zero_gravi
    hit_o          : out std_ulogic; -- hit access
392 45 zero_gravi
    -- ctrl cache access (write-only) --
393 70 zero_gravi
    ctrl_en_i      : in  std_ulogic; -- control interface enable
394
    ctrl_addr_i    : in  std_ulogic_vector(31 downto 0); -- access address
395
    ctrl_we_i      : in  std_ulogic; -- write enable (full-word)
396
    ctrl_wdata_i   : in  std_ulogic_vector(31 downto 0); -- write data
397
    ctrl_tag_we_i  : in  std_ulogic; -- write tag to selected block
398
    ctrl_valid_i   : in  std_ulogic; -- make selected block valid
399
    ctrl_invalid_i : in  std_ulogic  -- make selected block invalid
400 45 zero_gravi
  );
401
end neorv32_icache_memory;
402
 
403
architecture neorv32_icache_memory_rtl of neorv32_icache_memory is
404
 
405
  -- cache layout --
406 47 zero_gravi
  constant cache_offset_size_c : natural := index_size_f(ICACHE_BLOCK_SIZE/4); -- offset addresses full 32-bit words
407
  constant cache_index_size_c  : natural := index_size_f(ICACHE_NUM_BLOCKS);
408 70 zero_gravi
  constant cache_tag_size_c    : natural := 32 - (cache_offset_size_c + cache_index_size_c + 2); -- 2 additional bits for byte offset
409 47 zero_gravi
  constant cache_entries_c     : natural := ICACHE_NUM_BLOCKS * (ICACHE_BLOCK_SIZE/4); -- number of 32-bit entries (per set)
410 45 zero_gravi
 
411
  -- status flag memory --
412 47 zero_gravi
  signal valid_flag_s0 : std_ulogic_vector(ICACHE_NUM_BLOCKS-1 downto 0);
413
  signal valid_flag_s1 : std_ulogic_vector(ICACHE_NUM_BLOCKS-1 downto 0);
414 45 zero_gravi
  signal valid         : std_ulogic_vector(1 downto 0); -- valid flag read data
415
 
416
  -- tag memory --
417 47 zero_gravi
  type tag_mem_t is array (0 to ICACHE_NUM_BLOCKS-1) of std_ulogic_vector(cache_tag_size_c-1 downto 0);
418 45 zero_gravi
  signal tag_mem_s0 : tag_mem_t;
419
  signal tag_mem_s1 : tag_mem_t;
420
  type tag_rd_t is array (0 to 1) of std_ulogic_vector(cache_tag_size_c-1 downto 0);
421
  signal tag : tag_rd_t; -- tag read data
422
 
423
  -- access status --
424
  signal hit : std_ulogic_vector(1 downto 0);
425
 
426
  -- access address decomposition --
427
  type acc_addr_t is record
428
    tag    : std_ulogic_vector(cache_tag_size_c-1 downto 0);
429
    index  : std_ulogic_vector(cache_index_size_c-1 downto 0);
430
    offset : std_ulogic_vector(cache_offset_size_c-1 downto 0);
431
  end record;
432
  signal host_acc_addr, ctrl_acc_addr : acc_addr_t;
433
 
434
  -- cache data memory --
435
  type cache_mem_t is array (0 to cache_entries_c-1) of std_ulogic_vector(31 downto 0);
436
  signal cache_data_memory_s0 : cache_mem_t; -- set 0
437
  signal cache_data_memory_s1 : cache_mem_t; -- set 1
438
 
439
  -- cache data memory access --
440
  type cache_rdata_t is array (0 to 1) of std_ulogic_vector(31 downto 0);
441
  signal cache_rdata  : cache_rdata_t;
442
  signal cache_index  : std_ulogic_vector(cache_index_size_c-1 downto 0);
443
  signal cache_offset : std_ulogic_vector(cache_offset_size_c-1 downto 0);
444
  signal cache_addr   : std_ulogic_vector((cache_index_size_c+cache_offset_size_c)-1 downto 0); -- index & offset
445
  signal cache_we     : std_ulogic; -- write enable (full-word)
446
  signal set_select   : std_ulogic;
447
 
448
  -- access history --
449
  type history_t is record
450
    re_ff          : std_ulogic;
451 47 zero_gravi
    last_used_set  : std_ulogic_vector(ICACHE_NUM_BLOCKS-1 downto 0);
452 45 zero_gravi
    to_be_replaced : std_ulogic;
453
  end record;
454
  signal history : history_t;
455
 
456
begin
457
 
458
        -- Access Address Decomposition -----------------------------------------------------------
459
  -- -------------------------------------------------------------------------------------------
460
  host_acc_addr.tag    <= host_addr_i(31 downto 31-(cache_tag_size_c-1));
461
  host_acc_addr.index  <= host_addr_i(31-cache_tag_size_c downto 2+cache_offset_size_c);
462
  host_acc_addr.offset <= host_addr_i(2+(cache_offset_size_c-1) downto 2); -- discard byte offset
463
 
464
  ctrl_acc_addr.tag    <= ctrl_addr_i(31 downto 31-(cache_tag_size_c-1));
465
  ctrl_acc_addr.index  <= ctrl_addr_i(31-cache_tag_size_c downto 2+cache_offset_size_c);
466
  ctrl_acc_addr.offset <= ctrl_addr_i(2+(cache_offset_size_c-1) downto 2); -- discard byte offset
467
 
468
 
469
        -- Cache Access History -------------------------------------------------------------------
470
  -- -------------------------------------------------------------------------------------------
471
  access_history: process(clk_i)
472
  begin
473
    if rising_edge(clk_i) then
474
      history.re_ff <= host_re_i;
475
      if (invalidate_i = '1') then -- invalidate whole cache
476
        history.last_used_set <= (others => '1');
477 60 zero_gravi
      elsif (history.re_ff = '1') and (or_reduce_f(hit) = '1') and (ctrl_en_i = '0') then -- store last accessed set that caused a hit
478 45 zero_gravi
        history.last_used_set(to_integer(unsigned(cache_index))) <= not hit(0);
479
      end if;
480
      history.to_be_replaced <= history.last_used_set(to_integer(unsigned(cache_index)));
481
    end if;
482
  end process access_history;
483
 
484
  -- which set is going to be replaced? -> opposite of last used set = least recently used set --
485 47 zero_gravi
  set_select <= '0' when (ICACHE_NUM_SETS = 1) else (not history.to_be_replaced);
486 45 zero_gravi
 
487
 
488
        -- Status flag memory ---------------------------------------------------------------------
489
  -- -------------------------------------------------------------------------------------------
490
  status_memory: process(clk_i)
491
  begin
492
    if rising_edge(clk_i) then
493
      -- write access --
494
      if (invalidate_i = '1') then -- invalidate whole cache
495
        valid_flag_s0 <= (others => '0');
496
        valid_flag_s1 <= (others => '0');
497
      elsif (ctrl_en_i = '1') then
498
        if (ctrl_invalid_i = '1') then -- make current block invalid
499
          if (set_select = '0') then
500
            valid_flag_s0(to_integer(unsigned(cache_index))) <= '0';
501
          else
502
            valid_flag_s1(to_integer(unsigned(cache_index))) <= '0';
503
          end if;
504
        elsif (ctrl_valid_i = '1') then -- make current block valid
505
          if (set_select = '0') then
506
            valid_flag_s0(to_integer(unsigned(cache_index))) <= '1';
507
          else
508
            valid_flag_s1(to_integer(unsigned(cache_index))) <= '1';
509
          end if;
510
        end if;
511
      end if;
512
      -- read access (sync) --
513
      valid(0) <= valid_flag_s0(to_integer(unsigned(cache_index)));
514
      valid(1) <= valid_flag_s1(to_integer(unsigned(cache_index)));
515
    end if;
516
  end process status_memory;
517
 
518
 
519
        -- Tag memory -----------------------------------------------------------------------------
520
  -- -------------------------------------------------------------------------------------------
521
  tag_memory: process(clk_i)
522
  begin
523
    if rising_edge(clk_i) then
524
      if (ctrl_en_i = '1') and (ctrl_tag_we_i = '1') then -- write access
525
        if (set_select = '0') then
526
          tag_mem_s0(to_integer(unsigned(cache_index))) <= ctrl_acc_addr.tag;
527
        else
528
          tag_mem_s1(to_integer(unsigned(cache_index))) <= ctrl_acc_addr.tag;
529
        end if;
530
      end if;
531 56 zero_gravi
      tag(0) <= tag_mem_s0(to_integer(unsigned(cache_index)));
532
      tag(1) <= tag_mem_s1(to_integer(unsigned(cache_index)));
533 45 zero_gravi
    end if;
534
  end process tag_memory;
535
 
536
  -- comparator --
537
  comparator: process(host_acc_addr, tag, valid)
538
  begin
539
    hit <= (others => '0');
540 47 zero_gravi
    for i in 0 to ICACHE_NUM_SETS-1 loop
541 45 zero_gravi
      if (host_acc_addr.tag = tag(i)) and (valid(i) = '1') then
542
        hit(i) <= '1';
543
      end if;
544
    end loop; -- i
545
  end process comparator;
546
 
547
  -- global hit --
548 60 zero_gravi
  hit_o <= or_reduce_f(hit);
549 45 zero_gravi
 
550
 
551
        -- Cache Data Memory ----------------------------------------------------------------------
552
  -- -------------------------------------------------------------------------------------------
553
  cache_mem_access: process(clk_i)
554
  begin
555
    if rising_edge(clk_i) then
556
      if (cache_we = '1') then -- write access from control (full-word)
557 56 zero_gravi
        if (set_select = '0') or (ICACHE_NUM_SETS = 1) then
558 45 zero_gravi
          cache_data_memory_s0(to_integer(unsigned(cache_addr))) <= ctrl_wdata_i;
559
        else
560
          cache_data_memory_s1(to_integer(unsigned(cache_addr))) <= ctrl_wdata_i;
561
        end if;
562
      end if;
563 56 zero_gravi
      -- read access from host (full-word) --
564
      cache_rdata(0) <= cache_data_memory_s0(to_integer(unsigned(cache_addr)));
565
      cache_rdata(1) <= cache_data_memory_s1(to_integer(unsigned(cache_addr)));
566 45 zero_gravi
    end if;
567
  end process cache_mem_access;
568
 
569
  -- data output --
570 47 zero_gravi
  host_rdata_o <= cache_rdata(0) when (hit(0) = '1') or (ICACHE_NUM_SETS = 1) else cache_rdata(1);
571 45 zero_gravi
 
572
  -- cache block ram access address --
573
  cache_addr <= cache_index & cache_offset;
574
 
575
  -- cache access select --
576
  cache_index  <= host_acc_addr.index  when (ctrl_en_i = '0') else ctrl_acc_addr.index;
577
  cache_offset <= host_acc_addr.offset when (ctrl_en_i = '0') else ctrl_acc_addr.offset;
578
  cache_we     <= '0'                  when (ctrl_en_i = '0') else ctrl_we_i;
579
 
580
 
581
end neorv32_icache_memory_rtl;

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