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zero_gravi |
-- #################################################################################################
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-- # << NEORV32 - Machine System Timer (MTIME) >> #
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-- # ********************************************************************************************* #
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zero_gravi |
-- # Compatible to RISC-V spec's 64-bit MACHINE system timer including "mtime[h]" & "mtimecmp[h]". #
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zero_gravi |
-- # Note: The 64-bit counter and compare systems are de-coupled into two 32-bit systems. #
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zero_gravi |
-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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zero_gravi |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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zero_gravi |
-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_mtime is
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port (
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-- host access --
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zero_gravi |
clk_i : in std_ulogic; -- global clock line
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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zero_gravi |
-- time output for CPU --
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zero_gravi |
time_o : out std_ulogic_vector(63 downto 0); -- current system time
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-- interrupt --
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zero_gravi |
irq_o : out std_ulogic -- interrupt request
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zero_gravi |
);
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end neorv32_mtime;
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architecture neorv32_mtime_rtl of neorv32_mtime is
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-- IO space: module base address --
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant lo_abb_c : natural := index_size_f(mtime_size_c); -- low address boundary bit
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal wren : std_ulogic; -- module access enable
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zero_gravi |
signal rden : std_ulogic; -- read enable
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zero_gravi |
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zero_gravi |
-- time write access buffer --
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signal mtime_lo_we : std_ulogic;
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signal mtime_hi_we : std_ulogic;
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zero_gravi |
-- accessible regs --
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zero_gravi |
signal mtimecmp_lo : std_ulogic_vector(31 downto 0);
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signal mtimecmp_hi : std_ulogic_vector(31 downto 0);
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signal mtime_lo : std_ulogic_vector(31 downto 0);
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signal mtime_lo_nxt : std_ulogic_vector(32 downto 0);
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signal mtime_lo_ovfl : std_ulogic_vector(00 downto 0);
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signal mtime_hi : std_ulogic_vector(31 downto 0);
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zero_gravi |
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zero_gravi |
-- comparators --
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signal cmp_lo_ge : std_ulogic;
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signal cmp_lo_ge_ff : std_ulogic;
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signal cmp_hi_eq : std_ulogic;
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signal cmp_hi_gt : std_ulogic;
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zero_gravi |
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begin
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = mtime_base_c(hi_abb_c downto lo_abb_c)) else '0';
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addr <= mtime_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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wren <= acc_en and wren_i;
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rden <= acc_en and rden_i;
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zero_gravi |
-- Write Access ---------------------------------------------------------------------------
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zero_gravi |
-- -------------------------------------------------------------------------------------------
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wr_access: process(clk_i)
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begin
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if rising_edge(clk_i) then
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-- bus handshake --
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ack_o <= rden or wren;
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zero_gravi |
-- mtimecmp --
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if (wren = '1') then
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if (addr = mtime_cmp_lo_addr_c) then
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mtimecmp_lo <= data_i;
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end if;
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if (addr = mtime_cmp_hi_addr_c) then
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mtimecmp_hi <= data_i;
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end if;
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end if;
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-- mtime write access buffer --
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if (wren = '1') and (addr = mtime_time_lo_addr_c) then
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mtime_lo_we <= '1';
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else
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mtime_lo_we <= '0';
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end if;
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--
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if (wren = '1') and (addr = mtime_time_hi_addr_c) then
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mtime_hi_we <= '1';
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else
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mtime_hi_we <= '0';
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end if;
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zero_gravi |
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zero_gravi |
-- mtime low --
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if (mtime_lo_we = '1') then -- write access
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mtime_lo <= data_i;
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else -- auto increment
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mtime_lo <= mtime_lo_nxt(31 downto 0);
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end if;
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mtime_lo_ovfl(0) <= mtime_lo_nxt(32); -- overflow (carry)
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zero_gravi |
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-- mtime high --
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if (mtime_hi_we = '1') then -- write access
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mtime_hi <= data_i;
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else -- auto increment (if mtime.low overflows)
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mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + unsigned(mtime_lo_ovfl));
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end if;
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end if;
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end process wr_access;
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-- mtime.time_LO increment --
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mtime_lo_nxt <= std_ulogic_vector(unsigned('0' & mtime_lo) + 1);
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zero_gravi |
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zero_gravi |
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zero_gravi |
-- Read Access ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rd_access: process(clk_i)
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begin
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if rising_edge(clk_i) then
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data_o <= (others => '0'); -- default
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zero_gravi |
if (rden = '1') then
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case addr(3 downto 2) is
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when "00" => data_o <= mtime_lo; -- mtime low
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when "01" => data_o <= mtime_hi; -- mtime high
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when "10" => data_o <= mtimecmp_lo; -- mtimecmp low
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when others => data_o <= mtimecmp_hi; -- mtimecmp high
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zero_gravi |
end case;
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end if;
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end if;
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end process rd_access;
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zero_gravi |
-- system time output for cpu --
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zero_gravi |
time_o <= mtime_hi & mtime_lo; -- NOTE: low and high words are not synchronized here!
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zero_gravi |
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zero_gravi |
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zero_gravi |
-- Comparator -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cmp_sync: process(clk_i)
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begin
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if rising_edge(clk_i) then
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zero_gravi |
cmp_lo_ge_ff <= cmp_lo_ge; -- there is one cycle delay between low (earlier) and high (later) word
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zero_gravi |
irq_o <= cmp_hi_gt or (cmp_hi_eq and cmp_lo_ge_ff);
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end if;
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end process cmp_sync;
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-- sub-word comparators --
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cmp_lo_ge <= '1' when (unsigned(mtime_lo) >= unsigned(mtimecmp_lo)) else '0'; -- low-word: greater than or equal
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cmp_hi_eq <= '1' when (unsigned(mtime_hi) = unsigned(mtimecmp_hi)) else '0'; -- high-word: equal
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cmp_hi_gt <= '1' when (unsigned(mtime_hi) > unsigned(mtimecmp_hi)) else '0'; -- high-word: greater than
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zero_gravi |
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end neorv32_mtime_rtl;
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