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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_neoled.vhd] - Blame information for rev 52

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1 52 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - Smart LED (WS2811/WS2812) Interface (NEOLED) >>                                  #
3
-- # ********************************************************************************************* #
4
-- # Hardware interface for direct control of "smart LEDs" using an asynchronouse serial data      #
5
-- # line. Compatible with the WS2811 and WS2812 LEDs.                                             #
6
-- #                                                                                               #
7
-- # NeoPixel-compatible, RGB (24-bit) and RGBW (32-bit)                                           #
8
-- # (c) "NeoPixel" is a trademark of Adafruit Industries.                                         #
9
-- #                                                                                               #
10
-- # The interface uses a programmable carries frequency (800 KHz for the WS2812 LEDs)             #
11
-- # configurable via the control register's clock prescaler bits (ctrl_clksel*_c) and the period  #
12
-- # length configuration bits (ctrl_t_tot_*_c). "high-times" for sending a ZERO or a ONE bit are  #
13
-- # configured using the ctrl_t_0h_*_c and ctrl_t_1h_*_c bits, respectively. 32-bit transfers     #
14
-- # (for RGBW modules) and 24-bit transfers (for RGB modules) are supported via ctrl_mode__c.     #
15
-- #                                                                                               #
16
-- # The device features a TX buffer with <tx_buffer_entries_c> entries. The devices busy flag and #
17
-- # IRQ generator can be programmed to either clear the busy flag / send an IRQ when AT LEAST ONE #
18
-- # FREE BUFFER ENTRY is available (ctrl_bscon_c = 0) or when the WHOLE BUFFER IS EMPTY           #
19
-- # (ctrl_bscon_c = 1).                                                                           #
20
-- # ********************************************************************************************* #
21
-- # BSD 3-Clause License                                                                          #
22
-- #                                                                                               #
23
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
24
-- #                                                                                               #
25
-- # Redistribution and use in source and binary forms, with or without modification, are          #
26
-- # permitted provided that the following conditions are met:                                     #
27
-- #                                                                                               #
28
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
29
-- #    conditions and the following disclaimer.                                                   #
30
-- #                                                                                               #
31
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
32
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
33
-- #    provided with the distribution.                                                            #
34
-- #                                                                                               #
35
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
36
-- #    endorse or promote products derived from this software without specific prior written      #
37
-- #    permission.                                                                                #
38
-- #                                                                                               #
39
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
40
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
41
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
42
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
43
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
44
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
45
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
46
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
47
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
48
-- # ********************************************************************************************* #
49
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
50
-- #################################################################################################
51
 
52
library ieee;
53
use ieee.std_logic_1164.all;
54
use ieee.numeric_std.all;
55
 
56
library neorv32;
57
use neorv32.neorv32_package.all;
58
 
59
entity neorv32_neoled is
60
  port (
61
    -- host access --
62
    clk_i       : in  std_ulogic; -- global clock line
63
    addr_i      : in  std_ulogic_vector(31 downto 0); -- address
64
    rden_i      : in  std_ulogic; -- read enable
65
    wren_i      : in  std_ulogic; -- write enable
66
    data_i      : in  std_ulogic_vector(31 downto 0); -- data in
67
    data_o      : out std_ulogic_vector(31 downto 0); -- data out
68
    ack_o       : out std_ulogic; -- transfer acknowledge
69
    -- clock generator --
70
    clkgen_en_o : out std_ulogic; -- enable clock generator
71
    clkgen_i    : in  std_ulogic_vector(07 downto 0);
72
    -- interrupt --
73
    irq_o       : out std_ulogic; -- interrupt request
74
    -- NEOLED output --
75
    neoled_o    : out std_ulogic -- serial async data line
76
  );
77
end neorv32_neoled;
78
 
79
architecture neorv32_neoled_rtl of neorv32_neoled is
80
 
81
  -- TX buffer size configuration --
82
  constant tx_buffer_entries_c : natural := 4; -- number of entries in TX buffer, has to be a power of two, min=0
83
 
84
  -- IO space: module base address --
85
  constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
86
  constant lo_abb_c : natural := index_size_f(neoled_size_c); -- low address boundary bit
87
 
88
  -- access control --
89
  signal acc_en : std_ulogic; -- module access enable
90
  signal addr   : std_ulogic_vector(31 downto 0); -- access address
91
  signal wren   : std_ulogic; -- word write enable
92
  signal rden   : std_ulogic; -- read enable
93
 
94
  -- Control register bits --
95
  constant ctrl_enable_c    : natural :=  0; -- r/w: module enable
96
  constant ctrl_mode_c      : natural :=  1; -- r/w: 0 = 24-bit RGB mode, 1 = 32-bit RGBW mode
97
  constant ctrl_bscon_c     : natural :=  2; -- r/w: buffer status configuration -> busy_flag/IRQ config
98
  constant ctrl_clksel0_c   : natural :=  3; -- r/w: prescaler select bit 0
99
  constant ctrl_clksel1_c   : natural :=  4; -- r/w: prescaler select bit 1
100
  constant ctrl_clksel2_c   : natural :=  5; -- r/w: prescaler select bit 2
101
  --
102
  constant ctrl_bufs_0_c    : natural :=  6; -- r/-: log2(tx_buffer_entries_c) bit 0
103
  constant ctrl_bufs_1_c    : natural :=  7; -- r/-: log2(tx_buffer_entries_c) bit 1
104
  constant ctrl_bufs_2_c    : natural :=  8; -- r/-: log2(tx_buffer_entries_c) bit 2
105
  constant ctrl_bufs_3_c    : natural :=  9; -- r/-: log2(tx_buffer_entries_c) bit 3
106
  --
107
  constant ctrl_t_tot_0_c   : natural := 10; -- r/w: pulse-clock ticks per total period bit 0
108
  constant ctrl_t_tot_1_c   : natural := 11; -- r/w: pulse-clock ticks per total period bit 1
109
  constant ctrl_t_tot_2_c   : natural := 12; -- r/w: pulse-clock ticks per total period bit 2
110
  constant ctrl_t_tot_3_c   : natural := 13; -- r/w: pulse-clock ticks per total period bit 3
111
  constant ctrl_t_tot_4_c   : natural := 14; -- r/w: pulse-clock ticks per total period bit 4
112
  --
113
  constant ctrl_t_0h_0_c    : natural := 15; -- r/w: pulse-clock ticks per ZERO high-time bit 0
114
  constant ctrl_t_0h_1_c    : natural := 16; -- r/w: pulse-clock ticks per ZERO high-time bit 1
115
  constant ctrl_t_0h_2_c    : natural := 17; -- r/w: pulse-clock ticks per ZERO high-time bit 2
116
  constant ctrl_t_0h_3_c    : natural := 18; -- r/w: pulse-clock ticks per ZERO high-time bit 3
117
  constant ctrl_t_0h_4_c    : natural := 19; -- r/w: pulse-clock ticks per ZERO high-time bit 4
118
  --
119
  constant ctrl_t_1h_0_c    : natural := 20; -- r/w: pulse-clock ticks per ONE high-time bit 0
120
  constant ctrl_t_1h_1_c    : natural := 21; -- r/w: pulse-clock ticks per ONE high-time bit 1
121
  constant ctrl_t_1h_2_c    : natural := 22; -- r/w: pulse-clock ticks per ONE high-time bit 2
122
  constant ctrl_t_1h_3_c    : natural := 23; -- r/w: pulse-clock ticks per ONE high-time bit 3
123
  constant ctrl_t_1h_4_c    : natural := 24; -- r/w: pulse-clock ticks per ONE high-time bit 4
124
  --
125
  constant ctrl_tx_status_c : natural := 30; -- r/-: serial TX engine busy when set
126
  constant ctrl_busy_c      : natural := 31; -- r/-: busy / buffer status flag (configured via ctrl_bscon_c)
127
 
128
  -- control register --
129
  type ctrl_t is record
130
    enable   : std_ulogic;
131
    bscon    : std_ulogic; -- buffer/busy status flag configuration
132
    mode     : std_ulogic;
133
    clk_prsc : std_ulogic_vector(2 downto 0);
134
    ready    : std_ulogic; -- buffer ready to accept new data
135
    -- pulse config --
136
    t_total  : std_ulogic_vector(4 downto 0);
137
    t0_high  : std_ulogic_vector(4 downto 0);
138
    t1_high  : std_ulogic_vector(4 downto 0);
139
  end record;
140
  signal ctrl : ctrl_t;
141
 
142
  -- transmission buffer --
143
  type tx_fifo_t is array (0 to tx_buffer_entries_c-1) of std_ulogic_vector(31+1 downto 0);
144
  type tx_buffer_t is record
145
    we       : std_ulogic; -- write enable
146
    re       : std_ulogic; -- read enable
147
    wdata    : std_ulogic_vector(31 downto 0); -- write data (excluding excluding)
148
    rdata    : std_ulogic_vector(31+1 downto 0); -- read data (including mode)
149
    --
150
    w_pnt    : std_ulogic_vector(index_size_f(tx_buffer_entries_c) downto 0); -- write pointer
151
    r_pnt    : std_ulogic_vector(index_size_f(tx_buffer_entries_c) downto 0); -- read pointer
152
    match    : std_ulogic;
153
    empty    : std_ulogic;
154
    empty_ff : std_ulogic;
155
    full     : std_ulogic;
156
    avail    : std_ulogic; -- data available?
157
    free     : std_ulogic; -- free entry available?
158
    free_ff  : std_ulogic;
159
    --
160
    data  : tx_fifo_t; -- fifo memory
161
  end record;
162
  signal tx_buffer : tx_buffer_t;
163
 
164
  -- serial transmission engine --
165
  type serial_state_t is (S_IDLE, S_INIT, S_GETBIT, S_PULSE);
166
  type serial_t is record
167
    -- state control --
168
    state     : serial_state_t;
169
    mode      : std_ulogic;
170
    busy      : std_ulogic;
171
    bit_cnt   : std_ulogic_vector(5 downto 0);
172
    -- shift register --
173
    sreg      : std_ulogic_vector(31 downto 0);
174
    next_bit  : std_ulogic; -- next bit to send
175
    -- pulse generator --
176
    pulse_clk : std_ulogic; -- pulse cycle "clock"
177
    pulse_cnt : std_ulogic_vector(4 downto 0);
178
    t_high    : std_ulogic_vector(4 downto 0);
179
    output    : std_ulogic;
180
  end record;
181
  signal serial : serial_t;
182
 
183
begin
184
 
185
  -- Sanity Checks --------------------------------------------------------------------------
186
  -- -------------------------------------------------------------------------------------------
187
  assert not ((is_power_of_two_f(tx_buffer_entries_c) = false) or (tx_buffer_entries_c > 32768)) report "NEORV32 PROCESSOR CONFIG ERROR! Invalid <IO.NEOPIX> buffer size configuration!" severity error;
188
 
189
 
190
  -- Access Control -------------------------------------------------------------------------
191
  -- -------------------------------------------------------------------------------------------
192
  acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = neoled_base_c(hi_abb_c downto lo_abb_c)) else '0';
193
  addr   <= neoled_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
194
  wren   <= acc_en and wren_i;
195
  rden   <= acc_en and rden_i;
196
 
197
 
198
  -- Read/Write Access ----------------------------------------------------------------------
199
  -- -------------------------------------------------------------------------------------------
200
  rw_access: process(clk_i)
201
  begin
202
    if rising_edge(clk_i) then
203
      -- access acknowledge --
204
      ack_o <= wren or rden;
205
 
206
      -- write access --
207
      tx_buffer.we <= '0';
208
      if (wren = '1') then
209
        -- control register --
210
        if (addr = neoled_ctrl_addr_c) then
211
          ctrl.enable   <= data_i(ctrl_enable_c);
212
          ctrl.mode     <= data_i(ctrl_mode_c);
213
          ctrl.bscon    <= data_i(ctrl_bscon_c);
214
          ctrl.clk_prsc <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c);
215
          ctrl.t_total  <= data_i(ctrl_t_tot_4_c downto ctrl_t_tot_0_c);
216
          ctrl.t0_high  <= data_i(ctrl_t_0h_4_c  downto ctrl_t_0h_0_c);
217
          ctrl.t1_high  <= data_i(ctrl_t_1h_4_c  downto ctrl_t_1h_0_c);
218
        end if;
219
        -- tx data register (FIFO) --
220
        if (addr = neoled_data_addr_c) then
221
          tx_buffer.wdata <= data_i;
222
          tx_buffer.we    <= tx_buffer.free; -- only write new data if there is at least one free entry left
223
        end if;
224
      end if;
225
 
226
      -- read access: control register --
227
      data_o <= (others => '0');
228
      if (rden = '1') and (addr = neoled_ctrl_addr_c) then
229
        data_o(ctrl_enable_c)                        <= ctrl.enable;
230
        data_o(ctrl_mode_c)                          <= ctrl.mode;
231
        data_o(ctrl_bscon_c)                         <= ctrl.bscon;
232
        data_o(ctrl_clksel2_c downto ctrl_clksel0_c) <= ctrl.clk_prsc;
233
        data_o(ctrl_bufs_3_c  downto ctrl_bufs_0_c)  <= std_ulogic_vector(to_unsigned(index_size_f(tx_buffer_entries_c), 4));
234
        data_o(ctrl_t_tot_4_c downto ctrl_t_tot_0_c) <= ctrl.t_total;
235
        data_o(ctrl_t_0h_4_c  downto ctrl_t_0h_0_c)  <= ctrl.t0_high;
236
        data_o(ctrl_t_1h_4_c  downto ctrl_t_1h_0_c)  <= ctrl.t1_high;
237
        data_o(ctrl_tx_status_c)                     <= serial.busy;
238
        data_o(ctrl_busy_c)                          <= not ctrl.ready;
239
      end if;
240
    end if;
241
  end process rw_access;
242
 
243
  -- enable external clock generator --
244
  clkgen_en_o <= ctrl.enable;
245
 
246
 
247
  -- TX Buffer (FIFO) -----------------------------------------------------------------------
248
  -- -------------------------------------------------------------------------------------------
249
  instr_prefetch_buffer: process(clk_i)
250
  begin
251
    if rising_edge(clk_i) then
252
      -- write port --
253
      if (ctrl.enable = '0') then
254
        tx_buffer.w_pnt <= (others => '0');
255
      elsif (tx_buffer.we = '1') then
256
        tx_buffer.w_pnt <= std_ulogic_vector(unsigned(tx_buffer.w_pnt) + 1);
257
      end if;
258
      if (tx_buffer.we = '1') then -- write data
259
        tx_buffer.data(to_integer(unsigned(tx_buffer.w_pnt(tx_buffer.w_pnt'left-1 downto 0)))) <=  ctrl.mode & tx_buffer.wdata;
260
      end if;
261
      -- read port --
262
      if (ctrl.enable = '0') then
263
        tx_buffer.r_pnt <= (others => '0');
264
      elsif (tx_buffer.re = '1') then
265
        tx_buffer.r_pnt <= std_ulogic_vector(unsigned(tx_buffer.r_pnt) + 1);
266
      end if;
267
      tx_buffer.rdata <= tx_buffer.data(to_integer(unsigned(tx_buffer.r_pnt(tx_buffer.r_pnt'left-1 downto 0)))); -- sync read
268
      -- status buffer --
269
      tx_buffer.empty_ff <= tx_buffer.empty;
270
      tx_buffer.free_ff  <= tx_buffer.free;
271
    end if;
272
  end process instr_prefetch_buffer;
273
 
274
  -- status --
275
  tx_buffer.match <= '1' when (tx_buffer.r_pnt(tx_buffer.r_pnt'left-1 downto 0) = tx_buffer.w_pnt(tx_buffer.w_pnt'left-1 downto 0)) else '0';
276
  tx_buffer.full  <= '1' when (tx_buffer.r_pnt(tx_buffer.r_pnt'left) /= tx_buffer.w_pnt(tx_buffer.w_pnt'left)) and (tx_buffer.match = '1') else '0';
277
  tx_buffer.empty <= '1' when (tx_buffer.r_pnt(tx_buffer.r_pnt'left)  = tx_buffer.w_pnt(tx_buffer.w_pnt'left)) and (tx_buffer.match = '1') else '0';
278
  tx_buffer.free  <= not tx_buffer.full;
279
  tx_buffer.avail <= not tx_buffer.empty;
280
 
281
 
282
  -- Buffer Status Flag and IRQ Generator ---------------------------------------------------
283
  -- -------------------------------------------------------------------------------------------
284
  -- ctrl.bscon = 0: clear buffer/busy status flag and send IRQ if -> there is at least one free entry in buffer
285
  -- ctrl.bscon = 1: clear buffer/busy status flag and send IRQ if -> the complete buffer is empty
286
  irq_generator: process(clk_i)
287
  begin
288
    if rising_edge(clk_i) then
289
      if (ctrl.enable = '1') then
290
        if (ctrl.bscon = '0') then -- one entry is becoming free
291
          irq_o <= (not tx_buffer.free_ff) and tx_buffer.free;
292
        else -- buffer is becoming empty
293
          irq_o <= (not tx_buffer.empty_ff) and tx_buffer.empty;
294
        end if;
295
      else
296
        irq_o <= '0';
297
      end if;
298
    end if;
299
  end process irq_generator;
300
 
301
  -- ready flag --
302
  ctrl.ready <= tx_buffer.free when (ctrl.bscon = '0') else tx_buffer.empty;
303
 
304
 
305
  -- Serial TX Engine -----------------------------------------------------------------------
306
  -- -------------------------------------------------------------------------------------------
307
  serial_engine: process(clk_i)
308
  begin
309
    if rising_edge(clk_i) then
310
      -- defaults --
311
      serial.pulse_clk <= clkgen_i(to_integer(unsigned(ctrl.clk_prsc)));
312
 
313
      -- disabled --
314
      if (ctrl.enable = '0') then -- disabled
315
        serial.output <= '0';
316
        serial.state  <= S_IDLE;
317
      else
318
        case serial.state is
319
 
320
          when S_IDLE => -- waiting for new TX data
321
          -- ------------------------------------------------------------
322
            serial.output    <= '0';
323
            serial.pulse_cnt <= (others => '0');
324
            if (tx_buffer.avail = '1') then
325
              serial.state <= S_INIT;
326
            end if;
327
 
328
          when S_INIT => -- initialize TX shift engine
329
          -- ------------------------------------------------------------
330
            if (tx_buffer.rdata(32) = '0') then -- mode = "RGB" 
331
              serial.mode    <= '0';
332
              serial.bit_cnt <= "011000"; -- total number of bits to send: 3x8=24
333
            else -- mode = "RGBW"
334
              serial.mode    <= '1';
335
              serial.bit_cnt <= "100000"; -- total number of bits to send: 4x8=32
336
            end if;
337
            serial.sreg  <= tx_buffer.rdata(31 downto 00);
338
            serial.state <= S_GETBIT;
339
 
340
          when S_GETBIT => -- get next TX bit
341
          -- ------------------------------------------------------------
342
            serial.sreg      <= serial.sreg(serial.sreg'left-1 downto 0) & '0'; -- shift left by one position (MSB-first)
343
            serial.bit_cnt   <= std_ulogic_vector(unsigned(serial.bit_cnt) - 1);
344
            serial.pulse_cnt <= (others => '0');
345
            if (serial.bit_cnt = "000000") then -- all done?
346
              serial.state <= S_IDLE;
347
            else -- check current data MSB
348
              if (serial.next_bit = '0') then -- send zero-bit
349
                serial.t_high <= ctrl.t0_high;
350
              else -- send one-bit
351
                serial.t_high <= ctrl.t1_high;
352
              end if;
353
              serial.state  <= S_PULSE; -- transmit single pulse
354
              serial.output <= '1';
355
            end if;
356
 
357
          when S_PULSE => -- send pulse with specific duty cycle
358
          -- ------------------------------------------------------------
359
            -- total pulse length = ctrl.t_total
360
            -- pulse high time    = serial.t_high
361
            if (serial.pulse_clk = '1') then
362
              serial.pulse_cnt <= std_ulogic_vector(unsigned(serial.pulse_cnt) + 1);
363
              -- T_high reached? --
364
              if (serial.pulse_cnt = serial.t_high) then
365
                serial.output <= '0';
366
              end if;
367
              -- T_total reached? --
368
              if (serial.pulse_cnt = ctrl.t_total) then
369
                serial.state <= S_GETBIT; -- get next bit to send
370
              end if;
371
            end if;
372
 
373
          when others => -- undefined
374
          -- ------------------------------------------------------------
375
            serial.state <= S_IDLE;
376
 
377
        end case;
378
      end if;
379
      -- serial data output --
380
      neoled_o <= serial.output; -- IOB.FF
381
    end if;
382
  end process serial_engine;
383
 
384
  -- SREG's TX data: bit 23 for RGB mode (24-bit), bit 31 for RGBW mode (32-bit) --
385
  serial.next_bit <= serial.sreg(23) when (serial.mode = '0') else serial.sreg(31);
386
 
387
  -- get new TX data --
388
  tx_buffer.re <= '1' when (serial.state = S_IDLE) and (tx_buffer.avail = '1') else '0';
389
 
390
  -- TX engine status --
391
  serial.busy <= '0' when (serial.state = S_IDLE) or (ctrl.enable = '0') else '1';
392
 
393
 
394
end neorv32_neoled_rtl;

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