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-- #################################################################################################
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-- # << NEORV32 - Main VHDL package file >> #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package neorv32_package is
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant data_width_c : natural := 32; -- data width - FIXED!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01030600"; -- no touchy!
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constant pmp_max_r_c : natural := 8; -- max PMP regions
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-- Helper Functions -----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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function index_size_f(input : natural) return natural;
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function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
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function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
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function bool_to_ulogic_f(cond : boolean) return std_ulogic;
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function or_all_f(a : std_ulogic_vector) return std_ulogic;
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function and_all_f(a : std_ulogic_vector) return std_ulogic;
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function xor_all_f(a : std_ulogic_vector) return std_ulogic;
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function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
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function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
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-- Internal Types -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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type pmp_ctrl_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(7 downto 0);
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type pmp_addr_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(33 downto 0);
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-- Processor-internal Address Space Layout ------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- Instruction Memory & Data Memory --
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-- => configured via top's generics
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-- Bootloader ROM --
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constant boot_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!
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constant boot_size_c : natural := 4*1024; -- bytes
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constant boot_max_size_c : natural := 32*1024; -- bytes, fixed!
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-- IO: Peripheral Devices ("IO") Area --
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-- Control register(s) (including the device-enable) should be located at the base address of each device
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constant io_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80";
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constant io_size_c : natural := 32*4; -- bytes, fixed!
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-- General Purpose Input/Output Unit (GPIO) --
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constant gpio_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address, fixed!
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constant gpio_size_c : natural := 2*4; -- bytes, fixed!
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constant gpio_in_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"00000000");
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constant gpio_out_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"00000004");
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-- Dummy Device (with SIMULATION output) (DEVNULL) --
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constant devnull_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address, fixed!
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constant devnull_size_c : natural := 1*4; -- bytes, fixed!
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constant devnull_data_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(devnull_base_c) + x"00000000");
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-- Watch Dog Timer (WDT) --
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constant wdt_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address, fixed!
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constant wdt_size_c : natural := 1*4; -- bytes, fixed!
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constant wdt_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(wdt_base_c) + x"00000000");
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-- Machine System Timer (MTIME) --
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constant mtime_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90"; -- base address, fixed!
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constant mtime_size_c : natural := 4*4; -- bytes, fixed!
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constant mtime_time_lo_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(mtime_base_c) + x"00000000");
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constant mtime_time_hi_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(mtime_base_c) + x"00000004");
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constant mtime_cmp_lo_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(mtime_base_c) + x"00000008");
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constant mtime_cmp_hi_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(mtime_base_c) + x"0000000C");
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-- Universal Asynchronous Receiver/Transmitter (UART) --
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constant uart_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address, fixed!
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constant uart_size_c : natural := 2*4; -- bytes, fixed!
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constant uart_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(uart_base_c) + x"00000000");
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constant uart_rtx_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(uart_base_c) + x"00000004");
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-- Serial Peripheral Interface (SPI) --
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constant spi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address, fixed!
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constant spi_size_c : natural := 2*4; -- bytes, fixed!
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constant spi_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(spi_base_c) + x"00000000");
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constant spi_rtx_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(spi_base_c) + x"00000004");
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-- Two Wire Interface (TWI) --
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constant twi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0"; -- base address, fixed!
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constant twi_size_c : natural := 2*4; -- bytes, fixed!
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constant twi_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(twi_base_c) + x"00000000");
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constant twi_rtx_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(twi_base_c) + x"00000004");
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-- Pulse-Width Modulation Controller (PWM) --
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constant pwm_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address, fixed!
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constant pwm_size_c : natural := 2*4; -- bytes, fixed!
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constant pwm_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(pwm_base_c) + x"00000000");
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constant pwm_duty_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(pwm_base_c) + x"00000004");
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-- True Random Number generator (TRNG) --
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constant trng_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address, fixed!
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constant trng_size_c : natural := 2*4; -- bytes, fixed!
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constant trng_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(trng_base_c) + x"00000000");
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constant trng_data_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(trng_base_c) + x"00000004");
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zero_gravi |
-- RESERVED --
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--constant ???_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8"; -- base address, fixed!
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--constant ???_size_c : natural := 6*4; -- bytes, fixed!
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-- System Information Memory (with SIMULATION output) (SYSINFO) --
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constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address, fixed!
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constant sysinfo_size_c : natural := 8*4; -- bytes, fixed!
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-- Main Control Bus -----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- register file --
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constant ctrl_rf_in_mux_lsb_c : natural := 0; -- input source select lsb (00=ALU, 01=MEM)
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constant ctrl_rf_in_mux_msb_c : natural := 1; -- input source select msb (10=PC, 11=CSR)
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constant ctrl_rf_rs1_adr0_c : natural := 2; -- source register 1 address bit 0
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constant ctrl_rf_rs1_adr1_c : natural := 3; -- source register 1 address bit 1
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constant ctrl_rf_rs1_adr2_c : natural := 4; -- source register 1 address bit 2
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constant ctrl_rf_rs1_adr3_c : natural := 5; -- source register 1 address bit 3
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constant ctrl_rf_rs1_adr4_c : natural := 6; -- source register 1 address bit 4
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constant ctrl_rf_rs2_adr0_c : natural := 7; -- source register 2 address bit 0
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constant ctrl_rf_rs2_adr1_c : natural := 8; -- source register 2 address bit 1
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constant ctrl_rf_rs2_adr2_c : natural := 9; -- source register 2 address bit 2
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constant ctrl_rf_rs2_adr3_c : natural := 10; -- source register 2 address bit 3
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constant ctrl_rf_rs2_adr4_c : natural := 11; -- source register 2 address bit 4
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constant ctrl_rf_rd_adr0_c : natural := 12; -- destiantion register address bit 0
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constant ctrl_rf_rd_adr1_c : natural := 13; -- destiantion register address bit 1
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constant ctrl_rf_rd_adr2_c : natural := 14; -- destiantion register address bit 2
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constant ctrl_rf_rd_adr3_c : natural := 15; -- destiantion register address bit 3
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constant ctrl_rf_rd_adr4_c : natural := 16; -- destiantion register address bit 4
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constant ctrl_rf_wb_en_c : natural := 17; -- write back enable
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constant ctrl_rf_clear_rs1_c : natural := 18; -- force rs1=r0
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constant ctrl_rf_clear_rs2_c : natural := 19; -- force rs2=r0
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-- alu --
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constant ctrl_alu_cmd0_c : natural := 20; -- ALU command bit 0
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constant ctrl_alu_cmd1_c : natural := 21; -- ALU command bit 1
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constant ctrl_alu_cmd2_c : natural := 22; -- ALU command bit 2
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constant ctrl_alu_opa_mux_lsb_c : natural := 23; -- operand A select lsb (00=rs1, 01=PC)
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zero_gravi |
constant ctrl_alu_opa_mux_msb_c : natural := 24; -- operand A select msb (1-=CSR)
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zero_gravi |
constant ctrl_alu_opb_mux_lsb_c : natural := 25; -- operand B select lsb (00=rs2, 01=IMM)
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zero_gravi |
constant ctrl_alu_opb_mux_msb_c : natural := 26; -- operand B select msb (1-=rs1)
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zero_gravi |
constant ctrl_alu_opc_mux_c : natural := 27; -- operand C select (0=IMM, 1=rs2)
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constant ctrl_alu_unsigned_c : natural := 28; -- is unsigned ALU operation
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constant ctrl_alu_shift_dir_c : natural := 29; -- shift direction (0=left, 1=right)
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constant ctrl_alu_shift_ar_c : natural := 30; -- is arithmetic shift
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-- bus interface --
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constant ctrl_bus_size_lsb_c : natural := 31; -- transfer size lsb (00=byte, 01=half-word)
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constant ctrl_bus_size_msb_c : natural := 32; -- transfer size msb (10=word, 11=?)
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constant ctrl_bus_rd_c : natural := 33; -- read data request
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constant ctrl_bus_wr_c : natural := 34; -- write data request
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zero_gravi |
constant ctrl_bus_if_c : natural := 35; -- instruction fetch request
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zero_gravi |
constant ctrl_bus_mar_we_c : natural := 36; -- memory address register write enable
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constant ctrl_bus_mdo_we_c : natural := 37; -- memory data out register write enable
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constant ctrl_bus_mdi_we_c : natural := 38; -- memory data in register write enable
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constant ctrl_bus_unsigned_c : natural := 39; -- is unsigned load
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zero_gravi |
constant ctrl_bus_ierr_ack_c : natural := 40; -- acknowledge instruction fetch bus exception
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constant ctrl_bus_derr_ack_c : natural := 41; -- acknowledge data access bus exception
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constant ctrl_bus_fence_c : natural := 42; -- executed fence operation
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constant ctrl_bus_fencei_c : natural := 43; -- executed fencei operation
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zero_gravi |
-- co-processor --
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zero_gravi |
constant ctrl_cp_use_c : natural := 44; -- is cp operation
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constant ctrl_cp_id_lsb_c : natural := 45; -- cp select lsb
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constant ctrl_cp_id_msb_c : natural := 46; -- cp select msb
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constant ctrl_cp_cmd0_c : natural := 47; -- cp command bit 0
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constant ctrl_cp_cmd1_c : natural := 48; -- cp command bit 1
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constant ctrl_cp_cmd2_c : natural := 49; -- cp command bit 2
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zero_gravi |
-- control bus size --
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zero_gravi |
constant ctrl_width_c : natural := 50; -- control bus size
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zero_gravi |
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-- ALU Comparator Bus ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant alu_cmp_equal_c : natural := 0;
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zero_gravi |
constant alu_cmp_less_c : natural := 1; -- for signed and unsigned comparisons
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2 |
zero_gravi |
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-- RISC-V Opcode Layout -------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant instr_opcode_lsb_c : natural := 0; -- opcode bit 0
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constant instr_opcode_msb_c : natural := 6; -- opcode bit 6
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constant instr_rd_lsb_c : natural := 7; -- destination register address bit 0
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constant instr_rd_msb_c : natural := 11; -- destination register address bit 4
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constant instr_funct3_lsb_c : natural := 12; -- funct3 bit 0
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constant instr_funct3_msb_c : natural := 14; -- funct3 bit 2
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constant instr_rs1_lsb_c : natural := 15; -- source register 1 address bit 0
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constant instr_rs1_msb_c : natural := 19; -- source register 1 address bit 4
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constant instr_rs2_lsb_c : natural := 20; -- source register 2 address bit 0
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constant instr_rs2_msb_c : natural := 24; -- source register 2 address bit 4
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constant instr_funct7_lsb_c : natural := 25; -- funct7 bit 0
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constant instr_funct7_msb_c : natural := 31; -- funct7 bit 6
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constant instr_funct12_lsb_c : natural := 20; -- funct12 bit 0
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constant instr_funct12_msb_c : natural := 31; -- funct12 bit 11
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constant instr_imm12_lsb_c : natural := 20; -- immediate12 bit 0
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constant instr_imm12_msb_c : natural := 31; -- immediate12 bit 11
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constant instr_imm20_lsb_c : natural := 12; -- immediate20 bit 0
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constant instr_imm20_msb_c : natural := 31; -- immediate20 bit 21
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constant instr_csr_id_lsb_c : natural := 20; -- csr select bit 0
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constant instr_csr_id_msb_c : natural := 31; -- csr select bit 11
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-- RISC-V Opcodes -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- alu --
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constant opcode_lui_c : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate
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constant opcode_auipc_c : std_ulogic_vector(6 downto 0) := "0010111"; -- add upper immediate to PC
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constant opcode_alui_c : std_ulogic_vector(6 downto 0) := "0010011"; -- ALU operation with immediate (operation via funct3 and funct7)
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constant opcode_alu_c : std_ulogic_vector(6 downto 0) := "0110011"; -- ALU operation (operation via funct3 and funct7)
|
235 |
|
|
-- control flow --
|
236 |
|
|
constant opcode_jal_c : std_ulogic_vector(6 downto 0) := "1101111"; -- jump and link
|
237 |
|
|
constant opcode_jalr_c : std_ulogic_vector(6 downto 0) := "1100111"; -- jump and register
|
238 |
|
|
constant opcode_branch_c : std_ulogic_vector(6 downto 0) := "1100011"; -- branch (condition set via funct3)
|
239 |
|
|
-- memory access --
|
240 |
|
|
constant opcode_load_c : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)
|
241 |
|
|
constant opcode_store_c : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)
|
242 |
|
|
-- system/csr --
|
243 |
8 |
zero_gravi |
constant opcode_fence_c : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
|
244 |
2 |
zero_gravi |
constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
|
245 |
|
|
|
246 |
|
|
-- RISC-V Funct3 --------------------------------------------------------------------------
|
247 |
|
|
-- -------------------------------------------------------------------------------------------
|
248 |
|
|
-- control flow --
|
249 |
|
|
constant funct3_beq_c : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
|
250 |
|
|
constant funct3_bne_c : std_ulogic_vector(2 downto 0) := "001"; -- branch if not equal
|
251 |
|
|
constant funct3_blt_c : std_ulogic_vector(2 downto 0) := "100"; -- branch if less than
|
252 |
|
|
constant funct3_bge_c : std_ulogic_vector(2 downto 0) := "101"; -- branch if greater than or equal
|
253 |
|
|
constant funct3_bltu_c : std_ulogic_vector(2 downto 0) := "110"; -- branch if less than (unsigned)
|
254 |
|
|
constant funct3_bgeu_c : std_ulogic_vector(2 downto 0) := "111"; -- branch if greater than or equal (unsigned)
|
255 |
|
|
-- memory access --
|
256 |
|
|
constant funct3_lb_c : std_ulogic_vector(2 downto 0) := "000"; -- load byte
|
257 |
|
|
constant funct3_lh_c : std_ulogic_vector(2 downto 0) := "001"; -- load half word
|
258 |
|
|
constant funct3_lw_c : std_ulogic_vector(2 downto 0) := "010"; -- load word
|
259 |
|
|
constant funct3_lbu_c : std_ulogic_vector(2 downto 0) := "100"; -- load byte (unsigned)
|
260 |
|
|
constant funct3_lhu_c : std_ulogic_vector(2 downto 0) := "101"; -- load half word (unsigned)
|
261 |
|
|
constant funct3_sb_c : std_ulogic_vector(2 downto 0) := "000"; -- store byte
|
262 |
|
|
constant funct3_sh_c : std_ulogic_vector(2 downto 0) := "001"; -- store half word
|
263 |
|
|
constant funct3_sw_c : std_ulogic_vector(2 downto 0) := "010"; -- store word
|
264 |
|
|
-- alu --
|
265 |
|
|
constant funct3_subadd_c : std_ulogic_vector(2 downto 0) := "000"; -- sub/add via funct7
|
266 |
|
|
constant funct3_sll_c : std_ulogic_vector(2 downto 0) := "001"; -- shift logical left
|
267 |
|
|
constant funct3_slt_c : std_ulogic_vector(2 downto 0) := "010"; -- set on less
|
268 |
|
|
constant funct3_sltu_c : std_ulogic_vector(2 downto 0) := "011"; -- set on less unsigned
|
269 |
|
|
constant funct3_xor_c : std_ulogic_vector(2 downto 0) := "100"; -- xor
|
270 |
|
|
constant funct3_sr_c : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7
|
271 |
|
|
constant funct3_or_c : std_ulogic_vector(2 downto 0) := "110"; -- or
|
272 |
|
|
constant funct3_and_c : std_ulogic_vector(2 downto 0) := "111"; -- and
|
273 |
|
|
-- system/csr --
|
274 |
|
|
constant funct3_env_c : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi
|
275 |
|
|
constant funct3_csrrw_c : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w
|
276 |
|
|
constant funct3_csrrs_c : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit
|
277 |
|
|
constant funct3_csrrc_c : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit
|
278 |
|
|
--
|
279 |
|
|
constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate
|
280 |
|
|
constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate
|
281 |
|
|
constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
|
282 |
8 |
zero_gravi |
-- fence --
|
283 |
|
|
constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
|
284 |
|
|
constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync
|
285 |
2 |
zero_gravi |
|
286 |
11 |
zero_gravi |
-- RISC-V Funct12 --------------------------------------------------------------------------
|
287 |
|
|
-- -------------------------------------------------------------------------------------------
|
288 |
|
|
-- system --
|
289 |
|
|
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
|
290 |
|
|
constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
|
291 |
|
|
constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
|
292 |
|
|
constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
|
293 |
|
|
|
294 |
2 |
zero_gravi |
-- Co-Processor Operations ----------------------------------------------------------------
|
295 |
|
|
-- -------------------------------------------------------------------------------------------
|
296 |
|
|
-- cp ids --
|
297 |
|
|
constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "00"; -- MULDIV CP
|
298 |
|
|
-- muldiv cp --
|
299 |
6 |
zero_gravi |
constant cp_op_mul_c : std_ulogic_vector(2 downto 0) := "000"; -- mul
|
300 |
|
|
constant cp_op_mulh_c : std_ulogic_vector(2 downto 0) := "001"; -- mulh
|
301 |
|
|
constant cp_op_mulhsu_c : std_ulogic_vector(2 downto 0) := "010"; -- mulhsu
|
302 |
|
|
constant cp_op_mulhu_c : std_ulogic_vector(2 downto 0) := "011"; -- mulhu
|
303 |
|
|
constant cp_op_div_c : std_ulogic_vector(2 downto 0) := "100"; -- div
|
304 |
|
|
constant cp_op_divu_c : std_ulogic_vector(2 downto 0) := "101"; -- divu
|
305 |
|
|
constant cp_op_rem_c : std_ulogic_vector(2 downto 0) := "110"; -- rem
|
306 |
|
|
constant cp_op_remu_c : std_ulogic_vector(2 downto 0) := "111"; -- remu
|
307 |
2 |
zero_gravi |
|
308 |
|
|
-- ALU Function Codes ---------------------------------------------------------------------
|
309 |
|
|
-- -------------------------------------------------------------------------------------------
|
310 |
|
|
constant alu_cmd_add_c : std_ulogic_vector(2 downto 0) := "000"; -- r <= A + B
|
311 |
|
|
constant alu_cmd_sub_c : std_ulogic_vector(2 downto 0) := "001"; -- r <= A - B
|
312 |
|
|
constant alu_cmd_slt_c : std_ulogic_vector(2 downto 0) := "010"; -- r <= A < B
|
313 |
|
|
constant alu_cmd_shift_c : std_ulogic_vector(2 downto 0) := "011"; -- r <= A <</>> B
|
314 |
|
|
constant alu_cmd_xor_c : std_ulogic_vector(2 downto 0) := "100"; -- r <= A xor B
|
315 |
|
|
constant alu_cmd_or_c : std_ulogic_vector(2 downto 0) := "101"; -- r <= A or B
|
316 |
|
|
constant alu_cmd_and_c : std_ulogic_vector(2 downto 0) := "110"; -- r <= A and B
|
317 |
|
|
constant alu_cmd_bitc_c : std_ulogic_vector(2 downto 0) := "111"; -- r <= A and (not B)
|
318 |
|
|
|
319 |
12 |
zero_gravi |
-- Trap ID Codes --------------------------------------------------------------------------
|
320 |
|
|
-- -------------------------------------------------------------------------------------------
|
321 |
14 |
zero_gravi |
-- risc-v compliant --
|
322 |
|
|
constant trap_ima_c : std_ulogic_vector(5 downto 0) := "000000"; -- 0.0: instruction misaligned
|
323 |
|
|
constant trap_iba_c : std_ulogic_vector(5 downto 0) := "000001"; -- 0.1: instruction access fault
|
324 |
|
|
constant trap_iil_c : std_ulogic_vector(5 downto 0) := "000010"; -- 0.2: illegal instruction
|
325 |
|
|
constant trap_brk_c : std_ulogic_vector(5 downto 0) := "000011"; -- 0.3: breakpoint
|
326 |
|
|
constant trap_lma_c : std_ulogic_vector(5 downto 0) := "000100"; -- 0.4: load address misaligned
|
327 |
|
|
constant trap_lbe_c : std_ulogic_vector(5 downto 0) := "000101"; -- 0.5: load access fault
|
328 |
|
|
constant trap_sma_c : std_ulogic_vector(5 downto 0) := "000110"; -- 0.6: store address misaligned
|
329 |
|
|
constant trap_sbe_c : std_ulogic_vector(5 downto 0) := "000111"; -- 0.7: store access fault
|
330 |
|
|
constant trap_menv_c : std_ulogic_vector(5 downto 0) := "001011"; -- 0.11: environment call from m-mode
|
331 |
|
|
--
|
332 |
|
|
constant trap_msi_c : std_ulogic_vector(5 downto 0) := "100011"; -- 1.3: machine software interrupt
|
333 |
|
|
constant trap_mti_c : std_ulogic_vector(5 downto 0) := "100111"; -- 1.7: machine timer interrupt
|
334 |
|
|
constant trap_mei_c : std_ulogic_vector(5 downto 0) := "101011"; -- 1.11: machine external interrupt
|
335 |
|
|
-- custom --
|
336 |
|
|
constant trap_firq0_c : std_ulogic_vector(5 downto 0) := "110000"; -- 1.16: fast interrupt 0
|
337 |
|
|
constant trap_firq1_c : std_ulogic_vector(5 downto 0) := "110001"; -- 1.17: fast interrupt 1
|
338 |
|
|
constant trap_firq2_c : std_ulogic_vector(5 downto 0) := "110010"; -- 1.18: fast interrupt 2
|
339 |
|
|
constant trap_firq3_c : std_ulogic_vector(5 downto 0) := "110011"; -- 1.19: fast interrupt 3
|
340 |
12 |
zero_gravi |
|
341 |
2 |
zero_gravi |
-- CPU Control Exception System -----------------------------------------------------------
|
342 |
|
|
-- -------------------------------------------------------------------------------------------
|
343 |
|
|
-- exception source bits --
|
344 |
|
|
constant exception_iaccess_c : natural := 0; -- instrution access fault
|
345 |
|
|
constant exception_iillegal_c : natural := 1; -- illegal instrution
|
346 |
|
|
constant exception_ialign_c : natural := 2; -- instrution address misaligned
|
347 |
|
|
constant exception_m_envcall_c : natural := 3; -- ENV call from m-mode
|
348 |
|
|
constant exception_break_c : natural := 4; -- breakpoint
|
349 |
|
|
constant exception_salign_c : natural := 5; -- store address misaligned
|
350 |
|
|
constant exception_lalign_c : natural := 6; -- load address misaligned
|
351 |
|
|
constant exception_saccess_c : natural := 7; -- store access fault
|
352 |
|
|
constant exception_laccess_c : natural := 8; -- load access fault
|
353 |
14 |
zero_gravi |
--
|
354 |
2 |
zero_gravi |
constant exception_width_c : natural := 9; -- length of this list in bits
|
355 |
|
|
-- interrupt source bits --
|
356 |
12 |
zero_gravi |
constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt
|
357 |
|
|
constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt
|
358 |
2 |
zero_gravi |
constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt
|
359 |
14 |
zero_gravi |
constant interrupt_firq_0_c : natural := 3; -- fast interrupt channel 0
|
360 |
|
|
constant interrupt_firq_1_c : natural := 4; -- fast interrupt channel 1
|
361 |
|
|
constant interrupt_firq_2_c : natural := 5; -- fast interrupt channel 2
|
362 |
|
|
constant interrupt_firq_3_c : natural := 6; -- fast interrupt channel 3
|
363 |
|
|
--
|
364 |
|
|
constant interrupt_width_c : natural := 7; -- length of this list in bits
|
365 |
2 |
zero_gravi |
|
366 |
15 |
zero_gravi |
-- CPU Privilege Modes --------------------------------------------------------------------
|
367 |
|
|
-- -------------------------------------------------------------------------------------------
|
368 |
|
|
constant m_priv_mode_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
|
369 |
|
|
constant u_priv_mode_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
|
370 |
|
|
|
371 |
2 |
zero_gravi |
-- Clock Generator -------------------------------------------------------------------------
|
372 |
|
|
-- -------------------------------------------------------------------------------------------
|
373 |
|
|
constant clk_div2_c : natural := 0;
|
374 |
|
|
constant clk_div4_c : natural := 1;
|
375 |
|
|
constant clk_div8_c : natural := 2;
|
376 |
|
|
constant clk_div64_c : natural := 3;
|
377 |
|
|
constant clk_div128_c : natural := 4;
|
378 |
|
|
constant clk_div1024_c : natural := 5;
|
379 |
|
|
constant clk_div2048_c : natural := 6;
|
380 |
|
|
constant clk_div4096_c : natural := 7;
|
381 |
|
|
|
382 |
|
|
-- Component: NEORV32 Processor Top Entity ------------------------------------------------
|
383 |
|
|
-- -------------------------------------------------------------------------------------------
|
384 |
|
|
component neorv32_top
|
385 |
|
|
generic (
|
386 |
|
|
-- General --
|
387 |
12 |
zero_gravi |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
388 |
8 |
zero_gravi |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
389 |
|
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
390 |
12 |
zero_gravi |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
391 |
2 |
zero_gravi |
-- RISC-V CPU Extensions --
|
392 |
18 |
zero_gravi |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
393 |
8 |
zero_gravi |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
394 |
18 |
zero_gravi |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
395 |
|
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
396 |
8 |
zero_gravi |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
397 |
|
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
398 |
15 |
zero_gravi |
-- Physical Memory Protection (PMP) --
|
399 |
|
|
PMP_USE : boolean := false; -- implement PMP?
|
400 |
16 |
zero_gravi |
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
|
401 |
|
|
PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
402 |
2 |
zero_gravi |
-- Memory configuration: Instruction memory --
|
403 |
8 |
zero_gravi |
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
404 |
|
|
MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
|
405 |
|
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
406 |
|
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
407 |
|
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
408 |
2 |
zero_gravi |
-- Memory configuration: Data memory --
|
409 |
8 |
zero_gravi |
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
|
410 |
|
|
MEM_DSPACE_SIZE : natural := 8*1024; -- total size of data memory space in byte
|
411 |
|
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
412 |
|
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
413 |
2 |
zero_gravi |
-- Memory configuration: External memory interface --
|
414 |
8 |
zero_gravi |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
415 |
|
|
MEM_EXT_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
416 |
|
|
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout (>=1)
|
417 |
2 |
zero_gravi |
-- Processor peripherals --
|
418 |
8 |
zero_gravi |
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
419 |
|
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
420 |
|
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
421 |
|
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
422 |
|
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
423 |
|
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
424 |
|
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
425 |
|
|
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
|
426 |
|
|
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
|
427 |
2 |
zero_gravi |
);
|
428 |
|
|
port (
|
429 |
|
|
-- Global control --
|
430 |
|
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
431 |
|
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
432 |
|
|
-- Wishbone bus interface --
|
433 |
|
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
434 |
|
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
435 |
|
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
436 |
|
|
wb_we_o : out std_ulogic; -- read/write
|
437 |
|
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
438 |
|
|
wb_stb_o : out std_ulogic; -- strobe
|
439 |
|
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
440 |
|
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
441 |
|
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
442 |
12 |
zero_gravi |
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
|
443 |
|
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
444 |
|
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
445 |
2 |
zero_gravi |
-- GPIO --
|
446 |
|
|
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output
|
447 |
|
|
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
|
448 |
|
|
-- UART --
|
449 |
|
|
uart_txd_o : out std_ulogic; -- UART send data
|
450 |
|
|
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
|
451 |
|
|
-- SPI --
|
452 |
6 |
zero_gravi |
spi_sck_o : out std_ulogic; -- SPI serial clock
|
453 |
|
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
454 |
14 |
zero_gravi |
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
|
455 |
2 |
zero_gravi |
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
456 |
|
|
-- TWI --
|
457 |
|
|
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
|
458 |
|
|
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
|
459 |
|
|
-- PWM --
|
460 |
|
|
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
|
461 |
|
|
-- Interrupts --
|
462 |
14 |
zero_gravi |
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
463 |
|
|
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
|
464 |
2 |
zero_gravi |
);
|
465 |
|
|
end component;
|
466 |
|
|
|
467 |
4 |
zero_gravi |
-- Component: CPU Top Entity --------------------------------------------------------------
|
468 |
|
|
-- -------------------------------------------------------------------------------------------
|
469 |
|
|
component neorv32_cpu
|
470 |
|
|
generic (
|
471 |
|
|
-- General --
|
472 |
12 |
zero_gravi |
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
473 |
14 |
zero_gravi |
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
|
474 |
|
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
|
475 |
4 |
zero_gravi |
-- RISC-V CPU Extensions --
|
476 |
12 |
zero_gravi |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
477 |
|
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
478 |
|
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
479 |
15 |
zero_gravi |
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
480 |
12 |
zero_gravi |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
481 |
|
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
482 |
15 |
zero_gravi |
-- Physical Memory Protection (PMP) --
|
483 |
|
|
PMP_USE : boolean := false; -- implement PMP?
|
484 |
16 |
zero_gravi |
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
|
485 |
|
|
PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
486 |
14 |
zero_gravi |
-- Bus Interface --
|
487 |
|
|
BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
|
488 |
4 |
zero_gravi |
);
|
489 |
|
|
port (
|
490 |
|
|
-- global control --
|
491 |
14 |
zero_gravi |
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
492 |
|
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
493 |
12 |
zero_gravi |
-- instruction bus interface --
|
494 |
|
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
495 |
14 |
zero_gravi |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
496 |
12 |
zero_gravi |
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
497 |
|
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
498 |
|
|
i_bus_we_o : out std_ulogic; -- write enable
|
499 |
|
|
i_bus_re_o : out std_ulogic; -- read enable
|
500 |
|
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
501 |
14 |
zero_gravi |
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
502 |
|
|
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
503 |
12 |
zero_gravi |
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
504 |
|
|
-- data bus interface --
|
505 |
|
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
506 |
14 |
zero_gravi |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
507 |
12 |
zero_gravi |
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
508 |
|
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
509 |
|
|
d_bus_we_o : out std_ulogic; -- write enable
|
510 |
|
|
d_bus_re_o : out std_ulogic; -- read enable
|
511 |
|
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
512 |
14 |
zero_gravi |
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
513 |
|
|
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
514 |
12 |
zero_gravi |
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
515 |
11 |
zero_gravi |
-- system time input from MTIME --
|
516 |
14 |
zero_gravi |
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
517 |
|
|
-- interrupts (risc-v compliant) --
|
518 |
|
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
519 |
|
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
520 |
|
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
|
521 |
|
|
-- fast interrupts (custom) --
|
522 |
|
|
firq_i : in std_ulogic_vector(3 downto 0) := (others => '0')
|
523 |
4 |
zero_gravi |
);
|
524 |
|
|
end component;
|
525 |
|
|
|
526 |
2 |
zero_gravi |
-- Component: CPU Control -----------------------------------------------------------------
|
527 |
|
|
-- -------------------------------------------------------------------------------------------
|
528 |
|
|
component neorv32_cpu_control
|
529 |
|
|
generic (
|
530 |
|
|
-- General --
|
531 |
12 |
zero_gravi |
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
532 |
|
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
|
533 |
|
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
|
534 |
2 |
zero_gravi |
-- RISC-V CPU Extensions --
|
535 |
12 |
zero_gravi |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
536 |
|
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
537 |
|
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
538 |
15 |
zero_gravi |
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
539 |
12 |
zero_gravi |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
540 |
15 |
zero_gravi |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
541 |
|
|
-- Physical memory protection (PMP) --
|
542 |
|
|
PMP_USE : boolean := false; -- implement physical memory protection?
|
543 |
|
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (1..4)
|
544 |
|
|
PMP_GRANULARITY : natural := 0 -- granularity (0=none, 1=8B, 2=16B, 3=32B, ...)
|
545 |
2 |
zero_gravi |
);
|
546 |
|
|
port (
|
547 |
|
|
-- global control --
|
548 |
|
|
clk_i : in std_ulogic; -- global clock, rising edge
|
549 |
|
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
550 |
|
|
ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
551 |
|
|
-- status input --
|
552 |
|
|
alu_wait_i : in std_ulogic; -- wait for ALU
|
553 |
12 |
zero_gravi |
bus_i_wait_i : in std_ulogic; -- wait for bus
|
554 |
|
|
bus_d_wait_i : in std_ulogic; -- wait for bus
|
555 |
2 |
zero_gravi |
-- data input --
|
556 |
|
|
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
|
557 |
|
|
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
|
558 |
|
|
alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU.add result
|
559 |
|
|
-- data output --
|
560 |
|
|
imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
561 |
6 |
zero_gravi |
fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
|
562 |
|
|
curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
|
563 |
|
|
next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)
|
564 |
2 |
zero_gravi |
-- csr interface --
|
565 |
|
|
csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
|
566 |
|
|
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
567 |
14 |
zero_gravi |
-- interrupts (risc-v compliant) --
|
568 |
|
|
msw_irq_i : in std_ulogic; -- machine software interrupt
|
569 |
|
|
mext_irq_i : in std_ulogic; -- machine external interrupt
|
570 |
2 |
zero_gravi |
mtime_irq_i : in std_ulogic; -- machine timer interrupt
|
571 |
14 |
zero_gravi |
-- fast interrupts (custom) --
|
572 |
|
|
firq_i : in std_ulogic_vector(3 downto 0);
|
573 |
11 |
zero_gravi |
-- system time input from MTIME --
|
574 |
|
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
575 |
15 |
zero_gravi |
-- physical memory protection --
|
576 |
|
|
pmp_addr_o : out pmp_addr_if_t; -- addresses
|
577 |
|
|
pmp_ctrl_o : out pmp_ctrl_if_t; -- configs
|
578 |
|
|
priv_mode_o : out std_ulogic_vector(1 downto 0); -- current CPU privilege level
|
579 |
2 |
zero_gravi |
-- bus access exceptions --
|
580 |
|
|
mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
|
581 |
|
|
ma_instr_i : in std_ulogic; -- misaligned instruction address
|
582 |
|
|
ma_load_i : in std_ulogic; -- misaligned load data address
|
583 |
|
|
ma_store_i : in std_ulogic; -- misaligned store data address
|
584 |
|
|
be_instr_i : in std_ulogic; -- bus error on instruction access
|
585 |
|
|
be_load_i : in std_ulogic; -- bus error on load data access
|
586 |
12 |
zero_gravi |
be_store_i : in std_ulogic -- bus error on store data access
|
587 |
2 |
zero_gravi |
);
|
588 |
|
|
end component;
|
589 |
|
|
|
590 |
|
|
-- Component: CPU Register File -----------------------------------------------------------
|
591 |
|
|
-- -------------------------------------------------------------------------------------------
|
592 |
|
|
component neorv32_cpu_regfile
|
593 |
|
|
generic (
|
594 |
|
|
CPU_EXTENSION_RISCV_E : boolean := false -- implement embedded RF extension?
|
595 |
|
|
);
|
596 |
|
|
port (
|
597 |
|
|
-- global control --
|
598 |
|
|
clk_i : in std_ulogic; -- global clock, rising edge
|
599 |
|
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
600 |
|
|
-- data input --
|
601 |
|
|
mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
|
602 |
|
|
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
603 |
|
|
csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
604 |
|
|
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current pc
|
605 |
|
|
-- data output --
|
606 |
|
|
rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
|
607 |
|
|
rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2
|
608 |
|
|
);
|
609 |
|
|
end component;
|
610 |
|
|
|
611 |
|
|
-- Component: CPU ALU ---------------------------------------------------------------------
|
612 |
|
|
-- -------------------------------------------------------------------------------------------
|
613 |
|
|
component neorv32_cpu_alu
|
614 |
11 |
zero_gravi |
generic (
|
615 |
|
|
CPU_EXTENSION_RISCV_M : boolean := true -- implement muld/div extension?
|
616 |
|
|
);
|
617 |
2 |
zero_gravi |
port (
|
618 |
|
|
-- global control --
|
619 |
|
|
clk_i : in std_ulogic; -- global clock, rising edge
|
620 |
|
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
621 |
|
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
622 |
|
|
-- data input --
|
623 |
|
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
624 |
|
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
625 |
|
|
pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
|
626 |
|
|
imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
627 |
|
|
csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
628 |
|
|
-- data output --
|
629 |
|
|
cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
|
630 |
|
|
add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- OPA + OPB
|
631 |
|
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
632 |
|
|
-- co-processor interface --
|
633 |
|
|
cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
|
634 |
|
|
cp0_valid_i : in std_ulogic; -- co-processor 0 result valid
|
635 |
|
|
cp1_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result
|
636 |
|
|
cp1_valid_i : in std_ulogic; -- co-processor 1 result valid
|
637 |
|
|
-- status --
|
638 |
|
|
wait_o : out std_ulogic -- busy due to iterative processing units
|
639 |
|
|
);
|
640 |
|
|
end component;
|
641 |
|
|
|
642 |
|
|
-- Component: CPU Co-Processor MULDIV -----------------------------------------------------
|
643 |
|
|
-- -------------------------------------------------------------------------------------------
|
644 |
|
|
component neorv32_cpu_cp_muldiv
|
645 |
|
|
port (
|
646 |
|
|
-- global control --
|
647 |
|
|
clk_i : in std_ulogic; -- global clock, rising edge
|
648 |
|
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
649 |
|
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
650 |
|
|
-- data input --
|
651 |
|
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
652 |
|
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
653 |
|
|
-- result and status --
|
654 |
|
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
|
655 |
|
|
valid_o : out std_ulogic -- data output valid
|
656 |
|
|
);
|
657 |
|
|
end component;
|
658 |
|
|
|
659 |
|
|
-- Component: CPU Bus Interface -----------------------------------------------------------
|
660 |
|
|
-- -------------------------------------------------------------------------------------------
|
661 |
|
|
component neorv32_cpu_bus
|
662 |
|
|
generic (
|
663 |
11 |
zero_gravi |
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
664 |
15 |
zero_gravi |
BUS_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
|
665 |
|
|
-- Physical memory protection (PMP) --
|
666 |
|
|
PMP_USE : boolean := false; -- implement physical memory protection?
|
667 |
|
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (1..4)
|
668 |
18 |
zero_gravi |
PMP_GRANULARITY : natural := 0 -- granularity (1=8B, 2=16B, 3=32B, ...)
|
669 |
2 |
zero_gravi |
);
|
670 |
|
|
port (
|
671 |
|
|
-- global control --
|
672 |
12 |
zero_gravi |
clk_i : in std_ulogic; -- global clock, rising edge
|
673 |
|
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
674 |
|
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
675 |
|
|
-- cpu instruction fetch interface --
|
676 |
|
|
fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
|
677 |
|
|
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
|
678 |
|
|
i_wait_o : out std_ulogic; -- wait for fetch to complete
|
679 |
|
|
--
|
680 |
|
|
ma_instr_o : out std_ulogic; -- misaligned instruction address
|
681 |
|
|
be_instr_o : out std_ulogic; -- bus error on instruction access
|
682 |
|
|
-- cpu data access interface --
|
683 |
|
|
addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
|
684 |
|
|
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
|
685 |
|
|
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
|
686 |
|
|
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
|
687 |
|
|
d_wait_o : out std_ulogic; -- wait for access to complete
|
688 |
|
|
--
|
689 |
|
|
ma_load_o : out std_ulogic; -- misaligned load data address
|
690 |
|
|
ma_store_o : out std_ulogic; -- misaligned store data address
|
691 |
|
|
be_load_o : out std_ulogic; -- bus error on load data access
|
692 |
|
|
be_store_o : out std_ulogic; -- bus error on store data access
|
693 |
15 |
zero_gravi |
-- physical memory protection --
|
694 |
|
|
pmp_addr_i : in pmp_addr_if_t; -- addresses
|
695 |
|
|
pmp_ctrl_i : in pmp_ctrl_if_t; -- configs
|
696 |
|
|
priv_mode_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level
|
697 |
12 |
zero_gravi |
-- instruction bus --
|
698 |
|
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
699 |
|
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
700 |
|
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
701 |
|
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
702 |
|
|
i_bus_we_o : out std_ulogic; -- write enable
|
703 |
|
|
i_bus_re_o : out std_ulogic; -- read enable
|
704 |
|
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
705 |
|
|
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
706 |
|
|
i_bus_err_i : in std_ulogic; -- bus transfer error
|
707 |
|
|
i_bus_fence_o : out std_ulogic; -- fence operation
|
708 |
|
|
-- data bus --
|
709 |
|
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
710 |
|
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
711 |
|
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
712 |
|
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
713 |
|
|
d_bus_we_o : out std_ulogic; -- write enable
|
714 |
|
|
d_bus_re_o : out std_ulogic; -- read enable
|
715 |
|
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
716 |
|
|
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
717 |
|
|
d_bus_err_i : in std_ulogic; -- bus transfer error
|
718 |
|
|
d_bus_fence_o : out std_ulogic -- fence operation
|
719 |
2 |
zero_gravi |
);
|
720 |
|
|
end component;
|
721 |
|
|
|
722 |
12 |
zero_gravi |
-- Component: CPU Bus Switch --------------------------------------------------------------
|
723 |
|
|
-- -------------------------------------------------------------------------------------------
|
724 |
|
|
component neorv32_busswitch
|
725 |
|
|
generic (
|
726 |
|
|
PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only
|
727 |
|
|
PORT_CB_READ_ONLY : boolean := false -- set if controller port B is read-only
|
728 |
|
|
);
|
729 |
|
|
port (
|
730 |
|
|
-- global control --
|
731 |
|
|
clk_i : in std_ulogic; -- global clock, rising edge
|
732 |
|
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
733 |
|
|
-- controller interface a --
|
734 |
|
|
ca_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
735 |
|
|
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
736 |
|
|
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
737 |
|
|
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
738 |
|
|
ca_bus_we_i : in std_ulogic; -- write enable
|
739 |
|
|
ca_bus_re_i : in std_ulogic; -- read enable
|
740 |
|
|
ca_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
741 |
|
|
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
742 |
|
|
ca_bus_err_o : out std_ulogic; -- bus transfer error
|
743 |
|
|
-- controller interface b --
|
744 |
|
|
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
745 |
|
|
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
746 |
|
|
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
747 |
|
|
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
748 |
|
|
cb_bus_we_i : in std_ulogic; -- write enable
|
749 |
|
|
cb_bus_re_i : in std_ulogic; -- read enable
|
750 |
|
|
cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
751 |
|
|
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
752 |
|
|
cb_bus_err_o : out std_ulogic; -- bus transfer error
|
753 |
|
|
-- peripheral bus --
|
754 |
|
|
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
755 |
|
|
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
756 |
|
|
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
757 |
|
|
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
758 |
|
|
p_bus_we_o : out std_ulogic; -- write enable
|
759 |
|
|
p_bus_re_o : out std_ulogic; -- read enable
|
760 |
|
|
p_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
761 |
|
|
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
762 |
|
|
p_bus_err_i : in std_ulogic -- bus transfer error
|
763 |
|
|
);
|
764 |
|
|
end component;
|
765 |
|
|
|
766 |
2 |
zero_gravi |
-- Component: CPU Compressed Instructions Decompressor ------------------------------------
|
767 |
|
|
-- -------------------------------------------------------------------------------------------
|
768 |
|
|
component neorv32_cpu_decompressor
|
769 |
|
|
port (
|
770 |
|
|
-- instruction input --
|
771 |
|
|
ci_instr16_i : in std_ulogic_vector(15 downto 0); -- compressed instruction input
|
772 |
|
|
-- instruction output --
|
773 |
|
|
ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
|
774 |
|
|
ci_instr32_o : out std_ulogic_vector(31 downto 0) -- 32-bit decompressed instruction
|
775 |
|
|
);
|
776 |
|
|
end component;
|
777 |
|
|
|
778 |
|
|
-- Component: Processor-internal instruction memory (IMEM) --------------------------------
|
779 |
|
|
-- -------------------------------------------------------------------------------------------
|
780 |
|
|
component neorv32_imem
|
781 |
|
|
generic (
|
782 |
|
|
IMEM_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
|
783 |
|
|
IMEM_SIZE : natural := 4*1024; -- processor-internal instruction memory size in bytes
|
784 |
|
|
IMEM_AS_ROM : boolean := false; -- implement IMEM as read-only memory?
|
785 |
|
|
BOOTLOADER_USE : boolean := true -- implement and use bootloader?
|
786 |
|
|
);
|
787 |
|
|
port (
|
788 |
|
|
clk_i : in std_ulogic; -- global clock line
|
789 |
|
|
rden_i : in std_ulogic; -- read enable
|
790 |
|
|
wren_i : in std_ulogic; -- write enable
|
791 |
|
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
792 |
|
|
upen_i : in std_ulogic; -- update enable
|
793 |
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
794 |
|
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
795 |
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
796 |
|
|
ack_o : out std_ulogic -- transfer acknowledge
|
797 |
|
|
);
|
798 |
|
|
end component;
|
799 |
|
|
|
800 |
|
|
-- Component: Processor-internal data memory (DMEM) ---------------------------------------
|
801 |
|
|
-- -------------------------------------------------------------------------------------------
|
802 |
|
|
component neorv32_dmem
|
803 |
|
|
generic (
|
804 |
|
|
DMEM_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- memory base address
|
805 |
|
|
DMEM_SIZE : natural := 4*1024 -- processor-internal instruction memory size in bytes
|
806 |
|
|
);
|
807 |
|
|
port (
|
808 |
|
|
clk_i : in std_ulogic; -- global clock line
|
809 |
|
|
rden_i : in std_ulogic; -- read enable
|
810 |
|
|
wren_i : in std_ulogic; -- write enable
|
811 |
|
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
812 |
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
813 |
|
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
814 |
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
815 |
|
|
ack_o : out std_ulogic -- transfer acknowledge
|
816 |
|
|
);
|
817 |
|
|
end component;
|
818 |
|
|
|
819 |
|
|
-- Component: Processor-internal bootloader ROM (BOOTROM) ---------------------------------
|
820 |
|
|
-- -------------------------------------------------------------------------------------------
|
821 |
|
|
component neorv32_boot_rom
|
822 |
|
|
port (
|
823 |
|
|
clk_i : in std_ulogic; -- global clock line
|
824 |
|
|
rden_i : in std_ulogic; -- read enable
|
825 |
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
826 |
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
827 |
|
|
ack_o : out std_ulogic -- transfer acknowledge
|
828 |
|
|
);
|
829 |
|
|
end component;
|
830 |
|
|
|
831 |
|
|
-- Component: Machine System Timer (mtime) ------------------------------------------------
|
832 |
|
|
-- -------------------------------------------------------------------------------------------
|
833 |
|
|
component neorv32_mtime
|
834 |
|
|
port (
|
835 |
|
|
-- host access --
|
836 |
|
|
clk_i : in std_ulogic; -- global clock line
|
837 |
4 |
zero_gravi |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
838 |
2 |
zero_gravi |
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
839 |
|
|
rden_i : in std_ulogic; -- read enable
|
840 |
|
|
wren_i : in std_ulogic; -- write enable
|
841 |
|
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
842 |
|
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
843 |
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
844 |
|
|
ack_o : out std_ulogic; -- transfer acknowledge
|
845 |
11 |
zero_gravi |
-- time output for CPU --
|
846 |
|
|
time_o : out std_ulogic_vector(63 downto 0); -- current system time
|
847 |
2 |
zero_gravi |
-- interrupt --
|
848 |
|
|
irq_o : out std_ulogic -- interrupt request
|
849 |
|
|
);
|
850 |
|
|
end component;
|
851 |
|
|
|
852 |
|
|
-- Component: General Purpose Input/Output Port (GPIO) ------------------------------------
|
853 |
|
|
-- -------------------------------------------------------------------------------------------
|
854 |
|
|
component neorv32_gpio
|
855 |
|
|
port (
|
856 |
|
|
-- host access --
|
857 |
|
|
clk_i : in std_ulogic; -- global clock line
|
858 |
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
859 |
|
|
rden_i : in std_ulogic; -- read enable
|
860 |
|
|
wren_i : in std_ulogic; -- write enable
|
861 |
|
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
862 |
|
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
863 |
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
864 |
|
|
ack_o : out std_ulogic; -- transfer acknowledge
|
865 |
|
|
-- parallel io --
|
866 |
|
|
gpio_o : out std_ulogic_vector(15 downto 0);
|
867 |
|
|
gpio_i : in std_ulogic_vector(15 downto 0);
|
868 |
|
|
-- interrupt --
|
869 |
|
|
irq_o : out std_ulogic
|
870 |
|
|
);
|
871 |
|
|
end component;
|
872 |
|
|
|
873 |
|
|
-- Component: Watchdog Timer (WDT) --------------------------------------------------------
|
874 |
|
|
-- -------------------------------------------------------------------------------------------
|
875 |
|
|
component neorv32_wdt
|
876 |
|
|
port (
|
877 |
|
|
-- host access --
|
878 |
|
|
clk_i : in std_ulogic; -- global clock line
|
879 |
|
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
880 |
|
|
rden_i : in std_ulogic; -- read enable
|
881 |
|
|
wren_i : in std_ulogic; -- write enable
|
882 |
|
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
883 |
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
884 |
|
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
885 |
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
886 |
|
|
ack_o : out std_ulogic; -- transfer acknowledge
|
887 |
|
|
-- clock generator --
|
888 |
|
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
889 |
|
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
890 |
|
|
-- timeout event --
|
891 |
|
|
irq_o : out std_ulogic; -- timeout IRQ
|
892 |
|
|
rstn_o : out std_ulogic -- timeout reset, low_active, use it as async!
|
893 |
|
|
);
|
894 |
|
|
end component;
|
895 |
|
|
|
896 |
|
|
-- Component: Universal Asynchronous Receiver and Transmitter (UART) ----------------------
|
897 |
|
|
-- -------------------------------------------------------------------------------------------
|
898 |
|
|
component neorv32_uart
|
899 |
|
|
port (
|
900 |
|
|
-- host access --
|
901 |
|
|
clk_i : in std_ulogic; -- global clock line
|
902 |
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
903 |
|
|
rden_i : in std_ulogic; -- read enable
|
904 |
|
|
wren_i : in std_ulogic; -- write enable
|
905 |
|
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
906 |
|
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
907 |
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
908 |
|
|
ack_o : out std_ulogic; -- transfer acknowledge
|
909 |
|
|
-- clock generator --
|
910 |
|
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
911 |
|
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
912 |
|
|
-- com lines --
|
913 |
|
|
uart_txd_o : out std_ulogic;
|
914 |
|
|
uart_rxd_i : in std_ulogic;
|
915 |
|
|
-- interrupts --
|
916 |
|
|
uart_irq_o : out std_ulogic -- uart rx/tx interrupt
|
917 |
|
|
);
|
918 |
|
|
end component;
|
919 |
|
|
|
920 |
|
|
-- Component: Serial Peripheral Interface (SPI) -------------------------------------------
|
921 |
|
|
-- -------------------------------------------------------------------------------------------
|
922 |
|
|
component neorv32_spi
|
923 |
|
|
port (
|
924 |
|
|
-- host access --
|
925 |
|
|
clk_i : in std_ulogic; -- global clock line
|
926 |
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
927 |
|
|
rden_i : in std_ulogic; -- read enable
|
928 |
|
|
wren_i : in std_ulogic; -- write enable
|
929 |
|
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
930 |
|
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
931 |
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
932 |
|
|
ack_o : out std_ulogic; -- transfer acknowledge
|
933 |
|
|
-- clock generator --
|
934 |
|
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
935 |
|
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
936 |
|
|
-- com lines --
|
937 |
6 |
zero_gravi |
spi_sck_o : out std_ulogic; -- SPI serial clock
|
938 |
|
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
939 |
|
|
spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out
|
940 |
2 |
zero_gravi |
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
941 |
|
|
-- interrupt --
|
942 |
|
|
spi_irq_o : out std_ulogic -- transmission done interrupt
|
943 |
|
|
);
|
944 |
|
|
end component;
|
945 |
|
|
|
946 |
|
|
-- Component: Two-Wire Interface (TWI) ----------------------------------------------------
|
947 |
|
|
-- -------------------------------------------------------------------------------------------
|
948 |
|
|
component neorv32_twi
|
949 |
|
|
port (
|
950 |
|
|
-- host access --
|
951 |
|
|
clk_i : in std_ulogic; -- global clock line
|
952 |
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
953 |
|
|
rden_i : in std_ulogic; -- read enable
|
954 |
|
|
wren_i : in std_ulogic; -- write enable
|
955 |
|
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
956 |
|
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
957 |
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
958 |
|
|
ack_o : out std_ulogic; -- transfer acknowledge
|
959 |
|
|
-- clock generator --
|
960 |
|
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
961 |
|
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
962 |
|
|
-- com lines --
|
963 |
|
|
twi_sda_io : inout std_logic; -- serial data line
|
964 |
|
|
twi_scl_io : inout std_logic; -- serial clock line
|
965 |
|
|
-- interrupt --
|
966 |
|
|
twi_irq_o : out std_ulogic -- transfer done IRQ
|
967 |
|
|
);
|
968 |
|
|
end component;
|
969 |
|
|
|
970 |
|
|
-- Component: Pulse-Width Modulation Controller (PWM) -------------------------------------
|
971 |
|
|
-- -------------------------------------------------------------------------------------------
|
972 |
|
|
component neorv32_pwm
|
973 |
|
|
port (
|
974 |
|
|
-- host access --
|
975 |
|
|
clk_i : in std_ulogic; -- global clock line
|
976 |
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
977 |
|
|
rden_i : in std_ulogic; -- read enable
|
978 |
|
|
wren_i : in std_ulogic; -- write enable
|
979 |
|
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
980 |
|
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
981 |
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
982 |
|
|
ack_o : out std_ulogic; -- transfer acknowledge
|
983 |
|
|
-- clock generator --
|
984 |
|
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
985 |
|
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
986 |
|
|
-- pwm output channels --
|
987 |
|
|
pwm_o : out std_ulogic_vector(03 downto 0)
|
988 |
|
|
);
|
989 |
|
|
end component;
|
990 |
|
|
|
991 |
|
|
-- Component: True Random Number Generator (TRNG) -----------------------------------------
|
992 |
|
|
-- -------------------------------------------------------------------------------------------
|
993 |
|
|
component neorv32_trng
|
994 |
|
|
port (
|
995 |
|
|
-- host access --
|
996 |
|
|
clk_i : in std_ulogic; -- global clock line
|
997 |
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
998 |
|
|
rden_i : in std_ulogic; -- read enable
|
999 |
|
|
wren_i : in std_ulogic; -- write enable
|
1000 |
|
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
1001 |
|
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
1002 |
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
1003 |
|
|
ack_o : out std_ulogic -- transfer acknowledge
|
1004 |
|
|
);
|
1005 |
|
|
end component;
|
1006 |
|
|
|
1007 |
|
|
-- Component: Wishbone Bus Gateway (WISHBONE) ---------------------------------------------
|
1008 |
|
|
-- -------------------------------------------------------------------------------------------
|
1009 |
|
|
component neorv32_wishbone
|
1010 |
|
|
generic (
|
1011 |
|
|
INTERFACE_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
1012 |
|
|
-- Memory configuration: Instruction memory --
|
1013 |
|
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
1014 |
|
|
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
|
1015 |
|
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
1016 |
|
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
1017 |
|
|
-- Memory configuration: Data memory --
|
1018 |
|
|
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
|
1019 |
|
|
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
|
1020 |
|
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
1021 |
|
|
MEM_INT_DMEM_SIZE : natural := 4*1024 -- size of processor-internal data memory in bytes
|
1022 |
|
|
);
|
1023 |
|
|
port (
|
1024 |
|
|
-- global control --
|
1025 |
|
|
clk_i : in std_ulogic; -- global clock line
|
1026 |
|
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
1027 |
|
|
-- host access --
|
1028 |
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
1029 |
|
|
rden_i : in std_ulogic; -- read enable
|
1030 |
|
|
wren_i : in std_ulogic; -- write enable
|
1031 |
|
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
1032 |
|
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
1033 |
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
1034 |
11 |
zero_gravi |
cancel_i : in std_ulogic; -- cancel current bus transaction
|
1035 |
2 |
zero_gravi |
ack_o : out std_ulogic; -- transfer acknowledge
|
1036 |
|
|
err_o : out std_ulogic; -- transfer error
|
1037 |
|
|
-- wishbone interface --
|
1038 |
|
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
1039 |
|
|
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
|
1040 |
|
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
1041 |
|
|
wb_we_o : out std_ulogic; -- read/write
|
1042 |
|
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
1043 |
|
|
wb_stb_o : out std_ulogic; -- strobe
|
1044 |
|
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
1045 |
|
|
wb_ack_i : in std_ulogic; -- transfer acknowledge
|
1046 |
|
|
wb_err_i : in std_ulogic -- transfer error
|
1047 |
|
|
);
|
1048 |
|
|
end component;
|
1049 |
|
|
|
1050 |
4 |
zero_gravi |
---- Component: Dummy Device with SIM Output (DEVNULL) -------------------------------------
|
1051 |
|
|
---- -------------------------------------------------------------------------------------------
|
1052 |
3 |
zero_gravi |
component neorv32_devnull
|
1053 |
|
|
port (
|
1054 |
|
|
-- host access --
|
1055 |
|
|
clk_i : in std_ulogic; -- global clock line
|
1056 |
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
1057 |
|
|
rden_i : in std_ulogic; -- read enable
|
1058 |
|
|
wren_i : in std_ulogic; -- write enable
|
1059 |
|
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
1060 |
|
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
1061 |
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
1062 |
|
|
ack_o : out std_ulogic -- transfer acknowledge
|
1063 |
|
|
);
|
1064 |
|
|
end component;
|
1065 |
|
|
|
1066 |
12 |
zero_gravi |
---- Component: System Configuration Information Memory (SYSINFO) ---------------------------
|
1067 |
|
|
---- -------------------------------------------------------------------------------------------
|
1068 |
|
|
component neorv32_sysinfo
|
1069 |
|
|
generic (
|
1070 |
|
|
-- General --
|
1071 |
|
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
1072 |
|
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
1073 |
|
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
1074 |
|
|
-- Memory configuration: Instruction memory --
|
1075 |
|
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
1076 |
|
|
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
|
1077 |
|
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
1078 |
|
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
1079 |
|
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
1080 |
|
|
-- Memory configuration: Data memory --
|
1081 |
|
|
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
|
1082 |
|
|
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
|
1083 |
|
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
1084 |
|
|
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
|
1085 |
|
|
-- Memory configuration: External memory interface --
|
1086 |
|
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
1087 |
|
|
-- Processor peripherals --
|
1088 |
|
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
1089 |
|
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
1090 |
|
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
1091 |
|
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
1092 |
|
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
1093 |
|
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
1094 |
|
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
1095 |
|
|
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
|
1096 |
|
|
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
|
1097 |
|
|
);
|
1098 |
|
|
port (
|
1099 |
|
|
-- host access --
|
1100 |
|
|
clk_i : in std_ulogic; -- global clock line
|
1101 |
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
1102 |
|
|
rden_i : in std_ulogic; -- read enable
|
1103 |
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
1104 |
|
|
ack_o : out std_ulogic -- transfer acknowledge
|
1105 |
|
|
);
|
1106 |
|
|
end component;
|
1107 |
|
|
|
1108 |
2 |
zero_gravi |
end neorv32_package;
|
1109 |
|
|
|
1110 |
|
|
package body neorv32_package is
|
1111 |
|
|
|
1112 |
|
|
-- Function: Minimal required bit width ---------------------------------------------------
|
1113 |
|
|
-- -------------------------------------------------------------------------------------------
|
1114 |
|
|
function index_size_f(input : natural) return natural is
|
1115 |
|
|
begin
|
1116 |
|
|
for i in 0 to natural'high loop
|
1117 |
|
|
if (2**i >= input) then
|
1118 |
|
|
return i;
|
1119 |
|
|
end if;
|
1120 |
|
|
end loop; -- i
|
1121 |
|
|
return 0;
|
1122 |
|
|
end function index_size_f;
|
1123 |
|
|
|
1124 |
|
|
-- Function: Conditional select natural ---------------------------------------------------
|
1125 |
|
|
-- -------------------------------------------------------------------------------------------
|
1126 |
|
|
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural is
|
1127 |
|
|
begin
|
1128 |
|
|
if (cond = true) then
|
1129 |
|
|
return val_t;
|
1130 |
|
|
else
|
1131 |
|
|
return val_f;
|
1132 |
|
|
end if;
|
1133 |
|
|
end function cond_sel_natural_f;
|
1134 |
|
|
|
1135 |
|
|
-- Function: Conditional select std_ulogic_vector -----------------------------------------
|
1136 |
|
|
-- -------------------------------------------------------------------------------------------
|
1137 |
|
|
function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector is
|
1138 |
|
|
begin
|
1139 |
|
|
if (cond = true) then
|
1140 |
|
|
return val_t;
|
1141 |
|
|
else
|
1142 |
|
|
return val_f;
|
1143 |
|
|
end if;
|
1144 |
|
|
end function cond_sel_stdulogicvector_f;
|
1145 |
|
|
|
1146 |
|
|
-- Function: Convert BOOL to STD_ULOGIC ---------------------------------------------------
|
1147 |
|
|
-- -------------------------------------------------------------------------------------------
|
1148 |
|
|
function bool_to_ulogic_f(cond : boolean) return std_ulogic is
|
1149 |
|
|
begin
|
1150 |
|
|
if (cond = true) then
|
1151 |
|
|
return '1';
|
1152 |
|
|
else
|
1153 |
|
|
return '0';
|
1154 |
|
|
end if;
|
1155 |
|
|
end function bool_to_ulogic_f;
|
1156 |
|
|
|
1157 |
|
|
-- Function: OR all bits ------------------------------------------------------------------
|
1158 |
|
|
-- -------------------------------------------------------------------------------------------
|
1159 |
|
|
function or_all_f(a : std_ulogic_vector) return std_ulogic is
|
1160 |
|
|
variable tmp_v : std_ulogic;
|
1161 |
|
|
begin
|
1162 |
|
|
tmp_v := a(a'low);
|
1163 |
15 |
zero_gravi |
if (a'low < a'high) then -- not null range?
|
1164 |
|
|
for i in a'low+1 to a'high loop
|
1165 |
|
|
tmp_v := tmp_v or a(i);
|
1166 |
|
|
end loop; -- i
|
1167 |
|
|
end if;
|
1168 |
2 |
zero_gravi |
return tmp_v;
|
1169 |
|
|
end function or_all_f;
|
1170 |
|
|
|
1171 |
|
|
-- Function: AND all bits -----------------------------------------------------------------
|
1172 |
|
|
-- -------------------------------------------------------------------------------------------
|
1173 |
|
|
function and_all_f(a : std_ulogic_vector) return std_ulogic is
|
1174 |
|
|
variable tmp_v : std_ulogic;
|
1175 |
|
|
begin
|
1176 |
|
|
tmp_v := a(a'low);
|
1177 |
15 |
zero_gravi |
if (a'low < a'high) then -- not null range?
|
1178 |
|
|
for i in a'low+1 to a'high loop
|
1179 |
|
|
tmp_v := tmp_v and a(i);
|
1180 |
|
|
end loop; -- i
|
1181 |
|
|
end if;
|
1182 |
2 |
zero_gravi |
return tmp_v;
|
1183 |
|
|
end function and_all_f;
|
1184 |
|
|
|
1185 |
|
|
-- Function: XOR all bits -----------------------------------------------------------------
|
1186 |
|
|
-- -------------------------------------------------------------------------------------------
|
1187 |
|
|
function xor_all_f(a : std_ulogic_vector) return std_ulogic is
|
1188 |
|
|
variable tmp_v : std_ulogic;
|
1189 |
|
|
begin
|
1190 |
|
|
tmp_v := a(a'low);
|
1191 |
15 |
zero_gravi |
if (a'low < a'high) then -- not null range?
|
1192 |
|
|
for i in a'low+1 to a'high loop
|
1193 |
|
|
tmp_v := tmp_v xor a(i);
|
1194 |
|
|
end loop; -- i
|
1195 |
|
|
end if;
|
1196 |
2 |
zero_gravi |
return tmp_v;
|
1197 |
|
|
end function xor_all_f;
|
1198 |
|
|
|
1199 |
|
|
-- Function: XNOR all bits ----------------------------------------------------------------
|
1200 |
|
|
-- -------------------------------------------------------------------------------------------
|
1201 |
|
|
function xnor_all_f(a : std_ulogic_vector) return std_ulogic is
|
1202 |
|
|
variable tmp_v : std_ulogic;
|
1203 |
|
|
begin
|
1204 |
|
|
tmp_v := a(a'low);
|
1205 |
15 |
zero_gravi |
if (a'low < a'high) then -- not null range?
|
1206 |
|
|
for i in a'low+1 to a'high loop
|
1207 |
|
|
tmp_v := tmp_v xnor a(i);
|
1208 |
|
|
end loop; -- i
|
1209 |
|
|
end if;
|
1210 |
2 |
zero_gravi |
return tmp_v;
|
1211 |
|
|
end function xnor_all_f;
|
1212 |
|
|
|
1213 |
6 |
zero_gravi |
-- Function: Convert to hex char ----------------------------------------------------------
|
1214 |
|
|
-- -------------------------------------------------------------------------------------------
|
1215 |
|
|
function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character is
|
1216 |
|
|
variable output_v : character;
|
1217 |
|
|
begin
|
1218 |
|
|
case input is
|
1219 |
7 |
zero_gravi |
when x"0" => output_v := '0';
|
1220 |
|
|
when x"1" => output_v := '1';
|
1221 |
|
|
when x"2" => output_v := '2';
|
1222 |
|
|
when x"3" => output_v := '3';
|
1223 |
|
|
when x"4" => output_v := '4';
|
1224 |
|
|
when x"5" => output_v := '5';
|
1225 |
|
|
when x"6" => output_v := '6';
|
1226 |
|
|
when x"7" => output_v := '7';
|
1227 |
|
|
when x"8" => output_v := '8';
|
1228 |
|
|
when x"9" => output_v := '9';
|
1229 |
|
|
when x"a" => output_v := 'a';
|
1230 |
|
|
when x"b" => output_v := 'b';
|
1231 |
|
|
when x"c" => output_v := 'c';
|
1232 |
|
|
when x"d" => output_v := 'd';
|
1233 |
|
|
when x"e" => output_v := 'e';
|
1234 |
|
|
when x"f" => output_v := 'f';
|
1235 |
6 |
zero_gravi |
when others => output_v := '?';
|
1236 |
|
|
end case;
|
1237 |
|
|
return output_v;
|
1238 |
|
|
end function to_hexchar_f;
|
1239 |
|
|
|
1240 |
2 |
zero_gravi |
end neorv32_package;
|