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-- #################################################################################################

-- # << NEORV32 - Main VHDL package file >>                                                        #

-- # ********************************************************************************************* #

-- # BSD 3-Clause License                                                                          #

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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #

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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #

-- #################################################################################################

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

package neorv32_package is

  -- Architecture Configuration -------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- address space --

  constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address

  constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address

  -- (external) bus interface --

  constant bus_timeout_c     : natural := 127; -- cycles after which an *unacknowledged* bus access will timeout and trigger a bus fault exception (min 2)

  constant wb_pipe_mode_c    : boolean := false; -- *external* bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode

  constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian

  -- CPU core --

  constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2

  -- Architecture Constants (do not modify!)= -----------------------------------------------

  -- -------------------------------------------------------------------------------------------

  constant data_width_c   : natural := 32; -- data width - do not change!

  constant hw_version_c   : std_ulogic_vector(31 downto 0) := x"01040908"; -- no touchy!

  constant pmp_max_r_c    : natural := 8; -- max PMP regions - FIXED!

  constant archid_c       : natural := 19; -- official NEORV32 architecture ID - hands off!

  constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW

  -- Helper Functions -----------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  function index_size_f(input : natural) return natural;

  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;

  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;

  function bool_to_ulogic_f(cond : boolean) return std_ulogic;

  function or_all_f(a : std_ulogic_vector) return std_ulogic;

  function and_all_f(a : std_ulogic_vector) return std_ulogic;

  function xor_all_f(a : std_ulogic_vector) return std_ulogic;

  function xnor_all_f(a : std_ulogic_vector) return std_ulogic;

  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;

  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector;

  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector;

  function is_power_of_two_f(input : natural) return boolean;

  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;

  -- Internal Types -------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);

  type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0);

  -- Processor-Internal Address Space Layout ------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --

  constant imem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address

  constant dmem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address

  --> internal data/instruction memory sizes are configured via top's generics

  -- Internal Bootloader ROM --

  constant boot_rom_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!

  constant boot_rom_size_c      : natural := 4*1024; -- bytes

  constant boot_rom_max_size_c  : natural := 32*1024; -- bytes, fixed!

  -- IO: Peripheral Devices ("IO") Area --

  -- Control register(s) (including the device-enable) should be located at the base address of each device

  constant io_base_c            : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80";

  constant io_size_c            : natural := 32*4; -- bytes, fixed!

  -- General Purpose Input/Output Unit (GPIO) --

  constant gpio_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address, fixed!

  constant gpio_size_c          : natural := 2*4; -- bytes

  constant gpio_in_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80";

  constant gpio_out_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF84";

  -- True Random Number Generator (TRNG) --

  constant trng_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address, fixed!

  constant trng_size_c          : natural := 1*4; -- bytes

  constant trng_ctrl_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88";

  -- Watch Dog Timer (WDT) --

  constant wdt_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address, fixed!

  constant wdt_size_c           : natural := 1*4; -- bytes

  constant wdt_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C";

  -- Machine System Timer (MTIME) --

  constant mtime_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90"; -- base address, fixed!

  constant mtime_size_c         : natural := 4*4; -- bytes

  constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90";

  constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF94";

  constant mtime_cmp_lo_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF98";

  constant mtime_cmp_hi_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF9C";

  -- Universal Asynchronous Receiver/Transmitter (UART) --

  constant uart_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address, fixed!

  constant uart_size_c          : natural := 2*4; -- bytes

  constant uart_ctrl_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0";

  constant uart_rtx_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA4";

  -- Serial Peripheral Interface (SPI) --

  constant spi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address, fixed!

  constant spi_size_c           : natural := 2*4; -- bytes

  constant spi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8";

  constant spi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFAC";

  -- Two Wire Interface (TWI) --

  constant twi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0"; -- base address, fixed!

  constant twi_size_c           : natural := 2*4; -- bytes

  constant twi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0";

  constant twi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB4";

  -- Pulse-Width Modulation Controller (PWM) --

  constant pwm_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address, fixed!

  constant pwm_size_c           : natural := 2*4; -- bytes

  constant pwm_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8";

  constant pwm_duty_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFBC";

  -- Custom Functions Unit 0 (CFU0) --

  constant cfu0_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address, fixed!

  constant cfu0_size_c          : natural := 4*4; -- bytes

  constant cfu0_reg0_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0";

  constant cfu0_reg1_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC4";

  constant cfu0_reg2_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8";

  constant cfu0_reg3_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC";

  -- Custom Functions Unit 1 (CFU1) --

  constant cfu1_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address, fixed!

  constant cfu1_size_c          : natural := 4*4; -- bytes

  constant cfu1_reg0_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0";

  constant cfu1_reg1_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD4";

  constant cfu1_reg2_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD8";

  constant cfu1_reg3_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFDC";

  -- System Information Memory (SYSINFO) --

  constant sysinfo_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address, fixed!

  constant sysinfo_size_c       : natural := 8*4; -- bytes

  -- Main Control Bus -----------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- register file --

  constant ctrl_rf_in_mux_lsb_c : natural :=  0; -- input source select lsb (10=MEM, 11=CSR)

  constant ctrl_rf_in_mux_msb_c : natural :=  1; -- input source select msb (0-=ALU)

  constant ctrl_rf_rs1_adr0_c   : natural :=  2; -- source register 1 address bit 0

  constant ctrl_rf_rs1_adr1_c   : natural :=  3; -- source register 1 address bit 1

  constant ctrl_rf_rs1_adr2_c   : natural :=  4; -- source register 1 address bit 2

  constant ctrl_rf_rs1_adr3_c   : natural :=  5; -- source register 1 address bit 3

  constant ctrl_rf_rs1_adr4_c   : natural :=  6; -- source register 1 address bit 4

  constant ctrl_rf_rs2_adr0_c   : natural :=  7; -- source register 2 address bit 0

  constant ctrl_rf_rs2_adr1_c   : natural :=  8; -- source register 2 address bit 1

  constant ctrl_rf_rs2_adr2_c   : natural :=  9; -- source register 2 address bit 2

  constant ctrl_rf_rs2_adr3_c   : natural := 10; -- source register 2 address bit 3

  constant ctrl_rf_rs2_adr4_c   : natural := 11; -- source register 2 address bit 4

  constant ctrl_rf_rd_adr0_c    : natural := 12; -- destiantion register address bit 0

  constant ctrl_rf_rd_adr1_c    : natural := 13; -- destiantion register address bit 1

  constant ctrl_rf_rd_adr2_c    : natural := 14; -- destiantion register address bit 2

  constant ctrl_rf_rd_adr3_c    : natural := 15; -- destiantion register address bit 3

  constant ctrl_rf_rd_adr4_c    : natural := 16; -- destiantion register address bit 4

  constant ctrl_rf_wb_en_c      : natural := 17; -- write back enable

  constant ctrl_rf_r0_we_c      : natural := 18; -- force write access and force rd=r0

  -- alu --

  constant ctrl_alu_arith_c     : natural := 19; -- ALU arithmetic command

  constant ctrl_alu_logic0_c    : natural := 20; -- ALU logic command bit 0

  constant ctrl_alu_logic1_c    : natural := 21; -- ALU logic command bit 1

  constant ctrl_alu_func0_c     : natural := 22; -- ALU function select command bit 0

  constant ctrl_alu_func1_c     : natural := 23; -- ALU function select command bit 1

  constant ctrl_alu_addsub_c    : natural := 24; -- 0=ADD, 1=SUB

  constant ctrl_alu_opa_mux_c   : natural := 25; -- operand A select (0=rs1, 1=PC)

  constant ctrl_alu_opb_mux_c   : natural := 26; -- operand B select (0=rs2, 1=IMM)

  constant ctrl_alu_unsigned_c  : natural := 27; -- is unsigned ALU operation

  constant ctrl_alu_shift_dir_c : natural := 28; -- shift direction (0=left, 1=right)

  constant ctrl_alu_shift_ar_c  : natural := 29; -- is arithmetic shift

  -- bus interface --

  constant ctrl_bus_size_lsb_c  : natural := 30; -- transfer size lsb (00=byte, 01=half-word)

  constant ctrl_bus_size_msb_c  : natural := 31; -- transfer size msb (10=word, 11=?)

  constant ctrl_bus_rd_c        : natural := 32; -- read data request

  constant ctrl_bus_wr_c        : natural := 33; -- write data request

  constant ctrl_bus_if_c        : natural := 34; -- instruction fetch request

  constant ctrl_bus_mo_we_c     : natural := 35; -- memory address and data output register write enable

  constant ctrl_bus_mi_we_c     : natural := 36; -- memory data input register write enable

  constant ctrl_bus_unsigned_c  : natural := 37; -- is unsigned load

  constant ctrl_bus_ierr_ack_c  : natural := 38; -- acknowledge instruction fetch bus exceptions

  constant ctrl_bus_derr_ack_c  : natural := 39; -- acknowledge data access bus exceptions

  constant ctrl_bus_fence_c     : natural := 40; -- executed fence operation

  constant ctrl_bus_fencei_c    : natural := 41; -- executed fencei operation

  constant ctrl_bus_lock_c      : natural := 42; -- locked/exclusive bus access

  -- co-processors --

  constant ctrl_cp_id_lsb_c     : natural := 43; -- cp select ID lsb

  constant ctrl_cp_id_msb_c     : natural := 44; -- cp select ID msb

  -- current privilege level --

  constant ctrl_priv_lvl_lsb_c  : natural := 45; -- privilege level lsb

  constant ctrl_priv_lvl_msb_c  : natural := 46; -- privilege level msb

  -- instruction's control blocks --

  constant ctrl_ir_funct3_0_c   : natural := 47; -- funct3 bit 0

  constant ctrl_ir_funct3_1_c   : natural := 48; -- funct3 bit 1

  constant ctrl_ir_funct3_2_c   : natural := 49; -- funct3 bit 2

  constant ctrl_ir_funct12_0_c  : natural := 50; -- funct12 bit 0

  constant ctrl_ir_funct12_1_c  : natural := 51; -- funct12 bit 1

  constant ctrl_ir_funct12_2_c  : natural := 52; -- funct12 bit 2

  constant ctrl_ir_funct12_3_c  : natural := 53; -- funct12 bit 3

  constant ctrl_ir_funct12_4_c  : natural := 54; -- funct12 bit 4

  constant ctrl_ir_funct12_5_c  : natural := 55; -- funct12 bit 5

  constant ctrl_ir_funct12_6_c  : natural := 56; -- funct12 bit 6

  constant ctrl_ir_funct12_7_c  : natural := 57; -- funct12 bit 7

  constant ctrl_ir_funct12_8_c  : natural := 58; -- funct12 bit 8

  constant ctrl_ir_funct12_9_c  : natural := 59; -- funct12 bit 9

  constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10

  constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11

  -- control bus size --

  constant ctrl_width_c         : natural := 62; -- control bus size

  -- ALU Comparator Bus ---------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  constant alu_cmp_equal_c : natural := 0;

  constant alu_cmp_less_c  : natural := 1; -- for signed and unsigned comparisons

  -- RISC-V Opcode Layout -------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  constant instr_opcode_lsb_c  : natural :=  0; -- opcode bit 0

  constant instr_opcode_msb_c  : natural :=  6; -- opcode bit 6

  constant instr_rd_lsb_c      : natural :=  7; -- destination register address bit 0

  constant instr_rd_msb_c      : natural := 11; -- destination register address bit 4

  constant instr_funct3_lsb_c  : natural := 12; -- funct3 bit 0

  constant instr_funct3_msb_c  : natural := 14; -- funct3 bit 2

  constant instr_rs1_lsb_c     : natural := 15; -- source register 1 address bit 0

  constant instr_rs1_msb_c     : natural := 19; -- source register 1 address bit 4

  constant instr_rs2_lsb_c     : natural := 20; -- source register 2 address bit 0

  constant instr_rs2_msb_c     : natural := 24; -- source register 2 address bit 4

  constant instr_funct7_lsb_c  : natural := 25; -- funct7 bit 0

  constant instr_funct7_msb_c  : natural := 31; -- funct7 bit 6

  constant instr_funct12_lsb_c : natural := 20; -- funct12 bit 0

  constant instr_funct12_msb_c : natural := 31; -- funct12 bit 11

  constant instr_imm12_lsb_c   : natural := 20; -- immediate12 bit 0

  constant instr_imm12_msb_c   : natural := 31; -- immediate12 bit 11

  constant instr_imm20_lsb_c   : natural := 12; -- immediate20 bit 0

  constant instr_imm20_msb_c   : natural := 31; -- immediate20 bit 21

  constant instr_csr_id_lsb_c  : natural := 20; -- csr select bit 0

  constant instr_csr_id_msb_c  : natural := 31; -- csr select bit 11

  constant instr_funct5_lsb_c  : natural := 27; -- funct5 select bit 0

  constant instr_funct5_msb_c  : natural := 31; -- funct5 select bit 4

  -- RISC-V Opcodes -------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- alu --

  constant opcode_lui_c    : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate

  constant opcode_auipc_c  : std_ulogic_vector(6 downto 0) := "0010111"; -- add upper immediate to PC

  constant opcode_alui_c   : std_ulogic_vector(6 downto 0) := "0010011"; -- ALU operation with immediate (operation via funct3 and funct7)

  constant opcode_alu_c    : std_ulogic_vector(6 downto 0) := "0110011"; -- ALU operation (operation via funct3 and funct7)

  -- control flow --

  constant opcode_jal_c    : std_ulogic_vector(6 downto 0) := "1101111"; -- jump and link

  constant opcode_jalr_c   : std_ulogic_vector(6 downto 0) := "1100111"; -- jump and link with register

  constant opcode_branch_c : std_ulogic_vector(6 downto 0) := "1100011"; -- branch (condition set via funct3)

  -- memory access --

  constant opcode_load_c   : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)

  constant opcode_store_c  : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)

  -- system/csr --

  constant opcode_fence_c  : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i

  constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)

  -- atomic operations (A) --

  constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)

  -- RISC-V Funct3 --------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- control flow --

  constant funct3_beq_c    : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal

  constant funct3_bne_c    : std_ulogic_vector(2 downto 0) := "001"; -- branch if not equal

  constant funct3_blt_c    : std_ulogic_vector(2 downto 0) := "100"; -- branch if less than

  constant funct3_bge_c    : std_ulogic_vector(2 downto 0) := "101"; -- branch if greater than or equal

  constant funct3_bltu_c   : std_ulogic_vector(2 downto 0) := "110"; -- branch if less than (unsigned)

  constant funct3_bgeu_c   : std_ulogic_vector(2 downto 0) := "111"; -- branch if greater than or equal (unsigned)

  -- memory access --

  constant funct3_lb_c     : std_ulogic_vector(2 downto 0) := "000"; -- load byte

  constant funct3_lh_c     : std_ulogic_vector(2 downto 0) := "001"; -- load half word

  constant funct3_lw_c     : std_ulogic_vector(2 downto 0) := "010"; -- load word

  constant funct3_lbu_c    : std_ulogic_vector(2 downto 0) := "100"; -- load byte (unsigned)

  constant funct3_lhu_c    : std_ulogic_vector(2 downto 0) := "101"; -- load half word (unsigned)

  constant funct3_sb_c     : std_ulogic_vector(2 downto 0) := "000"; -- store byte

  constant funct3_sh_c     : std_ulogic_vector(2 downto 0) := "001"; -- store half word

  constant funct3_sw_c     : std_ulogic_vector(2 downto 0) := "010"; -- store word

  -- alu --

  constant funct3_subadd_c : std_ulogic_vector(2 downto 0) := "000"; -- sub/add via funct7

  constant funct3_sll_c    : std_ulogic_vector(2 downto 0) := "001"; -- shift logical left

  constant funct3_slt_c    : std_ulogic_vector(2 downto 0) := "010"; -- set on less

  constant funct3_sltu_c   : std_ulogic_vector(2 downto 0) := "011"; -- set on less unsigned

  constant funct3_xor_c    : std_ulogic_vector(2 downto 0) := "100"; -- xor

  constant funct3_sr_c     : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7

  constant funct3_or_c     : std_ulogic_vector(2 downto 0) := "110"; -- or

  constant funct3_and_c    : std_ulogic_vector(2 downto 0) := "111"; -- and

  -- system/csr --

  constant funct3_env_c    : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi

  constant funct3_csrrw_c  : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w

  constant funct3_csrrs_c  : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit

  constant funct3_csrrc_c  : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit

  constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate

  constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate

  constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate

  -- fence --

  constant funct3_fence_c  : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)

  constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync

  -- RISC-V Funct12 -------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- system --

  constant funct12_ecall_c  : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL

  constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK

  constant funct12_mret_c   : std_ulogic_vector(11 downto 0) := x"302"; -- MRET

  constant funct12_wfi_c    : std_ulogic_vector(11 downto 0) := x"105"; -- WFI

  -- RISC-V Funct5 --------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- atomic operations --

  constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR

  constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC

  -- RISC-V CSR Addresses -------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- read/write CSRs --

  constant csr_mstatus_c        : std_ulogic_vector(11 downto 0) := x"300";

  constant csr_misa_c           : std_ulogic_vector(11 downto 0) := x"301";

  constant csr_mie_c            : std_ulogic_vector(11 downto 0) := x"304";

  constant csr_mtvec_c          : std_ulogic_vector(11 downto 0) := x"305";

  constant csr_mcounteren_c     : std_ulogic_vector(11 downto 0) := x"306";

  constant csr_mstatush_c       : std_ulogic_vector(11 downto 0) := x"310";

  --

  constant csr_mcountinhibit_c  : std_ulogic_vector(11 downto 0) := x"320";

  --

  constant csr_mhpmevent3_c     : std_ulogic_vector(11 downto 0) := x"323";

  constant csr_mhpmevent4_c     : std_ulogic_vector(11 downto 0) := x"324";

  constant csr_mhpmevent5_c     : std_ulogic_vector(11 downto 0) := x"325";

  constant csr_mhpmevent6_c     : std_ulogic_vector(11 downto 0) := x"326";

  constant csr_mhpmevent7_c     : std_ulogic_vector(11 downto 0) := x"327";

  constant csr_mhpmevent8_c     : std_ulogic_vector(11 downto 0) := x"328";

  constant csr_mhpmevent9_c     : std_ulogic_vector(11 downto 0) := x"329";

  constant csr_mhpmevent10_c    : std_ulogic_vector(11 downto 0) := x"32a";

  constant csr_mhpmevent11_c    : std_ulogic_vector(11 downto 0) := x"32b";

  constant csr_mhpmevent12_c    : std_ulogic_vector(11 downto 0) := x"32c";

  constant csr_mhpmevent13_c    : std_ulogic_vector(11 downto 0) := x"32d";

  constant csr_mhpmevent14_c    : std_ulogic_vector(11 downto 0) := x"32e";

  constant csr_mhpmevent15_c    : std_ulogic_vector(11 downto 0) := x"32f";

  constant csr_mhpmevent16_c    : std_ulogic_vector(11 downto 0) := x"330";

  constant csr_mhpmevent17_c    : std_ulogic_vector(11 downto 0) := x"331";

  constant csr_mhpmevent18_c    : std_ulogic_vector(11 downto 0) := x"332";

  constant csr_mhpmevent19_c    : std_ulogic_vector(11 downto 0) := x"333";

  constant csr_mhpmevent20_c    : std_ulogic_vector(11 downto 0) := x"334";

  constant csr_mhpmevent21_c    : std_ulogic_vector(11 downto 0) := x"335";

  constant csr_mhpmevent22_c    : std_ulogic_vector(11 downto 0) := x"336";

  constant csr_mhpmevent23_c    : std_ulogic_vector(11 downto 0) := x"337";

  constant csr_mhpmevent24_c    : std_ulogic_vector(11 downto 0) := x"338";

  constant csr_mhpmevent25_c    : std_ulogic_vector(11 downto 0) := x"339";

  constant csr_mhpmevent26_c    : std_ulogic_vector(11 downto 0) := x"33a";

  constant csr_mhpmevent27_c    : std_ulogic_vector(11 downto 0) := x"33b";

  constant csr_mhpmevent28_c    : std_ulogic_vector(11 downto 0) := x"33c";

  constant csr_mhpmevent29_c    : std_ulogic_vector(11 downto 0) := x"33d";

  constant csr_mhpmevent30_c    : std_ulogic_vector(11 downto 0) := x"33e";

  constant csr_mhpmevent31_c    : std_ulogic_vector(11 downto 0) := x"33f";

  --

  constant csr_mscratch_c       : std_ulogic_vector(11 downto 0) := x"340";

  constant csr_mepc_c           : std_ulogic_vector(11 downto 0) := x"341";

  constant csr_mcause_c         : std_ulogic_vector(11 downto 0) := x"342";

  constant csr_mtval_c          : std_ulogic_vector(11 downto 0) := x"343";

  constant csr_mip_c            : std_ulogic_vector(11 downto 0) := x"344";

  --

  constant csr_pmpcfg0_c        : std_ulogic_vector(11 downto 0) := x"3a0";

  constant csr_pmpcfg1_c        : std_ulogic_vector(11 downto 0) := x"3a1";

  constant csr_pmpcfg2_c        : std_ulogic_vector(11 downto 0) := x"3a2";

  constant csr_pmpcfg3_c        : std_ulogic_vector(11 downto 0) := x"3a3";

  constant csr_pmpcfg4_c        : std_ulogic_vector(11 downto 0) := x"3a4";

  constant csr_pmpcfg5_c        : std_ulogic_vector(11 downto 0) := x"3a5";

  constant csr_pmpcfg6_c        : std_ulogic_vector(11 downto 0) := x"3a6";

  constant csr_pmpcfg7_c        : std_ulogic_vector(11 downto 0) := x"3a7";

  constant csr_pmpcfg8_c        : std_ulogic_vector(11 downto 0) := x"3a8";

  constant csr_pmpcfg9_c        : std_ulogic_vector(11 downto 0) := x"3a9";

  constant csr_pmpcfg10_c       : std_ulogic_vector(11 downto 0) := x"3aa";

  constant csr_pmpcfg11_c       : std_ulogic_vector(11 downto 0) := x"3ab";

  constant csr_pmpcfg12_c       : std_ulogic_vector(11 downto 0) := x"3ac";

  constant csr_pmpcfg13_c       : std_ulogic_vector(11 downto 0) := x"3ad";

  constant csr_pmpcfg14_c       : std_ulogic_vector(11 downto 0) := x"3ae";

  constant csr_pmpcfg15_c       : std_ulogic_vector(11 downto 0) := x"3af";

  --

  constant csr_pmpaddr0_c       : std_ulogic_vector(11 downto 0) := x"3b0";

  constant csr_pmpaddr1_c       : std_ulogic_vector(11 downto 0) := x"3b1";

  constant csr_pmpaddr2_c       : std_ulogic_vector(11 downto 0) := x"3b2";

  constant csr_pmpaddr3_c       : std_ulogic_vector(11 downto 0) := x"3b3";

  constant csr_pmpaddr4_c       : std_ulogic_vector(11 downto 0) := x"3b4";

  constant csr_pmpaddr5_c       : std_ulogic_vector(11 downto 0) := x"3b5";

  constant csr_pmpaddr6_c       : std_ulogic_vector(11 downto 0) := x"3b6";

  constant csr_pmpaddr7_c       : std_ulogic_vector(11 downto 0) := x"3b7";

  constant csr_pmpaddr8_c       : std_ulogic_vector(11 downto 0) := x"3b8";

  constant csr_pmpaddr9_c       : std_ulogic_vector(11 downto 0) := x"3b9";

  constant csr_pmpaddr10_c      : std_ulogic_vector(11 downto 0) := x"3ba";

  constant csr_pmpaddr11_c      : std_ulogic_vector(11 downto 0) := x"3bb";

  constant csr_pmpaddr12_c      : std_ulogic_vector(11 downto 0) := x"3bc";

  constant csr_pmpaddr13_c      : std_ulogic_vector(11 downto 0) := x"3bd";

  constant csr_pmpaddr14_c      : std_ulogic_vector(11 downto 0) := x"3be";

  constant csr_pmpaddr15_c      : std_ulogic_vector(11 downto 0) := x"3bf";

  constant csr_pmpaddr16_c      : std_ulogic_vector(11 downto 0) := x"3c0";

  constant csr_pmpaddr17_c      : std_ulogic_vector(11 downto 0) := x"3c1";

  constant csr_pmpaddr18_c      : std_ulogic_vector(11 downto 0) := x"3c2";

  constant csr_pmpaddr19_c      : std_ulogic_vector(11 downto 0) := x"3c3";

  constant csr_pmpaddr20_c      : std_ulogic_vector(11 downto 0) := x"3c4";

  constant csr_pmpaddr21_c      : std_ulogic_vector(11 downto 0) := x"3c5";

  constant csr_pmpaddr22_c      : std_ulogic_vector(11 downto 0) := x"3c6";

  constant csr_pmpaddr23_c      : std_ulogic_vector(11 downto 0) := x"3c7";

  constant csr_pmpaddr24_c      : std_ulogic_vector(11 downto 0) := x"3c8";

  constant csr_pmpaddr25_c      : std_ulogic_vector(11 downto 0) := x"3c9";

  constant csr_pmpaddr26_c      : std_ulogic_vector(11 downto 0) := x"3ca";

  constant csr_pmpaddr27_c      : std_ulogic_vector(11 downto 0) := x"3cb";

  constant csr_pmpaddr28_c      : std_ulogic_vector(11 downto 0) := x"3cc";

  constant csr_pmpaddr29_c      : std_ulogic_vector(11 downto 0) := x"3cd";

  constant csr_pmpaddr30_c      : std_ulogic_vector(11 downto 0) := x"3ce";

  constant csr_pmpaddr31_c      : std_ulogic_vector(11 downto 0) := x"3cf";

  constant csr_pmpaddr32_c      : std_ulogic_vector(11 downto 0) := x"3d0";

  constant csr_pmpaddr33_c      : std_ulogic_vector(11 downto 0) := x"3d1";

  constant csr_pmpaddr34_c      : std_ulogic_vector(11 downto 0) := x"3d2";

  constant csr_pmpaddr35_c      : std_ulogic_vector(11 downto 0) := x"3d3";

  constant csr_pmpaddr36_c      : std_ulogic_vector(11 downto 0) := x"3d4";

  constant csr_pmpaddr37_c      : std_ulogic_vector(11 downto 0) := x"3d5";

  constant csr_pmpaddr38_c      : std_ulogic_vector(11 downto 0) := x"3d6";

  constant csr_pmpaddr39_c      : std_ulogic_vector(11 downto 0) := x"3d7";

  constant csr_pmpaddr40_c      : std_ulogic_vector(11 downto 0) := x"3d8";

  constant csr_pmpaddr41_c      : std_ulogic_vector(11 downto 0) := x"3d9";

  constant csr_pmpaddr42_c      : std_ulogic_vector(11 downto 0) := x"3da";

  constant csr_pmpaddr43_c      : std_ulogic_vector(11 downto 0) := x"3db";

  constant csr_pmpaddr44_c      : std_ulogic_vector(11 downto 0) := x"3dc";

  constant csr_pmpaddr45_c      : std_ulogic_vector(11 downto 0) := x"3dd";

  constant csr_pmpaddr46_c      : std_ulogic_vector(11 downto 0) := x"3de";

  constant csr_pmpaddr47_c      : std_ulogic_vector(11 downto 0) := x"3df";

  constant csr_pmpaddr48_c      : std_ulogic_vector(11 downto 0) := x"3e0";