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1 2 zero_gravi 
-- #################################################################################################
2 
-- # << NEORV32 - Main VHDL package file >>                                                        #
3 
-- # ********************************************************************************************* #
4 
-- # BSD 3-Clause License                                                                          #
5 
-- #                                                                                               #
6 42 zero_gravi 
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
7 2 zero_gravi 
-- #                                                                                               #
8 
-- # Redistribution and use in source and binary forms, with or without modification, are          #
9 
-- # permitted provided that the following conditions are met:                                     #
10 
-- #                                                                                               #
11 
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
12 
-- #    conditions and the following disclaimer.                                                   #
13 
-- #                                                                                               #
14 
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
15 
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
16 
-- #    provided with the distribution.                                                            #
17 
-- #                                                                                               #
18 
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
19 
-- #    endorse or promote products derived from this software without specific prior written      #
20 
-- #    permission.                                                                                #
21 
-- #                                                                                               #
22 
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
23 
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
24 
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
25 
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
26 
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
27 
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
28 
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
29 
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
30 
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
31 
-- # ********************************************************************************************* #
32 
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
33 
-- #################################################################################################
34 
 
35 
library ieee;
36 
use ieee.std_logic_1164.all;
37 
use ieee.numeric_std.all;
38 
 
39 
package neorv32_package is
40 
 
41 36 zero_gravi 
  -- Architecture Configuration -------------------------------------------------------------
42 
  -- -------------------------------------------------------------------------------------------
43 40 zero_gravi 
  -- address space --
44 
  constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
45 
  constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
46 36 zero_gravi 
 
47 40 zero_gravi 
  -- (external) bus interface --
48 41 zero_gravi 
  constant bus_timeout_c     : natural := 127; -- cycles after which an *unacknowledged* bus access will timeout and trigger a bus fault exception (min 2)
49 40 zero_gravi 
  constant wb_pipe_mode_c    : boolean := false; -- *external* bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode
50 
  constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian
51 
 
52 
  -- CPU core --
53 41 zero_gravi 
  constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
54 40 zero_gravi 
 
55 
  -- Architecture Constants (do not modify!)= -----------------------------------------------
56 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
57 40 zero_gravi 
  constant data_width_c   : natural := 32; -- data width - do not change!
58 45 zero_gravi 
  constant hw_version_c   : std_ulogic_vector(31 downto 0) := x"01050003"; -- no touchy!
59 40 zero_gravi 
  constant pmp_max_r_c    : natural := 8; -- max PMP regions - FIXED!
60 
  constant archid_c       : natural := 19; -- official NEORV32 architecture ID - hands off!
61 42 zero_gravi 
  constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
62 27 zero_gravi 
 
63 12 zero_gravi 
  -- Helper Functions -----------------------------------------------------------------------
64 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
65 
  function index_size_f(input : natural) return natural;
66 
  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
67 
  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
68 
  function bool_to_ulogic_f(cond : boolean) return std_ulogic;
69 15 zero_gravi 
  function or_all_f(a : std_ulogic_vector) return std_ulogic;
70 
  function and_all_f(a : std_ulogic_vector) return std_ulogic;
71 
  function xor_all_f(a : std_ulogic_vector) return std_ulogic;
72 2 zero_gravi 
  function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
73 6 zero_gravi 
  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
74 40 zero_gravi 
  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector;
75 32 zero_gravi 
  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector;
76 36 zero_gravi 
  function is_power_of_two_f(input : natural) return boolean;
77 40 zero_gravi 
  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;
78 2 zero_gravi 
 
79 15 zero_gravi 
  -- Internal Types -------------------------------------------------------------------------
80 
  -- -------------------------------------------------------------------------------------------
81 42 zero_gravi 
  type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);
82 
  type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0);
83 15 zero_gravi 
 
84 23 zero_gravi 
  -- Processor-Internal Address Space Layout ------------------------------------------------
85 
  -- -------------------------------------------------------------------------------------------
86 34 zero_gravi 
  -- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
87 39 zero_gravi 
  constant imem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
88 
  constant dmem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
89 42 zero_gravi 
  --> internal data/instruction memory sizes are configured via top's generics
90 2 zero_gravi 
 
91 23 zero_gravi 
  -- Internal Bootloader ROM --
92 
  constant boot_rom_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!
93 
  constant boot_rom_size_c      : natural := 4*1024; -- bytes
94 
  constant boot_rom_max_size_c  : natural := 32*1024; -- bytes, fixed!
95 
 
96 2 zero_gravi 
  -- IO: Peripheral Devices ("IO") Area --
97 
  -- Control register(s) (including the device-enable) should be located at the base address of each device
98 
  constant io_base_c            : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80";
99 
  constant io_size_c            : natural := 32*4; -- bytes, fixed!
100 
 
101 
  -- General Purpose Input/Output Unit (GPIO) --
102 
  constant gpio_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address, fixed!
103 23 zero_gravi 
  constant gpio_size_c          : natural := 2*4; -- bytes
104 
  constant gpio_in_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80";
105 
  constant gpio_out_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF84";
106 2 zero_gravi 
 
107 30 zero_gravi 
  -- True Random Number Generator (TRNG) --
108 
  constant trng_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address, fixed!
109 
  constant trng_size_c          : natural := 1*4; -- bytes
110 
  constant trng_ctrl_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88";
111 2 zero_gravi 
 
112 
  -- Watch Dog Timer (WDT) --
113 
  constant wdt_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address, fixed!
114 23 zero_gravi 
  constant wdt_size_c           : natural := 1*4; -- bytes
115 
  constant wdt_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C";
116 2 zero_gravi 
 
117 
  -- Machine System Timer (MTIME) --
118 
  constant mtime_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90"; -- base address, fixed!
119 23 zero_gravi 
  constant mtime_size_c         : natural := 4*4; -- bytes
120 
  constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90";
121 
  constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF94";
122 
  constant mtime_cmp_lo_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF98";
123 
  constant mtime_cmp_hi_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF9C";
124 2 zero_gravi 
 
125 
  -- Universal Asynchronous Receiver/Transmitter (UART) --
126 
  constant uart_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address, fixed!
127 23 zero_gravi 
  constant uart_size_c          : natural := 2*4; -- bytes
128 
  constant uart_ctrl_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0";
129 
  constant uart_rtx_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA4";
130 2 zero_gravi 
 
131 
  -- Serial Peripheral Interface (SPI) --
132 
  constant spi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address, fixed!
133 23 zero_gravi 
  constant spi_size_c           : natural := 2*4; -- bytes
134 
  constant spi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8";
135 
  constant spi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFAC";
136 2 zero_gravi 
 
137 
  -- Two Wire Interface (TWI) --
138 
  constant twi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0"; -- base address, fixed!
139 23 zero_gravi 
  constant twi_size_c           : natural := 2*4; -- bytes
140 
  constant twi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0";
141 
  constant twi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB4";
142 2 zero_gravi 
 
143 
  -- Pulse-Width Modulation Controller (PWM) --
144 
  constant pwm_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address, fixed!
145 23 zero_gravi 
  constant pwm_size_c           : natural := 2*4; -- bytes
146 
  constant pwm_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8";
147 
  constant pwm_duty_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFBC";
148 2 zero_gravi 
 
149 34 zero_gravi 
  -- Custom Functions Unit 0 (CFU0) --
150 
  constant cfu0_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address, fixed!
151 
  constant cfu0_size_c          : natural := 4*4; -- bytes
152 
  constant cfu0_reg0_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0";
153 
  constant cfu0_reg1_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC4";
154 
  constant cfu0_reg2_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8";
155 
  constant cfu0_reg3_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC";
156 12 zero_gravi 
 
157 34 zero_gravi 
  -- Custom Functions Unit 1 (CFU1) --
158 
  constant cfu1_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address, fixed!
159 
  constant cfu1_size_c          : natural := 4*4; -- bytes
160 
  constant cfu1_reg0_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0";
161 
  constant cfu1_reg1_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD4";
162 
  constant cfu1_reg2_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD8";
163 
  constant cfu1_reg3_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFDC";
164 23 zero_gravi 
 
165 
  -- System Information Memory (SYSINFO) --
166 12 zero_gravi 
  constant sysinfo_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address, fixed!
167 23 zero_gravi 
  constant sysinfo_size_c       : natural := 8*4; -- bytes
168 12 zero_gravi 
 
169 2 zero_gravi 
  -- Main Control Bus -----------------------------------------------------------------------
170 
  -- -------------------------------------------------------------------------------------------
171 
  -- register file --
172 39 zero_gravi 
  constant ctrl_rf_in_mux_lsb_c : natural :=  0; -- input source select lsb (10=MEM, 11=CSR)
173 
  constant ctrl_rf_in_mux_msb_c : natural :=  1; -- input source select msb (0-=ALU)
174 36 zero_gravi 
  constant ctrl_rf_rs1_adr0_c   : natural :=  2; -- source register 1 address bit 0
175 
  constant ctrl_rf_rs1_adr1_c   : natural :=  3; -- source register 1 address bit 1
176 
  constant ctrl_rf_rs1_adr2_c   : natural :=  4; -- source register 1 address bit 2
177 
  constant ctrl_rf_rs1_adr3_c   : natural :=  5; -- source register 1 address bit 3
178 
  constant ctrl_rf_rs1_adr4_c   : natural :=  6; -- source register 1 address bit 4
179 
  constant ctrl_rf_rs2_adr0_c   : natural :=  7; -- source register 2 address bit 0
180 
  constant ctrl_rf_rs2_adr1_c   : natural :=  8; -- source register 2 address bit 1
181 
  constant ctrl_rf_rs2_adr2_c   : natural :=  9; -- source register 2 address bit 2
182 
  constant ctrl_rf_rs2_adr3_c   : natural := 10; -- source register 2 address bit 3
183 
  constant ctrl_rf_rs2_adr4_c   : natural := 11; -- source register 2 address bit 4
184 
  constant ctrl_rf_rd_adr0_c    : natural := 12; -- destiantion register address bit 0
185 
  constant ctrl_rf_rd_adr1_c    : natural := 13; -- destiantion register address bit 1
186 
  constant ctrl_rf_rd_adr2_c    : natural := 14; -- destiantion register address bit 2
187 
  constant ctrl_rf_rd_adr3_c    : natural := 15; -- destiantion register address bit 3
188 
  constant ctrl_rf_rd_adr4_c    : natural := 16; -- destiantion register address bit 4
189 
  constant ctrl_rf_wb_en_c      : natural := 17; -- write back enable
190 
  constant ctrl_rf_r0_we_c      : natural := 18; -- force write access and force rd=r0
191 2 zero_gravi 
  -- alu --
192 39 zero_gravi 
  constant ctrl_alu_arith_c     : natural := 19; -- ALU arithmetic command
193 
  constant ctrl_alu_logic0_c    : natural := 20; -- ALU logic command bit 0
194 
  constant ctrl_alu_logic1_c    : natural := 21; -- ALU logic command bit 1
195 
  constant ctrl_alu_func0_c     : natural := 22; -- ALU function select command bit 0
196 
  constant ctrl_alu_func1_c     : natural := 23; -- ALU function select command bit 1
197 
  constant ctrl_alu_addsub_c    : natural := 24; -- 0=ADD, 1=SUB
198 
  constant ctrl_alu_opa_mux_c   : natural := 25; -- operand A select (0=rs1, 1=PC)
199 
  constant ctrl_alu_opb_mux_c   : natural := 26; -- operand B select (0=rs2, 1=IMM)
200 
  constant ctrl_alu_unsigned_c  : natural := 27; -- is unsigned ALU operation
201 
  constant ctrl_alu_shift_dir_c : natural := 28; -- shift direction (0=left, 1=right)
202 
  constant ctrl_alu_shift_ar_c  : natural := 29; -- is arithmetic shift
203 2 zero_gravi 
  -- bus interface --
204 39 zero_gravi 
  constant ctrl_bus_size_lsb_c  : natural := 30; -- transfer size lsb (00=byte, 01=half-word)
205 
  constant ctrl_bus_size_msb_c  : natural := 31; -- transfer size msb (10=word, 11=?)
206 
  constant ctrl_bus_rd_c        : natural := 32; -- read data request
207 
  constant ctrl_bus_wr_c        : natural := 33; -- write data request
208 
  constant ctrl_bus_if_c        : natural := 34; -- instruction fetch request
209 
  constant ctrl_bus_mo_we_c     : natural := 35; -- memory address and data output register write enable
210 
  constant ctrl_bus_mi_we_c     : natural := 36; -- memory data input register write enable
211 
  constant ctrl_bus_unsigned_c  : natural := 37; -- is unsigned load
212 
  constant ctrl_bus_ierr_ack_c  : natural := 38; -- acknowledge instruction fetch bus exceptions
213 
  constant ctrl_bus_derr_ack_c  : natural := 39; -- acknowledge data access bus exceptions
214 
  constant ctrl_bus_fence_c     : natural := 40; -- executed fence operation
215 
  constant ctrl_bus_fencei_c    : natural := 41; -- executed fencei operation
216 
  constant ctrl_bus_lock_c      : natural := 42; -- locked/exclusive bus access
217 26 zero_gravi 
  -- co-processors --
218 39 zero_gravi 
  constant ctrl_cp_id_lsb_c     : natural := 43; -- cp select ID lsb
219 
  constant ctrl_cp_id_msb_c     : natural := 44; -- cp select ID msb
220 36 zero_gravi 
  -- current privilege level --
221 39 zero_gravi 
  constant ctrl_priv_lvl_lsb_c  : natural := 45; -- privilege level lsb
222 
  constant ctrl_priv_lvl_msb_c  : natural := 46; -- privilege level msb
223 44 zero_gravi 
  -- instruction's control blocks (used by cpu co-processors) --
224 39 zero_gravi 
  constant ctrl_ir_funct3_0_c   : natural := 47; -- funct3 bit 0
225 
  constant ctrl_ir_funct3_1_c   : natural := 48; -- funct3 bit 1
226 
  constant ctrl_ir_funct3_2_c   : natural := 49; -- funct3 bit 2
227 
  constant ctrl_ir_funct12_0_c  : natural := 50; -- funct12 bit 0
228 
  constant ctrl_ir_funct12_1_c  : natural := 51; -- funct12 bit 1
229 
  constant ctrl_ir_funct12_2_c  : natural := 52; -- funct12 bit 2
230 
  constant ctrl_ir_funct12_3_c  : natural := 53; -- funct12 bit 3
231 
  constant ctrl_ir_funct12_4_c  : natural := 54; -- funct12 bit 4
232 
  constant ctrl_ir_funct12_5_c  : natural := 55; -- funct12 bit 5
233 
  constant ctrl_ir_funct12_6_c  : natural := 56; -- funct12 bit 6
234 
  constant ctrl_ir_funct12_7_c  : natural := 57; -- funct12 bit 7
235 
  constant ctrl_ir_funct12_8_c  : natural := 58; -- funct12 bit 8
236 
  constant ctrl_ir_funct12_9_c  : natural := 59; -- funct12 bit 9
237 
  constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10
238 
  constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11
239 44 zero_gravi 
  constant ctrl_ir_opcode7_0_c  : natural := 62; -- opcode7 bit 0
240 
  constant ctrl_ir_opcode7_1_c  : natural := 63; -- opcode7 bit 1
241 
  constant ctrl_ir_opcode7_2_c  : natural := 64; -- opcode7 bit 2
242 
  constant ctrl_ir_opcode7_3_c  : natural := 65; -- opcode7 bit 3
243 
  constant ctrl_ir_opcode7_4_c  : natural := 66; -- opcode7 bit 4
244 
  constant ctrl_ir_opcode7_5_c  : natural := 67; -- opcode7 bit 5
245 
  constant ctrl_ir_opcode7_6_c  : natural := 68; -- opcode7 bit 6
246 2 zero_gravi 
  -- control bus size --
247 44 zero_gravi 
  constant ctrl_width_c         : natural := 69; -- control bus size
248 2 zero_gravi 
 
249 
  -- ALU Comparator Bus ---------------------------------------------------------------------
250 
  -- -------------------------------------------------------------------------------------------
251 
  constant alu_cmp_equal_c : natural := 0;
252 6 zero_gravi 
  constant alu_cmp_less_c  : natural := 1; -- for signed and unsigned comparisons
253 2 zero_gravi 
 
254 
  -- RISC-V Opcode Layout -------------------------------------------------------------------
255 
  -- -------------------------------------------------------------------------------------------
256 
  constant instr_opcode_lsb_c  : natural :=  0; -- opcode bit 0
257 
  constant instr_opcode_msb_c  : natural :=  6; -- opcode bit 6
258 
  constant instr_rd_lsb_c      : natural :=  7; -- destination register address bit 0
259 
  constant instr_rd_msb_c      : natural := 11; -- destination register address bit 4
260 
  constant instr_funct3_lsb_c  : natural := 12; -- funct3 bit 0
261 
  constant instr_funct3_msb_c  : natural := 14; -- funct3 bit 2
262 
  constant instr_rs1_lsb_c     : natural := 15; -- source register 1 address bit 0
263 
  constant instr_rs1_msb_c     : natural := 19; -- source register 1 address bit 4
264 
  constant instr_rs2_lsb_c     : natural := 20; -- source register 2 address bit 0
265 
  constant instr_rs2_msb_c     : natural := 24; -- source register 2 address bit 4
266 
  constant instr_funct7_lsb_c  : natural := 25; -- funct7 bit 0
267 
  constant instr_funct7_msb_c  : natural := 31; -- funct7 bit 6
268 
  constant instr_funct12_lsb_c : natural := 20; -- funct12 bit 0
269 
  constant instr_funct12_msb_c : natural := 31; -- funct12 bit 11
270 
  constant instr_imm12_lsb_c   : natural := 20; -- immediate12 bit 0
271 
  constant instr_imm12_msb_c   : natural := 31; -- immediate12 bit 11
272 
  constant instr_imm20_lsb_c   : natural := 12; -- immediate20 bit 0
273 
  constant instr_imm20_msb_c   : natural := 31; -- immediate20 bit 21
274 
  constant instr_csr_id_lsb_c  : natural := 20; -- csr select bit 0
275 
  constant instr_csr_id_msb_c  : natural := 31; -- csr select bit 11
276 39 zero_gravi 
  constant instr_funct5_lsb_c  : natural := 27; -- funct5 select bit 0
277 
  constant instr_funct5_msb_c  : natural := 31; -- funct5 select bit 4
278 2 zero_gravi 
 
279 
  -- RISC-V Opcodes -------------------------------------------------------------------------
280 
  -- -------------------------------------------------------------------------------------------
281 
  -- alu --
282 
  constant opcode_lui_c    : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate
283 
  constant opcode_auipc_c  : std_ulogic_vector(6 downto 0) := "0010111"; -- add upper immediate to PC
284 
  constant opcode_alui_c   : std_ulogic_vector(6 downto 0) := "0010011"; -- ALU operation with immediate (operation via funct3 and funct7)
285 
  constant opcode_alu_c    : std_ulogic_vector(6 downto 0) := "0110011"; -- ALU operation (operation via funct3 and funct7)
286 
  -- control flow --
287 
  constant opcode_jal_c    : std_ulogic_vector(6 downto 0) := "1101111"; -- jump and link
288 29 zero_gravi 
  constant opcode_jalr_c   : std_ulogic_vector(6 downto 0) := "1100111"; -- jump and link with register
289 2 zero_gravi 
  constant opcode_branch_c : std_ulogic_vector(6 downto 0) := "1100011"; -- branch (condition set via funct3)
290 
  -- memory access --
291 
  constant opcode_load_c   : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)
292 
  constant opcode_store_c  : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)
293 
  -- system/csr --
294 8 zero_gravi 
  constant opcode_fence_c  : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
295 2 zero_gravi 
  constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
296 39 zero_gravi 
  -- atomic operations (A) --
297 
  constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)
298 2 zero_gravi 
 
299 
  -- RISC-V Funct3 --------------------------------------------------------------------------
300 
  -- -------------------------------------------------------------------------------------------
301 
  -- control flow --
302 
  constant funct3_beq_c    : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
303 
  constant funct3_bne_c    : std_ulogic_vector(2 downto 0) := "001"; -- branch if not equal
304 
  constant funct3_blt_c    : std_ulogic_vector(2 downto 0) := "100"; -- branch if less than
305 
  constant funct3_bge_c    : std_ulogic_vector(2 downto 0) := "101"; -- branch if greater than or equal
306 
  constant funct3_bltu_c   : std_ulogic_vector(2 downto 0) := "110"; -- branch if less than (unsigned)
307 
  constant funct3_bgeu_c   : std_ulogic_vector(2 downto 0) := "111"; -- branch if greater than or equal (unsigned)
308 
  -- memory access --
309 
  constant funct3_lb_c     : std_ulogic_vector(2 downto 0) := "000"; -- load byte
310 
  constant funct3_lh_c     : std_ulogic_vector(2 downto 0) := "001"; -- load half word
311 
  constant funct3_lw_c     : std_ulogic_vector(2 downto 0) := "010"; -- load word
312 
  constant funct3_lbu_c    : std_ulogic_vector(2 downto 0) := "100"; -- load byte (unsigned)
313 
  constant funct3_lhu_c    : std_ulogic_vector(2 downto 0) := "101"; -- load half word (unsigned)
314 
  constant funct3_sb_c     : std_ulogic_vector(2 downto 0) := "000"; -- store byte
315 
  constant funct3_sh_c     : std_ulogic_vector(2 downto 0) := "001"; -- store half word
316 
  constant funct3_sw_c     : std_ulogic_vector(2 downto 0) := "010"; -- store word
317 
  -- alu --
318 
  constant funct3_subadd_c : std_ulogic_vector(2 downto 0) := "000"; -- sub/add via funct7
319 
  constant funct3_sll_c    : std_ulogic_vector(2 downto 0) := "001"; -- shift logical left
320 
  constant funct3_slt_c    : std_ulogic_vector(2 downto 0) := "010"; -- set on less
321 
  constant funct3_sltu_c   : std_ulogic_vector(2 downto 0) := "011"; -- set on less unsigned
322 
  constant funct3_xor_c    : std_ulogic_vector(2 downto 0) := "100"; -- xor
323 
  constant funct3_sr_c     : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7
324 
  constant funct3_or_c     : std_ulogic_vector(2 downto 0) := "110"; -- or
325 
  constant funct3_and_c    : std_ulogic_vector(2 downto 0) := "111"; -- and
326 
  -- system/csr --
327 
  constant funct3_env_c    : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi
328 
  constant funct3_csrrw_c  : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w
329 
  constant funct3_csrrs_c  : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit
330 
  constant funct3_csrrc_c  : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit
331 
  constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate
332 
  constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate
333 
  constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
334 8 zero_gravi 
  -- fence --
335 
  constant funct3_fence_c  : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
336 
  constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync
337 2 zero_gravi 
 
338 39 zero_gravi 
  -- RISC-V Funct12 -------------------------------------------------------------------------
339 11 zero_gravi 
  -- -------------------------------------------------------------------------------------------
340 
  -- system --
341 
  constant funct12_ecall_c  : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
342 
  constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
343 
  constant funct12_mret_c   : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
344 
  constant funct12_wfi_c    : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
345 
 
346 39 zero_gravi 
  -- RISC-V Funct5 --------------------------------------------------------------------------
347 
  -- -------------------------------------------------------------------------------------------
348 
  -- atomic operations --
349 
  constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR
350 
  constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC
351 
 
352 29 zero_gravi 
  -- RISC-V CSR Addresses -------------------------------------------------------------------
353 
  -- -------------------------------------------------------------------------------------------
354 41 zero_gravi 
  -- read/write CSRs --
355 42 zero_gravi 
  constant csr_mstatus_c        : std_ulogic_vector(11 downto 0) := x"300";
356 
  constant csr_misa_c           : std_ulogic_vector(11 downto 0) := x"301";
357 
  constant csr_mie_c            : std_ulogic_vector(11 downto 0) := x"304";
358 
  constant csr_mtvec_c          : std_ulogic_vector(11 downto 0) := x"305";
359 
  constant csr_mcounteren_c     : std_ulogic_vector(11 downto 0) := x"306";
360 
  constant csr_mstatush_c       : std_ulogic_vector(11 downto 0) := x"310";
361 29 zero_gravi 
  --
362 42 zero_gravi 
  constant csr_mcountinhibit_c  : std_ulogic_vector(11 downto 0) := x"320";
363 29 zero_gravi 
  --
364 42 zero_gravi 
  constant csr_mhpmevent3_c     : std_ulogic_vector(11 downto 0) := x"323";
365 
  constant csr_mhpmevent4_c     : std_ulogic_vector(11 downto 0) := x"324";
366 
  constant csr_mhpmevent5_c     : std_ulogic_vector(11 downto 0) := x"325";
367 
  constant csr_mhpmevent6_c     : std_ulogic_vector(11 downto 0) := x"326";
368 
  constant csr_mhpmevent7_c     : std_ulogic_vector(11 downto 0) := x"327";
369 
  constant csr_mhpmevent8_c     : std_ulogic_vector(11 downto 0) := x"328";
370 
  constant csr_mhpmevent9_c     : std_ulogic_vector(11 downto 0) := x"329";
371 
  constant csr_mhpmevent10_c    : std_ulogic_vector(11 downto 0) := x"32a";
372 
  constant csr_mhpmevent11_c    : std_ulogic_vector(11 downto 0) := x"32b";
373 
  constant csr_mhpmevent12_c    : std_ulogic_vector(11 downto 0) := x"32c";
374 
  constant csr_mhpmevent13_c    : std_ulogic_vector(11 downto 0) := x"32d";
375 
  constant csr_mhpmevent14_c    : std_ulogic_vector(11 downto 0) := x"32e";
376 
  constant csr_mhpmevent15_c    : std_ulogic_vector(11 downto 0) := x"32f";
377 
  constant csr_mhpmevent16_c    : std_ulogic_vector(11 downto 0) := x"330";
378 
  constant csr_mhpmevent17_c    : std_ulogic_vector(11 downto 0) := x"331";
379 
  constant csr_mhpmevent18_c    : std_ulogic_vector(11 downto 0) := x"332";
380 
  constant csr_mhpmevent19_c    : std_ulogic_vector(11 downto 0) := x"333";
381 
  constant csr_mhpmevent20_c    : std_ulogic_vector(11 downto 0) := x"334";
382 
  constant csr_mhpmevent21_c    : std_ulogic_vector(11 downto 0) := x"335";
383 
  constant csr_mhpmevent22_c    : std_ulogic_vector(11 downto 0) := x"336";
384 
  constant csr_mhpmevent23_c    : std_ulogic_vector(11 downto 0) := x"337";
385 
  constant csr_mhpmevent24_c    : std_ulogic_vector(11 downto 0) := x"338";
386 
  constant csr_mhpmevent25_c    : std_ulogic_vector(11 downto 0) := x"339";
387 
  constant csr_mhpmevent26_c    : std_ulogic_vector(11 downto 0) := x"33a";
388 
  constant csr_mhpmevent27_c    : std_ulogic_vector(11 downto 0) := x"33b";
389 
  constant csr_mhpmevent28_c    : std_ulogic_vector(11 downto 0) := x"33c";
390 
  constant csr_mhpmevent29_c    : std_ulogic_vector(11 downto 0) := x"33d";
391 
  constant csr_mhpmevent30_c    : std_ulogic_vector(11 downto 0) := x"33e";
392 
  constant csr_mhpmevent31_c    : std_ulogic_vector(11 downto 0) := x"33f";
393 29 zero_gravi 
  --
394 42 zero_gravi 
  constant csr_mscratch_c       : std_ulogic_vector(11 downto 0) := x"340";
395 
  constant csr_mepc_c           : std_ulogic_vector(11 downto 0) := x"341";
396 
  constant csr_mcause_c         : std_ulogic_vector(11 downto 0) := x"342";
397 
  constant csr_mtval_c          : std_ulogic_vector(11 downto 0) := x"343";
398 
  constant csr_mip_c            : std_ulogic_vector(11 downto 0) := x"344";
399 29 zero_gravi 
  --
400 42 zero_gravi 
  constant csr_pmpcfg0_c        : std_ulogic_vector(11 downto 0) := x"3a0";
401 
  constant csr_pmpcfg1_c        : std_ulogic_vector(11 downto 0) := x"3a1";
402 
  constant csr_pmpcfg2_c        : std_ulogic_vector(11 downto 0) := x"3a2";
403 
  constant csr_pmpcfg3_c        : std_ulogic_vector(11 downto 0) := x"3a3";
404 
  constant csr_pmpcfg4_c        : std_ulogic_vector(11 downto 0) := x"3a4";
405 
  constant csr_pmpcfg5_c        : std_ulogic_vector(11 downto 0) := x"3a5";
406 
  constant csr_pmpcfg6_c        : std_ulogic_vector(11 downto 0) := x"3a6";
407 
  constant csr_pmpcfg7_c        : std_ulogic_vector(11 downto 0) := x"3a7";
408 
  constant csr_pmpcfg8_c        : std_ulogic_vector(11 downto 0) := x"3a8";
409 
  constant csr_pmpcfg9_c        : std_ulogic_vector(11 downto 0) := x"3a9";
410 
  constant csr_pmpcfg10_c       : std_ulogic_vector(11 downto 0) := x"3aa";
411 
  constant csr_pmpcfg11_c       : std_ulogic_vector(11 downto 0) := x"3ab";
412 
  constant csr_pmpcfg12_c       : std_ulogic_vector(11 downto 0) := x"3ac";
413 
  constant csr_pmpcfg13_c       : std_ulogic_vector(11 downto 0) := x"3ad";
414 
  constant csr_pmpcfg14_c       : std_ulogic_vector(11 downto 0) := x"3ae";
415 
  constant csr_pmpcfg15_c       : std_ulogic_vector(11 downto 0) := x"3af";
416 29 zero_gravi 
  --
417 42 zero_gravi 
  constant csr_pmpaddr0_c       : std_ulogic_vector(11 downto 0) := x"3b0";
418 
  constant csr_pmpaddr1_c       : std_ulogic_vector(11 downto 0) := x"3b1";
419 
  constant csr_pmpaddr2_c       : std_ulogic_vector(11 downto 0) := x"3b2";
420 
  constant csr_pmpaddr3_c       : std_ulogic_vector(11 downto 0) := x"3b3";
421 
  constant csr_pmpaddr4_c       : std_ulogic_vector(11 downto 0) := x"3b4";
422 
  constant csr_pmpaddr5_c       : std_ulogic_vector(11 downto 0) := x"3b5";
423 
  constant csr_pmpaddr6_c       : std_ulogic_vector(11 downto 0) := x"3b6";
424 
  constant csr_pmpaddr7_c       : std_ulogic_vector(11 downto 0) := x"3b7";
425 
  constant csr_pmpaddr8_c       : std_ulogic_vector(11 downto 0) := x"3b8";
426 
  constant csr_pmpaddr9_c       : std_ulogic_vector(11 downto 0) := x"3b9";
427 
  constant csr_pmpaddr10_c      : std_ulogic_vector(11 downto 0) := x"3ba";
428 
  constant csr_pmpaddr11_c      : std_ulogic_vector(11 downto 0) := x"3bb";
429 
  constant csr_pmpaddr12_c      : std_ulogic_vector(11 downto 0) := x"3bc";
430 
  constant csr_pmpaddr13_c      : std_ulogic_vector(11 downto 0) := x"3bd";
431 
  constant csr_pmpaddr14_c      : std_ulogic_vector(11 downto 0) := x"3be";
432 
  constant csr_pmpaddr15_c      : std_ulogic_vector(11 downto 0) := x"3bf";
433 
  constant csr_pmpaddr16_c      : std_ulogic_vector(11 downto 0) := x"3c0";
434 
  constant csr_pmpaddr17_c      : std_ulogic_vector(11 downto 0) := x"3c1";
435 
  constant csr_pmpaddr18_c      : std_ulogic_vector(11 downto 0) := x"3c2";
436 
  constant csr_pmpaddr19_c      : std_ulogic_vector(11 downto 0) := x"3c3";
437 
  constant csr_pmpaddr20_c      : std_ulogic_vector(11 downto 0) := x"3c4";
438 
  constant csr_pmpaddr21_c      : std_ulogic_vector(11 downto 0) := x"3c5";
439 
  constant csr_pmpaddr22_c      : std_ulogic_vector(11 downto 0) := x"3c6";
440 
  constant csr_pmpaddr23_c      : std_ulogic_vector(11 downto 0) := x"3c7";
441 
  constant csr_pmpaddr24_c      : std_ulogic_vector(11 downto 0) := x"3c8";
442 
  constant csr_pmpaddr25_c      : std_ulogic_vector(11 downto 0) := x"3c9";
443 
  constant csr_pmpaddr26_c      : std_ulogic_vector(11 downto 0) := x"3ca";
444 
  constant csr_pmpaddr27_c      : std_ulogic_vector(11 downto 0) := x"3cb";
445 
  constant csr_pmpaddr28_c      : std_ulogic_vector(11 downto 0) := x"3cc";
446 
  constant csr_pmpaddr29_c      : std_ulogic_vector(11 downto 0) := x"3cd";
447 
  constant csr_pmpaddr30_c      : std_ulogic_vector(11 downto 0) := x"3ce";
448 
  constant csr_pmpaddr31_c      : std_ulogic_vector(11 downto 0) := x"3cf";
449 
  constant csr_pmpaddr32_c      : std_ulogic_vector(11 downto 0) := x"3d0";
450 
  constant csr_pmpaddr33_c      : std_ulogic_vector(11 downto 0) := x"3d1";
451 
  constant csr_pmpaddr34_c      : std_ulogic_vector(11 downto 0) := x"3d2";
452 
  constant csr_pmpaddr35_c      : std_ulogic_vector(11 downto 0) := x"3d3";
453 
  constant csr_pmpaddr36_c      : std_ulogic_vector(11 downto 0) := x"3d4";
454 
  constant csr_pmpaddr37_c      : std_ulogic_vector(11 downto 0) := x"3d5";
455 
  constant csr_pmpaddr38_c      : std_ulogic_vector(11 downto 0) := x"3d6";
456 
  constant csr_pmpaddr39_c      : std_ulogic_vector(11 downto 0) := x"3d7";
457 
  constant csr_pmpaddr40_c      : std_ulogic_vector(11 downto 0) := x"3d8";
458 
  constant csr_pmpaddr41_c      : std_ulogic_vector(11 downto 0) := x"3d9";
459 
  constant csr_pmpaddr42_c      : std_ulogic_vector(11 downto 0) := x"3da";
460 
  constant csr_pmpaddr43_c      : std_ulogic_vector(11 downto 0) := x"3db";
461 
  constant csr_pmpaddr44_c      : std_ulogic_vector(11 downto 0) := x"3dc";
462 
  constant csr_pmpaddr45_c      : std_ulogic_vector(11 downto 0) := x"3dd";
463 
  constant csr_pmpaddr46_c      : std_ulogic_vector(11 downto 0) := x"3de";
464 
  constant csr_pmpaddr47_c      : std_ulogic_vector(11 downto 0) := x"3df";
465 
  constant csr_pmpaddr48_c      : std_ulogic_vector(11 downto 0) := x"3e0";
466 
  constant csr_pmpaddr49_c      : std_ulogic_vector(11 downto 0) := x"3e1";
467 
  constant csr_pmpaddr50_c      : std_ulogic_vector(11 downto 0) := x"3e2";
468 
  constant csr_pmpaddr51_c      : std_ulogic_vector(11 downto 0) := x"3e3";
469 
  constant csr_pmpaddr52_c      : std_ulogic_vector(11 downto 0) := x"3e4";
470 
  constant csr_pmpaddr53_c      : std_ulogic_vector(11 downto 0) := x"3e5";
471 
  constant csr_pmpaddr54_c      : std_ulogic_vector(11 downto 0) := x"3e6";
472 
  constant csr_pmpaddr55_c      : std_ulogic_vector(11 downto 0) := x"3e7";
473 
  constant csr_pmpaddr56_c      : std_ulogic_vector(11 downto 0) := x"3e8";
474 
  constant csr_pmpaddr57_c      : std_ulogic_vector(11 downto 0) := x"3e9";
475 
  constant csr_pmpaddr58_c      : std_ulogic_vector(11 downto 0) := x"3ea";
476 
  constant csr_pmpaddr59_c      : std_ulogic_vector(11 downto 0) := x"3eb";
477 
  constant csr_pmpaddr60_c      : std_ulogic_vector(11 downto 0) := x"3ec";
478 
  constant csr_pmpaddr61_c      : std_ulogic_vector(11 downto 0) := x"3ed";
479 
  constant csr_pmpaddr62_c      : std_ulogic_vector(11 downto 0) := x"3ee";
480 
  constant csr_pmpaddr63_c      : std_ulogic_vector(11 downto 0) := x"3ef";
481 29 zero_gravi 
  --
482 42 zero_gravi 
  constant csr_mcycle_c         : std_ulogic_vector(11 downto 0) := x"b00";
483 
  constant csr_minstret_c       : std_ulogic_vector(11 downto 0) := x"b02";
484 
  --
485 
  constant csr_mhpmcounter3_c   : std_ulogic_vector(11 downto 0) := x"b03";
486 
  constant csr_mhpmcounter4_c   : std_ulogic_vector(11 downto 0) := x"b04";
487 
  constant csr_mhpmcounter5_c   : std_ulogic_vector(11 downto 0) := x"b05";
488 
  constant csr_mhpmcounter6_c   : std_ulogic_vector(11 downto 0) := x"b06";
489 
  constant csr_mhpmcounter7_c   : std_ulogic_vector(11 downto 0) := x"b07";
490 
  constant csr_mhpmcounter8_c   : std_ulogic_vector(11 downto 0) := x"b08";
491 
  constant csr_mhpmcounter9_c   : std_ulogic_vector(11 downto 0) := x"b09";
492 
  constant csr_mhpmcounter10_c  : std_ulogic_vector(11 downto 0) := x"b0a";
493 
  constant csr_mhpmcounter11_c  : std_ulogic_vector(11 downto 0) := x"b0b";
494 
  constant csr_mhpmcounter12_c  : std_ulogic_vector(11 downto 0) := x"b0c";
495 
  constant csr_mhpmcounter13_c  : std_ulogic_vector(11 downto 0) := x"b0d";
496 
  constant csr_mhpmcounter14_c  : std_ulogic_vector(11 downto 0) := x"b0e";
497 
  constant csr_mhpmcounter15_c  : std_ulogic_vector(11 downto 0) := x"b0f";
498 
  constant csr_mhpmcounter16_c  : std_ulogic_vector(11 downto 0) := x"b10";
499 
  constant csr_mhpmcounter17_c  : std_ulogic_vector(11 downto 0) := x"b11";
500 
  constant csr_mhpmcounter18_c  : std_ulogic_vector(11 downto 0) := x"b12";
501 
  constant csr_mhpmcounter19_c  : std_ulogic_vector(11 downto 0) := x"b13";
502 
  constant csr_mhpmcounter20_c  : std_ulogic_vector(11 downto 0) := x"b14";
503 
  constant csr_mhpmcounter21_c  : std_ulogic_vector(11 downto 0) := x"b15";
504 
  constant csr_mhpmcounter22_c  : std_ulogic_vector(11 downto 0) := x"b16";
505 
  constant csr_mhpmcounter23_c  : std_ulogic_vector(11 downto 0) := x"b17";
506 
  constant csr_mhpmcounter24_c  : std_ulogic_vector(11 downto 0) := x"b18";
507 
  constant csr_mhpmcounter25_c  : std_ulogic_vector(11 downto 0) := x"b19";
508 
  constant csr_mhpmcounter26_c  : std_ulogic_vector(11 downto 0) := x"b1a";
509 
  constant csr_mhpmcounter27_c  : std_ulogic_vector(11 downto 0) := x"b1b";
510 
  constant csr_mhpmcounter28_c  : std_ulogic_vector(11 downto 0) := x"b1c";
511 
  constant csr_mhpmcounter29_c  : std_ulogic_vector(11 downto 0) := x"b1d";
512 
  constant csr_mhpmcounter30_c  : std_ulogic_vector(11 downto 0) := x"b1e";
513 
  constant csr_mhpmcounter31_c  : std_ulogic_vector(11 downto 0) := x"b1f";
514 
  --
515 
  constant csr_mcycleh_c        : std_ulogic_vector(11 downto 0) := x"b80";
516 
  constant csr_minstreth_c      : std_ulogic_vector(11 downto 0) := x"b82";
517 
  --
518 
  constant csr_mhpmcounter3h_c  : std_ulogic_vector(11 downto 0) := x"b83";
519 
  constant csr_mhpmcounter4h_c  : std_ulogic_vector(11 downto 0) := x"b84";
520 
  constant csr_mhpmcounter5h_c  : std_ulogic_vector(11 downto 0) := x"b85";
521 
  constant csr_mhpmcounter6h_c  : std_ulogic_vector(11 downto 0) := x"b86";
522 
  constant csr_mhpmcounter7h_c  : std_ulogic_vector(11 downto 0) := x"b87";
523 
  constant csr_mhpmcounter8h_c  : std_ulogic_vector(11 downto 0) := x"b88";
524 
  constant csr_mhpmcounter9h_c  : std_ulogic_vector(11 downto 0) := x"b89";
525 
  constant csr_mhpmcounter10h_c : std_ulogic_vector(11 downto 0) := x"b8a";
526 
  constant csr_mhpmcounter11h_c : std_ulogic_vector(11 downto 0) := x"b8b";
527 
  constant csr_mhpmcounter12h_c : std_ulogic_vector(11 downto 0) := x"b8c";
528 
  constant csr_mhpmcounter13h_c : std_ulogic_vector(11 downto 0) := x"b8d";
529 
  constant csr_mhpmcounter14h_c : std_ulogic_vector(11 downto 0) := x"b8e";
530 
  constant csr_mhpmcounter15h_c : std_ulogic_vector(11 downto 0) := x"b8f";
531 
  constant csr_mhpmcounter16h_c : std_ulogic_vector(11 downto 0) := x"b90";
532 
  constant csr_mhpmcounter17h_c : std_ulogic_vector(11 downto 0) := x"b91";
533 
  constant csr_mhpmcounter18h_c : std_ulogic_vector(11 downto 0) := x"b92";
534 
  constant csr_mhpmcounter19h_c : std_ulogic_vector(11 downto 0) := x"b93";
535 
  constant csr_mhpmcounter20h_c : std_ulogic_vector(11 downto 0) := x"b94";
536 
  constant csr_mhpmcounter21h_c : std_ulogic_vector(11 downto 0) := x"b95";
537 
  constant csr_mhpmcounter22h_c : std_ulogic_vector(11 downto 0) := x"b96";
538 
  constant csr_mhpmcounter23h_c : std_ulogic_vector(11 downto 0) := x"b97";
539 
  constant csr_mhpmcounter24h_c : std_ulogic_vector(11 downto 0) := x"b98";
540 
  constant csr_mhpmcounter25h_c : std_ulogic_vector(11 downto 0) := x"b99";
541 
  constant csr_mhpmcounter26h_c : std_ulogic_vector(11 downto 0) := x"b9a";
542 
  constant csr_mhpmcounter27h_c : std_ulogic_vector(11 downto 0) := x"b9b";
543 
  constant csr_mhpmcounter28h_c : std_ulogic_vector(11 downto 0) := x"b9c";
544 
  constant csr_mhpmcounter29h_c : std_ulogic_vector(11 downto 0) := x"b9d";
545 
  constant csr_mhpmcounter30h_c : std_ulogic_vector(11 downto 0) := x"b9e";
546 
  constant csr_mhpmcounter31h_c : std_ulogic_vector(11 downto 0) := x"b9f";
547 
 
548 41 zero_gravi 
  -- read-only CSRs --
549 42 zero_gravi 
  constant csr_cycle_c          : std_ulogic_vector(11 downto 0) := x"c00";
550 
  constant csr_time_c           : std_ulogic_vector(11 downto 0) := x"c01";
551 
  constant csr_instret_c        : std_ulogic_vector(11 downto 0) := x"c02";
552 29 zero_gravi 
  --
553 42 zero_gravi 
  constant csr_hpmcounter3_c    : std_ulogic_vector(11 downto 0) := x"c03";
554 
  constant csr_hpmcounter4_c    : std_ulogic_vector(11 downto 0) := x"c04";
555 
  constant csr_hpmcounter5_c    : std_ulogic_vector(11 downto 0) := x"c05";
556 
  constant csr_hpmcounter6_c    : std_ulogic_vector(11 downto 0) := x"c06";
557 
  constant csr_hpmcounter7_c    : std_ulogic_vector(11 downto 0) := x"c07";
558 
  constant csr_hpmcounter8_c    : std_ulogic_vector(11 downto 0) := x"c08";
559 
  constant csr_hpmcounter9_c    : std_ulogic_vector(11 downto 0) := x"c09";
560 
  constant csr_hpmcounter10_c   : std_ulogic_vector(11 downto 0) := x"c0a";
561 
  constant csr_hpmcounter11_c   : std_ulogic_vector(11 downto 0) := x"c0b";
562 
  constant csr_hpmcounter12_c   : std_ulogic_vector(11 downto 0) := x"c0c";
563 
  constant csr_hpmcounter13_c   : std_ulogic_vector(11 downto 0) := x"c0d";
564 
  constant csr_hpmcounter14_c   : std_ulogic_vector(11 downto 0) := x"c0e";
565 
  constant csr_hpmcounter15_c   : std_ulogic_vector(11 downto 0) := x"c0f";
566 
  constant csr_hpmcounter16_c   : std_ulogic_vector(11 downto 0) := x"c10";
567 
  constant csr_hpmcounter17_c   : std_ulogic_vector(11 downto 0) := x"c11";
568 
  constant csr_hpmcounter18_c   : std_ulogic_vector(11 downto 0) := x"c12";
569 
  constant csr_hpmcounter19_c   : std_ulogic_vector(11 downto 0) := x"c13";
570 
  constant csr_hpmcounter20_c   : std_ulogic_vector(11 downto 0) := x"c14";
571 
  constant csr_hpmcounter21_c   : std_ulogic_vector(11 downto 0) := x"c15";
572 
  constant csr_hpmcounter22_c   : std_ulogic_vector(11 downto 0) := x"c16";
573 
  constant csr_hpmcounter23_c   : std_ulogic_vector(11 downto 0) := x"c17";
574 
  constant csr_hpmcounter24_c   : std_ulogic_vector(11 downto 0) := x"c18";
575 
  constant csr_hpmcounter25_c   : std_ulogic_vector(11 downto 0) := x"c19";
576 
  constant csr_hpmcounter26_c   : std_ulogic_vector(11 downto 0) := x"c1a";
577 
  constant csr_hpmcounter27_c   : std_ulogic_vector(11 downto 0) := x"c1b";
578 
  constant csr_hpmcounter28_c   : std_ulogic_vector(11 downto 0) := x"c1c";
579 
  constant csr_hpmcounter29_c   : std_ulogic_vector(11 downto 0) := x"c1d";
580 
  constant csr_hpmcounter30_c   : std_ulogic_vector(11 downto 0) := x"c1e";
581 
  constant csr_hpmcounter31_c   : std_ulogic_vector(11 downto 0) := x"c1f";
582 29 zero_gravi 
  --
583 42 zero_gravi 
  constant csr_cycleh_c         : std_ulogic_vector(11 downto 0) := x"c80";
584 
  constant csr_timeh_c          : std_ulogic_vector(11 downto 0) := x"c81";
585 
  constant csr_instreth_c       : std_ulogic_vector(11 downto 0) := x"c82";
586 29 zero_gravi 
  --
587 42 zero_gravi 
  constant csr_hpmcounter3h_c   : std_ulogic_vector(11 downto 0) := x"c83";
588 
  constant csr_hpmcounter4h_c   : std_ulogic_vector(11 downto 0) := x"c84";
589 
  constant csr_hpmcounter5h_c   : std_ulogic_vector(11 downto 0) := x"c85";
590 
  constant csr_hpmcounter6h_c   : std_ulogic_vector(11 downto 0) := x"c86";
591 
  constant csr_hpmcounter7h_c   : std_ulogic_vector(11 downto 0) := x"c87";
592 
  constant csr_hpmcounter8h_c   : std_ulogic_vector(11 downto 0) := x"c88";
593 
  constant csr_hpmcounter9h_c   : std_ulogic_vector(11 downto 0) := x"c89";
594 
  constant csr_hpmcounter10h_c  : std_ulogic_vector(11 downto 0) := x"c8a";
595 
  constant csr_hpmcounter11h_c  : std_ulogic_vector(11 downto 0) := x"c8b";
596 
  constant csr_hpmcounter12h_c  : std_ulogic_vector(11 downto 0) := x"c8c";
597 
  constant csr_hpmcounter13h_c  : std_ulogic_vector(11 downto 0) := x"c8d";
598 
  constant csr_hpmcounter14h_c  : std_ulogic_vector(11 downto 0) := x"c8e";
599 
  constant csr_hpmcounter15h_c  : std_ulogic_vector(11 downto 0) := x"c8f";
600 
  constant csr_hpmcounter16h_c  : std_ulogic_vector(11 downto 0) := x"c90";
601 
  constant csr_hpmcounter17h_c  : std_ulogic_vector(11 downto 0) := x"c91";
602 
  constant csr_hpmcounter18h_c  : std_ulogic_vector(11 downto 0) := x"c92";
603 
  constant csr_hpmcounter19h_c  : std_ulogic_vector(11 downto 0) := x"c93";
604 
  constant csr_hpmcounter20h_c  : std_ulogic_vector(11 downto 0) := x"c94";
605 
  constant csr_hpmcounter21h_c  : std_ulogic_vector(11 downto 0) := x"c95";
606 
  constant csr_hpmcounter22h_c  : std_ulogic_vector(11 downto 0) := x"c96";
607 
  constant csr_hpmcounter23h_c  : std_ulogic_vector(11 downto 0) := x"c97";
608 
  constant csr_hpmcounter24h_c  : std_ulogic_vector(11 downto 0) := x"c98";
609 
  constant csr_hpmcounter25h_c  : std_ulogic_vector(11 downto 0) := x"c99";
610 
  constant csr_hpmcounter26h_c  : std_ulogic_vector(11 downto 0) := x"c9a";
611 
  constant csr_hpmcounter27h_c  : std_ulogic_vector(11 downto 0) := x"c9b";
612 
  constant csr_hpmcounter28h_c  : std_ulogic_vector(11 downto 0) := x"c9c";
613 
  constant csr_hpmcounter29h_c  : std_ulogic_vector(11 downto 0) := x"c9d";
614 
  constant csr_hpmcounter30h_c  : std_ulogic_vector(11 downto 0) := x"c9e";
615 
  constant csr_hpmcounter31h_c  : std_ulogic_vector(11 downto 0) := x"c9f";
616 
  --
617 
  constant csr_mvendorid_c      : std_ulogic_vector(11 downto 0) := x"f11";
618 
  constant csr_marchid_c        : std_ulogic_vector(11 downto 0) := x"f12";
619 
  constant csr_mimpid_c         : std_ulogic_vector(11 downto 0) := x"f13";
620 
  constant csr_mhartid_c        : std_ulogic_vector(11 downto 0) := x"f14";
621 29 zero_gravi 
 
622 42 zero_gravi 
  -- custom read-only CSRs --
623 
  constant csr_mzext_c          : std_ulogic_vector(11 downto 0) := x"fc0";
624 
 
625 44 zero_gravi 
  -- Co-Processor IDs -----------------------------------------------------------------------
626 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
627 44 zero_gravi 
  constant cp_sel_muldiv_c   : std_ulogic_vector(1 downto 0) := "00"; -- multiplication/division operations ('M' extension)
628 
  constant cp_sel_atomic_c   : std_ulogic_vector(1 downto 0) := "01"; -- atomic operations; success/failure evaluation ('A' extension)
629 
  constant cp_sel_bitmanip_c : std_ulogic_vector(1 downto 0) := "10"; -- bit manipulation ('B' extension)
630 
--constant cp_sel_float32_c  : std_ulogic_vector(1 downto 0) := "11"; -- reserved -- single-precision floating point operations ('F' extension)
631 2 zero_gravi 
 
632 
  -- ALU Function Codes ---------------------------------------------------------------------
633 
  -- -------------------------------------------------------------------------------------------
634 39 zero_gravi 
  -- arithmetic core --
635 
  constant alu_arith_cmd_addsub_c : std_ulogic := '0'; -- r.arith <= A +/- B
636 
  constant alu_arith_cmd_slt_c    : std_ulogic := '1'; -- r.arith <= A < B
637 
  -- logic core --
638 
  constant alu_logic_cmd_movb_c   : std_ulogic_vector(1 downto 0) := "00"; -- r.logic <= B
639 
  constant alu_logic_cmd_xor_c    : std_ulogic_vector(1 downto 0) := "01"; -- r.logic <= A xor B
640 
  constant alu_logic_cmd_or_c     : std_ulogic_vector(1 downto 0) := "10"; -- r.logic <= A or B
641 
  constant alu_logic_cmd_and_c    : std_ulogic_vector(1 downto 0) := "11"; -- r.logic <= A and B
642 
  -- function select (actual alu result) --
643 
  constant alu_func_cmd_arith_c   : std_ulogic_vector(1 downto 0) := "00"; -- r <= r.arith
644 
  constant alu_func_cmd_logic_c   : std_ulogic_vector(1 downto 0) := "01"; -- r <= r.logic
645 
  constant alu_func_cmd_shift_c   : std_ulogic_vector(1 downto 0) := "10"; -- r <= A <</>> B (iterative)
646 
  constant alu_func_cmd_copro_c   : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (iterative)
647 2 zero_gravi 
 
648 12 zero_gravi 
  -- Trap ID Codes --------------------------------------------------------------------------
649 
  -- -------------------------------------------------------------------------------------------
650 39 zero_gravi 
  -- RISC-V compliant exceptions --
651 
  constant trap_ima_c   : std_ulogic_vector(5 downto 0) := "0" & "00000"; -- 0.0:  instruction misaligned
652 
  constant trap_iba_c   : std_ulogic_vector(5 downto 0) := "0" & "00001"; -- 0.1:  instruction access fault
653 
  constant trap_iil_c   : std_ulogic_vector(5 downto 0) := "0" & "00010"; -- 0.2:  illegal instruction
654 
  constant trap_brk_c   : std_ulogic_vector(5 downto 0) := "0" & "00011"; -- 0.3:  breakpoint
655 
  constant trap_lma_c   : std_ulogic_vector(5 downto 0) := "0" & "00100"; -- 0.4:  load address misaligned
656 
  constant trap_lbe_c   : std_ulogic_vector(5 downto 0) := "0" & "00101"; -- 0.5:  load access fault
657 
  constant trap_sma_c   : std_ulogic_vector(5 downto 0) := "0" & "00110"; -- 0.6:  store address misaligned
658 
  constant trap_sbe_c   : std_ulogic_vector(5 downto 0) := "0" & "00111"; -- 0.7:  store access fault
659 40 zero_gravi 
  constant trap_uenv_c  : std_ulogic_vector(5 downto 0) := "0" & "01000"; -- 0.8:  environment call from u-mode
660 39 zero_gravi 
  constant trap_menv_c  : std_ulogic_vector(5 downto 0) := "0" & "01011"; -- 0.11: environment call from m-mode
661 
  -- RISC-V compliant interrupts --
662 
  constant trap_msi_c   : std_ulogic_vector(5 downto 0) := "1" & "00011"; -- 1.3:  machine software interrupt
663 
  constant trap_mti_c   : std_ulogic_vector(5 downto 0) := "1" & "00111"; -- 1.7:  machine timer interrupt
664 
  constant trap_mei_c   : std_ulogic_vector(5 downto 0) := "1" & "01011"; -- 1.11: machine external interrupt
665 
  -- NEORV32-specific (custom) interrupts --
666 40 zero_gravi 
  constant trap_reset_c : std_ulogic_vector(5 downto 0) := "1" & "00000"; -- 1.0:  hardware reset
667 39 zero_gravi 
  constant trap_firq0_c : std_ulogic_vector(5 downto 0) := "1" & "10000"; -- 1.16: fast interrupt 0
668 
  constant trap_firq1_c : std_ulogic_vector(5 downto 0) := "1" & "10001"; -- 1.17: fast interrupt 1
669 
  constant trap_firq2_c : std_ulogic_vector(5 downto 0) := "1" & "10010"; -- 1.18: fast interrupt 2
670 
  constant trap_firq3_c : std_ulogic_vector(5 downto 0) := "1" & "10011"; -- 1.19: fast interrupt 3
671 12 zero_gravi 
 
672 2 zero_gravi 
  -- CPU Control Exception System -----------------------------------------------------------
673 
  -- -------------------------------------------------------------------------------------------
674 
  -- exception source bits --
675 
  constant exception_iaccess_c   : natural := 0; -- instrution access fault
676 
  constant exception_iillegal_c  : natural := 1; -- illegal instrution
677 
  constant exception_ialign_c    : natural := 2; -- instrution address misaligned
678 
  constant exception_m_envcall_c : natural := 3; -- ENV call from m-mode
679 40 zero_gravi 
  constant exception_u_envcall_c : natural := 4; -- ENV call from u-mode
680 
  constant exception_break_c     : natural := 5; -- breakpoint
681 
  constant exception_salign_c    : natural := 6; -- store address misaligned
682 
  constant exception_lalign_c    : natural := 7; -- load address misaligned
683 
  constant exception_saccess_c   : natural := 8; -- store access fault
684 
  constant exception_laccess_c   : natural := 9; -- load access fault
685 14 zero_gravi 
  --
686 40 zero_gravi 
  constant exception_width_c     : natural := 10; -- length of this list in bits
687 2 zero_gravi 
  -- interrupt source bits --
688 12 zero_gravi 
  constant interrupt_msw_irq_c   : natural := 0; -- machine software interrupt
689 
  constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt
690 2 zero_gravi 
  constant interrupt_mext_irq_c  : natural := 2; -- machine external interrupt
691 14 zero_gravi 
  constant interrupt_firq_0_c    : natural := 3; -- fast interrupt channel 0
692 
  constant interrupt_firq_1_c    : natural := 4; -- fast interrupt channel 1
693 
  constant interrupt_firq_2_c    : natural := 5; -- fast interrupt channel 2
694 
  constant interrupt_firq_3_c    : natural := 6; -- fast interrupt channel 3
695 
  --
696 
  constant interrupt_width_c     : natural := 7; -- length of this list in bits
697 2 zero_gravi 
 
698 15 zero_gravi 
  -- CPU Privilege Modes --------------------------------------------------------------------
699 
  -- -------------------------------------------------------------------------------------------
700 29 zero_gravi 
  constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
701 
  constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
702 15 zero_gravi 
 
703 42 zero_gravi 
  -- HPM Event System -----------------------------------------------------------------------
704 
  -- -------------------------------------------------------------------------------------------
705 
  constant hpmcnt_event_cy_c      : natural := 0;  -- Active cycle
706 
  constant hpmcnt_event_never_c   : natural := 1;
707 
  constant hpmcnt_event_ir_c      : natural := 2;  -- Retired instruction
708 
  constant hpmcnt_event_cir_c     : natural := 3;  -- Retired compressed instruction
709 
  constant hpmcnt_event_wait_if_c : natural := 4;  -- Instruction fetch memory wait cycle
710 
  constant hpmcnt_event_wait_ii_c : natural := 5;  -- Instruction issue wait cycle
711 45 zero_gravi 
  constant hpmcnt_event_wait_mc_c : natural := 6;  -- Multi-cycle ALU-operation wait cycle
712 
  constant hpmcnt_event_load_c    : natural := 7;  -- Load operation
713 
  constant hpmcnt_event_store_c   : natural := 8;  -- Store operation
714 
  constant hpmcnt_event_wait_ls_c : natural := 9;  -- Load/store memory wait cycle
715 
  constant hpmcnt_event_jump_c    : natural := 10; -- Unconditional jump
716 
  constant hpmcnt_event_branch_c  : natural := 11; -- Conditional branch (taken or not taken)
717 
  constant hpmcnt_event_tbranch_c : natural := 12; -- Conditional taken branch
718 
  constant hpmcnt_event_trap_c    : natural := 13; -- Entered trap
719 
  constant hpmcnt_event_illegal_c : natural := 14; -- Illegal instruction exception
720 42 zero_gravi 
  --
721 45 zero_gravi 
  constant hpmcnt_event_size_c    : natural := 15; -- length of this list
722 42 zero_gravi 
 
723 39 zero_gravi 
  -- Clock Generator ------------------------------------------------------------------------
724 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
725 
  constant clk_div2_c    : natural := 0;
726 
  constant clk_div4_c    : natural := 1;
727 
  constant clk_div8_c    : natural := 2;
728 
  constant clk_div64_c   : natural := 3;
729 
  constant clk_div128_c  : natural := 4;
730 
  constant clk_div1024_c : natural := 5;
731 
  constant clk_div2048_c : natural := 6;
732 
  constant clk_div4096_c : natural := 7;
733 
 
734 
  -- Component: NEORV32 Processor Top Entity ------------------------------------------------
735 
  -- -------------------------------------------------------------------------------------------
736 
  component neorv32_top
737 
    generic (
738 
      -- General --
739 12 zero_gravi 
      CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz
740 44 zero_gravi 
      BOOTLOADER_EN                : boolean := true;   -- implement processor-internal bootloader?
741 12 zero_gravi 
      USER_CODE                    : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
742 36 zero_gravi 
      HW_THREAD_ID                 : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id (hartid)
743 2 zero_gravi 
      -- RISC-V CPU Extensions --
744 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false;  -- implement atomic extension?
745 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false;  -- implement bit manipulation extensions?
746 18 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?
747 8 zero_gravi 
      CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
748 18 zero_gravi 
      CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement muld/div extension?
749 
      CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?
750 8 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?
751 39 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false;  -- implement instruction stream sync.?
752 19 zero_gravi 
      -- Extension Options --
753 34 zero_gravi 
      FAST_MUL_EN                  : boolean := false;  -- use DSPs for M extension's multiplier
754 
      FAST_SHIFT_EN                : boolean := false;  -- use barrel shifter for shift operations
755 15 zero_gravi 
      -- Physical Memory Protection (PMP) --
756 42 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0;      -- number of regions (0..64)
757 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
758 
      -- Hardware Performance Monitors (HPM) --
759 
      HPM_NUM_CNTS                 : natural := 0;      -- number of inmplemnted HPM counters (0..29)
760 23 zero_gravi 
      -- Internal Instruction memory --
761 44 zero_gravi 
      MEM_INT_IMEM_EN              : boolean := true;   -- implement processor-internal instruction memory
762 8 zero_gravi 
      MEM_INT_IMEM_SIZE            : natural := 16*1024; -- size of processor-internal instruction memory in bytes
763 34 zero_gravi 
      MEM_INT_IMEM_ROM             : boolean := false;  -- implement processor-internal instruction memory as ROM
764 23 zero_gravi 
      -- Internal Data memory --
765 44 zero_gravi 
      MEM_INT_DMEM_EN              : boolean := true;   -- implement processor-internal data memory
766 8 zero_gravi 
      MEM_INT_DMEM_SIZE            : natural := 8*1024; -- size of processor-internal data memory in bytes
767 41 zero_gravi 
      -- Internal Cache memory --
768 44 zero_gravi 
      ICACHE_EN                    : boolean := false;  -- implement instruction cache
769 41 zero_gravi 
      ICACHE_NUM_BLOCKS            : natural := 4;      -- i-cache: number of blocks (min 1), has to be a power of 2
770 
      ICACHE_BLOCK_SIZE            : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
771 45 zero_gravi 
      ICACHE_ASSOCIATIVITY         : natural := 1;      -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
772 23 zero_gravi 
      -- External memory interface --
773 44 zero_gravi 
      MEM_EXT_EN                   : boolean := false;  -- implement external memory bus interface?
774 2 zero_gravi 
      -- Processor peripherals --
775 44 zero_gravi 
      IO_GPIO_EN                   : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
776 
      IO_MTIME_EN                  : boolean := true;   -- implement machine system timer (MTIME)?
777 
      IO_UART_EN                   : boolean := true;   -- implement universal asynchronous receiver/transmitter (UART)?
778 
      IO_SPI_EN                    : boolean := true;   -- implement serial peripheral interface (SPI)?
779 
      IO_TWI_EN                    : boolean := true;   -- implement two-wire interface (TWI)?
780 
      IO_PWM_EN                    : boolean := true;   -- implement pulse-width modulation unit (PWM)?
781 
      IO_WDT_EN                    : boolean := true;   -- implement watch dog timer (WDT)?
782 
      IO_TRNG_EN                   : boolean := false;  -- implement true random number generator (TRNG)?
783 
      IO_CFU0_EN                   : boolean := false;  -- implement custom functions unit 0 (CFU0)?
784 
      IO_CFU1_EN                   : boolean := false   -- implement custom functions unit 1 (CFU1)?
785 2 zero_gravi 
    );
786 
    port (
787 
      -- Global control --
788 34 zero_gravi 
      clk_i       : in  std_ulogic := '0'; -- global clock, rising edge
789 
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
790 2 zero_gravi 
      -- Wishbone bus interface --
791 36 zero_gravi 
      wb_tag_o    : out std_ulogic_vector(02 downto 0); -- tag
792 34 zero_gravi 
      wb_adr_o    : out std_ulogic_vector(31 downto 0); -- address
793 
      wb_dat_i    : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
794 
      wb_dat_o    : out std_ulogic_vector(31 downto 0); -- write data
795 
      wb_we_o     : out std_ulogic; -- read/write
796 
      wb_sel_o    : out std_ulogic_vector(03 downto 0); -- byte enable
797 
      wb_stb_o    : out std_ulogic; -- strobe
798 
      wb_cyc_o    : out std_ulogic; -- valid cycle
799 39 zero_gravi 
      wb_lock_o   : out std_ulogic; -- locked/exclusive bus access
800 34 zero_gravi 
      wb_ack_i    : in  std_ulogic := '0'; -- transfer acknowledge
801 
      wb_err_i    : in  std_ulogic := '0'; -- transfer error
802 44 zero_gravi 
      -- Advanced memory control signals (available if MEM_EXT_EN = true) --
803 34 zero_gravi 
      fence_o     : out std_ulogic; -- indicates an executed FENCE operation
804 
      fencei_o    : out std_ulogic; -- indicates an executed FENCEI operation
805 2 zero_gravi 
      -- GPIO --
806 34 zero_gravi 
      gpio_o      : out std_ulogic_vector(31 downto 0); -- parallel output
807 
      gpio_i      : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
808 2 zero_gravi 
      -- UART --
809 34 zero_gravi 
      uart_txd_o  : out std_ulogic; -- UART send data
810 
      uart_rxd_i  : in  std_ulogic := '0'; -- UART receive data
811 2 zero_gravi 
      -- SPI --
812 34 zero_gravi 
      spi_sck_o   : out std_ulogic; -- SPI serial clock
813 
      spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
814 
      spi_sdi_i   : in  std_ulogic := '0'; -- controller data in, peripheral data out
815 
      spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
816 2 zero_gravi 
      -- TWI --
817 35 zero_gravi 
      twi_sda_io  : inout std_logic; -- twi serial data line
818 
      twi_scl_io  : inout std_logic; -- twi serial clock line
819 2 zero_gravi 
      -- PWM --
820 40 zero_gravi 
      pwm_o       : out std_ulogic_vector(03 downto 0); -- pwm channels
821 44 zero_gravi 
      -- system time input from external MTIME (available if IO_MTIME_EN = false) --
822 40 zero_gravi 
      mtime_i     : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
823 2 zero_gravi 
      -- Interrupts --
824 44 zero_gravi 
      mtime_irq_i : in  std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
825 34 zero_gravi 
      msw_irq_i   : in  std_ulogic := '0'; -- machine software interrupt
826 
      mext_irq_i  : in  std_ulogic := '0'  -- machine external interrupt
827 2 zero_gravi 
    );
828 
  end component;
829 
 
830 4 zero_gravi 
  -- Component: CPU Top Entity --------------------------------------------------------------
831 
  -- -------------------------------------------------------------------------------------------
832 
  component neorv32_cpu
833 
    generic (
834 
      -- General --
835 36 zero_gravi 
      HW_THREAD_ID                 : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id
836 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0) := (others => '0'); -- cpu boot address
837 41 zero_gravi 
      BUS_TIMEOUT                  : natural := 63;    -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
838 4 zero_gravi 
      -- RISC-V CPU Extensions --
839 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
840 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
841 12 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
842 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
843 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
844 15 zero_gravi 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
845 12 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
846 
      CPU_EXTENSION_RISCV_Zifencei : boolean := true;  -- implement instruction stream sync.?
847 19 zero_gravi 
      -- Extension Options --
848 
      FAST_MUL_EN                  : boolean := false; -- use DSPs for M extension's multiplier
849 34 zero_gravi 
      FAST_SHIFT_EN                : boolean := false; -- use barrel shifter for shift operations
850 15 zero_gravi 
      -- Physical Memory Protection (PMP) --
851 42 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0; -- number of regions (0..64)
852 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
853 
      -- Hardware Performance Monitors (HPM) --
854 
      HPM_NUM_CNTS                 : natural := 0      -- number of inmplemnted HPM counters (0..29)
855 4 zero_gravi 
    );
856 
    port (
857 
      -- global control --
858 14 zero_gravi 
      clk_i          : in  std_ulogic := '0'; -- global clock, rising edge
859 
      rstn_i         : in  std_ulogic := '0'; -- global reset, low-active, async
860 12 zero_gravi 
      -- instruction bus interface --
861 
      i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
862 14 zero_gravi 
      i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
863 12 zero_gravi 
      i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
864 
      i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
865 
      i_bus_we_o     : out std_ulogic; -- write enable
866 
      i_bus_re_o     : out std_ulogic; -- read enable
867 
      i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
868 14 zero_gravi 
      i_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
869 
      i_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
870 12 zero_gravi 
      i_bus_fence_o  : out std_ulogic; -- executed FENCEI operation
871 35 zero_gravi 
      i_bus_priv_o   : out std_ulogic_vector(1 downto 0); -- privilege level
872 39 zero_gravi 
      i_bus_lock_o   : out std_ulogic; -- locked/exclusive access
873 12 zero_gravi 
      -- data bus interface --
874 
      d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
875 14 zero_gravi 
      d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
876 12 zero_gravi 
      d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
877 
      d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
878 
      d_bus_we_o     : out std_ulogic; -- write enable
879 
      d_bus_re_o     : out std_ulogic; -- read enable
880 
      d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
881 14 zero_gravi 
      d_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
882 
      d_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
883 12 zero_gravi 
      d_bus_fence_o  : out std_ulogic; -- executed FENCE operation
884 35 zero_gravi 
      d_bus_priv_o   : out std_ulogic_vector(1 downto 0); -- privilege level
885 39 zero_gravi 
      d_bus_lock_o   : out std_ulogic; -- locked/exclusive access
886 11 zero_gravi 
      -- system time input from MTIME --
887 14 zero_gravi 
      time_i         : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
888 
      -- interrupts (risc-v compliant) --
889 
      msw_irq_i      : in  std_ulogic := '0'; -- machine software interrupt
890 
      mext_irq_i     : in  std_ulogic := '0'; -- machine external interrupt
891 
      mtime_irq_i    : in  std_ulogic := '0'; -- machine timer interrupt
892 
      -- fast interrupts (custom) --
893 
      firq_i         : in  std_ulogic_vector(3 downto 0) := (others => '0')
894 4 zero_gravi 
    );
895 
  end component;
896 
 
897 2 zero_gravi 
  -- Component: CPU Control -----------------------------------------------------------------
898 
  -- -------------------------------------------------------------------------------------------
899 
  component neorv32_cpu_control
900 
    generic (
901 
      -- General --
902 12 zero_gravi 
      HW_THREAD_ID                 : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
903 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
904 2 zero_gravi 
      -- RISC-V CPU Extensions --
905 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
906 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
907 12 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
908 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
909 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
910 15 zero_gravi 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
911 12 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
912 15 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := true;  -- implement instruction stream sync.?
913 
      -- Physical memory protection (PMP) --
914 42 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0; -- number of regions (0..64)
915 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
916 
      -- Hardware Performance Monitors (HPM) --
917 
      HPM_NUM_CNTS                 : natural := 0      -- number of inmplemnted HPM counters (0..29)
918 2 zero_gravi 
    );
919 
    port (
920 
      -- global control --
921 
      clk_i         : in  std_ulogic; -- global clock, rising edge
922 
      rstn_i        : in  std_ulogic; -- global reset, low-active, async
923 
      ctrl_o        : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
924 
      -- status input --
925 
      alu_wait_i    : in  std_ulogic; -- wait for ALU
926 12 zero_gravi 
      bus_i_wait_i  : in  std_ulogic; -- wait for bus
927 
      bus_d_wait_i  : in  std_ulogic; -- wait for bus
928 2 zero_gravi 
      -- data input --
929 
      instr_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- instruction
930 
      cmp_i         : in  std_ulogic_vector(1 downto 0); -- comparator status
931 36 zero_gravi 
      alu_add_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result
932 
      rs1_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
933 2 zero_gravi 
      -- data output --
934 
      imm_o         : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
935 6 zero_gravi 
      fetch_pc_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
936 
      curr_pc_o     : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
937 2 zero_gravi 
      csr_rdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
938 14 zero_gravi 
      -- interrupts (risc-v compliant) --
939 
      msw_irq_i     : in  std_ulogic; -- machine software interrupt
940 
      mext_irq_i    : in  std_ulogic; -- machine external interrupt
941 2 zero_gravi 
      mtime_irq_i   : in  std_ulogic; -- machine timer interrupt
942 14 zero_gravi 
      -- fast interrupts (custom) --
943 
      firq_i        : in  std_ulogic_vector(3 downto 0);
944 11 zero_gravi 
      -- system time input from MTIME --
945 
      time_i        : in  std_ulogic_vector(63 downto 0); -- current system time
946 15 zero_gravi 
      -- physical memory protection --
947 
      pmp_addr_o    : out pmp_addr_if_t; -- addresses
948 
      pmp_ctrl_o    : out pmp_ctrl_if_t; -- configs
949 2 zero_gravi 
      -- bus access exceptions --
950 
      mar_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
951 
      ma_instr_i    : in  std_ulogic; -- misaligned instruction address
952 
      ma_load_i     : in  std_ulogic; -- misaligned load data address
953 
      ma_store_i    : in  std_ulogic; -- misaligned store data address
954 
      be_instr_i    : in  std_ulogic; -- bus error on instruction access
955 
      be_load_i     : in  std_ulogic; -- bus error on load data access
956 12 zero_gravi 
      be_store_i    : in  std_ulogic  -- bus error on store data access
957 2 zero_gravi 
    );
958 
  end component;
959 
 
960 
  -- Component: CPU Register File -----------------------------------------------------------
961 
  -- -------------------------------------------------------------------------------------------
962 
  component neorv32_cpu_regfile
963 
    generic (
964 
      CPU_EXTENSION_RISCV_E : boolean := false -- implement embedded RF extension?
965 
    );
966 
    port (
967 
      -- global control --
968 
      clk_i  : in  std_ulogic; -- global clock, rising edge
969 
      ctrl_i : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
970 
      -- data input --
971 
      mem_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
972 
      alu_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
973 
      csr_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
974 
      -- data output --
975 
      rs1_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
976 
      rs2_o  : out std_ulogic_vector(data_width_c-1 downto 0)  -- operand 2
977 
    );
978 
  end component;
979 
 
980 
  -- Component: CPU ALU ---------------------------------------------------------------------
981 
  -- -------------------------------------------------------------------------------------------
982 
  component neorv32_cpu_alu
983 11 zero_gravi 
    generic (
984 34 zero_gravi 
      CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
985 
      FAST_SHIFT_EN         : boolean := false -- use barrel shifter for shift operations
986 11 zero_gravi 
    );
987 2 zero_gravi 
    port (
988 
      -- global control --
989 
      clk_i       : in  std_ulogic; -- global clock, rising edge
990 
      rstn_i      : in  std_ulogic; -- global reset, low-active, async
991 
      ctrl_i      : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
992 
      -- data input --
993 
      rs1_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
994 
      rs2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
995 
      pc2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
996 
      imm_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- immediate
997 
      -- data output --
998 
      cmp_o       : out std_ulogic_vector(1 downto 0); -- comparator status
999 
      res_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
1000 36 zero_gravi 
      add_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
1001 2 zero_gravi 
      -- co-processor interface --
1002 19 zero_gravi 
      cp0_start_o : out std_ulogic; -- trigger co-processor 0
1003 2 zero_gravi 
      cp0_data_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
1004 
      cp0_valid_i : in  std_ulogic; -- co-processor 0 result valid
1005 19 zero_gravi 
      cp1_start_o : out std_ulogic; -- trigger co-processor 1
1006 2 zero_gravi 
      cp1_data_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result
1007 
      cp1_valid_i : in  std_ulogic; -- co-processor 1 result valid
1008 36 zero_gravi 
      cp2_start_o : out std_ulogic; -- trigger co-processor 2
1009 
      cp2_data_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 2 result
1010 
      cp2_valid_i : in  std_ulogic; -- co-processor 2 result valid
1011 
      cp3_start_o : out std_ulogic; -- trigger co-processor 3
1012 
      cp3_data_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 3 result
1013 
      cp3_valid_i : in  std_ulogic; -- co-processor 3 result valid
1014 2 zero_gravi 
      -- status --
1015 
      wait_o      : out std_ulogic -- busy due to iterative processing units
1016 
    );
1017 
  end component;
1018 
 
1019 44 zero_gravi 
  -- Component: CPU Co-Processor MULDIV ('M' extension) -------------------------------------
1020 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1021 
  component neorv32_cpu_cp_muldiv
1022 19 zero_gravi 
    generic (
1023 
      FAST_MUL_EN : boolean := false -- use DSPs for faster multiplication
1024 
    );
1025 2 zero_gravi 
    port (
1026 
      -- global control --
1027 
      clk_i   : in  std_ulogic; -- global clock, rising edge
1028 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
1029 
      ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1030 36 zero_gravi 
      start_i : in  std_ulogic; -- trigger operation
1031 2 zero_gravi 
      -- data input --
1032 
      rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1033 
      rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1034 
      -- result and status --
1035 
      res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1036 
      valid_o : out std_ulogic -- data output valid
1037 
    );
1038 
  end component;
1039 
 
1040 44 zero_gravi 
  -- Component: CPU Co-Processor Bit Manipulation ('B' extension) ---------------------------
1041 
  -- -------------------------------------------------------------------------------------------
1042 
  component neorv32_cpu_cp_bitmanip
1043 
    port (
1044 
      -- global control --
1045 
      clk_i   : in  std_ulogic; -- global clock, rising edge
1046 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
1047 
      ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1048 
      start_i : in  std_ulogic; -- trigger operation
1049 
      -- data input --
1050 
      cmp_i   : in  std_ulogic_vector(1 downto 0); -- comparator status
1051 
      rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1052 
      rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1053 
      -- result and status --
1054 
      res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1055 
      valid_o : out std_ulogic -- data output valid
1056 
    );
1057 
  end component;
1058 
 
1059 2 zero_gravi 
  -- Component: CPU Bus Interface -----------------------------------------------------------
1060 
  -- -------------------------------------------------------------------------------------------
1061 
  component neorv32_cpu_bus
1062 
    generic (
1063 40 zero_gravi 
      CPU_EXTENSION_RISCV_C : boolean := true;  -- implement compressed extension?
1064 15 zero_gravi 
      -- Physical memory protection (PMP) --
1065 42 zero_gravi 
      PMP_NUM_REGIONS       : natural := 0;       -- number of regions (0..64)
1066 
      PMP_MIN_GRANULARITY   : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
1067 41 zero_gravi 
      -- Bus Timeout --
1068 
      BUS_TIMEOUT           : natural := 63     -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
1069 2 zero_gravi 
    );
1070 
    port (
1071 
      -- global control --
1072 12 zero_gravi 
      clk_i          : in  std_ulogic; -- global clock, rising edge
1073 38 zero_gravi 
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
1074 12 zero_gravi 
      ctrl_i         : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1075 
      -- cpu instruction fetch interface --
1076 
      fetch_pc_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
1077 
      instr_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
1078 
      i_wait_o       : out std_ulogic; -- wait for fetch to complete
1079 
      --
1080 
      ma_instr_o     : out std_ulogic; -- misaligned instruction address
1081 
      be_instr_o     : out std_ulogic; -- bus error on instruction access
1082 
      -- cpu data access interface --
1083 
      addr_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
1084 
      wdata_i        : in  std_ulogic_vector(data_width_c-1 downto 0); -- write data
1085 
      rdata_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
1086 
      mar_o          : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
1087 
      d_wait_o       : out std_ulogic; -- wait for access to complete
1088 
      --
1089 
      ma_load_o      : out std_ulogic; -- misaligned load data address
1090 
      ma_store_o     : out std_ulogic; -- misaligned store data address
1091 
      be_load_o      : out std_ulogic; -- bus error on load data access
1092 
      be_store_o     : out std_ulogic; -- bus error on store data access
1093 15 zero_gravi 
      -- physical memory protection --
1094 
      pmp_addr_i     : in  pmp_addr_if_t; -- addresses
1095 
      pmp_ctrl_i     : in  pmp_ctrl_if_t; -- configs
1096 12 zero_gravi 
      -- instruction bus --
1097 
      i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1098 
      i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1099 
      i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1100 
      i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1101 
      i_bus_we_o     : out std_ulogic; -- write enable
1102 
      i_bus_re_o     : out std_ulogic; -- read enable
1103 
      i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
1104 
      i_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
1105 
      i_bus_err_i    : in  std_ulogic; -- bus transfer error
1106 
      i_bus_fence_o  : out std_ulogic; -- fence operation
1107 39 zero_gravi 
      i_bus_lock_o   : out std_ulogic; -- locked/exclusive access
1108 12 zero_gravi 
      -- data bus --
1109 
      d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1110 
      d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1111 
      d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1112 
      d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1113 
      d_bus_we_o     : out std_ulogic; -- write enable
1114 
      d_bus_re_o     : out std_ulogic; -- read enable
1115 
      d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
1116 
      d_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
1117 
      d_bus_err_i    : in  std_ulogic; -- bus transfer error
1118 39 zero_gravi 
      d_bus_fence_o  : out std_ulogic; -- fence operation
1119 
      d_bus_lock_o   : out std_ulogic  -- locked/exclusive access
1120 2 zero_gravi 
    );
1121 
  end component;
1122 
 
1123 45 zero_gravi 
  -- Component: CPU Instruction Cache -------------------------------------------------------
1124 41 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1125 45 zero_gravi 
  component neorv32_icache
1126 41 zero_gravi 
    generic (
1127 45 zero_gravi 
      CACHE_NUM_BLOCKS : natural := 4;  -- number of blocks (min 1), has to be a power of 2
1128 
      CACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2
1129 
      CACHE_NUM_SETS   : natural := 1   -- associativity / number of sets (1=direct_mapped), has to be a power of 2
1130 41 zero_gravi 
    );
1131 
    port (
1132 
      -- global control --
1133 
      clk_i         : in  std_ulogic; -- global clock, rising edge
1134 
      rstn_i        : in  std_ulogic; -- global reset, low-active, async
1135 
      clear_i       : in  std_ulogic; -- cache clear
1136 
      -- host controller interface --
1137 
      host_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1138 
      host_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1139 
      host_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1140 
      host_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1141 
      host_we_i     : in  std_ulogic; -- write enable
1142 
      host_re_i     : in  std_ulogic; -- read enable
1143 
      host_cancel_i : in  std_ulogic; -- cancel current bus transaction
1144 
      host_lock_i   : in  std_ulogic; -- locked/exclusive access
1145 
      host_ack_o    : out std_ulogic; -- bus transfer acknowledge
1146 
      host_err_o    : out std_ulogic; -- bus transfer error
1147 
      -- peripheral bus interface --
1148 
      bus_addr_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1149 
      bus_rdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1150 
      bus_wdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1151 
      bus_ben_o     : out std_ulogic_vector(03 downto 0); -- byte enable
1152 
      bus_we_o      : out std_ulogic; -- write enable
1153 
      bus_re_o      : out std_ulogic; -- read enable
1154 
      bus_cancel_o  : out std_ulogic; -- cancel current bus transaction
1155 
      bus_lock_o    : out std_ulogic; -- locked/exclusive access
1156 
      bus_ack_i     : in  std_ulogic; -- bus transfer acknowledge
1157 
      bus_err_i     : in  std_ulogic  -- bus transfer error
1158 
    );
1159 
  end component;
1160 
 
1161 12 zero_gravi 
  -- Component: CPU Bus Switch --------------------------------------------------------------
1162 
  -- -------------------------------------------------------------------------------------------
1163 
  component neorv32_busswitch
1164 
    generic (
1165 
      PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only
1166 
      PORT_CB_READ_ONLY : boolean := false  -- set if controller port B is read-only
1167 
    );
1168 
    port (
1169 
      -- global control --
1170 
      clk_i           : in  std_ulogic; -- global clock, rising edge
1171 
      rstn_i          : in  std_ulogic; -- global reset, low-active, async
1172 
      -- controller interface a --
1173 
      ca_bus_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1174 
      ca_bus_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1175 
      ca_bus_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1176 
      ca_bus_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1177 
      ca_bus_we_i     : in  std_ulogic; -- write enable
1178 
      ca_bus_re_i     : in  std_ulogic; -- read enable
1179 
      ca_bus_cancel_i : in  std_ulogic; -- cancel current bus transaction
1180 39 zero_gravi 
      ca_bus_lock_i   : in  std_ulogic; -- locked/exclusive access
1181 12 zero_gravi 
      ca_bus_ack_o    : out std_ulogic; -- bus transfer acknowledge
1182 
      ca_bus_err_o    : out std_ulogic; -- bus transfer error
1183 
      -- controller interface b --
1184 
      cb_bus_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1185 
      cb_bus_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1186 
      cb_bus_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1187 
      cb_bus_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1188 
      cb_bus_we_i     : in  std_ulogic; -- write enable
1189 
      cb_bus_re_i     : in  std_ulogic; -- read enable
1190 
      cb_bus_cancel_i : in  std_ulogic; -- cancel current bus transaction
1191 39 zero_gravi 
      cb_bus_lock_i   : in  std_ulogic; -- locked/exclusive access
1192 12 zero_gravi 
      cb_bus_ack_o    : out std_ulogic; -- bus transfer acknowledge
1193 
      cb_bus_err_o    : out std_ulogic; -- bus transfer error
1194 
      -- peripheral bus --
1195 36 zero_gravi 
      p_bus_src_o     : out std_ulogic; -- access source: 0 = A, 1 = B
1196 12 zero_gravi 
      p_bus_addr_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1197 
      p_bus_rdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1198 
      p_bus_wdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1199 
      p_bus_ben_o     : out std_ulogic_vector(03 downto 0); -- byte enable
1200 
      p_bus_we_o      : out std_ulogic; -- write enable
1201 
      p_bus_re_o      : out std_ulogic; -- read enable
1202 
      p_bus_cancel_o  : out std_ulogic; -- cancel current bus transaction
1203 39 zero_gravi 
      p_bus_lock_o    : out std_ulogic; -- locked/exclusive access
1204 12 zero_gravi 
      p_bus_ack_i     : in  std_ulogic; -- bus transfer acknowledge
1205 
      p_bus_err_i     : in  std_ulogic  -- bus transfer error
1206 
    );
1207 
  end component;
1208 
 
1209 2 zero_gravi 
  -- Component: CPU Compressed Instructions Decompressor ------------------------------------
1210 
  -- -------------------------------------------------------------------------------------------
1211 
  component neorv32_cpu_decompressor
1212 
    port (
1213 
      -- instruction input --
1214 
      ci_instr16_i : in  std_ulogic_vector(15 downto 0); -- compressed instruction input
1215 
      -- instruction output --
1216 
      ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
1217 
      ci_instr32_o : out std_ulogic_vector(31 downto 0)  -- 32-bit decompressed instruction
1218 
    );
1219 
  end component;
1220 
 
1221 
  -- Component: Processor-internal instruction memory (IMEM) --------------------------------
1222 
  -- -------------------------------------------------------------------------------------------
1223 
  component neorv32_imem
1224 
    generic (
1225 
      IMEM_BASE      : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
1226 
      IMEM_SIZE      : natural := 4*1024; -- processor-internal instruction memory size in bytes
1227 
      IMEM_AS_ROM    : boolean := false;  -- implement IMEM as read-only memory?
1228 44 zero_gravi 
      BOOTLOADER_EN  : boolean := true    -- implement and use bootloader?
1229 2 zero_gravi 
    );
1230 
    port (
1231 
      clk_i  : in  std_ulogic; -- global clock line
1232 
      rden_i : in  std_ulogic; -- read enable
1233 
      wren_i : in  std_ulogic; -- write enable
1234 
      ben_i  : in  std_ulogic_vector(03 downto 0); -- byte write enable
1235 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1236 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1237 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1238 
      ack_o  : out std_ulogic -- transfer acknowledge
1239 
    );
1240 
  end component;
1241 
 
1242 
  -- Component: Processor-internal data memory (DMEM) ---------------------------------------
1243 
  -- -------------------------------------------------------------------------------------------
1244 
  component neorv32_dmem
1245 
    generic (
1246 
      DMEM_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- memory base address
1247 
      DMEM_SIZE : natural := 4*1024  -- processor-internal instruction memory size in bytes
1248 
    );
1249 
    port (
1250 
      clk_i  : in  std_ulogic; -- global clock line
1251 
      rden_i : in  std_ulogic; -- read enable
1252 
      wren_i : in  std_ulogic; -- write enable
1253 
      ben_i  : in  std_ulogic_vector(03 downto 0); -- byte write enable
1254 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1255 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1256 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1257 
      ack_o  : out std_ulogic -- transfer acknowledge
1258 
    );
1259 
  end component;
1260 
 
1261 
  -- Component: Processor-internal bootloader ROM (BOOTROM) ---------------------------------
1262 
  -- -------------------------------------------------------------------------------------------
1263 
  component neorv32_boot_rom
1264 23 zero_gravi 
    generic (
1265 
      BOOTROM_BASE : std_ulogic_vector(31 downto 0) := x"FFFF0000"; -- boot ROM base address
1266 
      BOOTROM_SIZE : natural := 4*1024  -- processor-internal boot ROM memory size in bytes
1267 
    );
1268 2 zero_gravi 
    port (
1269 
      clk_i  : in  std_ulogic; -- global clock line
1270 
      rden_i : in  std_ulogic; -- read enable
1271 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1272 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1273 
      ack_o  : out std_ulogic -- transfer acknowledge
1274 
    );
1275 
  end component;
1276 
 
1277 
  -- Component: Machine System Timer (mtime) ------------------------------------------------
1278 
  -- -------------------------------------------------------------------------------------------
1279 
  component neorv32_mtime
1280 
    port (
1281 
      -- host access --
1282 
      clk_i     : in  std_ulogic; -- global clock line
1283 4 zero_gravi 
      rstn_i    : in  std_ulogic := '0'; -- global reset, low-active, async
1284 2 zero_gravi 
      addr_i    : in  std_ulogic_vector(31 downto 0); -- address
1285 
      rden_i    : in  std_ulogic; -- read enable
1286 
      wren_i    : in  std_ulogic; -- write enable
1287 
      data_i    : in  std_ulogic_vector(31 downto 0); -- data in
1288 
      data_o    : out std_ulogic_vector(31 downto 0); -- data out
1289 
      ack_o     : out std_ulogic; -- transfer acknowledge
1290 11 zero_gravi 
      -- time output for CPU --
1291 
      time_o    : out std_ulogic_vector(63 downto 0); -- current system time
1292 2 zero_gravi 
      -- interrupt --
1293 
      irq_o     : out std_ulogic  -- interrupt request
1294 
    );
1295 
  end component;
1296 
 
1297 
  -- Component: General Purpose Input/Output Port (GPIO) ------------------------------------
1298 
  -- -------------------------------------------------------------------------------------------
1299 
  component neorv32_gpio
1300 
    port (
1301 
      -- host access --
1302 
      clk_i  : in  std_ulogic; -- global clock line
1303 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1304 
      rden_i : in  std_ulogic; -- read enable
1305 
      wren_i : in  std_ulogic; -- write enable
1306 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1307 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1308 
      ack_o  : out std_ulogic; -- transfer acknowledge
1309 
      -- parallel io --
1310 22 zero_gravi 
      gpio_o : out std_ulogic_vector(31 downto 0);
1311 
      gpio_i : in  std_ulogic_vector(31 downto 0);
1312 2 zero_gravi 
      -- interrupt --
1313 
      irq_o  : out std_ulogic
1314 
    );
1315 
  end component;
1316 
 
1317 
  -- Component: Watchdog Timer (WDT) --------------------------------------------------------
1318 
  -- -------------------------------------------------------------------------------------------
1319 
  component neorv32_wdt
1320 
    port (
1321 
      -- host access --
1322 
      clk_i       : in  std_ulogic; -- global clock line
1323 
      rstn_i      : in  std_ulogic; -- global reset line, low-active
1324 
      rden_i      : in  std_ulogic; -- read enable
1325 
      wren_i      : in  std_ulogic; -- write enable
1326 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1327 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1328 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1329 
      ack_o       : out std_ulogic; -- transfer acknowledge
1330 
      -- clock generator --
1331 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1332 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1333 
      -- timeout event --
1334 
      irq_o       : out std_ulogic; -- timeout IRQ
1335 
      rstn_o      : out std_ulogic  -- timeout reset, low_active, use it as async!
1336 
    );
1337 
  end component;
1338 
 
1339 
  -- Component: Universal Asynchronous Receiver and Transmitter (UART) ----------------------
1340 
  -- -------------------------------------------------------------------------------------------
1341 
  component neorv32_uart
1342 
    port (
1343 
      -- host access --
1344 
      clk_i       : in  std_ulogic; -- global clock line
1345 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1346 
      rden_i      : in  std_ulogic; -- read enable
1347 
      wren_i      : in  std_ulogic; -- write enable
1348 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1349 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1350 
      ack_o       : out std_ulogic; -- transfer acknowledge
1351 
      -- clock generator --
1352 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1353 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1354 
      -- com lines --
1355 
      uart_txd_o  : out std_ulogic;
1356 
      uart_rxd_i  : in  std_ulogic;
1357 
      -- interrupts --
1358 
      uart_irq_o  : out std_ulogic  -- uart rx/tx interrupt
1359 
    );
1360 
  end component;
1361 
 
1362 
  -- Component: Serial Peripheral Interface (SPI) -------------------------------------------
1363 
  -- -------------------------------------------------------------------------------------------
1364 
  component neorv32_spi
1365 
    port (
1366 
      -- host access --
1367 
      clk_i       : in  std_ulogic; -- global clock line
1368 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1369 
      rden_i      : in  std_ulogic; -- read enable
1370 
      wren_i      : in  std_ulogic; -- write enable
1371 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1372 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1373 
      ack_o       : out std_ulogic; -- transfer acknowledge
1374 
      -- clock generator --
1375 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1376 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1377 
      -- com lines --
1378 6 zero_gravi 
      spi_sck_o   : out std_ulogic; -- SPI serial clock
1379 
      spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
1380 
      spi_sdi_i   : in  std_ulogic; -- controller data in, peripheral data out
1381 2 zero_gravi 
      spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
1382 
      -- interrupt --
1383 
      spi_irq_o   : out std_ulogic -- transmission done interrupt
1384 
    );
1385 
  end component;
1386 
 
1387 
  -- Component: Two-Wire Interface (TWI) ----------------------------------------------------
1388 
  -- -------------------------------------------------------------------------------------------
1389 
  component neorv32_twi
1390 
    port (
1391 
      -- host access --
1392 
      clk_i       : in  std_ulogic; -- global clock line
1393 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1394 
      rden_i      : in  std_ulogic; -- read enable
1395 
      wren_i      : in  std_ulogic; -- write enable
1396 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1397 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1398 
      ack_o       : out std_ulogic; -- transfer acknowledge
1399 
      -- clock generator --
1400 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1401 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1402 
      -- com lines --
1403 
      twi_sda_io  : inout std_logic; -- serial data line
1404 
      twi_scl_io  : inout std_logic; -- serial clock line
1405 
      -- interrupt --
1406 
      twi_irq_o   : out std_ulogic -- transfer done IRQ
1407 
    );
1408 
  end component;
1409 
 
1410 
  -- Component: Pulse-Width Modulation Controller (PWM) -------------------------------------
1411 
  -- -------------------------------------------------------------------------------------------
1412 
  component neorv32_pwm
1413 
    port (
1414 
      -- host access --
1415 
      clk_i       : in  std_ulogic; -- global clock line
1416 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1417 
      rden_i      : in  std_ulogic; -- read enable
1418 
      wren_i      : in  std_ulogic; -- write enable
1419 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1420 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1421 
      ack_o       : out std_ulogic; -- transfer acknowledge
1422 
      -- clock generator --
1423 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1424 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1425 
      -- pwm output channels --
1426 
      pwm_o       : out std_ulogic_vector(03 downto 0)
1427 
    );
1428 
  end component;
1429 
 
1430 
  -- Component: True Random Number Generator (TRNG) -----------------------------------------
1431 
  -- -------------------------------------------------------------------------------------------
1432 
  component neorv32_trng
1433 
    port (
1434 
      -- host access --
1435 
      clk_i  : in  std_ulogic; -- global clock line
1436 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1437 
      rden_i : in  std_ulogic; -- read enable
1438 
      wren_i : in  std_ulogic; -- write enable
1439 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1440 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1441 
      ack_o  : out std_ulogic  -- transfer acknowledge
1442 
    );
1443 
  end component;
1444 
 
1445 
  -- Component: Wishbone Bus Gateway (WISHBONE) ---------------------------------------------
1446 
  -- -------------------------------------------------------------------------------------------
1447 
  component neorv32_wishbone
1448 
    generic (
1449 35 zero_gravi 
      WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
1450 23 zero_gravi 
      -- Internal instruction memory --
1451 44 zero_gravi 
      MEM_INT_IMEM_EN   : boolean := true;   -- implement processor-internal instruction memory
1452 35 zero_gravi 
      MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
1453 23 zero_gravi 
      -- Internal data memory --
1454 44 zero_gravi 
      MEM_INT_DMEM_EN   : boolean := true;   -- implement processor-internal data memory
1455 35 zero_gravi 
      MEM_INT_DMEM_SIZE : natural := 4*1024  -- size of processor-internal data memory in bytes
1456 2 zero_gravi 
    );
1457 
    port (
1458 
      -- global control --
1459 39 zero_gravi 
      clk_i     : in  std_ulogic; -- global clock line
1460 
      rstn_i    : in  std_ulogic; -- global reset line, low-active
1461 2 zero_gravi 
      -- host access --
1462 39 zero_gravi 
      src_i     : in  std_ulogic; -- access type (0: data, 1:instruction)
1463 
      addr_i    : in  std_ulogic_vector(31 downto 0); -- address
1464 
      rden_i    : in  std_ulogic; -- read enable
1465 
      wren_i    : in  std_ulogic; -- write enable
1466 
      ben_i     : in  std_ulogic_vector(03 downto 0); -- byte write enable
1467 
      data_i    : in  std_ulogic_vector(31 downto 0); -- data in
1468 
      data_o    : out std_ulogic_vector(31 downto 0); -- data out
1469 
      cancel_i  : in  std_ulogic; -- cancel current bus transaction
1470 
      lock_i    : in  std_ulogic; -- locked/exclusive bus access
1471 
      ack_o     : out std_ulogic; -- transfer acknowledge
1472 
      err_o     : out std_ulogic; -- transfer error
1473 
      priv_i    : in  std_ulogic_vector(1 downto 0); -- current CPU privilege level
1474 2 zero_gravi 
      -- wishbone interface --
1475 39 zero_gravi 
      wb_tag_o  : out std_ulogic_vector(2 downto 0); -- tag
1476 
      wb_adr_o  : out std_ulogic_vector(31 downto 0); -- address
1477 
      wb_dat_i  : in  std_ulogic_vector(31 downto 0); -- read data
1478 
      wb_dat_o  : out std_ulogic_vector(31 downto 0); -- write data
1479 
      wb_we_o   : out std_ulogic; -- read/write
1480 
      wb_sel_o  : out std_ulogic_vector(03 downto 0); -- byte enable
1481 
      wb_stb_o  : out std_ulogic; -- strobe
1482 
      wb_cyc_o  : out std_ulogic; -- valid cycle
1483 
      wb_lock_o : out std_ulogic; -- locked/exclusive bus access
1484 
      wb_ack_i  : in  std_ulogic; -- transfer acknowledge
1485 
      wb_err_i  : in  std_ulogic  -- transfer error
1486 2 zero_gravi 
    );
1487 
  end component;
1488 
 
1489 34 zero_gravi 
  -- Component: Custom Functions Unit 0 (CFU0) ----------------------------------------------
1490 23 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1491 34 zero_gravi 
  component neorv32_cfu0
1492 23 zero_gravi 
    port (
1493 
      -- host access --
1494 
      clk_i       : in  std_ulogic; -- global clock line
1495 
      rstn_i      : in  std_ulogic; -- global reset line, low-active, use as async
1496 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1497 
      rden_i      : in  std_ulogic; -- read enable
1498 
      wren_i      : in  std_ulogic; -- write enable
1499 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1500 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1501 
      ack_o       : out std_ulogic; -- transfer acknowledge
1502 
      -- clock generator --
1503 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1504 34 zero_gravi 
      clkgen_i    : in  std_ulogic_vector(07 downto 0) -- "clock" inputs
1505 23 zero_gravi 
      -- custom io --
1506 
      -- ...
1507 
    );
1508 
  end component;
1509 
 
1510 34 zero_gravi 
  -- Component: Custom Functions Unit 1 (CFU1) ----------------------------------------------
1511 
  -- -------------------------------------------------------------------------------------------
1512 
  component neorv32_cfu1
1513 
    port (
1514 
      -- host access --
1515 
      clk_i       : in  std_ulogic; -- global clock line
1516 
      rstn_i      : in  std_ulogic; -- global reset line, low-active, use as async
1517 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1518 
      rden_i      : in  std_ulogic; -- read enable
1519 
      wren_i      : in  std_ulogic; -- write enable
1520 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1521 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1522 
      ack_o       : out std_ulogic; -- transfer acknowledge
1523 
      -- clock generator --
1524 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1525 
      clkgen_i    : in  std_ulogic_vector(07 downto 0) -- "clock" inputs
1526 
      -- custom io --
1527 
      -- ...
1528 
    );
1529 
  end component;
1530 
 
1531 23 zero_gravi 
  -- Component: System Configuration Information Memory (SYSINFO) ---------------------------
1532 
  -- -------------------------------------------------------------------------------------------
1533 12 zero_gravi 
  component neorv32_sysinfo
1534 
    generic (
1535 
      -- General --
1536 41 zero_gravi 
      CLOCK_FREQUENCY      : natural := 0;      -- clock frequency of clk_i in Hz
1537 44 zero_gravi 
      BOOTLOADER_EN        : boolean := true;   -- implement processor-internal bootloader?
1538 41 zero_gravi 
      USER_CODE            : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
1539 23 zero_gravi 
      -- Internal Instruction memory --
1540 44 zero_gravi 
      MEM_INT_IMEM_EN      : boolean := true;   -- implement processor-internal instruction memory
1541 41 zero_gravi 
      MEM_INT_IMEM_SIZE    : natural := 8*1024; -- size of processor-internal instruction memory in bytes
1542 
      MEM_INT_IMEM_ROM     : boolean := false;  -- implement processor-internal instruction memory as ROM
1543 23 zero_gravi 
      -- Internal Data memory --
1544 44 zero_gravi 
      MEM_INT_DMEM_EN      : boolean := true;   -- implement processor-internal data memory
1545 41 zero_gravi 
      MEM_INT_DMEM_SIZE    : natural := 4*1024; -- size of processor-internal data memory in bytes
1546 
      -- Internal Cache memory --
1547 44 zero_gravi 
      ICACHE_EN            : boolean := true;   -- implement instruction cache
1548 41 zero_gravi 
      ICACHE_NUM_BLOCKS    : natural := 4;      -- i-cache: number of blocks (min 2), has to be a power of 2
1549 
      ICACHE_BLOCK_SIZE    : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
1550 
      ICACHE_ASSOCIATIVITY : natural := 1;      -- i-cache: associativity (min 1), has to be a power 2
1551 23 zero_gravi 
      -- External memory interface --
1552 44 zero_gravi 
      MEM_EXT_EN           : boolean := false;  -- implement external memory bus interface?
1553 12 zero_gravi 
      -- Processor peripherals --
1554 44 zero_gravi 
      IO_GPIO_EN           : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
1555 
      IO_MTIME_EN          : boolean := true;   -- implement machine system timer (MTIME)?
1556 
      IO_UART_EN           : boolean := true;   -- implement universal asynchronous receiver/transmitter (UART)?
1557 
      IO_SPI_EN            : boolean := true;   -- implement serial peripheral interface (SPI)?
1558 
      IO_TWI_EN            : boolean := true;   -- implement two-wire interface (TWI)?
1559 
      IO_PWM_EN            : boolean := true;   -- implement pulse-width modulation unit (PWM)?
1560 
      IO_WDT_EN            : boolean := true;   -- implement watch dog timer (WDT)?
1561 
      IO_TRNG_EN           : boolean := true;   -- implement true random number generator (TRNG)?
1562 
      IO_CFU0_EN           : boolean := true;   -- implement custom functions unit 0 (CFU0)?
1563 
      IO_CFU1_EN           : boolean := true    -- implement custom functions unit 1 (CFU1)?
1564 12 zero_gravi 
    );
1565 
    port (
1566 
      -- host access --
1567 
      clk_i  : in  std_ulogic; -- global clock line
1568 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1569 
      rden_i : in  std_ulogic; -- read enable
1570 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1571 
      ack_o  : out std_ulogic  -- transfer acknowledge
1572 
    );
1573 
  end component;
1574 
 
1575 2 zero_gravi 
end neorv32_package;
1576 
 
1577 
package body neorv32_package is
1578 
 
1579 41 zero_gravi 
  -- Function: Minimal required number of bits to represent input number --------------------
1580 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1581 
  function index_size_f(input : natural) return natural is
1582 
  begin
1583 
    for i in 0 to natural'high loop
1584 
      if (2**i >= input) then
1585 
        return i;
1586 
      end if;
1587 
    end loop; -- i
1588 
    return 0;
1589 
  end function index_size_f;
1590 
 
1591 
  -- Function: Conditional select natural ---------------------------------------------------
1592 
  -- -------------------------------------------------------------------------------------------
1593 
  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural is
1594 
  begin
1595 
    if (cond = true) then
1596 
      return val_t;
1597 
    else
1598 
      return val_f;
1599 
    end if;
1600 
  end function cond_sel_natural_f;
1601 
 
1602 
  -- Function: Conditional select std_ulogic_vector -----------------------------------------
1603 
  -- -------------------------------------------------------------------------------------------
1604 
  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector is
1605 
  begin
1606 
    if (cond = true) then
1607 
      return val_t;
1608 
    else
1609 
      return val_f;
1610 
    end if;
1611 
  end function cond_sel_stdulogicvector_f;
1612 
 
1613 
  -- Function: Convert BOOL to STD_ULOGIC ---------------------------------------------------
1614 
  -- -------------------------------------------------------------------------------------------
1615 
  function bool_to_ulogic_f(cond : boolean) return std_ulogic is
1616 
  begin
1617 
    if (cond = true) then
1618 
      return '1';
1619 
    else
1620 
      return '0';
1621 
    end if;
1622 
  end function bool_to_ulogic_f;
1623 
 
1624 
  -- Function: OR all bits ------------------------------------------------------------------
1625 
  -- -------------------------------------------------------------------------------------------
1626 
  function or_all_f(a : std_ulogic_vector) return std_ulogic is
1627 
    variable tmp_v : std_ulogic;
1628 
  begin
1629 
    tmp_v := a(a'low);
1630 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1631 
      for i in a'low+1 to a'high loop
1632 
        tmp_v := tmp_v or a(i);
1633 
      end loop; -- i
1634 
    end if;
1635 2 zero_gravi 
    return tmp_v;
1636 
  end function or_all_f;
1637 
 
1638 
  -- Function: AND all bits -----------------------------------------------------------------
1639 
  -- -------------------------------------------------------------------------------------------
1640 
  function and_all_f(a : std_ulogic_vector) return std_ulogic is
1641 
    variable tmp_v : std_ulogic;
1642 
  begin
1643 
    tmp_v := a(a'low);
1644 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1645 
      for i in a'low+1 to a'high loop
1646 
        tmp_v := tmp_v and a(i);
1647 
      end loop; -- i
1648 
    end if;
1649 2 zero_gravi 
    return tmp_v;
1650 
  end function and_all_f;
1651 
 
1652 
  -- Function: XOR all bits -----------------------------------------------------------------
1653 
  -- -------------------------------------------------------------------------------------------
1654 
  function xor_all_f(a : std_ulogic_vector) return std_ulogic is
1655 
    variable tmp_v : std_ulogic;
1656 
  begin
1657 
    tmp_v := a(a'low);
1658 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1659 
      for i in a'low+1 to a'high loop
1660 
        tmp_v := tmp_v xor a(i);
1661 
      end loop; -- i
1662 
    end if;
1663 2 zero_gravi 
    return tmp_v;
1664 
  end function xor_all_f;
1665 
 
1666 
  -- Function: XNOR all bits ----------------------------------------------------------------
1667 
  -- -------------------------------------------------------------------------------------------
1668 
  function xnor_all_f(a : std_ulogic_vector) return std_ulogic is
1669 
    variable tmp_v : std_ulogic;
1670 
  begin
1671 
    tmp_v := a(a'low);
1672 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1673 
      for i in a'low+1 to a'high loop
1674 
        tmp_v := tmp_v xnor a(i);
1675 
      end loop; -- i
1676 
    end if;
1677 2 zero_gravi 
    return tmp_v;
1678 
  end function xnor_all_f;
1679 
 
1680 40 zero_gravi 
  -- Function: Convert std_ulogic_vector to hex char ----------------------------------------
1681 6 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1682 
  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character is
1683 
    variable output_v : character;
1684 
  begin
1685 
    case input is
1686 7 zero_gravi 
      when x"0"   => output_v := '0';
1687 
      when x"1"   => output_v := '1';
1688 
      when x"2"   => output_v := '2';
1689 
      when x"3"   => output_v := '3';
1690 
      when x"4"   => output_v := '4';
1691 
      when x"5"   => output_v := '5';
1692 
      when x"6"   => output_v := '6';
1693 
      when x"7"   => output_v := '7';
1694 
      when x"8"   => output_v := '8';
1695 
      when x"9"   => output_v := '9';
1696 
      when x"a"   => output_v := 'a';
1697 
      when x"b"   => output_v := 'b';
1698 
      when x"c"   => output_v := 'c';
1699 
      when x"d"   => output_v := 'd';
1700 
      when x"e"   => output_v := 'e';
1701 
      when x"f"   => output_v := 'f';
1702 6 zero_gravi 
      when others => output_v := '?';
1703 
    end case;
1704 
    return output_v;
1705 
  end function to_hexchar_f;
1706 
 
1707 40 zero_gravi 
  -- Function: Convert hex char to std_ulogic_vector ----------------------------------------
1708 
  -- -------------------------------------------------------------------------------------------
1709 
  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector is
1710 
    variable hex_value_v : std_ulogic_vector(3 downto 0);
1711 
  begin
1712 
    case input is
1713 
      when '0'       => hex_value_v := x"0";
1714 
      when '1'       => hex_value_v := x"1";
1715 
      when '2'       => hex_value_v := x"2";
1716 
      when '3'       => hex_value_v := x"3";
1717 
      when '4'       => hex_value_v := x"4";
1718 
      when '5'       => hex_value_v := x"5";
1719 
      when '6'       => hex_value_v := x"6";
1720 
      when '7'       => hex_value_v := x"7";
1721 
      when '8'       => hex_value_v := x"8";
1722 
      when '9'       => hex_value_v := x"9";
1723 
      when 'a' | 'A' => hex_value_v := x"a";
1724 
      when 'b' | 'B' => hex_value_v := x"b";
1725 
      when 'c' | 'C' => hex_value_v := x"c";
1726 
      when 'd' | 'D' => hex_value_v := x"d";
1727 
      when 'e' | 'E' => hex_value_v := x"e";
1728 
      when 'f' | 'F' => hex_value_v := x"f";
1729 
      when others    => hex_value_v := (others => 'X');
1730 
    end case;
1731 
    return hex_value_v;
1732 
  end function hexchar_to_stdulogicvector_f;
1733 
 
1734 32 zero_gravi 
  -- Function: Bit reversal -----------------------------------------------------------------
1735 
  -- -------------------------------------------------------------------------------------------
1736 
  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector is
1737 
    variable output_v : std_ulogic_vector(input'range);
1738 
  begin
1739 
    for i in 0 to input'length-1 loop
1740 
      output_v(input'length-i-1) := input(i);
1741 
    end loop; -- i
1742 
    return output_v;
1743 
  end function bit_rev_f;
1744 
 
1745 36 zero_gravi 
  -- Function: Test if input number is a power of two ---------------------------------------
1746 
  -- -------------------------------------------------------------------------------------------
1747 
  function is_power_of_two_f(input : natural) return boolean is
1748 
  begin
1749 38 zero_gravi 
    if (input = 1) then -- 2^0
1750 36 zero_gravi 
      return true;
1751 38 zero_gravi 
    elsif ((input / 2) /= 0) and ((input mod 2) = 0) then
1752 
      return true;
1753 36 zero_gravi 
    else
1754 
      return false;
1755 
    end if;
1756 
  end function is_power_of_two_f;
1757 
 
1758 40 zero_gravi 
  -- Function: Swap all bytes of a 32-bit word (endianness conversion) ----------------------
1759 
  -- -------------------------------------------------------------------------------------------
1760 
  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector is
1761 
    variable output_v : std_ulogic_vector(input'range);
1762 
  begin
1763 
    output_v(07 downto 00) := input(31 downto 24);
1764 
    output_v(15 downto 08) := input(23 downto 16);
1765 
    output_v(23 downto 16) := input(15 downto 08);
1766 
    output_v(31 downto 24) := input(07 downto 00);
1767 
    return output_v;
1768 
  end function bswap32_f;
1769 
 
1770 2 zero_gravi 
end neorv32_package;

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