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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_package.vhd] - Blame information for rev 47

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1 2 zero_gravi 
-- #################################################################################################
2 
-- # << NEORV32 - Main VHDL package file >>                                                        #
3 
-- # ********************************************************************************************* #
4 
-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
6 42 zero_gravi 
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
7 2 zero_gravi 
-- #                                                                                               #
8 
-- # Redistribution and use in source and binary forms, with or without modification, are          #
9 
-- # permitted provided that the following conditions are met:                                     #
10 
-- #                                                                                               #
11 
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
12 
-- #    conditions and the following disclaimer.                                                   #
13 
-- #                                                                                               #
14 
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
15 
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
16 
-- #    provided with the distribution.                                                            #
17 
-- #                                                                                               #
18 
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
19 
-- #    endorse or promote products derived from this software without specific prior written      #
20 
-- #    permission.                                                                                #
21 
-- #                                                                                               #
22 
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
23 
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
24 
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
25 
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
26 
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
27 
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
28 
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
29 
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
30 
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
32 
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
33 
-- #################################################################################################
34 
 
35 
library ieee;
36 
use ieee.std_logic_1164.all;
37 
use ieee.numeric_std.all;
38 
 
39 
package neorv32_package is
40 
 
41 36 zero_gravi 
  -- Architecture Configuration -------------------------------------------------------------
42 
  -- -------------------------------------------------------------------------------------------
43 40 zero_gravi 
  -- address space --
44 
  constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
45 
  constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
46 36 zero_gravi 
 
47 40 zero_gravi 
  -- (external) bus interface --
48 41 zero_gravi 
  constant bus_timeout_c     : natural := 127; -- cycles after which an *unacknowledged* bus access will timeout and trigger a bus fault exception (min 2)
49 40 zero_gravi 
  constant wb_pipe_mode_c    : boolean := false; -- *external* bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode
50 
  constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian
51 
 
52 
  -- CPU core --
53 41 zero_gravi 
  constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
54 40 zero_gravi 
 
55 47 zero_gravi 
  -- "critical" number of PMP regions --
56 
  -- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically
57 
  -- inserted into the memory interfaces increasing instruction fetch & data access latency by +1 cycle!
58 
  constant pmp_num_regions_critical_c : natural := 8;
59 
 
60 40 zero_gravi 
  -- Architecture Constants (do not modify!)= -----------------------------------------------
61 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
62 47 zero_gravi 
  constant data_width_c   : natural := 32; -- native data path width - do not change!
63 
  constant hw_version_c   : std_ulogic_vector(31 downto 0) := x"01050009"; -- no touchy!
64 40 zero_gravi 
  constant pmp_max_r_c    : natural := 8; -- max PMP regions - FIXED!
65 
  constant archid_c       : natural := 19; -- official NEORV32 architecture ID - hands off!
66 42 zero_gravi 
  constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
67 27 zero_gravi 
 
68 12 zero_gravi 
  -- Helper Functions -----------------------------------------------------------------------
69 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
70 
  function index_size_f(input : natural) return natural;
71 
  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
72 
  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
73 
  function bool_to_ulogic_f(cond : boolean) return std_ulogic;
74 15 zero_gravi 
  function or_all_f(a : std_ulogic_vector) return std_ulogic;
75 
  function and_all_f(a : std_ulogic_vector) return std_ulogic;
76 
  function xor_all_f(a : std_ulogic_vector) return std_ulogic;
77 2 zero_gravi 
  function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
78 6 zero_gravi 
  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
79 40 zero_gravi 
  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector;
80 32 zero_gravi 
  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector;
81 36 zero_gravi 
  function is_power_of_two_f(input : natural) return boolean;
82 40 zero_gravi 
  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;
83 2 zero_gravi 
 
84 15 zero_gravi 
  -- Internal Types -------------------------------------------------------------------------
85 
  -- -------------------------------------------------------------------------------------------
86 42 zero_gravi 
  type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);
87 
  type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0);
88 15 zero_gravi 
 
89 23 zero_gravi 
  -- Processor-Internal Address Space Layout ------------------------------------------------
90 
  -- -------------------------------------------------------------------------------------------
91 34 zero_gravi 
  -- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
92 39 zero_gravi 
  constant imem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
93 
  constant dmem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
94 42 zero_gravi 
  --> internal data/instruction memory sizes are configured via top's generics
95 2 zero_gravi 
 
96 23 zero_gravi 
  -- Internal Bootloader ROM --
97 
  constant boot_rom_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!
98 47 zero_gravi 
  constant boot_rom_size_c      : natural := 4*1024; -- module's address space in bytes
99 
  constant boot_rom_max_size_c  : natural := 32*1024; -- max module's address space in bytes, fixed!
100 23 zero_gravi 
 
101 2 zero_gravi 
  -- IO: Peripheral Devices ("IO") Area --
102 
  -- Control register(s) (including the device-enable) should be located at the base address of each device
103 47 zero_gravi 
  constant io_base_c            : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00";
104 
  constant io_size_c            : natural := 64*4; -- module's address space in bytes, fixed!
105 2 zero_gravi 
 
106 47 zero_gravi 
  -- Custom Functions Subsystem (CFS) --
107 
  constant cfs_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00"; -- base address
108 
  constant cfs_size_c           : natural := 32*4; -- module's address space in bytes
109 
  constant cfs_reg0_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00";
110 
  constant cfs_reg1_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF04";
111 
  constant cfs_reg2_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF08";
112 
  constant cfs_reg3_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF0C";
113 
  constant cfs_reg4_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF10";
114 
  constant cfs_reg5_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF14";
115 
  constant cfs_reg6_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF18";
116 
  constant cfs_reg7_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF1C";
117 
  constant cfs_reg8_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF20";
118 
  constant cfs_reg9_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF24";
119 
  constant cfs_reg10_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF28";
120 
  constant cfs_reg11_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF2C";
121 
  constant cfs_reg12_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF30";
122 
  constant cfs_reg13_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF34";
123 
  constant cfs_reg14_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF38";
124 
  constant cfs_reg15_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF3C";
125 
  constant cfs_reg16_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF40";
126 
  constant cfs_reg17_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF44";
127 
  constant cfs_reg18_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF48";
128 
  constant cfs_reg19_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF4C";
129 
  constant cfs_reg20_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF50";
130 
  constant cfs_reg21_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF54";
131 
  constant cfs_reg22_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF58";
132 
  constant cfs_reg23_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF5C";
133 
  constant cfs_reg24_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF60";
134 
  constant cfs_reg25_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF64";
135 
  constant cfs_reg26_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF68";
136 
  constant cfs_reg27_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF6C";
137 
  constant cfs_reg28_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF70";
138 
  constant cfs_reg29_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF74";
139 
  constant cfs_reg30_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF78";
140 
  constant cfs_reg31_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF7C";
141 
 
142 2 zero_gravi 
  -- General Purpose Input/Output Unit (GPIO) --
143 47 zero_gravi 
  constant gpio_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address
144 
  constant gpio_size_c          : natural := 2*4; -- module's address space in bytes
145 23 zero_gravi 
  constant gpio_in_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80";
146 
  constant gpio_out_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF84";
147 2 zero_gravi 
 
148 30 zero_gravi 
  -- True Random Number Generator (TRNG) --
149 47 zero_gravi 
  constant trng_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address
150 
  constant trng_size_c          : natural := 1*4; -- module's address space in bytes
151 30 zero_gravi 
  constant trng_ctrl_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88";
152 2 zero_gravi 
 
153 
  -- Watch Dog Timer (WDT) --
154 47 zero_gravi 
  constant wdt_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address
155 
  constant wdt_size_c           : natural := 1*4; -- module's address space in bytes
156 23 zero_gravi 
  constant wdt_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C";
157 2 zero_gravi 
 
158 
  -- Machine System Timer (MTIME) --
159 47 zero_gravi 
  constant mtime_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90"; -- base address
160 
  constant mtime_size_c         : natural := 4*4; -- module's address space in bytes
161 23 zero_gravi 
  constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90";
162 
  constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF94";
163 
  constant mtime_cmp_lo_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF98";
164 
  constant mtime_cmp_hi_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF9C";
165 2 zero_gravi 
 
166 
  -- Universal Asynchronous Receiver/Transmitter (UART) --
167 47 zero_gravi 
  constant uart_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address
168 
  constant uart_size_c          : natural := 2*4; -- module's address space in bytes
169 23 zero_gravi 
  constant uart_ctrl_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0";
170 
  constant uart_rtx_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA4";
171 2 zero_gravi 
 
172 
  -- Serial Peripheral Interface (SPI) --
173 47 zero_gravi 
  constant spi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address
174 
  constant spi_size_c           : natural := 2*4; -- module's address space in bytes
175 23 zero_gravi 
  constant spi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8";
176 
  constant spi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFAC";
177 2 zero_gravi 
 
178 
  -- Two Wire Interface (TWI) --
179 47 zero_gravi 
  constant twi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0"; -- base address
180 
  constant twi_size_c           : natural := 2*4; -- module's address space in bytes
181 23 zero_gravi 
  constant twi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0";
182 
  constant twi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB4";
183 2 zero_gravi 
 
184 
  -- Pulse-Width Modulation Controller (PWM) --
185 47 zero_gravi 
  constant pwm_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address
186 
  constant pwm_size_c           : natural := 2*4; -- module's address space in bytes
187 23 zero_gravi 
  constant pwm_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8";
188 
  constant pwm_duty_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFBC";
189 2 zero_gravi 
 
190 47 zero_gravi 
  -- reserved --
191 
--constant reserved_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address
192 
--constant reserved_size_c      : natural := 8*4; -- module's address space in bytes
193 12 zero_gravi 
 
194 23 zero_gravi 
  -- System Information Memory (SYSINFO) --
195 47 zero_gravi 
  constant sysinfo_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address
196 
  constant sysinfo_size_c       : natural := 8*4; -- module's address space in bytes
197 12 zero_gravi 
 
198 2 zero_gravi 
  -- Main Control Bus -----------------------------------------------------------------------
199 
  -- -------------------------------------------------------------------------------------------
200 
  -- register file --
201 39 zero_gravi 
  constant ctrl_rf_in_mux_lsb_c : natural :=  0; -- input source select lsb (10=MEM, 11=CSR)
202 
  constant ctrl_rf_in_mux_msb_c : natural :=  1; -- input source select msb (0-=ALU)
203 36 zero_gravi 
  constant ctrl_rf_rs1_adr0_c   : natural :=  2; -- source register 1 address bit 0
204 
  constant ctrl_rf_rs1_adr1_c   : natural :=  3; -- source register 1 address bit 1
205 
  constant ctrl_rf_rs1_adr2_c   : natural :=  4; -- source register 1 address bit 2
206 
  constant ctrl_rf_rs1_adr3_c   : natural :=  5; -- source register 1 address bit 3
207 
  constant ctrl_rf_rs1_adr4_c   : natural :=  6; -- source register 1 address bit 4
208 
  constant ctrl_rf_rs2_adr0_c   : natural :=  7; -- source register 2 address bit 0
209 
  constant ctrl_rf_rs2_adr1_c   : natural :=  8; -- source register 2 address bit 1
210 
  constant ctrl_rf_rs2_adr2_c   : natural :=  9; -- source register 2 address bit 2
211 
  constant ctrl_rf_rs2_adr3_c   : natural := 10; -- source register 2 address bit 3
212 
  constant ctrl_rf_rs2_adr4_c   : natural := 11; -- source register 2 address bit 4
213 
  constant ctrl_rf_rd_adr0_c    : natural := 12; -- destiantion register address bit 0
214 
  constant ctrl_rf_rd_adr1_c    : natural := 13; -- destiantion register address bit 1
215 
  constant ctrl_rf_rd_adr2_c    : natural := 14; -- destiantion register address bit 2
216 
  constant ctrl_rf_rd_adr3_c    : natural := 15; -- destiantion register address bit 3
217 
  constant ctrl_rf_rd_adr4_c    : natural := 16; -- destiantion register address bit 4
218 
  constant ctrl_rf_wb_en_c      : natural := 17; -- write back enable
219 
  constant ctrl_rf_r0_we_c      : natural := 18; -- force write access and force rd=r0
220 2 zero_gravi 
  -- alu --
221 39 zero_gravi 
  constant ctrl_alu_arith_c     : natural := 19; -- ALU arithmetic command
222 
  constant ctrl_alu_logic0_c    : natural := 20; -- ALU logic command bit 0
223 
  constant ctrl_alu_logic1_c    : natural := 21; -- ALU logic command bit 1
224 
  constant ctrl_alu_func0_c     : natural := 22; -- ALU function select command bit 0
225 
  constant ctrl_alu_func1_c     : natural := 23; -- ALU function select command bit 1
226 
  constant ctrl_alu_addsub_c    : natural := 24; -- 0=ADD, 1=SUB
227 
  constant ctrl_alu_opa_mux_c   : natural := 25; -- operand A select (0=rs1, 1=PC)
228 
  constant ctrl_alu_opb_mux_c   : natural := 26; -- operand B select (0=rs2, 1=IMM)
229 
  constant ctrl_alu_unsigned_c  : natural := 27; -- is unsigned ALU operation
230 
  constant ctrl_alu_shift_dir_c : natural := 28; -- shift direction (0=left, 1=right)
231 
  constant ctrl_alu_shift_ar_c  : natural := 29; -- is arithmetic shift
232 2 zero_gravi 
  -- bus interface --
233 39 zero_gravi 
  constant ctrl_bus_size_lsb_c  : natural := 30; -- transfer size lsb (00=byte, 01=half-word)
234 
  constant ctrl_bus_size_msb_c  : natural := 31; -- transfer size msb (10=word, 11=?)
235 
  constant ctrl_bus_rd_c        : natural := 32; -- read data request
236 
  constant ctrl_bus_wr_c        : natural := 33; -- write data request
237 
  constant ctrl_bus_if_c        : natural := 34; -- instruction fetch request
238 
  constant ctrl_bus_mo_we_c     : natural := 35; -- memory address and data output register write enable
239 
  constant ctrl_bus_mi_we_c     : natural := 36; -- memory data input register write enable
240 
  constant ctrl_bus_unsigned_c  : natural := 37; -- is unsigned load
241 
  constant ctrl_bus_ierr_ack_c  : natural := 38; -- acknowledge instruction fetch bus exceptions
242 
  constant ctrl_bus_derr_ack_c  : natural := 39; -- acknowledge data access bus exceptions
243 
  constant ctrl_bus_fence_c     : natural := 40; -- executed fence operation
244 
  constant ctrl_bus_fencei_c    : natural := 41; -- executed fencei operation
245 
  constant ctrl_bus_lock_c      : natural := 42; -- locked/exclusive bus access
246 26 zero_gravi 
  -- co-processors --
247 39 zero_gravi 
  constant ctrl_cp_id_lsb_c     : natural := 43; -- cp select ID lsb
248 
  constant ctrl_cp_id_msb_c     : natural := 44; -- cp select ID msb
249 36 zero_gravi 
  -- current privilege level --
250 39 zero_gravi 
  constant ctrl_priv_lvl_lsb_c  : natural := 45; -- privilege level lsb
251 
  constant ctrl_priv_lvl_msb_c  : natural := 46; -- privilege level msb
252 44 zero_gravi 
  -- instruction's control blocks (used by cpu co-processors) --
253 39 zero_gravi 
  constant ctrl_ir_funct3_0_c   : natural := 47; -- funct3 bit 0
254 
  constant ctrl_ir_funct3_1_c   : natural := 48; -- funct3 bit 1
255 
  constant ctrl_ir_funct3_2_c   : natural := 49; -- funct3 bit 2
256 
  constant ctrl_ir_funct12_0_c  : natural := 50; -- funct12 bit 0
257 
  constant ctrl_ir_funct12_1_c  : natural := 51; -- funct12 bit 1
258 
  constant ctrl_ir_funct12_2_c  : natural := 52; -- funct12 bit 2
259 
  constant ctrl_ir_funct12_3_c  : natural := 53; -- funct12 bit 3
260 
  constant ctrl_ir_funct12_4_c  : natural := 54; -- funct12 bit 4
261 
  constant ctrl_ir_funct12_5_c  : natural := 55; -- funct12 bit 5
262 
  constant ctrl_ir_funct12_6_c  : natural := 56; -- funct12 bit 6
263 
  constant ctrl_ir_funct12_7_c  : natural := 57; -- funct12 bit 7
264 
  constant ctrl_ir_funct12_8_c  : natural := 58; -- funct12 bit 8
265 
  constant ctrl_ir_funct12_9_c  : natural := 59; -- funct12 bit 9
266 
  constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10
267 
  constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11
268 44 zero_gravi 
  constant ctrl_ir_opcode7_0_c  : natural := 62; -- opcode7 bit 0
269 
  constant ctrl_ir_opcode7_1_c  : natural := 63; -- opcode7 bit 1
270 
  constant ctrl_ir_opcode7_2_c  : natural := 64; -- opcode7 bit 2
271 
  constant ctrl_ir_opcode7_3_c  : natural := 65; -- opcode7 bit 3
272 
  constant ctrl_ir_opcode7_4_c  : natural := 66; -- opcode7 bit 4
273 
  constant ctrl_ir_opcode7_5_c  : natural := 67; -- opcode7 bit 5
274 
  constant ctrl_ir_opcode7_6_c  : natural := 68; -- opcode7 bit 6
275 47 zero_gravi 
  -- CPU status --
276 
  constant ctrl_sleep_c         : natural := 69; -- set when CPU is in sleep mode
277 2 zero_gravi 
  -- control bus size --
278 47 zero_gravi 
  constant ctrl_width_c         : natural := 70; -- control bus size
279 2 zero_gravi 
 
280 47 zero_gravi 
  -- Comparator Bus -------------------------------------------------------------------------
281 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
282 47 zero_gravi 
  constant cmp_equal_c : natural := 0;
283 
  constant cmp_less_c  : natural := 1; -- for signed and unsigned comparisons
284 2 zero_gravi 
 
285 
  -- RISC-V Opcode Layout -------------------------------------------------------------------
286 
  -- -------------------------------------------------------------------------------------------
287 
  constant instr_opcode_lsb_c  : natural :=  0; -- opcode bit 0
288 
  constant instr_opcode_msb_c  : natural :=  6; -- opcode bit 6
289 
  constant instr_rd_lsb_c      : natural :=  7; -- destination register address bit 0
290 
  constant instr_rd_msb_c      : natural := 11; -- destination register address bit 4
291 
  constant instr_funct3_lsb_c  : natural := 12; -- funct3 bit 0
292 
  constant instr_funct3_msb_c  : natural := 14; -- funct3 bit 2
293 
  constant instr_rs1_lsb_c     : natural := 15; -- source register 1 address bit 0
294 
  constant instr_rs1_msb_c     : natural := 19; -- source register 1 address bit 4
295 
  constant instr_rs2_lsb_c     : natural := 20; -- source register 2 address bit 0
296 
  constant instr_rs2_msb_c     : natural := 24; -- source register 2 address bit 4
297 
  constant instr_funct7_lsb_c  : natural := 25; -- funct7 bit 0
298 
  constant instr_funct7_msb_c  : natural := 31; -- funct7 bit 6
299 
  constant instr_funct12_lsb_c : natural := 20; -- funct12 bit 0
300 
  constant instr_funct12_msb_c : natural := 31; -- funct12 bit 11
301 
  constant instr_imm12_lsb_c   : natural := 20; -- immediate12 bit 0
302 
  constant instr_imm12_msb_c   : natural := 31; -- immediate12 bit 11
303 
  constant instr_imm20_lsb_c   : natural := 12; -- immediate20 bit 0
304 
  constant instr_imm20_msb_c   : natural := 31; -- immediate20 bit 21
305 
  constant instr_csr_id_lsb_c  : natural := 20; -- csr select bit 0
306 
  constant instr_csr_id_msb_c  : natural := 31; -- csr select bit 11
307 39 zero_gravi 
  constant instr_funct5_lsb_c  : natural := 27; -- funct5 select bit 0
308 
  constant instr_funct5_msb_c  : natural := 31; -- funct5 select bit 4
309 2 zero_gravi 
 
310 
  -- RISC-V Opcodes -------------------------------------------------------------------------
311 
  -- -------------------------------------------------------------------------------------------
312 
  -- alu --
313 
  constant opcode_lui_c    : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate
314 
  constant opcode_auipc_c  : std_ulogic_vector(6 downto 0) := "0010111"; -- add upper immediate to PC
315 
  constant opcode_alui_c   : std_ulogic_vector(6 downto 0) := "0010011"; -- ALU operation with immediate (operation via funct3 and funct7)
316 
  constant opcode_alu_c    : std_ulogic_vector(6 downto 0) := "0110011"; -- ALU operation (operation via funct3 and funct7)
317 
  -- control flow --
318 
  constant opcode_jal_c    : std_ulogic_vector(6 downto 0) := "1101111"; -- jump and link
319 29 zero_gravi 
  constant opcode_jalr_c   : std_ulogic_vector(6 downto 0) := "1100111"; -- jump and link with register
320 2 zero_gravi 
  constant opcode_branch_c : std_ulogic_vector(6 downto 0) := "1100011"; -- branch (condition set via funct3)
321 
  -- memory access --
322 
  constant opcode_load_c   : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)
323 
  constant opcode_store_c  : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)
324 
  -- system/csr --
325 8 zero_gravi 
  constant opcode_fence_c  : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
326 2 zero_gravi 
  constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
327 39 zero_gravi 
  -- atomic operations (A) --
328 
  constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)
329 2 zero_gravi 
 
330 
  -- RISC-V Funct3 --------------------------------------------------------------------------
331 
  -- -------------------------------------------------------------------------------------------
332 
  -- control flow --
333 
  constant funct3_beq_c    : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
334 
  constant funct3_bne_c    : std_ulogic_vector(2 downto 0) := "001"; -- branch if not equal
335 
  constant funct3_blt_c    : std_ulogic_vector(2 downto 0) := "100"; -- branch if less than
336 
  constant funct3_bge_c    : std_ulogic_vector(2 downto 0) := "101"; -- branch if greater than or equal
337 
  constant funct3_bltu_c   : std_ulogic_vector(2 downto 0) := "110"; -- branch if less than (unsigned)
338 
  constant funct3_bgeu_c   : std_ulogic_vector(2 downto 0) := "111"; -- branch if greater than or equal (unsigned)
339 
  -- memory access --
340 
  constant funct3_lb_c     : std_ulogic_vector(2 downto 0) := "000"; -- load byte
341 
  constant funct3_lh_c     : std_ulogic_vector(2 downto 0) := "001"; -- load half word
342 
  constant funct3_lw_c     : std_ulogic_vector(2 downto 0) := "010"; -- load word
343 
  constant funct3_lbu_c    : std_ulogic_vector(2 downto 0) := "100"; -- load byte (unsigned)
344 
  constant funct3_lhu_c    : std_ulogic_vector(2 downto 0) := "101"; -- load half word (unsigned)
345 
  constant funct3_sb_c     : std_ulogic_vector(2 downto 0) := "000"; -- store byte
346 
  constant funct3_sh_c     : std_ulogic_vector(2 downto 0) := "001"; -- store half word
347 
  constant funct3_sw_c     : std_ulogic_vector(2 downto 0) := "010"; -- store word
348 
  -- alu --
349 
  constant funct3_subadd_c : std_ulogic_vector(2 downto 0) := "000"; -- sub/add via funct7
350 
  constant funct3_sll_c    : std_ulogic_vector(2 downto 0) := "001"; -- shift logical left
351 
  constant funct3_slt_c    : std_ulogic_vector(2 downto 0) := "010"; -- set on less
352 
  constant funct3_sltu_c   : std_ulogic_vector(2 downto 0) := "011"; -- set on less unsigned
353 
  constant funct3_xor_c    : std_ulogic_vector(2 downto 0) := "100"; -- xor
354 
  constant funct3_sr_c     : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7
355 
  constant funct3_or_c     : std_ulogic_vector(2 downto 0) := "110"; -- or
356 
  constant funct3_and_c    : std_ulogic_vector(2 downto 0) := "111"; -- and
357 
  -- system/csr --
358 
  constant funct3_env_c    : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi
359 
  constant funct3_csrrw_c  : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w
360 
  constant funct3_csrrs_c  : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit
361 
  constant funct3_csrrc_c  : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit
362 
  constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate
363 
  constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate
364 
  constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
365 8 zero_gravi 
  -- fence --
366 
  constant funct3_fence_c  : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
367 
  constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync
368 2 zero_gravi 
 
369 39 zero_gravi 
  -- RISC-V Funct12 -------------------------------------------------------------------------
370 11 zero_gravi 
  -- -------------------------------------------------------------------------------------------
371 
  -- system --
372 
  constant funct12_ecall_c  : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
373 
  constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
374 
  constant funct12_mret_c   : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
375 
  constant funct12_wfi_c    : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
376 
 
377 39 zero_gravi 
  -- RISC-V Funct5 --------------------------------------------------------------------------
378 
  -- -------------------------------------------------------------------------------------------
379 
  -- atomic operations --
380 
  constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR
381 
  constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC
382 
 
383 29 zero_gravi 
  -- RISC-V CSR Addresses -------------------------------------------------------------------
384 
  -- -------------------------------------------------------------------------------------------
385 41 zero_gravi 
  -- read/write CSRs --
386 42 zero_gravi 
  constant csr_mstatus_c        : std_ulogic_vector(11 downto 0) := x"300";
387 
  constant csr_misa_c           : std_ulogic_vector(11 downto 0) := x"301";
388 
  constant csr_mie_c            : std_ulogic_vector(11 downto 0) := x"304";
389 
  constant csr_mtvec_c          : std_ulogic_vector(11 downto 0) := x"305";
390 
  constant csr_mcounteren_c     : std_ulogic_vector(11 downto 0) := x"306";
391 
  constant csr_mstatush_c       : std_ulogic_vector(11 downto 0) := x"310";
392 29 zero_gravi 
  --
393 42 zero_gravi 
  constant csr_mcountinhibit_c  : std_ulogic_vector(11 downto 0) := x"320";
394 29 zero_gravi 
  --
395 42 zero_gravi 
  constant csr_mhpmevent3_c     : std_ulogic_vector(11 downto 0) := x"323";
396 
  constant csr_mhpmevent4_c     : std_ulogic_vector(11 downto 0) := x"324";
397 
  constant csr_mhpmevent5_c     : std_ulogic_vector(11 downto 0) := x"325";
398 
  constant csr_mhpmevent6_c     : std_ulogic_vector(11 downto 0) := x"326";
399 
  constant csr_mhpmevent7_c     : std_ulogic_vector(11 downto 0) := x"327";
400 
  constant csr_mhpmevent8_c     : std_ulogic_vector(11 downto 0) := x"328";
401 
  constant csr_mhpmevent9_c     : std_ulogic_vector(11 downto 0) := x"329";
402 
  constant csr_mhpmevent10_c    : std_ulogic_vector(11 downto 0) := x"32a";
403 
  constant csr_mhpmevent11_c    : std_ulogic_vector(11 downto 0) := x"32b";
404 
  constant csr_mhpmevent12_c    : std_ulogic_vector(11 downto 0) := x"32c";
405 
  constant csr_mhpmevent13_c    : std_ulogic_vector(11 downto 0) := x"32d";
406 
  constant csr_mhpmevent14_c    : std_ulogic_vector(11 downto 0) := x"32e";
407 
  constant csr_mhpmevent15_c    : std_ulogic_vector(11 downto 0) := x"32f";
408 
  constant csr_mhpmevent16_c    : std_ulogic_vector(11 downto 0) := x"330";
409 
  constant csr_mhpmevent17_c    : std_ulogic_vector(11 downto 0) := x"331";
410 
  constant csr_mhpmevent18_c    : std_ulogic_vector(11 downto 0) := x"332";
411 
  constant csr_mhpmevent19_c    : std_ulogic_vector(11 downto 0) := x"333";
412 
  constant csr_mhpmevent20_c    : std_ulogic_vector(11 downto 0) := x"334";
413 
  constant csr_mhpmevent21_c    : std_ulogic_vector(11 downto 0) := x"335";
414 
  constant csr_mhpmevent22_c    : std_ulogic_vector(11 downto 0) := x"336";
415 
  constant csr_mhpmevent23_c    : std_ulogic_vector(11 downto 0) := x"337";
416 
  constant csr_mhpmevent24_c    : std_ulogic_vector(11 downto 0) := x"338";
417 
  constant csr_mhpmevent25_c    : std_ulogic_vector(11 downto 0) := x"339";
418 
  constant csr_mhpmevent26_c    : std_ulogic_vector(11 downto 0) := x"33a";
419 
  constant csr_mhpmevent27_c    : std_ulogic_vector(11 downto 0) := x"33b";
420 
  constant csr_mhpmevent28_c    : std_ulogic_vector(11 downto 0) := x"33c";
421 
  constant csr_mhpmevent29_c    : std_ulogic_vector(11 downto 0) := x"33d";
422 
  constant csr_mhpmevent30_c    : std_ulogic_vector(11 downto 0) := x"33e";
423 
  constant csr_mhpmevent31_c    : std_ulogic_vector(11 downto 0) := x"33f";
424 29 zero_gravi 
  --
425 42 zero_gravi 
  constant csr_mscratch_c       : std_ulogic_vector(11 downto 0) := x"340";
426 
  constant csr_mepc_c           : std_ulogic_vector(11 downto 0) := x"341";
427 
  constant csr_mcause_c         : std_ulogic_vector(11 downto 0) := x"342";
428 
  constant csr_mtval_c          : std_ulogic_vector(11 downto 0) := x"343";
429 
  constant csr_mip_c            : std_ulogic_vector(11 downto 0) := x"344";
430 29 zero_gravi 
  --
431 42 zero_gravi 
  constant csr_pmpcfg0_c        : std_ulogic_vector(11 downto 0) := x"3a0";
432 
  constant csr_pmpcfg1_c        : std_ulogic_vector(11 downto 0) := x"3a1";
433 
  constant csr_pmpcfg2_c        : std_ulogic_vector(11 downto 0) := x"3a2";
434 
  constant csr_pmpcfg3_c        : std_ulogic_vector(11 downto 0) := x"3a3";
435 
  constant csr_pmpcfg4_c        : std_ulogic_vector(11 downto 0) := x"3a4";
436 
  constant csr_pmpcfg5_c        : std_ulogic_vector(11 downto 0) := x"3a5";
437 
  constant csr_pmpcfg6_c        : std_ulogic_vector(11 downto 0) := x"3a6";
438 
  constant csr_pmpcfg7_c        : std_ulogic_vector(11 downto 0) := x"3a7";
439 
  constant csr_pmpcfg8_c        : std_ulogic_vector(11 downto 0) := x"3a8";
440 
  constant csr_pmpcfg9_c        : std_ulogic_vector(11 downto 0) := x"3a9";
441 
  constant csr_pmpcfg10_c       : std_ulogic_vector(11 downto 0) := x"3aa";
442 
  constant csr_pmpcfg11_c       : std_ulogic_vector(11 downto 0) := x"3ab";
443 
  constant csr_pmpcfg12_c       : std_ulogic_vector(11 downto 0) := x"3ac";
444 
  constant csr_pmpcfg13_c       : std_ulogic_vector(11 downto 0) := x"3ad";
445 
  constant csr_pmpcfg14_c       : std_ulogic_vector(11 downto 0) := x"3ae";
446 
  constant csr_pmpcfg15_c       : std_ulogic_vector(11 downto 0) := x"3af";
447 29 zero_gravi 
  --
448 42 zero_gravi 
  constant csr_pmpaddr0_c       : std_ulogic_vector(11 downto 0) := x"3b0";
449 
  constant csr_pmpaddr1_c       : std_ulogic_vector(11 downto 0) := x"3b1";
450 
  constant csr_pmpaddr2_c       : std_ulogic_vector(11 downto 0) := x"3b2";
451 
  constant csr_pmpaddr3_c       : std_ulogic_vector(11 downto 0) := x"3b3";
452 
  constant csr_pmpaddr4_c       : std_ulogic_vector(11 downto 0) := x"3b4";
453 
  constant csr_pmpaddr5_c       : std_ulogic_vector(11 downto 0) := x"3b5";
454 
  constant csr_pmpaddr6_c       : std_ulogic_vector(11 downto 0) := x"3b6";
455 
  constant csr_pmpaddr7_c       : std_ulogic_vector(11 downto 0) := x"3b7";
456 
  constant csr_pmpaddr8_c       : std_ulogic_vector(11 downto 0) := x"3b8";
457 
  constant csr_pmpaddr9_c       : std_ulogic_vector(11 downto 0) := x"3b9";
458 
  constant csr_pmpaddr10_c      : std_ulogic_vector(11 downto 0) := x"3ba";
459 
  constant csr_pmpaddr11_c      : std_ulogic_vector(11 downto 0) := x"3bb";
460 
  constant csr_pmpaddr12_c      : std_ulogic_vector(11 downto 0) := x"3bc";
461 
  constant csr_pmpaddr13_c      : std_ulogic_vector(11 downto 0) := x"3bd";
462 
  constant csr_pmpaddr14_c      : std_ulogic_vector(11 downto 0) := x"3be";
463 
  constant csr_pmpaddr15_c      : std_ulogic_vector(11 downto 0) := x"3bf";
464 
  constant csr_pmpaddr16_c      : std_ulogic_vector(11 downto 0) := x"3c0";
465 
  constant csr_pmpaddr17_c      : std_ulogic_vector(11 downto 0) := x"3c1";
466 
  constant csr_pmpaddr18_c      : std_ulogic_vector(11 downto 0) := x"3c2";
467 
  constant csr_pmpaddr19_c      : std_ulogic_vector(11 downto 0) := x"3c3";
468 
  constant csr_pmpaddr20_c      : std_ulogic_vector(11 downto 0) := x"3c4";
469 
  constant csr_pmpaddr21_c      : std_ulogic_vector(11 downto 0) := x"3c5";
470 
  constant csr_pmpaddr22_c      : std_ulogic_vector(11 downto 0) := x"3c6";
471 
  constant csr_pmpaddr23_c      : std_ulogic_vector(11 downto 0) := x"3c7";
472 
  constant csr_pmpaddr24_c      : std_ulogic_vector(11 downto 0) := x"3c8";
473 
  constant csr_pmpaddr25_c      : std_ulogic_vector(11 downto 0) := x"3c9";
474 
  constant csr_pmpaddr26_c      : std_ulogic_vector(11 downto 0) := x"3ca";
475 
  constant csr_pmpaddr27_c      : std_ulogic_vector(11 downto 0) := x"3cb";
476 
  constant csr_pmpaddr28_c      : std_ulogic_vector(11 downto 0) := x"3cc";
477 
  constant csr_pmpaddr29_c      : std_ulogic_vector(11 downto 0) := x"3cd";
478 
  constant csr_pmpaddr30_c      : std_ulogic_vector(11 downto 0) := x"3ce";
479 
  constant csr_pmpaddr31_c      : std_ulogic_vector(11 downto 0) := x"3cf";
480 
  constant csr_pmpaddr32_c      : std_ulogic_vector(11 downto 0) := x"3d0";
481 
  constant csr_pmpaddr33_c      : std_ulogic_vector(11 downto 0) := x"3d1";
482 
  constant csr_pmpaddr34_c      : std_ulogic_vector(11 downto 0) := x"3d2";
483 
  constant csr_pmpaddr35_c      : std_ulogic_vector(11 downto 0) := x"3d3";
484 
  constant csr_pmpaddr36_c      : std_ulogic_vector(11 downto 0) := x"3d4";
485 
  constant csr_pmpaddr37_c      : std_ulogic_vector(11 downto 0) := x"3d5";
486 
  constant csr_pmpaddr38_c      : std_ulogic_vector(11 downto 0) := x"3d6";
487 
  constant csr_pmpaddr39_c      : std_ulogic_vector(11 downto 0) := x"3d7";
488 
  constant csr_pmpaddr40_c      : std_ulogic_vector(11 downto 0) := x"3d8";
489 
  constant csr_pmpaddr41_c      : std_ulogic_vector(11 downto 0) := x"3d9";
490 
  constant csr_pmpaddr42_c      : std_ulogic_vector(11 downto 0) := x"3da";
491 
  constant csr_pmpaddr43_c      : std_ulogic_vector(11 downto 0) := x"3db";
492 
  constant csr_pmpaddr44_c      : std_ulogic_vector(11 downto 0) := x"3dc";
493 
  constant csr_pmpaddr45_c      : std_ulogic_vector(11 downto 0) := x"3dd";
494 
  constant csr_pmpaddr46_c      : std_ulogic_vector(11 downto 0) := x"3de";
495 
  constant csr_pmpaddr47_c      : std_ulogic_vector(11 downto 0) := x"3df";
496 
  constant csr_pmpaddr48_c      : std_ulogic_vector(11 downto 0) := x"3e0";
497 
  constant csr_pmpaddr49_c      : std_ulogic_vector(11 downto 0) := x"3e1";
498 
  constant csr_pmpaddr50_c      : std_ulogic_vector(11 downto 0) := x"3e2";
499 
  constant csr_pmpaddr51_c      : std_ulogic_vector(11 downto 0) := x"3e3";
500 
  constant csr_pmpaddr52_c      : std_ulogic_vector(11 downto 0) := x"3e4";
501 
  constant csr_pmpaddr53_c      : std_ulogic_vector(11 downto 0) := x"3e5";
502 
  constant csr_pmpaddr54_c      : std_ulogic_vector(11 downto 0) := x"3e6";
503 
  constant csr_pmpaddr55_c      : std_ulogic_vector(11 downto 0) := x"3e7";
504 
  constant csr_pmpaddr56_c      : std_ulogic_vector(11 downto 0) := x"3e8";
505 
  constant csr_pmpaddr57_c      : std_ulogic_vector(11 downto 0) := x"3e9";
506 
  constant csr_pmpaddr58_c      : std_ulogic_vector(11 downto 0) := x"3ea";
507 
  constant csr_pmpaddr59_c      : std_ulogic_vector(11 downto 0) := x"3eb";
508 
  constant csr_pmpaddr60_c      : std_ulogic_vector(11 downto 0) := x"3ec";
509 
  constant csr_pmpaddr61_c      : std_ulogic_vector(11 downto 0) := x"3ed";
510 
  constant csr_pmpaddr62_c      : std_ulogic_vector(11 downto 0) := x"3ee";
511 
  constant csr_pmpaddr63_c      : std_ulogic_vector(11 downto 0) := x"3ef";
512 29 zero_gravi 
  --
513 42 zero_gravi 
  constant csr_mcycle_c         : std_ulogic_vector(11 downto 0) := x"b00";
514 
  constant csr_minstret_c       : std_ulogic_vector(11 downto 0) := x"b02";
515 
  --
516 
  constant csr_mhpmcounter3_c   : std_ulogic_vector(11 downto 0) := x"b03";
517 
  constant csr_mhpmcounter4_c   : std_ulogic_vector(11 downto 0) := x"b04";
518 
  constant csr_mhpmcounter5_c   : std_ulogic_vector(11 downto 0) := x"b05";
519 
  constant csr_mhpmcounter6_c   : std_ulogic_vector(11 downto 0) := x"b06";
520 
  constant csr_mhpmcounter7_c   : std_ulogic_vector(11 downto 0) := x"b07";
521 
  constant csr_mhpmcounter8_c   : std_ulogic_vector(11 downto 0) := x"b08";
522 
  constant csr_mhpmcounter9_c   : std_ulogic_vector(11 downto 0) := x"b09";
523 
  constant csr_mhpmcounter10_c  : std_ulogic_vector(11 downto 0) := x"b0a";
524 
  constant csr_mhpmcounter11_c  : std_ulogic_vector(11 downto 0) := x"b0b";
525 
  constant csr_mhpmcounter12_c  : std_ulogic_vector(11 downto 0) := x"b0c";
526 
  constant csr_mhpmcounter13_c  : std_ulogic_vector(11 downto 0) := x"b0d";
527 
  constant csr_mhpmcounter14_c  : std_ulogic_vector(11 downto 0) := x"b0e";
528 
  constant csr_mhpmcounter15_c  : std_ulogic_vector(11 downto 0) := x"b0f";
529 
  constant csr_mhpmcounter16_c  : std_ulogic_vector(11 downto 0) := x"b10";
530 
  constant csr_mhpmcounter17_c  : std_ulogic_vector(11 downto 0) := x"b11";
531 
  constant csr_mhpmcounter18_c  : std_ulogic_vector(11 downto 0) := x"b12";
532 
  constant csr_mhpmcounter19_c  : std_ulogic_vector(11 downto 0) := x"b13";
533 
  constant csr_mhpmcounter20_c  : std_ulogic_vector(11 downto 0) := x"b14";
534 
  constant csr_mhpmcounter21_c  : std_ulogic_vector(11 downto 0) := x"b15";
535 
  constant csr_mhpmcounter22_c  : std_ulogic_vector(11 downto 0) := x"b16";
536 
  constant csr_mhpmcounter23_c  : std_ulogic_vector(11 downto 0) := x"b17";
537 
  constant csr_mhpmcounter24_c  : std_ulogic_vector(11 downto 0) := x"b18";
538 
  constant csr_mhpmcounter25_c  : std_ulogic_vector(11 downto 0) := x"b19";
539 
  constant csr_mhpmcounter26_c  : std_ulogic_vector(11 downto 0) := x"b1a";
540 
  constant csr_mhpmcounter27_c  : std_ulogic_vector(11 downto 0) := x"b1b";
541 
  constant csr_mhpmcounter28_c  : std_ulogic_vector(11 downto 0) := x"b1c";
542 
  constant csr_mhpmcounter29_c  : std_ulogic_vector(11 downto 0) := x"b1d";
543 
  constant csr_mhpmcounter30_c  : std_ulogic_vector(11 downto 0) := x"b1e";
544 
  constant csr_mhpmcounter31_c  : std_ulogic_vector(11 downto 0) := x"b1f";
545 
  --
546 
  constant csr_mcycleh_c        : std_ulogic_vector(11 downto 0) := x"b80";
547 
  constant csr_minstreth_c      : std_ulogic_vector(11 downto 0) := x"b82";
548 
  --
549 
  constant csr_mhpmcounter3h_c  : std_ulogic_vector(11 downto 0) := x"b83";
550 
  constant csr_mhpmcounter4h_c  : std_ulogic_vector(11 downto 0) := x"b84";
551 
  constant csr_mhpmcounter5h_c  : std_ulogic_vector(11 downto 0) := x"b85";
552 
  constant csr_mhpmcounter6h_c  : std_ulogic_vector(11 downto 0) := x"b86";
553 
  constant csr_mhpmcounter7h_c  : std_ulogic_vector(11 downto 0) := x"b87";
554 
  constant csr_mhpmcounter8h_c  : std_ulogic_vector(11 downto 0) := x"b88";
555 
  constant csr_mhpmcounter9h_c  : std_ulogic_vector(11 downto 0) := x"b89";
556 
  constant csr_mhpmcounter10h_c : std_ulogic_vector(11 downto 0) := x"b8a";
557 
  constant csr_mhpmcounter11h_c : std_ulogic_vector(11 downto 0) := x"b8b";
558 
  constant csr_mhpmcounter12h_c : std_ulogic_vector(11 downto 0) := x"b8c";
559 
  constant csr_mhpmcounter13h_c : std_ulogic_vector(11 downto 0) := x"b8d";
560 
  constant csr_mhpmcounter14h_c : std_ulogic_vector(11 downto 0) := x"b8e";
561 
  constant csr_mhpmcounter15h_c : std_ulogic_vector(11 downto 0) := x"b8f";
562 
  constant csr_mhpmcounter16h_c : std_ulogic_vector(11 downto 0) := x"b90";
563 
  constant csr_mhpmcounter17h_c : std_ulogic_vector(11 downto 0) := x"b91";
564 
  constant csr_mhpmcounter18h_c : std_ulogic_vector(11 downto 0) := x"b92";
565 
  constant csr_mhpmcounter19h_c : std_ulogic_vector(11 downto 0) := x"b93";
566 
  constant csr_mhpmcounter20h_c : std_ulogic_vector(11 downto 0) := x"b94";
567 
  constant csr_mhpmcounter21h_c : std_ulogic_vector(11 downto 0) := x"b95";
568 
  constant csr_mhpmcounter22h_c : std_ulogic_vector(11 downto 0) := x"b96";
569 
  constant csr_mhpmcounter23h_c : std_ulogic_vector(11 downto 0) := x"b97";
570 
  constant csr_mhpmcounter24h_c : std_ulogic_vector(11 downto 0) := x"b98";
571 
  constant csr_mhpmcounter25h_c : std_ulogic_vector(11 downto 0) := x"b99";
572 
  constant csr_mhpmcounter26h_c : std_ulogic_vector(11 downto 0) := x"b9a";
573 
  constant csr_mhpmcounter27h_c : std_ulogic_vector(11 downto 0) := x"b9b";
574 
  constant csr_mhpmcounter28h_c : std_ulogic_vector(11 downto 0) := x"b9c";
575 
  constant csr_mhpmcounter29h_c : std_ulogic_vector(11 downto 0) := x"b9d";
576 
  constant csr_mhpmcounter30h_c : std_ulogic_vector(11 downto 0) := x"b9e";
577 
  constant csr_mhpmcounter31h_c : std_ulogic_vector(11 downto 0) := x"b9f";
578 
 
579 41 zero_gravi 
  -- read-only CSRs --
580 42 zero_gravi 
  constant csr_cycle_c          : std_ulogic_vector(11 downto 0) := x"c00";
581 
  constant csr_time_c           : std_ulogic_vector(11 downto 0) := x"c01";
582 
  constant csr_instret_c        : std_ulogic_vector(11 downto 0) := x"c02";
583 29 zero_gravi 
  --
584 42 zero_gravi 
  constant csr_hpmcounter3_c    : std_ulogic_vector(11 downto 0) := x"c03";
585 
  constant csr_hpmcounter4_c    : std_ulogic_vector(11 downto 0) := x"c04";
586 
  constant csr_hpmcounter5_c    : std_ulogic_vector(11 downto 0) := x"c05";
587 
  constant csr_hpmcounter6_c    : std_ulogic_vector(11 downto 0) := x"c06";
588 
  constant csr_hpmcounter7_c    : std_ulogic_vector(11 downto 0) := x"c07";
589 
  constant csr_hpmcounter8_c    : std_ulogic_vector(11 downto 0) := x"c08";
590 
  constant csr_hpmcounter9_c    : std_ulogic_vector(11 downto 0) := x"c09";
591 
  constant csr_hpmcounter10_c   : std_ulogic_vector(11 downto 0) := x"c0a";
592 
  constant csr_hpmcounter11_c   : std_ulogic_vector(11 downto 0) := x"c0b";
593 
  constant csr_hpmcounter12_c   : std_ulogic_vector(11 downto 0) := x"c0c";
594 
  constant csr_hpmcounter13_c   : std_ulogic_vector(11 downto 0) := x"c0d";
595 
  constant csr_hpmcounter14_c   : std_ulogic_vector(11 downto 0) := x"c0e";
596 
  constant csr_hpmcounter15_c   : std_ulogic_vector(11 downto 0) := x"c0f";
597 
  constant csr_hpmcounter16_c   : std_ulogic_vector(11 downto 0) := x"c10";
598 
  constant csr_hpmcounter17_c   : std_ulogic_vector(11 downto 0) := x"c11";
599 
  constant csr_hpmcounter18_c   : std_ulogic_vector(11 downto 0) := x"c12";
600 
  constant csr_hpmcounter19_c   : std_ulogic_vector(11 downto 0) := x"c13";
601 
  constant csr_hpmcounter20_c   : std_ulogic_vector(11 downto 0) := x"c14";
602 
  constant csr_hpmcounter21_c   : std_ulogic_vector(11 downto 0) := x"c15";
603 
  constant csr_hpmcounter22_c   : std_ulogic_vector(11 downto 0) := x"c16";
604 
  constant csr_hpmcounter23_c   : std_ulogic_vector(11 downto 0) := x"c17";
605 
  constant csr_hpmcounter24_c   : std_ulogic_vector(11 downto 0) := x"c18";
606 
  constant csr_hpmcounter25_c   : std_ulogic_vector(11 downto 0) := x"c19";
607 
  constant csr_hpmcounter26_c   : std_ulogic_vector(11 downto 0) := x"c1a";
608 
  constant csr_hpmcounter27_c   : std_ulogic_vector(11 downto 0) := x"c1b";
609 
  constant csr_hpmcounter28_c   : std_ulogic_vector(11 downto 0) := x"c1c";
610 
  constant csr_hpmcounter29_c   : std_ulogic_vector(11 downto 0) := x"c1d";
611 
  constant csr_hpmcounter30_c   : std_ulogic_vector(11 downto 0) := x"c1e";
612 
  constant csr_hpmcounter31_c   : std_ulogic_vector(11 downto 0) := x"c1f";
613 29 zero_gravi 
  --
614 42 zero_gravi 
  constant csr_cycleh_c         : std_ulogic_vector(11 downto 0) := x"c80";
615 
  constant csr_timeh_c          : std_ulogic_vector(11 downto 0) := x"c81";
616 
  constant csr_instreth_c       : std_ulogic_vector(11 downto 0) := x"c82";
617 29 zero_gravi 
  --
618 42 zero_gravi 
  constant csr_hpmcounter3h_c   : std_ulogic_vector(11 downto 0) := x"c83";
619 
  constant csr_hpmcounter4h_c   : std_ulogic_vector(11 downto 0) := x"c84";
620 
  constant csr_hpmcounter5h_c   : std_ulogic_vector(11 downto 0) := x"c85";
621 
  constant csr_hpmcounter6h_c   : std_ulogic_vector(11 downto 0) := x"c86";
622 
  constant csr_hpmcounter7h_c   : std_ulogic_vector(11 downto 0) := x"c87";
623 
  constant csr_hpmcounter8h_c   : std_ulogic_vector(11 downto 0) := x"c88";
624 
  constant csr_hpmcounter9h_c   : std_ulogic_vector(11 downto 0) := x"c89";
625 
  constant csr_hpmcounter10h_c  : std_ulogic_vector(11 downto 0) := x"c8a";
626 
  constant csr_hpmcounter11h_c  : std_ulogic_vector(11 downto 0) := x"c8b";
627 
  constant csr_hpmcounter12h_c  : std_ulogic_vector(11 downto 0) := x"c8c";
628 
  constant csr_hpmcounter13h_c  : std_ulogic_vector(11 downto 0) := x"c8d";
629 
  constant csr_hpmcounter14h_c  : std_ulogic_vector(11 downto 0) := x"c8e";
630 
  constant csr_hpmcounter15h_c  : std_ulogic_vector(11 downto 0) := x"c8f";
631 
  constant csr_hpmcounter16h_c  : std_ulogic_vector(11 downto 0) := x"c90";
632 
  constant csr_hpmcounter17h_c  : std_ulogic_vector(11 downto 0) := x"c91";
633 
  constant csr_hpmcounter18h_c  : std_ulogic_vector(11 downto 0) := x"c92";
634 
  constant csr_hpmcounter19h_c  : std_ulogic_vector(11 downto 0) := x"c93";
635 
  constant csr_hpmcounter20h_c  : std_ulogic_vector(11 downto 0) := x"c94";
636 
  constant csr_hpmcounter21h_c  : std_ulogic_vector(11 downto 0) := x"c95";
637 
  constant csr_hpmcounter22h_c  : std_ulogic_vector(11 downto 0) := x"c96";
638 
  constant csr_hpmcounter23h_c  : std_ulogic_vector(11 downto 0) := x"c97";
639 
  constant csr_hpmcounter24h_c  : std_ulogic_vector(11 downto 0) := x"c98";
640 
  constant csr_hpmcounter25h_c  : std_ulogic_vector(11 downto 0) := x"c99";
641 
  constant csr_hpmcounter26h_c  : std_ulogic_vector(11 downto 0) := x"c9a";
642 
  constant csr_hpmcounter27h_c  : std_ulogic_vector(11 downto 0) := x"c9b";
643 
  constant csr_hpmcounter28h_c  : std_ulogic_vector(11 downto 0) := x"c9c";
644 
  constant csr_hpmcounter29h_c  : std_ulogic_vector(11 downto 0) := x"c9d";
645 
  constant csr_hpmcounter30h_c  : std_ulogic_vector(11 downto 0) := x"c9e";
646 
  constant csr_hpmcounter31h_c  : std_ulogic_vector(11 downto 0) := x"c9f";
647 
  --
648 
  constant csr_mvendorid_c      : std_ulogic_vector(11 downto 0) := x"f11";
649 
  constant csr_marchid_c        : std_ulogic_vector(11 downto 0) := x"f12";
650 
  constant csr_mimpid_c         : std_ulogic_vector(11 downto 0) := x"f13";
651 
  constant csr_mhartid_c        : std_ulogic_vector(11 downto 0) := x"f14";
652 29 zero_gravi 
 
653 42 zero_gravi 
  -- custom read-only CSRs --
654 
  constant csr_mzext_c          : std_ulogic_vector(11 downto 0) := x"fc0";
655 
 
656 44 zero_gravi 
  -- Co-Processor IDs -----------------------------------------------------------------------
657 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
658 44 zero_gravi 
  constant cp_sel_muldiv_c   : std_ulogic_vector(1 downto 0) := "00"; -- multiplication/division operations ('M' extension)
659 
  constant cp_sel_atomic_c   : std_ulogic_vector(1 downto 0) := "01"; -- atomic operations; success/failure evaluation ('A' extension)
660 
  constant cp_sel_bitmanip_c : std_ulogic_vector(1 downto 0) := "10"; -- bit manipulation ('B' extension)
661 
--constant cp_sel_float32_c  : std_ulogic_vector(1 downto 0) := "11"; -- reserved -- single-precision floating point operations ('F' extension)
662 2 zero_gravi 
 
663 
  -- ALU Function Codes ---------------------------------------------------------------------
664 
  -- -------------------------------------------------------------------------------------------
665 39 zero_gravi 
  -- arithmetic core --
666 
  constant alu_arith_cmd_addsub_c : std_ulogic := '0'; -- r.arith <= A +/- B
667 
  constant alu_arith_cmd_slt_c    : std_ulogic := '1'; -- r.arith <= A < B
668 
  -- logic core --
669 
  constant alu_logic_cmd_movb_c   : std_ulogic_vector(1 downto 0) := "00"; -- r.logic <= B
670 
  constant alu_logic_cmd_xor_c    : std_ulogic_vector(1 downto 0) := "01"; -- r.logic <= A xor B
671 
  constant alu_logic_cmd_or_c     : std_ulogic_vector(1 downto 0) := "10"; -- r.logic <= A or B
672 
  constant alu_logic_cmd_and_c    : std_ulogic_vector(1 downto 0) := "11"; -- r.logic <= A and B
673 
  -- function select (actual alu result) --
674 
  constant alu_func_cmd_arith_c   : std_ulogic_vector(1 downto 0) := "00"; -- r <= r.arith
675 
  constant alu_func_cmd_logic_c   : std_ulogic_vector(1 downto 0) := "01"; -- r <= r.logic
676 
  constant alu_func_cmd_shift_c   : std_ulogic_vector(1 downto 0) := "10"; -- r <= A <</>> B (iterative)
677 
  constant alu_func_cmd_copro_c   : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (iterative)
678 2 zero_gravi 
 
679 12 zero_gravi 
  -- Trap ID Codes --------------------------------------------------------------------------
680 
  -- -------------------------------------------------------------------------------------------
681 39 zero_gravi 
  -- RISC-V compliant exceptions --
682 
  constant trap_ima_c   : std_ulogic_vector(5 downto 0) := "0" & "00000"; -- 0.0:  instruction misaligned
683 
  constant trap_iba_c   : std_ulogic_vector(5 downto 0) := "0" & "00001"; -- 0.1:  instruction access fault
684 
  constant trap_iil_c   : std_ulogic_vector(5 downto 0) := "0" & "00010"; -- 0.2:  illegal instruction
685 
  constant trap_brk_c   : std_ulogic_vector(5 downto 0) := "0" & "00011"; -- 0.3:  breakpoint
686 
  constant trap_lma_c   : std_ulogic_vector(5 downto 0) := "0" & "00100"; -- 0.4:  load address misaligned
687 
  constant trap_lbe_c   : std_ulogic_vector(5 downto 0) := "0" & "00101"; -- 0.5:  load access fault
688 
  constant trap_sma_c   : std_ulogic_vector(5 downto 0) := "0" & "00110"; -- 0.6:  store address misaligned
689 
  constant trap_sbe_c   : std_ulogic_vector(5 downto 0) := "0" & "00111"; -- 0.7:  store access fault
690 40 zero_gravi 
  constant trap_uenv_c  : std_ulogic_vector(5 downto 0) := "0" & "01000"; -- 0.8:  environment call from u-mode
691 39 zero_gravi 
  constant trap_menv_c  : std_ulogic_vector(5 downto 0) := "0" & "01011"; -- 0.11: environment call from m-mode
692 
  -- RISC-V compliant interrupts --
693 
  constant trap_msi_c   : std_ulogic_vector(5 downto 0) := "1" & "00011"; -- 1.3:  machine software interrupt
694 
  constant trap_mti_c   : std_ulogic_vector(5 downto 0) := "1" & "00111"; -- 1.7:  machine timer interrupt
695 
  constant trap_mei_c   : std_ulogic_vector(5 downto 0) := "1" & "01011"; -- 1.11: machine external interrupt
696 
  -- NEORV32-specific (custom) interrupts --
697 40 zero_gravi 
  constant trap_reset_c : std_ulogic_vector(5 downto 0) := "1" & "00000"; -- 1.0:  hardware reset
698 39 zero_gravi 
  constant trap_firq0_c : std_ulogic_vector(5 downto 0) := "1" & "10000"; -- 1.16: fast interrupt 0
699 
  constant trap_firq1_c : std_ulogic_vector(5 downto 0) := "1" & "10001"; -- 1.17: fast interrupt 1
700 
  constant trap_firq2_c : std_ulogic_vector(5 downto 0) := "1" & "10010"; -- 1.18: fast interrupt 2
701 
  constant trap_firq3_c : std_ulogic_vector(5 downto 0) := "1" & "10011"; -- 1.19: fast interrupt 3
702 47 zero_gravi 
  constant trap_firq4_c : std_ulogic_vector(5 downto 0) := "1" & "10100"; -- 1.20: fast interrupt 4
703 
  constant trap_firq5_c : std_ulogic_vector(5 downto 0) := "1" & "10101"; -- 1.21: fast interrupt 5
704 
  constant trap_firq6_c : std_ulogic_vector(5 downto 0) := "1" & "10110"; -- 1.22: fast interrupt 6
705 
  constant trap_firq7_c : std_ulogic_vector(5 downto 0) := "1" & "10111"; -- 1.23: fast interrupt 7
706 12 zero_gravi 
 
707 2 zero_gravi 
  -- CPU Control Exception System -----------------------------------------------------------
708 
  -- -------------------------------------------------------------------------------------------
709 
  -- exception source bits --
710 47 zero_gravi 
  constant exception_iaccess_c   : natural :=  0; -- instrution access fault
711 
  constant exception_iillegal_c  : natural :=  1; -- illegal instrution
712 
  constant exception_ialign_c    : natural :=  2; -- instrution address misaligned
713 
  constant exception_m_envcall_c : natural :=  3; -- ENV call from m-mode
714 
  constant exception_u_envcall_c : natural :=  4; -- ENV call from u-mode
715 
  constant exception_break_c     : natural :=  5; -- breakpoint
716 
  constant exception_salign_c    : natural :=  6; -- store address misaligned
717 
  constant exception_lalign_c    : natural :=  7; -- load address misaligned
718 
  constant exception_saccess_c   : natural :=  8; -- store access fault
719 
  constant exception_laccess_c   : natural :=  9; -- load access fault
720 14 zero_gravi 
  --
721 40 zero_gravi 
  constant exception_width_c     : natural := 10; -- length of this list in bits
722 2 zero_gravi 
  -- interrupt source bits --
723 47 zero_gravi 
  constant interrupt_msw_irq_c   : natural :=  0; -- machine software interrupt
724 
  constant interrupt_mtime_irq_c : natural :=  1; -- machine timer interrupt
725 
  constant interrupt_mext_irq_c  : natural :=  2; -- machine external interrupt
726 
  constant interrupt_firq_0_c    : natural :=  3; -- fast interrupt channel 0
727 
  constant interrupt_firq_1_c    : natural :=  4; -- fast interrupt channel 1
728 
  constant interrupt_firq_2_c    : natural :=  5; -- fast interrupt channel 2
729 
  constant interrupt_firq_3_c    : natural :=  6; -- fast interrupt channel 3
730 
  constant interrupt_firq_4_c    : natural :=  7; -- fast interrupt channel 4
731 
  constant interrupt_firq_5_c    : natural :=  8; -- fast interrupt channel 5
732 
  constant interrupt_firq_6_c    : natural :=  9; -- fast interrupt channel 6
733 
  constant interrupt_firq_7_c    : natural := 10; -- fast interrupt channel 7
734 14 zero_gravi 
  --
735 47 zero_gravi 
  constant interrupt_width_c     : natural := 11; -- length of this list in bits
736 2 zero_gravi 
 
737 15 zero_gravi 
  -- CPU Privilege Modes --------------------------------------------------------------------
738 
  -- -------------------------------------------------------------------------------------------
739 29 zero_gravi 
  constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
740 
  constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
741 15 zero_gravi 
 
742 42 zero_gravi 
  -- HPM Event System -----------------------------------------------------------------------
743 
  -- -------------------------------------------------------------------------------------------
744 
  constant hpmcnt_event_cy_c      : natural := 0;  -- Active cycle
745 
  constant hpmcnt_event_never_c   : natural := 1;
746 
  constant hpmcnt_event_ir_c      : natural := 2;  -- Retired instruction
747 
  constant hpmcnt_event_cir_c     : natural := 3;  -- Retired compressed instruction
748 
  constant hpmcnt_event_wait_if_c : natural := 4;  -- Instruction fetch memory wait cycle
749 
  constant hpmcnt_event_wait_ii_c : natural := 5;  -- Instruction issue wait cycle
750 45 zero_gravi 
  constant hpmcnt_event_wait_mc_c : natural := 6;  -- Multi-cycle ALU-operation wait cycle
751 
  constant hpmcnt_event_load_c    : natural := 7;  -- Load operation
752 
  constant hpmcnt_event_store_c   : natural := 8;  -- Store operation
753 
  constant hpmcnt_event_wait_ls_c : natural := 9;  -- Load/store memory wait cycle
754 
  constant hpmcnt_event_jump_c    : natural := 10; -- Unconditional jump
755 
  constant hpmcnt_event_branch_c  : natural := 11; -- Conditional branch (taken or not taken)
756 
  constant hpmcnt_event_tbranch_c : natural := 12; -- Conditional taken branch
757 
  constant hpmcnt_event_trap_c    : natural := 13; -- Entered trap
758 
  constant hpmcnt_event_illegal_c : natural := 14; -- Illegal instruction exception
759 42 zero_gravi 
  --
760 45 zero_gravi 
  constant hpmcnt_event_size_c    : natural := 15; -- length of this list
761 42 zero_gravi 
 
762 39 zero_gravi 
  -- Clock Generator ------------------------------------------------------------------------
763 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
764 
  constant clk_div2_c    : natural := 0;
765 
  constant clk_div4_c    : natural := 1;
766 
  constant clk_div8_c    : natural := 2;
767 
  constant clk_div64_c   : natural := 3;
768 
  constant clk_div128_c  : natural := 4;
769 
  constant clk_div1024_c : natural := 5;
770 
  constant clk_div2048_c : natural := 6;
771 
  constant clk_div4096_c : natural := 7;
772 
 
773 
  -- Component: NEORV32 Processor Top Entity ------------------------------------------------
774 
  -- -------------------------------------------------------------------------------------------
775 
  component neorv32_top
776 
    generic (
777 
      -- General --
778 12 zero_gravi 
      CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz
779 44 zero_gravi 
      BOOTLOADER_EN                : boolean := true;   -- implement processor-internal bootloader?
780 12 zero_gravi 
      USER_CODE                    : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
781 36 zero_gravi 
      HW_THREAD_ID                 : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id (hartid)
782 2 zero_gravi 
      -- RISC-V CPU Extensions --
783 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false;  -- implement atomic extension?
784 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false;  -- implement bit manipulation extensions?
785 18 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?
786 8 zero_gravi 
      CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
787 18 zero_gravi 
      CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement muld/div extension?
788 
      CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?
789 8 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?
790 39 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false;  -- implement instruction stream sync.?
791 19 zero_gravi 
      -- Extension Options --
792 34 zero_gravi 
      FAST_MUL_EN                  : boolean := false;  -- use DSPs for M extension's multiplier
793 
      FAST_SHIFT_EN                : boolean := false;  -- use barrel shifter for shift operations
794 15 zero_gravi 
      -- Physical Memory Protection (PMP) --
795 42 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0;      -- number of regions (0..64)
796 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
797 
      -- Hardware Performance Monitors (HPM) --
798 47 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0;      -- number of implemented HPM counters (0..29)
799 23 zero_gravi 
      -- Internal Instruction memory --
800 44 zero_gravi 
      MEM_INT_IMEM_EN              : boolean := true;   -- implement processor-internal instruction memory
801 8 zero_gravi 
      MEM_INT_IMEM_SIZE            : natural := 16*1024; -- size of processor-internal instruction memory in bytes
802 34 zero_gravi 
      MEM_INT_IMEM_ROM             : boolean := false;  -- implement processor-internal instruction memory as ROM
803 23 zero_gravi 
      -- Internal Data memory --
804 44 zero_gravi 
      MEM_INT_DMEM_EN              : boolean := true;   -- implement processor-internal data memory
805 8 zero_gravi 
      MEM_INT_DMEM_SIZE            : natural := 8*1024; -- size of processor-internal data memory in bytes
806 41 zero_gravi 
      -- Internal Cache memory --
807 44 zero_gravi 
      ICACHE_EN                    : boolean := false;  -- implement instruction cache
808 41 zero_gravi 
      ICACHE_NUM_BLOCKS            : natural := 4;      -- i-cache: number of blocks (min 1), has to be a power of 2
809 
      ICACHE_BLOCK_SIZE            : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
810 45 zero_gravi 
      ICACHE_ASSOCIATIVITY         : natural := 1;      -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
811 23 zero_gravi 
      -- External memory interface --
812 44 zero_gravi 
      MEM_EXT_EN                   : boolean := false;  -- implement external memory bus interface?
813 2 zero_gravi 
      -- Processor peripherals --
814 44 zero_gravi 
      IO_GPIO_EN                   : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
815 
      IO_MTIME_EN                  : boolean := true;   -- implement machine system timer (MTIME)?
816 
      IO_UART_EN                   : boolean := true;   -- implement universal asynchronous receiver/transmitter (UART)?
817 
      IO_SPI_EN                    : boolean := true;   -- implement serial peripheral interface (SPI)?
818 
      IO_TWI_EN                    : boolean := true;   -- implement two-wire interface (TWI)?
819 
      IO_PWM_EN                    : boolean := true;   -- implement pulse-width modulation unit (PWM)?
820 
      IO_WDT_EN                    : boolean := true;   -- implement watch dog timer (WDT)?
821 
      IO_TRNG_EN                   : boolean := false;  -- implement true random number generator (TRNG)?
822 47 zero_gravi 
      IO_CFS_EN                    : boolean := false;  -- implement custom functions subsystem (CFS)?
823 
      IO_CFS_CONFIG                : std_ulogic_vector(31 downto 0) := (others => '0') -- custom CFS configuration generic
824 2 zero_gravi 
    );
825 
    port (
826 
      -- Global control --
827 34 zero_gravi 
      clk_i       : in  std_ulogic := '0'; -- global clock, rising edge
828 
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
829 2 zero_gravi 
      -- Wishbone bus interface --
830 36 zero_gravi 
      wb_tag_o    : out std_ulogic_vector(02 downto 0); -- tag
831 34 zero_gravi 
      wb_adr_o    : out std_ulogic_vector(31 downto 0); -- address
832 
      wb_dat_i    : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
833 
      wb_dat_o    : out std_ulogic_vector(31 downto 0); -- write data
834 
      wb_we_o     : out std_ulogic; -- read/write
835 
      wb_sel_o    : out std_ulogic_vector(03 downto 0); -- byte enable
836 
      wb_stb_o    : out std_ulogic; -- strobe
837 
      wb_cyc_o    : out std_ulogic; -- valid cycle
838 39 zero_gravi 
      wb_lock_o   : out std_ulogic; -- locked/exclusive bus access
839 34 zero_gravi 
      wb_ack_i    : in  std_ulogic := '0'; -- transfer acknowledge
840 
      wb_err_i    : in  std_ulogic := '0'; -- transfer error
841 44 zero_gravi 
      -- Advanced memory control signals (available if MEM_EXT_EN = true) --
842 34 zero_gravi 
      fence_o     : out std_ulogic; -- indicates an executed FENCE operation
843 
      fencei_o    : out std_ulogic; -- indicates an executed FENCEI operation
844 2 zero_gravi 
      -- GPIO --
845 34 zero_gravi 
      gpio_o      : out std_ulogic_vector(31 downto 0); -- parallel output
846 
      gpio_i      : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
847 2 zero_gravi 
      -- UART --
848 34 zero_gravi 
      uart_txd_o  : out std_ulogic; -- UART send data
849 
      uart_rxd_i  : in  std_ulogic := '0'; -- UART receive data
850 2 zero_gravi 
      -- SPI --
851 34 zero_gravi 
      spi_sck_o   : out std_ulogic; -- SPI serial clock
852 
      spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
853 
      spi_sdi_i   : in  std_ulogic := '0'; -- controller data in, peripheral data out
854 
      spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
855 2 zero_gravi 
      -- TWI --
856 35 zero_gravi 
      twi_sda_io  : inout std_logic; -- twi serial data line
857 
      twi_scl_io  : inout std_logic; -- twi serial clock line
858 2 zero_gravi 
      -- PWM --
859 40 zero_gravi 
      pwm_o       : out std_ulogic_vector(03 downto 0); -- pwm channels
860 47 zero_gravi 
      -- Custom Functions Subsystem IO --
861 
      cfs_in_i    : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- custom CSF inputs
862 
      cfs_out_o   : out std_ulogic_vector(31 downto 0); -- custom CSF outputs
863 44 zero_gravi 
      -- system time input from external MTIME (available if IO_MTIME_EN = false) --
864 40 zero_gravi 
      mtime_i     : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
865 2 zero_gravi 
      -- Interrupts --
866 47 zero_gravi 
      soc_firq_i  : in  std_ulogic_vector(3 downto 0) := (others => '0'); -- fast interrupt channels
867 44 zero_gravi 
      mtime_irq_i : in  std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
868 34 zero_gravi 
      msw_irq_i   : in  std_ulogic := '0'; -- machine software interrupt
869 
      mext_irq_i  : in  std_ulogic := '0'  -- machine external interrupt
870 2 zero_gravi 
    );
871 
  end component;
872 
 
873 4 zero_gravi 
  -- Component: CPU Top Entity --------------------------------------------------------------
874 
  -- -------------------------------------------------------------------------------------------
875 
  component neorv32_cpu
876 
    generic (
877 
      -- General --
878 36 zero_gravi 
      HW_THREAD_ID                 : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id
879 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0) := (others => '0'); -- cpu boot address
880 41 zero_gravi 
      BUS_TIMEOUT                  : natural := 63;    -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
881 4 zero_gravi 
      -- RISC-V CPU Extensions --
882 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
883 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
884 12 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
885 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
886 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
887 15 zero_gravi 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
888 12 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
889 
      CPU_EXTENSION_RISCV_Zifencei : boolean := true;  -- implement instruction stream sync.?
890 19 zero_gravi 
      -- Extension Options --
891 
      FAST_MUL_EN                  : boolean := false; -- use DSPs for M extension's multiplier
892 34 zero_gravi 
      FAST_SHIFT_EN                : boolean := false; -- use barrel shifter for shift operations
893 15 zero_gravi 
      -- Physical Memory Protection (PMP) --
894 42 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0; -- number of regions (0..64)
895 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
896 
      -- Hardware Performance Monitors (HPM) --
897 47 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0      -- number of implemented HPM counters (0..29)
898 4 zero_gravi 
    );
899 
    port (
900 
      -- global control --
901 14 zero_gravi 
      clk_i          : in  std_ulogic := '0'; -- global clock, rising edge
902 
      rstn_i         : in  std_ulogic := '0'; -- global reset, low-active, async
903 47 zero_gravi 
      sleep_o        : out std_ulogic; -- cpu is in sleep mode when set
904 12 zero_gravi 
      -- instruction bus interface --
905 
      i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
906 14 zero_gravi 
      i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
907 12 zero_gravi 
      i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
908 
      i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
909 
      i_bus_we_o     : out std_ulogic; -- write enable
910 
      i_bus_re_o     : out std_ulogic; -- read enable
911 
      i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
912 14 zero_gravi 
      i_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
913 
      i_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
914 12 zero_gravi 
      i_bus_fence_o  : out std_ulogic; -- executed FENCEI operation
915 35 zero_gravi 
      i_bus_priv_o   : out std_ulogic_vector(1 downto 0); -- privilege level
916 39 zero_gravi 
      i_bus_lock_o   : out std_ulogic; -- locked/exclusive access
917 12 zero_gravi 
      -- data bus interface --
918 
      d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
919 14 zero_gravi 
      d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
920 12 zero_gravi 
      d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
921 
      d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
922 
      d_bus_we_o     : out std_ulogic; -- write enable
923 
      d_bus_re_o     : out std_ulogic; -- read enable
924 
      d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
925 14 zero_gravi 
      d_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
926 
      d_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
927 12 zero_gravi 
      d_bus_fence_o  : out std_ulogic; -- executed FENCE operation
928 35 zero_gravi 
      d_bus_priv_o   : out std_ulogic_vector(1 downto 0); -- privilege level
929 39 zero_gravi 
      d_bus_lock_o   : out std_ulogic; -- locked/exclusive access
930 11 zero_gravi 
      -- system time input from MTIME --
931 14 zero_gravi 
      time_i         : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
932 
      -- interrupts (risc-v compliant) --
933 
      msw_irq_i      : in  std_ulogic := '0'; -- machine software interrupt
934 
      mext_irq_i     : in  std_ulogic := '0'; -- machine external interrupt
935 
      mtime_irq_i    : in  std_ulogic := '0'; -- machine timer interrupt
936 
      -- fast interrupts (custom) --
937 47 zero_gravi 
      firq_i         : in  std_ulogic_vector(7 downto 0) := (others => '0');
938 
      firq_ack_o     : out std_ulogic_vector(7 downto 0)
939 4 zero_gravi 
    );
940 
  end component;
941 
 
942 2 zero_gravi 
  -- Component: CPU Control -----------------------------------------------------------------
943 
  -- -------------------------------------------------------------------------------------------
944 
  component neorv32_cpu_control
945 
    generic (
946 
      -- General --
947 12 zero_gravi 
      HW_THREAD_ID                 : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
948 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
949 2 zero_gravi 
      -- RISC-V CPU Extensions --
950 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
951 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
952 12 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
953 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
954 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
955 15 zero_gravi 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
956 12 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
957 15 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := true;  -- implement instruction stream sync.?
958 
      -- Physical memory protection (PMP) --
959 42 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0; -- number of regions (0..64)
960 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
961 
      -- Hardware Performance Monitors (HPM) --
962 47 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0      -- number of implemented HPM counters (0..29)
963 2 zero_gravi 
    );
964 
    port (
965 
      -- global control --
966 
      clk_i         : in  std_ulogic; -- global clock, rising edge
967 
      rstn_i        : in  std_ulogic; -- global reset, low-active, async
968 
      ctrl_o        : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
969 
      -- status input --
970 
      alu_wait_i    : in  std_ulogic; -- wait for ALU
971 12 zero_gravi 
      bus_i_wait_i  : in  std_ulogic; -- wait for bus
972 
      bus_d_wait_i  : in  std_ulogic; -- wait for bus
973 2 zero_gravi 
      -- data input --
974 
      instr_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- instruction
975 
      cmp_i         : in  std_ulogic_vector(1 downto 0); -- comparator status
976 36 zero_gravi 
      alu_add_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result
977 
      rs1_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
978 2 zero_gravi 
      -- data output --
979 
      imm_o         : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
980 6 zero_gravi 
      fetch_pc_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
981 
      curr_pc_o     : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
982 2 zero_gravi 
      csr_rdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
983 14 zero_gravi 
      -- interrupts (risc-v compliant) --
984 
      msw_irq_i     : in  std_ulogic; -- machine software interrupt
985 
      mext_irq_i    : in  std_ulogic; -- machine external interrupt
986 2 zero_gravi 
      mtime_irq_i   : in  std_ulogic; -- machine timer interrupt
987 14 zero_gravi 
      -- fast interrupts (custom) --
988 47 zero_gravi 
      firq_i        : in  std_ulogic_vector(7 downto 0);
989 
      firq_ack_o    : out std_ulogic_vector(7 downto 0);
990 11 zero_gravi 
      -- system time input from MTIME --
991 
      time_i        : in  std_ulogic_vector(63 downto 0); -- current system time
992 15 zero_gravi 
      -- physical memory protection --
993 
      pmp_addr_o    : out pmp_addr_if_t; -- addresses
994 
      pmp_ctrl_o    : out pmp_ctrl_if_t; -- configs
995 2 zero_gravi 
      -- bus access exceptions --
996 
      mar_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
997 
      ma_instr_i    : in  std_ulogic; -- misaligned instruction address
998 
      ma_load_i     : in  std_ulogic; -- misaligned load data address
999 
      ma_store_i    : in  std_ulogic; -- misaligned store data address
1000 
      be_instr_i    : in  std_ulogic; -- bus error on instruction access
1001 
      be_load_i     : in  std_ulogic; -- bus error on load data access
1002 12 zero_gravi 
      be_store_i    : in  std_ulogic  -- bus error on store data access
1003 2 zero_gravi 
    );
1004 
  end component;
1005 
 
1006 
  -- Component: CPU Register File -----------------------------------------------------------
1007 
  -- -------------------------------------------------------------------------------------------
1008 
  component neorv32_cpu_regfile
1009 
    generic (
1010 
      CPU_EXTENSION_RISCV_E : boolean := false -- implement embedded RF extension?
1011 
    );
1012 
    port (
1013 
      -- global control --
1014 
      clk_i  : in  std_ulogic; -- global clock, rising edge
1015 
      ctrl_i : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1016 
      -- data input --
1017 
      mem_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
1018 
      alu_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
1019 
      csr_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
1020 
      -- data output --
1021 
      rs1_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
1022 47 zero_gravi 
      rs2_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 2
1023 
      cmp_o  : out std_ulogic_vector(1 downto 0) -- comparator status
1024 2 zero_gravi 
    );
1025 
  end component;
1026 
 
1027 
  -- Component: CPU ALU ---------------------------------------------------------------------
1028 
  -- -------------------------------------------------------------------------------------------
1029 
  component neorv32_cpu_alu
1030 11 zero_gravi 
    generic (
1031 34 zero_gravi 
      CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
1032 
      FAST_SHIFT_EN         : boolean := false -- use barrel shifter for shift operations
1033 11 zero_gravi 
    );
1034 2 zero_gravi 
    port (
1035 
      -- global control --
1036 
      clk_i       : in  std_ulogic; -- global clock, rising edge
1037 
      rstn_i      : in  std_ulogic; -- global reset, low-active, async
1038 
      ctrl_i      : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1039 
      -- data input --
1040 
      rs1_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1041 
      rs2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1042 
      pc2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
1043 
      imm_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- immediate
1044 
      -- data output --
1045 
      res_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
1046 36 zero_gravi 
      add_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
1047 2 zero_gravi 
      -- co-processor interface --
1048 19 zero_gravi 
      cp0_start_o : out std_ulogic; -- trigger co-processor 0
1049 2 zero_gravi 
      cp0_data_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
1050 
      cp0_valid_i : in  std_ulogic; -- co-processor 0 result valid
1051 19 zero_gravi 
      cp1_start_o : out std_ulogic; -- trigger co-processor 1
1052 2 zero_gravi 
      cp1_data_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result
1053 
      cp1_valid_i : in  std_ulogic; -- co-processor 1 result valid
1054 36 zero_gravi 
      cp2_start_o : out std_ulogic; -- trigger co-processor 2
1055 
      cp2_data_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 2 result
1056 
      cp2_valid_i : in  std_ulogic; -- co-processor 2 result valid
1057 
      cp3_start_o : out std_ulogic; -- trigger co-processor 3
1058 
      cp3_data_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 3 result
1059 
      cp3_valid_i : in  std_ulogic; -- co-processor 3 result valid
1060 2 zero_gravi 
      -- status --
1061 
      wait_o      : out std_ulogic -- busy due to iterative processing units
1062 
    );
1063 
  end component;
1064 
 
1065 44 zero_gravi 
  -- Component: CPU Co-Processor MULDIV ('M' extension) -------------------------------------
1066 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1067 
  component neorv32_cpu_cp_muldiv
1068 19 zero_gravi 
    generic (
1069 
      FAST_MUL_EN : boolean := false -- use DSPs for faster multiplication
1070 
    );
1071 2 zero_gravi 
    port (
1072 
      -- global control --
1073 
      clk_i   : in  std_ulogic; -- global clock, rising edge
1074 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
1075 
      ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1076 36 zero_gravi 
      start_i : in  std_ulogic; -- trigger operation
1077 2 zero_gravi 
      -- data input --
1078 
      rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1079 
      rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1080 
      -- result and status --
1081 
      res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1082 
      valid_o : out std_ulogic -- data output valid
1083 
    );
1084 
  end component;
1085 
 
1086 44 zero_gravi 
  -- Component: CPU Co-Processor Bit Manipulation ('B' extension) ---------------------------
1087 
  -- -------------------------------------------------------------------------------------------
1088 
  component neorv32_cpu_cp_bitmanip
1089 
    port (
1090 
      -- global control --
1091 
      clk_i   : in  std_ulogic; -- global clock, rising edge
1092 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
1093 
      ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1094 
      start_i : in  std_ulogic; -- trigger operation
1095 
      -- data input --
1096 
      cmp_i   : in  std_ulogic_vector(1 downto 0); -- comparator status
1097 
      rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1098 
      rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1099 
      -- result and status --
1100 
      res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1101 
      valid_o : out std_ulogic -- data output valid
1102 
    );
1103 
  end component;
1104 
 
1105 2 zero_gravi 
  -- Component: CPU Bus Interface -----------------------------------------------------------
1106 
  -- -------------------------------------------------------------------------------------------
1107 
  component neorv32_cpu_bus
1108 
    generic (
1109 40 zero_gravi 
      CPU_EXTENSION_RISCV_C : boolean := true;  -- implement compressed extension?
1110 15 zero_gravi 
      -- Physical memory protection (PMP) --
1111 42 zero_gravi 
      PMP_NUM_REGIONS       : natural := 0;       -- number of regions (0..64)
1112 
      PMP_MIN_GRANULARITY   : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
1113 41 zero_gravi 
      -- Bus Timeout --
1114 
      BUS_TIMEOUT           : natural := 63     -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
1115 2 zero_gravi 
    );
1116 
    port (
1117 
      -- global control --
1118 12 zero_gravi 
      clk_i          : in  std_ulogic; -- global clock, rising edge
1119 38 zero_gravi 
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
1120 12 zero_gravi 
      ctrl_i         : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1121 
      -- cpu instruction fetch interface --
1122 
      fetch_pc_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
1123 
      instr_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
1124 
      i_wait_o       : out std_ulogic; -- wait for fetch to complete
1125 
      --
1126 
      ma_instr_o     : out std_ulogic; -- misaligned instruction address
1127 
      be_instr_o     : out std_ulogic; -- bus error on instruction access
1128 
      -- cpu data access interface --
1129 
      addr_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
1130 
      wdata_i        : in  std_ulogic_vector(data_width_c-1 downto 0); -- write data
1131 
      rdata_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
1132 
      mar_o          : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
1133 
      d_wait_o       : out std_ulogic; -- wait for access to complete
1134 
      --
1135 
      ma_load_o      : out std_ulogic; -- misaligned load data address
1136 
      ma_store_o     : out std_ulogic; -- misaligned store data address
1137 
      be_load_o      : out std_ulogic; -- bus error on load data access
1138 
      be_store_o     : out std_ulogic; -- bus error on store data access
1139 15 zero_gravi 
      -- physical memory protection --
1140 
      pmp_addr_i     : in  pmp_addr_if_t; -- addresses
1141 
      pmp_ctrl_i     : in  pmp_ctrl_if_t; -- configs
1142 12 zero_gravi 
      -- instruction bus --
1143 
      i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1144 
      i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1145 
      i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1146 
      i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1147 
      i_bus_we_o     : out std_ulogic; -- write enable
1148 
      i_bus_re_o     : out std_ulogic; -- read enable
1149 
      i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
1150 
      i_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
1151 
      i_bus_err_i    : in  std_ulogic; -- bus transfer error
1152 
      i_bus_fence_o  : out std_ulogic; -- fence operation
1153 39 zero_gravi 
      i_bus_lock_o   : out std_ulogic; -- locked/exclusive access
1154 12 zero_gravi 
      -- data bus --
1155 
      d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1156 
      d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1157 
      d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1158 
      d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1159 
      d_bus_we_o     : out std_ulogic; -- write enable
1160 
      d_bus_re_o     : out std_ulogic; -- read enable
1161 
      d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
1162 
      d_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
1163 
      d_bus_err_i    : in  std_ulogic; -- bus transfer error
1164 39 zero_gravi 
      d_bus_fence_o  : out std_ulogic; -- fence operation
1165 
      d_bus_lock_o   : out std_ulogic  -- locked/exclusive access
1166 2 zero_gravi 
    );
1167 
  end component;
1168 
 
1169 45 zero_gravi 
  -- Component: CPU Instruction Cache -------------------------------------------------------
1170 41 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1171 45 zero_gravi 
  component neorv32_icache
1172 41 zero_gravi 
    generic (
1173 47 zero_gravi 
      ICACHE_NUM_BLOCKS : natural := 4;  -- number of blocks (min 1), has to be a power of 2
1174 
      ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2
1175 
      ICACHE_NUM_SETS   : natural := 1   -- associativity / number of sets (1=direct_mapped), has to be a power of 2
1176 41 zero_gravi 
    );
1177 
    port (
1178 
      -- global control --
1179 
      clk_i         : in  std_ulogic; -- global clock, rising edge
1180 
      rstn_i        : in  std_ulogic; -- global reset, low-active, async
1181 
      clear_i       : in  std_ulogic; -- cache clear
1182 
      -- host controller interface --
1183 
      host_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1184 
      host_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1185 
      host_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1186 
      host_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1187 
      host_we_i     : in  std_ulogic; -- write enable
1188 
      host_re_i     : in  std_ulogic; -- read enable
1189 
      host_cancel_i : in  std_ulogic; -- cancel current bus transaction
1190 
      host_lock_i   : in  std_ulogic; -- locked/exclusive access
1191 
      host_ack_o    : out std_ulogic; -- bus transfer acknowledge
1192 
      host_err_o    : out std_ulogic; -- bus transfer error
1193 
      -- peripheral bus interface --
1194 
      bus_addr_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1195 
      bus_rdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1196 
      bus_wdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1197 
      bus_ben_o     : out std_ulogic_vector(03 downto 0); -- byte enable
1198 
      bus_we_o      : out std_ulogic; -- write enable
1199 
      bus_re_o      : out std_ulogic; -- read enable
1200 
      bus_cancel_o  : out std_ulogic; -- cancel current bus transaction
1201 
      bus_lock_o    : out std_ulogic; -- locked/exclusive access
1202 
      bus_ack_i     : in  std_ulogic; -- bus transfer acknowledge
1203 
      bus_err_i     : in  std_ulogic  -- bus transfer error
1204 
    );
1205 
  end component;
1206 
 
1207 12 zero_gravi 
  -- Component: CPU Bus Switch --------------------------------------------------------------
1208 
  -- -------------------------------------------------------------------------------------------
1209 
  component neorv32_busswitch
1210 
    generic (
1211 
      PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only
1212 
      PORT_CB_READ_ONLY : boolean := false  -- set if controller port B is read-only
1213 
    );
1214 
    port (
1215 
      -- global control --
1216 
      clk_i           : in  std_ulogic; -- global clock, rising edge
1217 
      rstn_i          : in  std_ulogic; -- global reset, low-active, async
1218 
      -- controller interface a --
1219 
      ca_bus_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1220 
      ca_bus_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1221 
      ca_bus_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1222 
      ca_bus_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1223 
      ca_bus_we_i     : in  std_ulogic; -- write enable
1224 
      ca_bus_re_i     : in  std_ulogic; -- read enable
1225 
      ca_bus_cancel_i : in  std_ulogic; -- cancel current bus transaction
1226 39 zero_gravi 
      ca_bus_lock_i   : in  std_ulogic; -- locked/exclusive access
1227 12 zero_gravi 
      ca_bus_ack_o    : out std_ulogic; -- bus transfer acknowledge
1228 
      ca_bus_err_o    : out std_ulogic; -- bus transfer error
1229 
      -- controller interface b --
1230 
      cb_bus_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1231 
      cb_bus_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1232 
      cb_bus_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1233 
      cb_bus_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1234 
      cb_bus_we_i     : in  std_ulogic; -- write enable
1235 
      cb_bus_re_i     : in  std_ulogic; -- read enable
1236 
      cb_bus_cancel_i : in  std_ulogic; -- cancel current bus transaction
1237 39 zero_gravi 
      cb_bus_lock_i   : in  std_ulogic; -- locked/exclusive access
1238 12 zero_gravi 
      cb_bus_ack_o    : out std_ulogic; -- bus transfer acknowledge
1239 
      cb_bus_err_o    : out std_ulogic; -- bus transfer error
1240 
      -- peripheral bus --
1241 36 zero_gravi 
      p_bus_src_o     : out std_ulogic; -- access source: 0 = A, 1 = B
1242 12 zero_gravi 
      p_bus_addr_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1243 
      p_bus_rdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1244 
      p_bus_wdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1245 
      p_bus_ben_o     : out std_ulogic_vector(03 downto 0); -- byte enable
1246 
      p_bus_we_o      : out std_ulogic; -- write enable
1247 
      p_bus_re_o      : out std_ulogic; -- read enable
1248 
      p_bus_cancel_o  : out std_ulogic; -- cancel current bus transaction
1249 39 zero_gravi 
      p_bus_lock_o    : out std_ulogic; -- locked/exclusive access
1250 12 zero_gravi 
      p_bus_ack_i     : in  std_ulogic; -- bus transfer acknowledge
1251 
      p_bus_err_i     : in  std_ulogic  -- bus transfer error
1252 
    );
1253 
  end component;
1254 
 
1255 2 zero_gravi 
  -- Component: CPU Compressed Instructions Decompressor ------------------------------------
1256 
  -- -------------------------------------------------------------------------------------------
1257 
  component neorv32_cpu_decompressor
1258 
    port (
1259 
      -- instruction input --
1260 
      ci_instr16_i : in  std_ulogic_vector(15 downto 0); -- compressed instruction input
1261 
      -- instruction output --
1262 
      ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
1263 
      ci_instr32_o : out std_ulogic_vector(31 downto 0)  -- 32-bit decompressed instruction
1264 
    );
1265 
  end component;
1266 
 
1267 
  -- Component: Processor-internal instruction memory (IMEM) --------------------------------
1268 
  -- -------------------------------------------------------------------------------------------
1269 
  component neorv32_imem
1270 
    generic (
1271 
      IMEM_BASE      : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
1272 
      IMEM_SIZE      : natural := 4*1024; -- processor-internal instruction memory size in bytes
1273 
      IMEM_AS_ROM    : boolean := false;  -- implement IMEM as read-only memory?
1274 44 zero_gravi 
      BOOTLOADER_EN  : boolean := true    -- implement and use bootloader?
1275 2 zero_gravi 
    );
1276 
    port (
1277 
      clk_i  : in  std_ulogic; -- global clock line
1278 
      rden_i : in  std_ulogic; -- read enable
1279 
      wren_i : in  std_ulogic; -- write enable
1280 
      ben_i  : in  std_ulogic_vector(03 downto 0); -- byte write enable
1281 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1282 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1283 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1284 
      ack_o  : out std_ulogic -- transfer acknowledge
1285 
    );
1286 
  end component;
1287 
 
1288 
  -- Component: Processor-internal data memory (DMEM) ---------------------------------------
1289 
  -- -------------------------------------------------------------------------------------------
1290 
  component neorv32_dmem
1291 
    generic (
1292 
      DMEM_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- memory base address
1293 
      DMEM_SIZE : natural := 4*1024  -- processor-internal instruction memory size in bytes
1294 
    );
1295 
    port (
1296 
      clk_i  : in  std_ulogic; -- global clock line
1297 
      rden_i : in  std_ulogic; -- read enable
1298 
      wren_i : in  std_ulogic; -- write enable
1299 
      ben_i  : in  std_ulogic_vector(03 downto 0); -- byte write enable
1300 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1301 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1302 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1303 
      ack_o  : out std_ulogic -- transfer acknowledge
1304 
    );
1305 
  end component;
1306 
 
1307 
  -- Component: Processor-internal bootloader ROM (BOOTROM) ---------------------------------
1308 
  -- -------------------------------------------------------------------------------------------
1309 
  component neorv32_boot_rom
1310 23 zero_gravi 
    generic (
1311 
      BOOTROM_BASE : std_ulogic_vector(31 downto 0) := x"FFFF0000"; -- boot ROM base address
1312 
      BOOTROM_SIZE : natural := 4*1024  -- processor-internal boot ROM memory size in bytes
1313 
    );
1314 2 zero_gravi 
    port (
1315 
      clk_i  : in  std_ulogic; -- global clock line
1316 
      rden_i : in  std_ulogic; -- read enable
1317 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1318 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1319 
      ack_o  : out std_ulogic -- transfer acknowledge
1320 
    );
1321 
  end component;
1322 
 
1323 
  -- Component: Machine System Timer (mtime) ------------------------------------------------
1324 
  -- -------------------------------------------------------------------------------------------
1325 
  component neorv32_mtime
1326 
    port (
1327 
      -- host access --
1328 
      clk_i     : in  std_ulogic; -- global clock line
1329 4 zero_gravi 
      rstn_i    : in  std_ulogic := '0'; -- global reset, low-active, async
1330 2 zero_gravi 
      addr_i    : in  std_ulogic_vector(31 downto 0); -- address
1331 
      rden_i    : in  std_ulogic; -- read enable
1332 
      wren_i    : in  std_ulogic; -- write enable
1333 
      data_i    : in  std_ulogic_vector(31 downto 0); -- data in
1334 
      data_o    : out std_ulogic_vector(31 downto 0); -- data out
1335 
      ack_o     : out std_ulogic; -- transfer acknowledge
1336 11 zero_gravi 
      -- time output for CPU --
1337 
      time_o    : out std_ulogic_vector(63 downto 0); -- current system time
1338 2 zero_gravi 
      -- interrupt --
1339 
      irq_o     : out std_ulogic  -- interrupt request
1340 
    );
1341 
  end component;
1342 
 
1343 
  -- Component: General Purpose Input/Output Port (GPIO) ------------------------------------
1344 
  -- -------------------------------------------------------------------------------------------
1345 
  component neorv32_gpio
1346 
    port (
1347 
      -- host access --
1348 
      clk_i  : in  std_ulogic; -- global clock line
1349 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1350 
      rden_i : in  std_ulogic; -- read enable
1351 
      wren_i : in  std_ulogic; -- write enable
1352 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1353 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1354 
      ack_o  : out std_ulogic; -- transfer acknowledge
1355 
      -- parallel io --
1356 22 zero_gravi 
      gpio_o : out std_ulogic_vector(31 downto 0);
1357 
      gpio_i : in  std_ulogic_vector(31 downto 0);
1358 2 zero_gravi 
      -- interrupt --
1359 
      irq_o  : out std_ulogic
1360 
    );
1361 
  end component;
1362 
 
1363 
  -- Component: Watchdog Timer (WDT) --------------------------------------------------------
1364 
  -- -------------------------------------------------------------------------------------------
1365 
  component neorv32_wdt
1366 
    port (
1367 
      -- host access --
1368 
      clk_i       : in  std_ulogic; -- global clock line
1369 
      rstn_i      : in  std_ulogic; -- global reset line, low-active
1370 
      rden_i      : in  std_ulogic; -- read enable
1371 
      wren_i      : in  std_ulogic; -- write enable
1372 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1373 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1374 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1375 
      ack_o       : out std_ulogic; -- transfer acknowledge
1376 
      -- clock generator --
1377 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1378 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1379 
      -- timeout event --
1380 
      irq_o       : out std_ulogic; -- timeout IRQ
1381 
      rstn_o      : out std_ulogic  -- timeout reset, low_active, use it as async!
1382 
    );
1383 
  end component;
1384 
 
1385 
  -- Component: Universal Asynchronous Receiver and Transmitter (UART) ----------------------
1386 
  -- -------------------------------------------------------------------------------------------
1387 
  component neorv32_uart
1388 
    port (
1389 
      -- host access --
1390 
      clk_i       : in  std_ulogic; -- global clock line
1391 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1392 
      rden_i      : in  std_ulogic; -- read enable
1393 
      wren_i      : in  std_ulogic; -- write enable
1394 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1395 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1396 
      ack_o       : out std_ulogic; -- transfer acknowledge
1397 
      -- clock generator --
1398 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1399 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1400 
      -- com lines --
1401 
      uart_txd_o  : out std_ulogic;
1402 
      uart_rxd_i  : in  std_ulogic;
1403 
      -- interrupts --
1404 
      uart_irq_o  : out std_ulogic  -- uart rx/tx interrupt
1405 
    );
1406 
  end component;
1407 
 
1408 
  -- Component: Serial Peripheral Interface (SPI) -------------------------------------------
1409 
  -- -------------------------------------------------------------------------------------------
1410 
  component neorv32_spi
1411 
    port (
1412 
      -- host access --
1413 
      clk_i       : in  std_ulogic; -- global clock line
1414 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1415 
      rden_i      : in  std_ulogic; -- read enable
1416 
      wren_i      : in  std_ulogic; -- write enable
1417 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1418 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1419 
      ack_o       : out std_ulogic; -- transfer acknowledge
1420 
      -- clock generator --
1421 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1422 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1423 
      -- com lines --
1424 6 zero_gravi 
      spi_sck_o   : out std_ulogic; -- SPI serial clock
1425 
      spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
1426 
      spi_sdi_i   : in  std_ulogic; -- controller data in, peripheral data out
1427 2 zero_gravi 
      spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
1428 
      -- interrupt --
1429 
      spi_irq_o   : out std_ulogic -- transmission done interrupt
1430 
    );
1431 
  end component;
1432 
 
1433 
  -- Component: Two-Wire Interface (TWI) ----------------------------------------------------
1434 
  -- -------------------------------------------------------------------------------------------
1435 
  component neorv32_twi
1436 
    port (
1437 
      -- host access --
1438 
      clk_i       : in  std_ulogic; -- global clock line
1439 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1440 
      rden_i      : in  std_ulogic; -- read enable
1441 
      wren_i      : in  std_ulogic; -- write enable
1442 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1443 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1444 
      ack_o       : out std_ulogic; -- transfer acknowledge
1445 
      -- clock generator --
1446 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1447 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1448 
      -- com lines --
1449 
      twi_sda_io  : inout std_logic; -- serial data line
1450 
      twi_scl_io  : inout std_logic; -- serial clock line
1451 
      -- interrupt --
1452 
      twi_irq_o   : out std_ulogic -- transfer done IRQ
1453 
    );
1454 
  end component;
1455 
 
1456 
  -- Component: Pulse-Width Modulation Controller (PWM) -------------------------------------
1457 
  -- -------------------------------------------------------------------------------------------
1458 
  component neorv32_pwm
1459 
    port (
1460 
      -- host access --
1461 
      clk_i       : in  std_ulogic; -- global clock line
1462 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1463 
      rden_i      : in  std_ulogic; -- read enable
1464 
      wren_i      : in  std_ulogic; -- write enable
1465 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1466 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1467 
      ack_o       : out std_ulogic; -- transfer acknowledge
1468 
      -- clock generator --
1469 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1470 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1471 
      -- pwm output channels --
1472 
      pwm_o       : out std_ulogic_vector(03 downto 0)
1473 
    );
1474 
  end component;
1475 
 
1476 
  -- Component: True Random Number Generator (TRNG) -----------------------------------------
1477 
  -- -------------------------------------------------------------------------------------------
1478 
  component neorv32_trng
1479 
    port (
1480 
      -- host access --
1481 
      clk_i  : in  std_ulogic; -- global clock line
1482 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1483 
      rden_i : in  std_ulogic; -- read enable
1484 
      wren_i : in  std_ulogic; -- write enable
1485 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1486 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1487 
      ack_o  : out std_ulogic  -- transfer acknowledge
1488 
    );
1489 
  end component;
1490 
 
1491 
  -- Component: Wishbone Bus Gateway (WISHBONE) ---------------------------------------------
1492 
  -- -------------------------------------------------------------------------------------------
1493 
  component neorv32_wishbone
1494 
    generic (
1495 35 zero_gravi 
      WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
1496 23 zero_gravi 
      -- Internal instruction memory --
1497 44 zero_gravi 
      MEM_INT_IMEM_EN   : boolean := true;   -- implement processor-internal instruction memory
1498 35 zero_gravi 
      MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
1499 23 zero_gravi 
      -- Internal data memory --
1500 44 zero_gravi 
      MEM_INT_DMEM_EN   : boolean := true;   -- implement processor-internal data memory
1501 35 zero_gravi 
      MEM_INT_DMEM_SIZE : natural := 4*1024  -- size of processor-internal data memory in bytes
1502 2 zero_gravi 
    );
1503 
    port (
1504 
      -- global control --
1505 39 zero_gravi 
      clk_i     : in  std_ulogic; -- global clock line
1506 
      rstn_i    : in  std_ulogic; -- global reset line, low-active
1507 2 zero_gravi 
      -- host access --
1508 39 zero_gravi 
      src_i     : in  std_ulogic; -- access type (0: data, 1:instruction)
1509 
      addr_i    : in  std_ulogic_vector(31 downto 0); -- address
1510 
      rden_i    : in  std_ulogic; -- read enable
1511 
      wren_i    : in  std_ulogic; -- write enable
1512 
      ben_i     : in  std_ulogic_vector(03 downto 0); -- byte write enable
1513 
      data_i    : in  std_ulogic_vector(31 downto 0); -- data in
1514 
      data_o    : out std_ulogic_vector(31 downto 0); -- data out
1515 
      cancel_i  : in  std_ulogic; -- cancel current bus transaction
1516 
      lock_i    : in  std_ulogic; -- locked/exclusive bus access
1517 
      ack_o     : out std_ulogic; -- transfer acknowledge
1518 
      err_o     : out std_ulogic; -- transfer error
1519 
      priv_i    : in  std_ulogic_vector(1 downto 0); -- current CPU privilege level
1520 2 zero_gravi 
      -- wishbone interface --
1521 39 zero_gravi 
      wb_tag_o  : out std_ulogic_vector(2 downto 0); -- tag
1522 
      wb_adr_o  : out std_ulogic_vector(31 downto 0); -- address
1523 
      wb_dat_i  : in  std_ulogic_vector(31 downto 0); -- read data
1524 
      wb_dat_o  : out std_ulogic_vector(31 downto 0); -- write data
1525 
      wb_we_o   : out std_ulogic; -- read/write
1526 
      wb_sel_o  : out std_ulogic_vector(03 downto 0); -- byte enable
1527 
      wb_stb_o  : out std_ulogic; -- strobe
1528 
      wb_cyc_o  : out std_ulogic; -- valid cycle
1529 
      wb_lock_o : out std_ulogic; -- locked/exclusive bus access
1530 
      wb_ack_i  : in  std_ulogic; -- transfer acknowledge
1531 
      wb_err_i  : in  std_ulogic  -- transfer error
1532 2 zero_gravi 
    );
1533 
  end component;
1534 
 
1535 47 zero_gravi 
  -- Component: Custom Functions Subsystem (CFS) --------------------------------------------
1536 23 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1537 47 zero_gravi 
  component neorv32_cfs
1538 
    generic (
1539 
      CFS_CONFIG : std_ulogic_vector(31 downto 0) := (others => '0') -- custom CFS configuration generic
1540 23 zero_gravi 
    );
1541 34 zero_gravi 
    port (
1542 
      -- host access --
1543 
      clk_i       : in  std_ulogic; -- global clock line
1544 
      rstn_i      : in  std_ulogic; -- global reset line, low-active, use as async
1545 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1546 
      rden_i      : in  std_ulogic; -- read enable
1547 47 zero_gravi 
      wren_i      : in  std_ulogic; -- word write enable
1548 34 zero_gravi 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1549 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1550 
      ack_o       : out std_ulogic; -- transfer acknowledge
1551 47 zero_gravi 
      err_o       : out std_ulogic; -- transfer error
1552 34 zero_gravi 
      -- clock generator --
1553 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1554 47 zero_gravi 
      clkgen_i    : in  std_ulogic_vector(07 downto 0); -- "clock" inputs
1555 
      -- CPU state --
1556 
      sleep_i     : in  std_ulogic; -- set if cpu is in sleep mode
1557 
      -- interrupt --
1558 
      irq_o       : out std_ulogic; -- interrupt request
1559 
      irq_ack_i   : in  std_ulogic; -- interrupt acknowledge
1560 
      -- custom io (conduit) --
1561 
      cfs_in_i    : in  std_ulogic_vector(31 downto 0); -- custom inputs
1562 
      cfs_out_o   : out std_ulogic_vector(31 downto 0)  -- custom outputs
1563 34 zero_gravi 
    );
1564 
  end component;
1565 
 
1566 23 zero_gravi 
  -- Component: System Configuration Information Memory (SYSINFO) ---------------------------
1567 
  -- -------------------------------------------------------------------------------------------
1568 12 zero_gravi 
  component neorv32_sysinfo
1569 
    generic (
1570 
      -- General --
1571 41 zero_gravi 
      CLOCK_FREQUENCY      : natural := 0;      -- clock frequency of clk_i in Hz
1572 44 zero_gravi 
      BOOTLOADER_EN        : boolean := true;   -- implement processor-internal bootloader?
1573 41 zero_gravi 
      USER_CODE            : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
1574 23 zero_gravi 
      -- Internal Instruction memory --
1575 44 zero_gravi 
      MEM_INT_IMEM_EN      : boolean := true;   -- implement processor-internal instruction memory
1576 41 zero_gravi 
      MEM_INT_IMEM_SIZE    : natural := 8*1024; -- size of processor-internal instruction memory in bytes
1577 
      MEM_INT_IMEM_ROM     : boolean := false;  -- implement processor-internal instruction memory as ROM
1578 23 zero_gravi 
      -- Internal Data memory --
1579 44 zero_gravi 
      MEM_INT_DMEM_EN      : boolean := true;   -- implement processor-internal data memory
1580 41 zero_gravi 
      MEM_INT_DMEM_SIZE    : natural := 4*1024; -- size of processor-internal data memory in bytes
1581 
      -- Internal Cache memory --
1582 44 zero_gravi 
      ICACHE_EN            : boolean := true;   -- implement instruction cache
1583 41 zero_gravi 
      ICACHE_NUM_BLOCKS    : natural := 4;      -- i-cache: number of blocks (min 2), has to be a power of 2
1584 
      ICACHE_BLOCK_SIZE    : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
1585 
      ICACHE_ASSOCIATIVITY : natural := 1;      -- i-cache: associativity (min 1), has to be a power 2
1586 23 zero_gravi 
      -- External memory interface --
1587 44 zero_gravi 
      MEM_EXT_EN           : boolean := false;  -- implement external memory bus interface?
1588 12 zero_gravi 
      -- Processor peripherals --
1589 44 zero_gravi 
      IO_GPIO_EN           : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
1590 
      IO_MTIME_EN          : boolean := true;   -- implement machine system timer (MTIME)?
1591 
      IO_UART_EN           : boolean := true;   -- implement universal asynchronous receiver/transmitter (UART)?
1592 
      IO_SPI_EN            : boolean := true;   -- implement serial peripheral interface (SPI)?
1593 
      IO_TWI_EN            : boolean := true;   -- implement two-wire interface (TWI)?
1594 
      IO_PWM_EN            : boolean := true;   -- implement pulse-width modulation unit (PWM)?
1595 
      IO_WDT_EN            : boolean := true;   -- implement watch dog timer (WDT)?
1596 
      IO_TRNG_EN           : boolean := true;   -- implement true random number generator (TRNG)?
1597 47 zero_gravi 
      IO_CFS_EN            : boolean := true    -- implement custom functions subsystem (CFS)?
1598 12 zero_gravi 
    );
1599 
    port (
1600 
      -- host access --
1601 
      clk_i  : in  std_ulogic; -- global clock line
1602 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1603 
      rden_i : in  std_ulogic; -- read enable
1604 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1605 
      ack_o  : out std_ulogic  -- transfer acknowledge
1606 
    );
1607 
  end component;
1608 
 
1609 2 zero_gravi 
end neorv32_package;
1610 
 
1611 
package body neorv32_package is
1612 
 
1613 41 zero_gravi 
  -- Function: Minimal required number of bits to represent input number --------------------
1614 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1615 
  function index_size_f(input : natural) return natural is
1616 
  begin
1617 
    for i in 0 to natural'high loop
1618 
      if (2**i >= input) then
1619 
        return i;
1620 
      end if;
1621 
    end loop; -- i
1622 
    return 0;
1623 
  end function index_size_f;
1624 
 
1625 
  -- Function: Conditional select natural ---------------------------------------------------
1626 
  -- -------------------------------------------------------------------------------------------
1627 
  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural is
1628 
  begin
1629 
    if (cond = true) then
1630 
      return val_t;
1631 
    else
1632 
      return val_f;
1633 
    end if;
1634 
  end function cond_sel_natural_f;
1635 
 
1636 
  -- Function: Conditional select std_ulogic_vector -----------------------------------------
1637 
  -- -------------------------------------------------------------------------------------------
1638 
  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector is
1639 
  begin
1640 
    if (cond = true) then
1641 
      return val_t;
1642 
    else
1643 
      return val_f;
1644 
    end if;
1645 
  end function cond_sel_stdulogicvector_f;
1646 
 
1647 
  -- Function: Convert BOOL to STD_ULOGIC ---------------------------------------------------
1648 
  -- -------------------------------------------------------------------------------------------
1649 
  function bool_to_ulogic_f(cond : boolean) return std_ulogic is
1650 
  begin
1651 
    if (cond = true) then
1652 
      return '1';
1653 
    else
1654 
      return '0';
1655 
    end if;
1656 
  end function bool_to_ulogic_f;
1657 
 
1658 
  -- Function: OR all bits ------------------------------------------------------------------
1659 
  -- -------------------------------------------------------------------------------------------
1660 
  function or_all_f(a : std_ulogic_vector) return std_ulogic is
1661 
    variable tmp_v : std_ulogic;
1662 
  begin
1663 
    tmp_v := a(a'low);
1664 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1665 
      for i in a'low+1 to a'high loop
1666 
        tmp_v := tmp_v or a(i);
1667 
      end loop; -- i
1668 
    end if;
1669 2 zero_gravi 
    return tmp_v;
1670 
  end function or_all_f;
1671 
 
1672 
  -- Function: AND all bits -----------------------------------------------------------------
1673 
  -- -------------------------------------------------------------------------------------------
1674 
  function and_all_f(a : std_ulogic_vector) return std_ulogic is
1675 
    variable tmp_v : std_ulogic;
1676 
  begin
1677 
    tmp_v := a(a'low);
1678 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1679 
      for i in a'low+1 to a'high loop
1680 
        tmp_v := tmp_v and a(i);
1681 
      end loop; -- i
1682 
    end if;
1683 2 zero_gravi 
    return tmp_v;
1684 
  end function and_all_f;
1685 
 
1686 
  -- Function: XOR all bits -----------------------------------------------------------------
1687 
  -- -------------------------------------------------------------------------------------------
1688 
  function xor_all_f(a : std_ulogic_vector) return std_ulogic is
1689 
    variable tmp_v : std_ulogic;
1690 
  begin
1691 
    tmp_v := a(a'low);
1692 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1693 
      for i in a'low+1 to a'high loop
1694 
        tmp_v := tmp_v xor a(i);
1695 
      end loop; -- i
1696 
    end if;
1697 2 zero_gravi 
    return tmp_v;
1698 
  end function xor_all_f;
1699 
 
1700 
  -- Function: XNOR all bits ----------------------------------------------------------------
1701 
  -- -------------------------------------------------------------------------------------------
1702 
  function xnor_all_f(a : std_ulogic_vector) return std_ulogic is
1703 
    variable tmp_v : std_ulogic;
1704 
  begin
1705 
    tmp_v := a(a'low);
1706 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1707 
      for i in a'low+1 to a'high loop
1708 
        tmp_v := tmp_v xnor a(i);
1709 
      end loop; -- i
1710 
    end if;
1711 2 zero_gravi 
    return tmp_v;
1712 
  end function xnor_all_f;
1713 
 
1714 40 zero_gravi 
  -- Function: Convert std_ulogic_vector to hex char ----------------------------------------
1715 6 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1716 
  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character is
1717 
    variable output_v : character;
1718 
  begin
1719 
    case input is
1720 7 zero_gravi 
      when x"0"   => output_v := '0';
1721 
      when x"1"   => output_v := '1';
1722 
      when x"2"   => output_v := '2';
1723 
      when x"3"   => output_v := '3';
1724 
      when x"4"   => output_v := '4';
1725 
      when x"5"   => output_v := '5';
1726 
      when x"6"   => output_v := '6';
1727 
      when x"7"   => output_v := '7';
1728 
      when x"8"   => output_v := '8';
1729 
      when x"9"   => output_v := '9';
1730 
      when x"a"   => output_v := 'a';
1731 
      when x"b"   => output_v := 'b';
1732 
      when x"c"   => output_v := 'c';
1733 
      when x"d"   => output_v := 'd';
1734 
      when x"e"   => output_v := 'e';
1735 
      when x"f"   => output_v := 'f';
1736 6 zero_gravi 
      when others => output_v := '?';
1737 
    end case;
1738 
    return output_v;
1739 
  end function to_hexchar_f;
1740 
 
1741 40 zero_gravi 
  -- Function: Convert hex char to std_ulogic_vector ----------------------------------------
1742 
  -- -------------------------------------------------------------------------------------------
1743 
  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector is
1744 
    variable hex_value_v : std_ulogic_vector(3 downto 0);
1745 
  begin
1746 
    case input is
1747 
      when '0'       => hex_value_v := x"0";
1748 
      when '1'       => hex_value_v := x"1";
1749 
      when '2'       => hex_value_v := x"2";
1750 
      when '3'       => hex_value_v := x"3";
1751 
      when '4'       => hex_value_v := x"4";
1752 
      when '5'       => hex_value_v := x"5";
1753 
      when '6'       => hex_value_v := x"6";
1754 
      when '7'       => hex_value_v := x"7";
1755 
      when '8'       => hex_value_v := x"8";
1756 
      when '9'       => hex_value_v := x"9";
1757 
      when 'a' | 'A' => hex_value_v := x"a";
1758 
      when 'b' | 'B' => hex_value_v := x"b";
1759 
      when 'c' | 'C' => hex_value_v := x"c";
1760 
      when 'd' | 'D' => hex_value_v := x"d";
1761 
      when 'e' | 'E' => hex_value_v := x"e";
1762 
      when 'f' | 'F' => hex_value_v := x"f";
1763 
      when others    => hex_value_v := (others => 'X');
1764 
    end case;
1765 
    return hex_value_v;
1766 
  end function hexchar_to_stdulogicvector_f;
1767 
 
1768 32 zero_gravi 
  -- Function: Bit reversal -----------------------------------------------------------------
1769 
  -- -------------------------------------------------------------------------------------------
1770 
  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector is
1771 
    variable output_v : std_ulogic_vector(input'range);
1772 
  begin
1773 
    for i in 0 to input'length-1 loop
1774 
      output_v(input'length-i-1) := input(i);
1775 
    end loop; -- i
1776 
    return output_v;
1777 
  end function bit_rev_f;
1778 
 
1779 36 zero_gravi 
  -- Function: Test if input number is a power of two ---------------------------------------
1780 
  -- -------------------------------------------------------------------------------------------
1781 
  function is_power_of_two_f(input : natural) return boolean is
1782 
  begin
1783 38 zero_gravi 
    if (input = 1) then -- 2^0
1784 36 zero_gravi 
      return true;
1785 38 zero_gravi 
    elsif ((input / 2) /= 0) and ((input mod 2) = 0) then
1786 
      return true;
1787 36 zero_gravi 
    else
1788 
      return false;
1789 
    end if;
1790 
  end function is_power_of_two_f;
1791 
 
1792 40 zero_gravi 
  -- Function: Swap all bytes of a 32-bit word (endianness conversion) ----------------------
1793 
  -- -------------------------------------------------------------------------------------------
1794 
  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector is
1795 
    variable output_v : std_ulogic_vector(input'range);
1796 
  begin
1797 
    output_v(07 downto 00) := input(31 downto 24);
1798 
    output_v(15 downto 08) := input(23 downto 16);
1799 
    output_v(23 downto 16) := input(15 downto 08);
1800 
    output_v(31 downto 24) := input(07 downto 00);
1801 
    return output_v;
1802 
  end function bswap32_f;
1803 
 
1804 2 zero_gravi 
end neorv32_package;

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