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-- #################################################################################################

-- # << NEORV32 - Main VHDL package file >>                                                        #

-- # ********************************************************************************************* #

-- # BSD 3-Clause License                                                                          #

-- #                                                                                               #

-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #

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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #

-- #################################################################################################

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

package neorv32_package is

  -- Architecture Configuration -------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- address space --

  constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address

  constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address

  -- (external) bus interface --

  constant bus_timeout_c     : natural := 127; -- cycles after which an *unacknowledged* bus access will timeout and trigger a bus fault exception (min 2)

  constant wb_pipe_mode_c    : boolean := false; -- *external* bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode

  constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian

  -- CPU core --

  constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2

  -- "critical" number of PMP regions --

  -- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically

  -- inserted into the memory interfaces increasing instruction fetch & data access latency by +1 cycle!

  constant pmp_num_regions_critical_c : natural := 8;

  -- Architecture Constants (do not modify!) ------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  constant data_width_c   : natural := 32; -- native data path width - do not change!

  constant hw_version_c   : std_ulogic_vector(31 downto 0) := x"01050204"; -- no touchy!

  constant pmp_max_r_c    : natural := 8; -- max PMP regions - FIXED!

  constant archid_c       : natural := 19; -- official NEORV32 architecture ID - hands off!

  constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW

  -- Helper Functions -----------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  function index_size_f(input : natural) return natural;

  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;

  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;

  function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string;

  function bool_to_ulogic_f(cond : boolean) return std_ulogic;

  function or_all_f(a : std_ulogic_vector) return std_ulogic;

  function and_all_f(a : std_ulogic_vector) return std_ulogic;

  function xor_all_f(a : std_ulogic_vector) return std_ulogic;

  function xnor_all_f(a : std_ulogic_vector) return std_ulogic;

  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;

  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector;

  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector;

  function is_power_of_two_f(input : natural) return boolean;

  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;

  -- Internal Types -------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);

  type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0);

  type cp_data_if_t  is array (0 to 7)  of std_ulogic_vector(data_width_c-1 downto 0);

  -- Processor-Internal Address Space Layout ------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --

  constant imem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address

  constant dmem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address

  --> internal data/instruction memory sizes are configured via top's generics

  -- Internal Bootloader ROM --

  constant boot_rom_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!

  constant boot_rom_size_c      : natural := 4*1024; -- module's address space in bytes

  constant boot_rom_max_size_c  : natural := 32*1024; -- max module's address space in bytes, fixed!

  -- IO: Peripheral Devices ("IO") Area --

  -- Control register(s) (including the device-enable) should be located at the base address of each device

  constant io_base_c            : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00";

  constant io_size_c            : natural := 64*4; -- module's address space in bytes, fixed!

  -- Custom Functions Subsystem (CFS) --

  constant cfs_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00"; -- base address

  constant cfs_size_c           : natural := 32*4; -- module's address space in bytes

  constant cfs_reg0_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00";

  constant cfs_reg1_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF04";

  constant cfs_reg2_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF08";

  constant cfs_reg3_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF0C";

  constant cfs_reg4_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF10";

  constant cfs_reg5_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF14";

  constant cfs_reg6_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF18";

  constant cfs_reg7_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF1C";

  constant cfs_reg8_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF20";

  constant cfs_reg9_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF24";

  constant cfs_reg10_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF28";

  constant cfs_reg11_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF2C";

  constant cfs_reg12_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF30";

  constant cfs_reg13_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF34";

  constant cfs_reg14_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF38";

  constant cfs_reg15_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF3C";

  constant cfs_reg16_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF40";

  constant cfs_reg17_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF44";

  constant cfs_reg18_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF48";

  constant cfs_reg19_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF4C";

  constant cfs_reg20_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF50";

  constant cfs_reg21_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF54";

  constant cfs_reg22_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF58";

  constant cfs_reg23_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF5C";

  constant cfs_reg24_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF60";

  constant cfs_reg25_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF64";

  constant cfs_reg26_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF68";

  constant cfs_reg27_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF6C";

  constant cfs_reg28_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF70";

  constant cfs_reg29_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF74";

  constant cfs_reg30_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF78";

  constant cfs_reg31_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF7C";

  -- General Purpose Input/Output Unit (GPIO) --

  constant gpio_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address

  constant gpio_size_c          : natural := 2*4; -- module's address space in bytes

  constant gpio_in_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80";

  constant gpio_out_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF84";

  -- True Random Number Generator (TRNG) --

  constant trng_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address

  constant trng_size_c          : natural := 1*4; -- module's address space in bytes

  constant trng_ctrl_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88";

  -- Watch Dog Timer (WDT) --

  constant wdt_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address

  constant wdt_size_c           : natural := 1*4; -- module's address space in bytes

  constant wdt_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C";

  -- Machine System Timer (MTIME) --

  constant mtime_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90"; -- base address

  constant mtime_size_c         : natural := 4*4; -- module's address space in bytes

  constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90";

  constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF94";

  constant mtime_cmp_lo_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF98";

  constant mtime_cmp_hi_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF9C";

  -- Universal Asynchronous Receiver/Transmitter 0 (UART0), primary UART --

  constant uart0_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address

  constant uart0_size_c         : natural := 2*4; -- module's address space in bytes

  constant uart0_ctrl_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0";

  constant uart0_rtx_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA4";

  -- Serial Peripheral Interface (SPI) --

  constant spi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address

  constant spi_size_c           : natural := 2*4; -- module's address space in bytes

  constant spi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8";

  constant spi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFAC";

  -- Two Wire Interface (TWI) --

  constant twi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0"; -- base address

  constant twi_size_c           : natural := 2*4; -- module's address space in bytes

  constant twi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0";

  constant twi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB4";

  -- Pulse-Width Modulation Controller (PWM) --

  constant pwm_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address

  constant pwm_size_c           : natural := 2*4; -- module's address space in bytes

  constant pwm_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8";

  constant pwm_duty_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFBC";

  -- Numerically-Controlled Oscillator (NCO) --

  constant nco_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address

  constant nco_size_c           : natural := 4*4; -- module's address space in bytes

  constant nco_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0";

  constant nco_ch0_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC4";

  constant nco_ch1_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8";

  constant nco_ch2_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC";

  -- Universal Asynchronous Receiver/Transmitter 1 (UART1), secondary UART --

  constant uart1_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address

  constant uart1_size_c         : natural := 2*4; -- module's address space in bytes

  constant uart1_ctrl_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0";

  constant uart1_rtx_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD4";

  -- Smart LED (WS2811/WS2812) Interface (NEOLED) --

  constant neoled_base_c        : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD8"; -- base address

  constant neoled_size_c        : natural := 2*4; -- module's address space in bytes

  constant neoled_ctrl_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD8";

  constant neoled_data_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFDC";

  -- System Information Memory (SYSINFO) --

  constant sysinfo_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address

  constant sysinfo_size_c       : natural := 8*4; -- module's address space in bytes

  -- Main Control Bus -----------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- register file --

  constant ctrl_rf_in_mux_c     : natural :=  0; -- input source select lsb (0=MEM, 1=ALU)

  constant ctrl_rf_rs1_adr0_c   : natural :=  1; -- source register 1 address bit 0

  constant ctrl_rf_rs1_adr1_c   : natural :=  2; -- source register 1 address bit 1

  constant ctrl_rf_rs1_adr2_c   : natural :=  3; -- source register 1 address bit 2

  constant ctrl_rf_rs1_adr3_c   : natural :=  4; -- source register 1 address bit 3

  constant ctrl_rf_rs1_adr4_c   : natural :=  5; -- source register 1 address bit 4

  constant ctrl_rf_rs2_adr0_c   : natural :=  6; -- source register 2 address bit 0

  constant ctrl_rf_rs2_adr1_c   : natural :=  7; -- source register 2 address bit 1

  constant ctrl_rf_rs2_adr2_c   : natural :=  8; -- source register 2 address bit 2

  constant ctrl_rf_rs2_adr3_c   : natural :=  9; -- source register 2 address bit 3

  constant ctrl_rf_rs2_adr4_c   : natural := 10; -- source register 2 address bit 4

  constant ctrl_rf_rd_adr0_c    : natural := 11; -- destiantion register address bit 0

  constant ctrl_rf_rd_adr1_c    : natural := 12; -- destiantion register address bit 1

  constant ctrl_rf_rd_adr2_c    : natural := 13; -- destiantion register address bit 2

  constant ctrl_rf_rd_adr3_c    : natural := 14; -- destiantion register address bit 3

  constant ctrl_rf_rd_adr4_c    : natural := 15; -- destiantion register address bit 4

  constant ctrl_rf_wb_en_c      : natural := 16; -- write back enable

  constant ctrl_rf_r0_we_c      : natural := 17; -- force write access and force rd=r0

  -- alu --

  constant ctrl_alu_arith_c     : natural := 18; -- ALU arithmetic command

  constant ctrl_alu_logic0_c    : natural := 19; -- ALU logic command bit 0

  constant ctrl_alu_logic1_c    : natural := 20; -- ALU logic command bit 1

  constant ctrl_alu_func0_c     : natural := 21; -- ALU function select command bit 0

  constant ctrl_alu_func1_c     : natural := 22; -- ALU function select command bit 1

  constant ctrl_alu_addsub_c    : natural := 23; -- 0=ADD, 1=SUB

  constant ctrl_alu_opa_mux_c   : natural := 24; -- operand A select (0=rs1, 1=PC)

  constant ctrl_alu_opb_mux_c   : natural := 25; -- operand B select (0=rs2, 1=IMM)

  constant ctrl_alu_unsigned_c  : natural := 26; -- is unsigned ALU operation

  constant ctrl_alu_shift_dir_c : natural := 27; -- shift direction (0=left, 1=right)

  constant ctrl_alu_shift_ar_c  : natural := 28; -- is arithmetic shift

  -- bus interface --

  constant ctrl_bus_size_lsb_c  : natural := 29; -- transfer size lsb (00=byte, 01=half-word)

  constant ctrl_bus_size_msb_c  : natural := 30; -- transfer size msb (10=word, 11=?)

  constant ctrl_bus_rd_c        : natural := 31; -- read data request

  constant ctrl_bus_wr_c        : natural := 32; -- write data request

  constant ctrl_bus_if_c        : natural := 33; -- instruction fetch request

  constant ctrl_bus_mo_we_c     : natural := 34; -- memory address and data output register write enable

  constant ctrl_bus_mi_we_c     : natural := 35; -- memory data input register write enable

  constant ctrl_bus_wd_sel_c    : natural := 36; -- memory write-data source select (0=reg_file, 1=co-proc.)

  constant ctrl_bus_unsigned_c  : natural := 37; -- is unsigned load

  constant ctrl_bus_ierr_ack_c  : natural := 38; -- acknowledge instruction fetch bus exceptions

  constant ctrl_bus_derr_ack_c  : natural := 39; -- acknowledge data access bus exceptions

  constant ctrl_bus_fence_c     : natural := 40; -- executed fence operation

  constant ctrl_bus_fencei_c    : natural := 41; -- executed fencei operation

  constant ctrl_bus_lock_c      : natural := 42; -- locked/exclusive bus access

  -- co-processors --

  constant ctrl_cp_id_lsb_c     : natural := 43; -- cp select ID lsb

  constant ctrl_cp_id_hsb_c     : natural := 44; -- cp select ID hsb

  constant ctrl_cp_id_msb_c     : natural := 45; -- cp select ID msb

  constant ctrl_cp_fpu_mem_we_c : natural := 46; -- fpu-cp memory-data write enable

  -- current privilege level --

  constant ctrl_priv_lvl_lsb_c  : natural := 47; -- privilege level lsb

  constant ctrl_priv_lvl_msb_c  : natural := 48; -- privilege level msb

  -- instruction's control blocks (used by cpu co-processors) --

  constant ctrl_ir_funct3_0_c   : natural := 49; -- funct3 bit 0

  constant ctrl_ir_funct3_1_c   : natural := 50; -- funct3 bit 1

  constant ctrl_ir_funct3_2_c   : natural := 51; -- funct3 bit 2

  constant ctrl_ir_funct12_0_c  : natural := 52; -- funct12 bit 0

  constant ctrl_ir_funct12_1_c  : natural := 53; -- funct12 bit 1

  constant ctrl_ir_funct12_2_c  : natural := 54; -- funct12 bit 2

  constant ctrl_ir_funct12_3_c  : natural := 55; -- funct12 bit 3

  constant ctrl_ir_funct12_4_c  : natural := 56; -- funct12 bit 4

  constant ctrl_ir_funct12_5_c  : natural := 57; -- funct12 bit 5

  constant ctrl_ir_funct12_6_c  : natural := 58; -- funct12 bit 6

  constant ctrl_ir_funct12_7_c  : natural := 59; -- funct12 bit 7

  constant ctrl_ir_funct12_8_c  : natural := 60; -- funct12 bit 8

  constant ctrl_ir_funct12_9_c  : natural := 61; -- funct12 bit 9

  constant ctrl_ir_funct12_10_c : natural := 62; -- funct12 bit 10

  constant ctrl_ir_funct12_11_c : natural := 63; -- funct12 bit 11

  constant ctrl_ir_opcode7_0_c  : natural := 64; -- opcode7 bit 0

  constant ctrl_ir_opcode7_1_c  : natural := 65; -- opcode7 bit 1

  constant ctrl_ir_opcode7_2_c  : natural := 66; -- opcode7 bit 2

  constant ctrl_ir_opcode7_3_c  : natural := 67; -- opcode7 bit 3

  constant ctrl_ir_opcode7_4_c  : natural := 68; -- opcode7 bit 4

  constant ctrl_ir_opcode7_5_c  : natural := 69; -- opcode7 bit 5

  constant ctrl_ir_opcode7_6_c  : natural := 70; -- opcode7 bit 6

  -- CPU status --

  constant ctrl_sleep_c         : natural := 71; -- set when CPU is in sleep mode

  -- control bus size --

  constant ctrl_width_c         : natural := 72; -- control bus size

  -- Comparator Bus -------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  constant cmp_equal_c : natural := 0;

  constant cmp_less_c  : natural := 1; -- for signed and unsigned comparisons

  -- RISC-V Opcode Layout -------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  constant instr_opcode_lsb_c  : natural :=  0; -- opcode bit 0

  constant instr_opcode_msb_c  : natural :=  6; -- opcode bit 6

  constant instr_rd_lsb_c      : natural :=  7; -- destination register address bit 0

  constant instr_rd_msb_c      : natural := 11; -- destination register address bit 4

  constant instr_funct3_lsb_c  : natural := 12; -- funct3 bit 0

  constant instr_funct3_msb_c  : natural := 14; -- funct3 bit 2

  constant instr_rs1_lsb_c     : natural := 15; -- source register 1 address bit 0

  constant instr_rs1_msb_c     : natural := 19; -- source register 1 address bit 4

  constant instr_rs2_lsb_c     : natural := 20; -- source register 2 address bit 0

  constant instr_rs2_msb_c     : natural := 24; -- source register 2 address bit 4

  constant instr_funct7_lsb_c  : natural := 25; -- funct7 bit 0

  constant instr_funct7_msb_c  : natural := 31; -- funct7 bit 6

  constant instr_funct12_lsb_c : natural := 20; -- funct12 bit 0

  constant instr_funct12_msb_c : natural := 31; -- funct12 bit 11

  constant instr_imm12_lsb_c   : natural := 20; -- immediate12 bit 0

  constant instr_imm12_msb_c   : natural := 31; -- immediate12 bit 11

  constant instr_imm20_lsb_c   : natural := 12; -- immediate20 bit 0

  constant instr_imm20_msb_c   : natural := 31; -- immediate20 bit 21

  constant instr_csr_id_lsb_c  : natural := 20; -- csr select bit 0

  constant instr_csr_id_msb_c  : natural := 31; -- csr select bit 11

  constant instr_funct5_lsb_c  : natural := 27; -- funct5 select bit 0

  constant instr_funct5_msb_c  : natural := 31; -- funct5 select bit 4

  -- RISC-V Opcodes -------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- alu --

  constant opcode_lui_c    : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate

  constant opcode_auipc_c  : std_ulogic_vector(6 downto 0) := "0010111"; -- add upper immediate to PC

  constant opcode_alui_c   : std_ulogic_vector(6 downto 0) := "0010011"; -- ALU operation with immediate (operation via funct3 and funct7)

  constant opcode_alu_c    : std_ulogic_vector(6 downto 0) := "0110011"; -- ALU operation (operation via funct3 and funct7)

  -- control flow --

  constant opcode_jal_c    : std_ulogic_vector(6 downto 0) := "1101111"; -- jump and link

  constant opcode_jalr_c   : std_ulogic_vector(6 downto 0) := "1100111"; -- jump and link with register

  constant opcode_branch_c : std_ulogic_vector(6 downto 0) := "1100011"; -- branch (condition set via funct3)

  -- memory access --

  constant opcode_load_c   : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)

  constant opcode_store_c  : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)

  -- system/csr --

  constant opcode_fence_c  : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i

  constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)

  -- atomic memory access (A) --

  constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)

  -- floating point operations (F/D/H/Q) --

  constant opcode_flw_c    : std_ulogic_vector(6 downto 0) := "0000111"; -- load word

  constant opcode_fsw_c    : std_ulogic_vector(6 downto 0) := "0100111"; -- store word

  constant opcode_fop_c    : std_ulogic_vector(6 downto 0) := "1010011"; -- dual/single opearand operation

  constant opcode_fmac_c   : std_ulogic_vector(6 downto 0) := "100--11"; -- fused multiply-add (three operands)

  -- RISC-V Funct3 --------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- control flow --

  constant funct3_beq_c    : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal

  constant funct3_bne_c    : std_ulogic_vector(2 downto 0) := "001"; -- branch if not equal

  constant funct3_blt_c    : std_ulogic_vector(2 downto 0) := "100"; -- branch if less than

  constant funct3_bge_c    : std_ulogic_vector(2 downto 0) := "101"; -- branch if greater than or equal

  constant funct3_bltu_c   : std_ulogic_vector(2 downto 0) := "110"; -- branch if less than (unsigned)

  constant funct3_bgeu_c   : std_ulogic_vector(2 downto 0) := "111"; -- branch if greater than or equal (unsigned)

  -- memory access --

  constant funct3_lb_c     : std_ulogic_vector(2 downto 0) := "000"; -- load byte

  constant funct3_lh_c     : std_ulogic_vector(2 downto 0) := "001"; -- load half word

  constant funct3_lw_c     : std_ulogic_vector(2 downto 0) := "010"; -- load word

  constant funct3_lbu_c    : std_ulogic_vector(2 downto 0) := "100"; -- load byte (unsigned)

  constant funct3_lhu_c    : std_ulogic_vector(2 downto 0) := "101"; -- load half word (unsigned)

  constant funct3_sb_c     : std_ulogic_vector(2 downto 0) := "000"; -- store byte

  constant funct3_sh_c     : std_ulogic_vector(2 downto 0) := "001"; -- store half word

  constant funct3_sw_c     : std_ulogic_vector(2 downto 0) := "010"; -- store word

  -- alu --

  constant funct3_subadd_c : std_ulogic_vector(2 downto 0) := "000"; -- sub/add via funct7

  constant funct3_sll_c    : std_ulogic_vector(2 downto 0) := "001"; -- shift logical left

  constant funct3_slt_c    : std_ulogic_vector(2 downto 0) := "010"; -- set on less

  constant funct3_sltu_c   : std_ulogic_vector(2 downto 0) := "011"; -- set on less unsigned

  constant funct3_xor_c    : std_ulogic_vector(2 downto 0) := "100"; -- xor

  constant funct3_sr_c     : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7

  constant funct3_or_c     : std_ulogic_vector(2 downto 0) := "110"; -- or

  constant funct3_and_c    : std_ulogic_vector(2 downto 0) := "111"; -- and

  -- system/csr --

  constant funct3_env_c    : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi

  constant funct3_csrrw_c  : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w

  constant funct3_csrrs_c  : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit

  constant funct3_csrrc_c  : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit

  constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate

  constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate

  constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate

  -- fence --

  constant funct3_fence_c  : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)

  constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync

  -- RISC-V Funct12 -------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- system --

  constant funct12_ecall_c  : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL

  constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK

  constant funct12_mret_c   : std_ulogic_vector(11 downto 0) := x"302"; -- MRET

  constant funct12_wfi_c    : std_ulogic_vector(11 downto 0) := x"105"; -- WFI

  -- RISC-V Funct5 --------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- atomic operations --

  constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR

  constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC

  -- RISC-V Floating-Point Formats ----------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  constant float_single_c : std_ulogic_vector(1 downto 0) := "00"; -- single-precisions (32-bit)

  constant float_double_c : std_ulogic_vector(1 downto 0) := "01"; -- double-precisions (64-bit)

  constant float_half_c   : std_ulogic_vector(1 downto 0) := "10"; -- half-precisions (16-bit)

  constant float_quad_c   : std_ulogic_vector(1 downto 0) := "11"; -- quad-precisions (64-bit)

  -- RISC-V CSR Addresses -------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- read/write CSRs --

  constant csr_class_float_c    : std_ulogic_vector(07 downto 0) := x"00"; -- floating point

  constant csr_fflags_c         : std_ulogic_vector(11 downto 0) := x"001";

  constant csr_frm_c            : std_ulogic_vector(11 downto 0) := x"002";

  constant csr_fcsr_c           : std_ulogic_vector(11 downto 0) := x"003";

  --

  constant csr_setup_c          : std_ulogic_vector(07 downto 0) := x"30"; -- trap setup

  constant csr_mstatus_c        : std_ulogic_vector(11 downto 0) := x"300";

  constant csr_misa_c           : std_ulogic_vector(11 downto 0) := x"301";

  constant csr_mie_c            : std_ulogic_vector(11 downto 0) := x"304";

  constant csr_mtvec_c          : std_ulogic_vector(11 downto 0) := x"305";

  constant csr_mcounteren_c     : std_ulogic_vector(11 downto 0) := x"306";

  --

  constant csr_mstatush_c       : std_ulogic_vector(11 downto 0) := x"310";

  --

  constant csr_mcountinhibit_c  : std_ulogic_vector(11 downto 0) := x"320";

  --

  constant csr_mhpmevent3_c     : std_ulogic_vector(11 downto 0) := x"323";

  constant csr_mhpmevent4_c     : std_ulogic_vector(11 downto 0) := x"324";

  constant csr_mhpmevent5_c     : std_ulogic_vector(11 downto 0) := x"325";

  constant csr_mhpmevent6_c     : std_ulogic_vector(11 downto 0) := x"326";

  constant csr_mhpmevent7_c     : std_ulogic_vector(11 downto 0) := x"327";

  constant csr_mhpmevent8_c     : std_ulogic_vector(11 downto 0) := x"328";

  constant csr_mhpmevent9_c     : std_ulogic_vector(11 downto 0) := x"329";

  constant csr_mhpmevent10_c    : std_ulogic_vector(11 downto 0) := x"32a";

  constant csr_mhpmevent11_c    : std_ulogic_vector(11 downto 0) := x"32b";

  constant csr_mhpmevent12_c    : std_ulogic_vector(11 downto 0) := x"32c";

  constant csr_mhpmevent13_c    : std_ulogic_vector(11 downto 0) := x"32d";

  constant csr_mhpmevent14_c    : std_ulogic_vector(11 downto 0) := x"32e";

  constant csr_mhpmevent15_c    : std_ulogic_vector(11 downto 0) := x"32f";

  constant csr_mhpmevent16_c    : std_ulogic_vector(11 downto 0) := x"330";

  constant csr_mhpmevent17_c    : std_ulogic_vector(11 downto 0) := x"331";

  constant csr_mhpmevent18_c    : std_ulogic_vector(11 downto 0) := x"332";

  constant csr_mhpmevent19_c    : std_ulogic_vector(11 downto 0) := x"333";

  constant csr_mhpmevent20_c    : std_ulogic_vector(11 downto 0) := x"334";

  constant csr_mhpmevent21_c    : std_ulogic_vector(11 downto 0) := x"335";

  constant csr_mhpmevent22_c    : std_ulogic_vector(11 downto 0) := x"336";

  constant csr_mhpmevent23_c    : std_ulogic_vector(11 downto 0) := x"337";

  constant csr_mhpmevent24_c    : std_ulogic_vector(11 downto 0) := x"338";

  constant csr_mhpmevent25_c    : std_ulogic_vector(11 downto 0) := x"339";

  constant csr_mhpmevent26_c    : std_ulogic_vector(11 downto 0) := x"33a";

  constant csr_mhpmevent27_c    : std_ulogic_vector(11 downto 0) := x"33b";

  constant csr_mhpmevent28_c    : std_ulogic_vector(11 downto 0) := x"33c";

  constant csr_mhpmevent29_c    : std_ulogic_vector(11 downto 0) := x"33d";

  constant csr_mhpmevent30_c    : std_ulogic_vector(11 downto 0) := x"33e";

  constant csr_mhpmevent31_c    : std_ulogic_vector(11 downto 0) := x"33f";

  --

  constant csr_class_trap_c     : std_ulogic_vector(07 downto 0) := x"34"; -- machine trap handling

  constant csr_mscratch_c       : std_ulogic_vector(11 downto 0) := x"340";

  constant csr_mepc_c           : std_ulogic_vector(11 downto 0) := x"341";