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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_package.vhd] - Blame information for rev 54

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1 2 zero_gravi 
-- #################################################################################################
2 
-- # << NEORV32 - Main VHDL package file >>                                                        #
3 
-- # ********************************************************************************************* #
4 
-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
6 42 zero_gravi 
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
7 2 zero_gravi 
-- #                                                                                               #
8 
-- # Redistribution and use in source and binary forms, with or without modification, are          #
9 
-- # permitted provided that the following conditions are met:                                     #
10 
-- #                                                                                               #
11 
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
12 
-- #    conditions and the following disclaimer.                                                   #
13 
-- #                                                                                               #
14 
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
15 
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
16 
-- #    provided with the distribution.                                                            #
17 
-- #                                                                                               #
18 
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
19 
-- #    endorse or promote products derived from this software without specific prior written      #
20 
-- #    permission.                                                                                #
21 
-- #                                                                                               #
22 
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
23 
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
24 
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
26 
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
27 
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
28 
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
29 
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
30 
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
32 
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
33 
-- #################################################################################################
34 
 
35 
library ieee;
36 
use ieee.std_logic_1164.all;
37 
use ieee.numeric_std.all;
38 
 
39 
package neorv32_package is
40 
 
41 36 zero_gravi 
  -- Architecture Configuration -------------------------------------------------------------
42 
  -- -------------------------------------------------------------------------------------------
43 40 zero_gravi 
  -- address space --
44 
  constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
45 
  constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
46 36 zero_gravi 
 
47 40 zero_gravi 
  -- (external) bus interface --
48 41 zero_gravi 
  constant bus_timeout_c     : natural := 127; -- cycles after which an *unacknowledged* bus access will timeout and trigger a bus fault exception (min 2)
49 40 zero_gravi 
  constant wb_pipe_mode_c    : boolean := false; -- *external* bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode
50 
  constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian
51 
 
52 
  -- CPU core --
53 41 zero_gravi 
  constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
54 40 zero_gravi 
 
55 54 zero_gravi 
  -- "critical" number of implemented PMP regions --
56 
  -- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
57 
  -- increasing instruction fetch & data access latency by +1 cycle but also reducing critical path length
58 
  constant pmp_num_regions_critical_c : natural := 8; -- default=8
59 47 zero_gravi 
 
60 48 zero_gravi 
  -- Architecture Constants (do not modify!) ------------------------------------------------
61 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
62 47 zero_gravi 
  constant data_width_c   : natural := 32; -- native data path width - do not change!
63 54 zero_gravi 
  constant hw_version_c   : std_ulogic_vector(31 downto 0) := x"01050208"; -- no touchy!
64 40 zero_gravi 
  constant pmp_max_r_c    : natural := 8; -- max PMP regions - FIXED!
65 
  constant archid_c       : natural := 19; -- official NEORV32 architecture ID - hands off!
66 42 zero_gravi 
  constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
67 27 zero_gravi 
 
68 12 zero_gravi 
  -- Helper Functions -----------------------------------------------------------------------
69 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
70 
  function index_size_f(input : natural) return natural;
71 
  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
72 
  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
73 50 zero_gravi 
  function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string;
74 2 zero_gravi 
  function bool_to_ulogic_f(cond : boolean) return std_ulogic;
75 15 zero_gravi 
  function or_all_f(a : std_ulogic_vector) return std_ulogic;
76 
  function and_all_f(a : std_ulogic_vector) return std_ulogic;
77 
  function xor_all_f(a : std_ulogic_vector) return std_ulogic;
78 2 zero_gravi 
  function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
79 6 zero_gravi 
  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
80 40 zero_gravi 
  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector;
81 32 zero_gravi 
  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector;
82 36 zero_gravi 
  function is_power_of_two_f(input : natural) return boolean;
83 40 zero_gravi 
  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;
84 2 zero_gravi 
 
85 15 zero_gravi 
  -- Internal Types -------------------------------------------------------------------------
86 
  -- -------------------------------------------------------------------------------------------
87 42 zero_gravi 
  type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);
88 
  type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0);
89 49 zero_gravi 
  type cp_data_if_t  is array (0 to 7)  of std_ulogic_vector(data_width_c-1 downto 0);
90 15 zero_gravi 
 
91 23 zero_gravi 
  -- Processor-Internal Address Space Layout ------------------------------------------------
92 
  -- -------------------------------------------------------------------------------------------
93 34 zero_gravi 
  -- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
94 39 zero_gravi 
  constant imem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
95 
  constant dmem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
96 42 zero_gravi 
  --> internal data/instruction memory sizes are configured via top's generics
97 2 zero_gravi 
 
98 23 zero_gravi 
  -- Internal Bootloader ROM --
99 
  constant boot_rom_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!
100 47 zero_gravi 
  constant boot_rom_size_c      : natural := 4*1024; -- module's address space in bytes
101 
  constant boot_rom_max_size_c  : natural := 32*1024; -- max module's address space in bytes, fixed!
102 23 zero_gravi 
 
103 2 zero_gravi 
  -- IO: Peripheral Devices ("IO") Area --
104 
  -- Control register(s) (including the device-enable) should be located at the base address of each device
105 47 zero_gravi 
  constant io_base_c            : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00";
106 
  constant io_size_c            : natural := 64*4; -- module's address space in bytes, fixed!
107 2 zero_gravi 
 
108 47 zero_gravi 
  -- Custom Functions Subsystem (CFS) --
109 
  constant cfs_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00"; -- base address
110 
  constant cfs_size_c           : natural := 32*4; -- module's address space in bytes
111 
  constant cfs_reg0_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00";
112 
  constant cfs_reg1_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF04";
113 
  constant cfs_reg2_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF08";
114 
  constant cfs_reg3_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF0C";
115 
  constant cfs_reg4_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF10";
116 
  constant cfs_reg5_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF14";
117 
  constant cfs_reg6_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF18";
118 
  constant cfs_reg7_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF1C";
119 
  constant cfs_reg8_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF20";
120 
  constant cfs_reg9_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF24";
121 
  constant cfs_reg10_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF28";
122 
  constant cfs_reg11_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF2C";
123 
  constant cfs_reg12_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF30";
124 
  constant cfs_reg13_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF34";
125 
  constant cfs_reg14_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF38";
126 
  constant cfs_reg15_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF3C";
127 
  constant cfs_reg16_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF40";
128 
  constant cfs_reg17_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF44";
129 
  constant cfs_reg18_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF48";
130 
  constant cfs_reg19_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF4C";
131 
  constant cfs_reg20_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF50";
132 
  constant cfs_reg21_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF54";
133 
  constant cfs_reg22_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF58";
134 
  constant cfs_reg23_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF5C";
135 
  constant cfs_reg24_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF60";
136 
  constant cfs_reg25_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF64";
137 
  constant cfs_reg26_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF68";
138 
  constant cfs_reg27_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF6C";
139 
  constant cfs_reg28_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF70";
140 
  constant cfs_reg29_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF74";
141 
  constant cfs_reg30_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF78";
142 
  constant cfs_reg31_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF7C";
143 
 
144 2 zero_gravi 
  -- General Purpose Input/Output Unit (GPIO) --
145 47 zero_gravi 
  constant gpio_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address
146 
  constant gpio_size_c          : natural := 2*4; -- module's address space in bytes
147 23 zero_gravi 
  constant gpio_in_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80";
148 
  constant gpio_out_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF84";
149 2 zero_gravi 
 
150 30 zero_gravi 
  -- True Random Number Generator (TRNG) --
151 47 zero_gravi 
  constant trng_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address
152 
  constant trng_size_c          : natural := 1*4; -- module's address space in bytes
153 30 zero_gravi 
  constant trng_ctrl_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88";
154 2 zero_gravi 
 
155 
  -- Watch Dog Timer (WDT) --
156 47 zero_gravi 
  constant wdt_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address
157 
  constant wdt_size_c           : natural := 1*4; -- module's address space in bytes
158 23 zero_gravi 
  constant wdt_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C";
159 2 zero_gravi 
 
160 
  -- Machine System Timer (MTIME) --
161 47 zero_gravi 
  constant mtime_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90"; -- base address
162 
  constant mtime_size_c         : natural := 4*4; -- module's address space in bytes
163 23 zero_gravi 
  constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90";
164 
  constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF94";
165 
  constant mtime_cmp_lo_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF98";
166 
  constant mtime_cmp_hi_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF9C";
167 2 zero_gravi 
 
168 50 zero_gravi 
  -- Universal Asynchronous Receiver/Transmitter 0 (UART0), primary UART --
169 
  constant uart0_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address
170 
  constant uart0_size_c         : natural := 2*4; -- module's address space in bytes
171 
  constant uart0_ctrl_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0";
172 
  constant uart0_rtx_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA4";
173 2 zero_gravi 
 
174 
  -- Serial Peripheral Interface (SPI) --
175 47 zero_gravi 
  constant spi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address
176 
  constant spi_size_c           : natural := 2*4; -- module's address space in bytes
177 23 zero_gravi 
  constant spi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8";
178 
  constant spi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFAC";
179 2 zero_gravi 
 
180 
  -- Two Wire Interface (TWI) --
181 47 zero_gravi 
  constant twi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0"; -- base address
182 
  constant twi_size_c           : natural := 2*4; -- module's address space in bytes
183 23 zero_gravi 
  constant twi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0";
184 
  constant twi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB4";
185 2 zero_gravi 
 
186 
  -- Pulse-Width Modulation Controller (PWM) --
187 47 zero_gravi 
  constant pwm_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address
188 
  constant pwm_size_c           : natural := 2*4; -- module's address space in bytes
189 23 zero_gravi 
  constant pwm_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8";
190 
  constant pwm_duty_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFBC";
191 2 zero_gravi 
 
192 49 zero_gravi 
  -- Numerically-Controlled Oscillator (NCO) --
193 
  constant nco_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address
194 
  constant nco_size_c           : natural := 4*4; -- module's address space in bytes
195 
  constant nco_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0";
196 
  constant nco_ch0_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC4";
197 
  constant nco_ch1_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8";
198 
  constant nco_ch2_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC";
199 
 
200 50 zero_gravi 
  -- Universal Asynchronous Receiver/Transmitter 1 (UART1), secondary UART --
201 
  constant uart1_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address
202 
  constant uart1_size_c         : natural := 2*4; -- module's address space in bytes
203 
  constant uart1_ctrl_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0";
204 
  constant uart1_rtx_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD4";
205 
 
206 52 zero_gravi 
  -- Smart LED (WS2811/WS2812) Interface (NEOLED) --
207 
  constant neoled_base_c        : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD8"; -- base address
208 
  constant neoled_size_c        : natural := 2*4; -- module's address space in bytes
209 
  constant neoled_ctrl_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD8";
210 
  constant neoled_data_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFDC";
211 12 zero_gravi 
 
212 23 zero_gravi 
  -- System Information Memory (SYSINFO) --
213 47 zero_gravi 
  constant sysinfo_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address
214 
  constant sysinfo_size_c       : natural := 8*4; -- module's address space in bytes
215 12 zero_gravi 
 
216 2 zero_gravi 
  -- Main Control Bus -----------------------------------------------------------------------
217 
  -- -------------------------------------------------------------------------------------------
218 
  -- register file --
219 49 zero_gravi 
  constant ctrl_rf_in_mux_c     : natural :=  0; -- input source select lsb (0=MEM, 1=ALU)
220 
  constant ctrl_rf_rs1_adr0_c   : natural :=  1; -- source register 1 address bit 0
221 
  constant ctrl_rf_rs1_adr1_c   : natural :=  2; -- source register 1 address bit 1
222 
  constant ctrl_rf_rs1_adr2_c   : natural :=  3; -- source register 1 address bit 2
223 
  constant ctrl_rf_rs1_adr3_c   : natural :=  4; -- source register 1 address bit 3
224 
  constant ctrl_rf_rs1_adr4_c   : natural :=  5; -- source register 1 address bit 4
225 
  constant ctrl_rf_rs2_adr0_c   : natural :=  6; -- source register 2 address bit 0
226 
  constant ctrl_rf_rs2_adr1_c   : natural :=  7; -- source register 2 address bit 1
227 
  constant ctrl_rf_rs2_adr2_c   : natural :=  8; -- source register 2 address bit 2
228 
  constant ctrl_rf_rs2_adr3_c   : natural :=  9; -- source register 2 address bit 3
229 
  constant ctrl_rf_rs2_adr4_c   : natural := 10; -- source register 2 address bit 4
230 
  constant ctrl_rf_rd_adr0_c    : natural := 11; -- destiantion register address bit 0
231 
  constant ctrl_rf_rd_adr1_c    : natural := 12; -- destiantion register address bit 1
232 
  constant ctrl_rf_rd_adr2_c    : natural := 13; -- destiantion register address bit 2
233 
  constant ctrl_rf_rd_adr3_c    : natural := 14; -- destiantion register address bit 3
234 
  constant ctrl_rf_rd_adr4_c    : natural := 15; -- destiantion register address bit 4
235 
  constant ctrl_rf_wb_en_c      : natural := 16; -- write back enable
236 
  constant ctrl_rf_r0_we_c      : natural := 17; -- force write access and force rd=r0
237 2 zero_gravi 
  -- alu --
238 49 zero_gravi 
  constant ctrl_alu_arith_c     : natural := 18; -- ALU arithmetic command
239 
  constant ctrl_alu_logic0_c    : natural := 19; -- ALU logic command bit 0
240 
  constant ctrl_alu_logic1_c    : natural := 20; -- ALU logic command bit 1
241 
  constant ctrl_alu_func0_c     : natural := 21; -- ALU function select command bit 0
242 
  constant ctrl_alu_func1_c     : natural := 22; -- ALU function select command bit 1
243 
  constant ctrl_alu_addsub_c    : natural := 23; -- 0=ADD, 1=SUB
244 
  constant ctrl_alu_opa_mux_c   : natural := 24; -- operand A select (0=rs1, 1=PC)
245 
  constant ctrl_alu_opb_mux_c   : natural := 25; -- operand B select (0=rs2, 1=IMM)
246 
  constant ctrl_alu_unsigned_c  : natural := 26; -- is unsigned ALU operation
247 
  constant ctrl_alu_shift_dir_c : natural := 27; -- shift direction (0=left, 1=right)
248 
  constant ctrl_alu_shift_ar_c  : natural := 28; -- is arithmetic shift
249 2 zero_gravi 
  -- bus interface --
250 49 zero_gravi 
  constant ctrl_bus_size_lsb_c  : natural := 29; -- transfer size lsb (00=byte, 01=half-word)
251 
  constant ctrl_bus_size_msb_c  : natural := 30; -- transfer size msb (10=word, 11=?)
252 
  constant ctrl_bus_rd_c        : natural := 31; -- read data request
253 
  constant ctrl_bus_wr_c        : natural := 32; -- write data request
254 
  constant ctrl_bus_if_c        : natural := 33; -- instruction fetch request
255 
  constant ctrl_bus_mo_we_c     : natural := 34; -- memory address and data output register write enable
256 
  constant ctrl_bus_mi_we_c     : natural := 35; -- memory data input register write enable
257 53 zero_gravi 
  constant ctrl_bus_unsigned_c  : natural := 36; -- is unsigned load
258 
  constant ctrl_bus_ierr_ack_c  : natural := 37; -- acknowledge instruction fetch bus exceptions
259 
  constant ctrl_bus_derr_ack_c  : natural := 38; -- acknowledge data access bus exceptions
260 
  constant ctrl_bus_fence_c     : natural := 39; -- executed fence operation
261 
  constant ctrl_bus_fencei_c    : natural := 40; -- executed fencei operation
262 
  constant ctrl_bus_excl_c      : natural := 41; -- exclusive bus access
263 26 zero_gravi 
  -- co-processors --
264 53 zero_gravi 
  constant ctrl_cp_id_lsb_c     : natural := 42; -- cp select ID lsb
265 
  constant ctrl_cp_id_hsb_c     : natural := 43; -- cp select ID hsb
266 
  constant ctrl_cp_id_msb_c     : natural := 44; -- cp select ID msb
267 36 zero_gravi 
  -- current privilege level --
268 53 zero_gravi 
  constant ctrl_priv_lvl_lsb_c  : natural := 45; -- privilege level lsb
269 
  constant ctrl_priv_lvl_msb_c  : natural := 46; -- privilege level msb
270 44 zero_gravi 
  -- instruction's control blocks (used by cpu co-processors) --
271 53 zero_gravi 
  constant ctrl_ir_funct3_0_c   : natural := 47; -- funct3 bit 0
272 
  constant ctrl_ir_funct3_1_c   : natural := 48; -- funct3 bit 1
273 
  constant ctrl_ir_funct3_2_c   : natural := 49; -- funct3 bit 2
274 
  constant ctrl_ir_funct12_0_c  : natural := 50; -- funct12 bit 0
275 
  constant ctrl_ir_funct12_1_c  : natural := 51; -- funct12 bit 1
276 
  constant ctrl_ir_funct12_2_c  : natural := 52; -- funct12 bit 2
277 
  constant ctrl_ir_funct12_3_c  : natural := 53; -- funct12 bit 3
278 
  constant ctrl_ir_funct12_4_c  : natural := 54; -- funct12 bit 4
279 
  constant ctrl_ir_funct12_5_c  : natural := 55; -- funct12 bit 5
280 
  constant ctrl_ir_funct12_6_c  : natural := 56; -- funct12 bit 6
281 
  constant ctrl_ir_funct12_7_c  : natural := 57; -- funct12 bit 7
282 
  constant ctrl_ir_funct12_8_c  : natural := 58; -- funct12 bit 8
283 
  constant ctrl_ir_funct12_9_c  : natural := 59; -- funct12 bit 9
284 
  constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10
285 
  constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11
286 
  constant ctrl_ir_opcode7_0_c  : natural := 62; -- opcode7 bit 0
287 
  constant ctrl_ir_opcode7_1_c  : natural := 63; -- opcode7 bit 1
288 
  constant ctrl_ir_opcode7_2_c  : natural := 64; -- opcode7 bit 2
289 
  constant ctrl_ir_opcode7_3_c  : natural := 65; -- opcode7 bit 3
290 
  constant ctrl_ir_opcode7_4_c  : natural := 66; -- opcode7 bit 4
291 
  constant ctrl_ir_opcode7_5_c  : natural := 67; -- opcode7 bit 5
292 
  constant ctrl_ir_opcode7_6_c  : natural := 68; -- opcode7 bit 6
293 47 zero_gravi 
  -- CPU status --
294 53 zero_gravi 
  constant ctrl_sleep_c         : natural := 69; -- set when CPU is in sleep mode
295 2 zero_gravi 
  -- control bus size --
296 53 zero_gravi 
  constant ctrl_width_c         : natural := 70; -- control bus size
297 2 zero_gravi 
 
298 47 zero_gravi 
  -- Comparator Bus -------------------------------------------------------------------------
299 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
300 47 zero_gravi 
  constant cmp_equal_c : natural := 0;
301 
  constant cmp_less_c  : natural := 1; -- for signed and unsigned comparisons
302 2 zero_gravi 
 
303 
  -- RISC-V Opcode Layout -------------------------------------------------------------------
304 
  -- -------------------------------------------------------------------------------------------
305 
  constant instr_opcode_lsb_c  : natural :=  0; -- opcode bit 0
306 
  constant instr_opcode_msb_c  : natural :=  6; -- opcode bit 6
307 
  constant instr_rd_lsb_c      : natural :=  7; -- destination register address bit 0
308 
  constant instr_rd_msb_c      : natural := 11; -- destination register address bit 4
309 
  constant instr_funct3_lsb_c  : natural := 12; -- funct3 bit 0
310 
  constant instr_funct3_msb_c  : natural := 14; -- funct3 bit 2
311 
  constant instr_rs1_lsb_c     : natural := 15; -- source register 1 address bit 0
312 
  constant instr_rs1_msb_c     : natural := 19; -- source register 1 address bit 4
313 
  constant instr_rs2_lsb_c     : natural := 20; -- source register 2 address bit 0
314 
  constant instr_rs2_msb_c     : natural := 24; -- source register 2 address bit 4
315 
  constant instr_funct7_lsb_c  : natural := 25; -- funct7 bit 0
316 
  constant instr_funct7_msb_c  : natural := 31; -- funct7 bit 6
317 
  constant instr_funct12_lsb_c : natural := 20; -- funct12 bit 0
318 
  constant instr_funct12_msb_c : natural := 31; -- funct12 bit 11
319 
  constant instr_imm12_lsb_c   : natural := 20; -- immediate12 bit 0
320 
  constant instr_imm12_msb_c   : natural := 31; -- immediate12 bit 11
321 
  constant instr_imm20_lsb_c   : natural := 12; -- immediate20 bit 0
322 
  constant instr_imm20_msb_c   : natural := 31; -- immediate20 bit 21
323 
  constant instr_csr_id_lsb_c  : natural := 20; -- csr select bit 0
324 
  constant instr_csr_id_msb_c  : natural := 31; -- csr select bit 11
325 39 zero_gravi 
  constant instr_funct5_lsb_c  : natural := 27; -- funct5 select bit 0
326 
  constant instr_funct5_msb_c  : natural := 31; -- funct5 select bit 4
327 2 zero_gravi 
 
328 
  -- RISC-V Opcodes -------------------------------------------------------------------------
329 
  -- -------------------------------------------------------------------------------------------
330 
  -- alu --
331 
  constant opcode_lui_c    : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate
332 
  constant opcode_auipc_c  : std_ulogic_vector(6 downto 0) := "0010111"; -- add upper immediate to PC
333 
  constant opcode_alui_c   : std_ulogic_vector(6 downto 0) := "0010011"; -- ALU operation with immediate (operation via funct3 and funct7)
334 
  constant opcode_alu_c    : std_ulogic_vector(6 downto 0) := "0110011"; -- ALU operation (operation via funct3 and funct7)
335 
  -- control flow --
336 
  constant opcode_jal_c    : std_ulogic_vector(6 downto 0) := "1101111"; -- jump and link
337 29 zero_gravi 
  constant opcode_jalr_c   : std_ulogic_vector(6 downto 0) := "1100111"; -- jump and link with register
338 2 zero_gravi 
  constant opcode_branch_c : std_ulogic_vector(6 downto 0) := "1100011"; -- branch (condition set via funct3)
339 
  -- memory access --
340 
  constant opcode_load_c   : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)
341 
  constant opcode_store_c  : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)
342 
  -- system/csr --
343 8 zero_gravi 
  constant opcode_fence_c  : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
344 2 zero_gravi 
  constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
345 52 zero_gravi 
  -- atomic memory access (A) --
346 39 zero_gravi 
  constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)
347 53 zero_gravi 
  -- floating point operations (Zfinx-only) (F/D/H/Q) --
348 
  constant opcode_fop_c    : std_ulogic_vector(6 downto 0) := "1010011"; -- dual/single opearand instruction
349 2 zero_gravi 
 
350 
  -- RISC-V Funct3 --------------------------------------------------------------------------
351 
  -- -------------------------------------------------------------------------------------------
352 
  -- control flow --
353 
  constant funct3_beq_c    : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
354 
  constant funct3_bne_c    : std_ulogic_vector(2 downto 0) := "001"; -- branch if not equal
355 
  constant funct3_blt_c    : std_ulogic_vector(2 downto 0) := "100"; -- branch if less than
356 
  constant funct3_bge_c    : std_ulogic_vector(2 downto 0) := "101"; -- branch if greater than or equal
357 
  constant funct3_bltu_c   : std_ulogic_vector(2 downto 0) := "110"; -- branch if less than (unsigned)
358 
  constant funct3_bgeu_c   : std_ulogic_vector(2 downto 0) := "111"; -- branch if greater than or equal (unsigned)
359 
  -- memory access --
360 
  constant funct3_lb_c     : std_ulogic_vector(2 downto 0) := "000"; -- load byte
361 
  constant funct3_lh_c     : std_ulogic_vector(2 downto 0) := "001"; -- load half word
362 
  constant funct3_lw_c     : std_ulogic_vector(2 downto 0) := "010"; -- load word
363 
  constant funct3_lbu_c    : std_ulogic_vector(2 downto 0) := "100"; -- load byte (unsigned)
364 
  constant funct3_lhu_c    : std_ulogic_vector(2 downto 0) := "101"; -- load half word (unsigned)
365 
  constant funct3_sb_c     : std_ulogic_vector(2 downto 0) := "000"; -- store byte
366 
  constant funct3_sh_c     : std_ulogic_vector(2 downto 0) := "001"; -- store half word
367 
  constant funct3_sw_c     : std_ulogic_vector(2 downto 0) := "010"; -- store word
368 
  -- alu --
369 
  constant funct3_subadd_c : std_ulogic_vector(2 downto 0) := "000"; -- sub/add via funct7
370 
  constant funct3_sll_c    : std_ulogic_vector(2 downto 0) := "001"; -- shift logical left
371 
  constant funct3_slt_c    : std_ulogic_vector(2 downto 0) := "010"; -- set on less
372 
  constant funct3_sltu_c   : std_ulogic_vector(2 downto 0) := "011"; -- set on less unsigned
373 
  constant funct3_xor_c    : std_ulogic_vector(2 downto 0) := "100"; -- xor
374 
  constant funct3_sr_c     : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7
375 
  constant funct3_or_c     : std_ulogic_vector(2 downto 0) := "110"; -- or
376 
  constant funct3_and_c    : std_ulogic_vector(2 downto 0) := "111"; -- and
377 
  -- system/csr --
378 
  constant funct3_env_c    : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi
379 
  constant funct3_csrrw_c  : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w
380 
  constant funct3_csrrs_c  : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit
381 
  constant funct3_csrrc_c  : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit
382 
  constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate
383 
  constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate
384 
  constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
385 8 zero_gravi 
  -- fence --
386 
  constant funct3_fence_c  : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
387 
  constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync
388 2 zero_gravi 
 
389 39 zero_gravi 
  -- RISC-V Funct12 -------------------------------------------------------------------------
390 11 zero_gravi 
  -- -------------------------------------------------------------------------------------------
391 
  -- system --
392 
  constant funct12_ecall_c  : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
393 
  constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
394 
  constant funct12_mret_c   : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
395 
  constant funct12_wfi_c    : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
396 
 
397 39 zero_gravi 
  -- RISC-V Funct5 --------------------------------------------------------------------------
398 
  -- -------------------------------------------------------------------------------------------
399 
  -- atomic operations --
400 
  constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR
401 
  constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC
402 
 
403 54 zero_gravi 
  -- RISC-V Floating-Point Stuff ------------------------------------------------------------
404 52 zero_gravi 
  -- -------------------------------------------------------------------------------------------
405 54 zero_gravi 
  -- formats --
406 
  constant float_single_c : std_ulogic_vector(1 downto 0) := "00"; -- single-precision (32-bit)
407 
  constant float_double_c : std_ulogic_vector(1 downto 0) := "01"; -- double-precision (64-bit)
408 
  constant float_half_c   : std_ulogic_vector(1 downto 0) := "10"; -- half-precision (16-bit)
409 
  constant float_quad_c   : std_ulogic_vector(1 downto 0) := "11"; -- quad-precision (128-bit)
410 52 zero_gravi 
 
411 54 zero_gravi 
  -- number class flags --
412 
  constant fp_class_neg_inf_c    : natural := 0; -- negative infinity
413 
  constant fp_class_neg_norm_c   : natural := 1; -- negative normal number
414 
  constant fp_class_neg_denorm_c : natural := 2; -- negative subnormal number
415 
  constant fp_class_neg_zero_c   : natural := 3; -- negative zero
416 
  constant fp_class_pos_zero_c   : natural := 4; -- positive zero
417 
  constant fp_class_pos_denorm_c : natural := 5; -- positive subnormal number
418 
  constant fp_class_pos_norm_c   : natural := 6; -- positive normal number
419 
  constant fp_class_pos_inf_c    : natural := 7; -- positive infinity
420 
  constant fp_class_snan_c       : natural := 8; -- signaling NaN (sNaN)
421 
  constant fp_class_qnan_c       : natural := 9; -- quiet NaN (qNaN)
422 
 
423 
  -- exception flags --
424 
  constant fp_exc_nv_c : natural := 0; -- invalid operation
425 
  constant fp_exc_dz_c : natural := 1; -- divide by zero
426 
  constant fp_exc_of_c : natural := 2; -- overflow
427 
  constant fp_exc_uf_c : natural := 3; -- underflow
428 
  constant fp_exc_nx_c : natural := 4; -- inexact
429 
 
430 
  -- special values (single-precision) --
431 
  constant fp_single_qnan_c     : std_ulogic_vector(31 downto 0) := x"7fc00000"; -- quiet NaN
432 
  constant fp_single_snan_c     : std_ulogic_vector(31 downto 0) := x"7fa00000"; -- signaling NaN
433 
  constant fp_single_pos_inf_c  : std_ulogic_vector(31 downto 0) := x"7f800000"; -- positive infinity
434 
  constant fp_single_neg_inf_c  : std_ulogic_vector(31 downto 0) := x"ff800000"; -- negative infinity
435 
  constant fp_single_pos_zero_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- positive zero
436 
  constant fp_single_neg_zero_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- negative zero
437 
 
438 29 zero_gravi 
  -- RISC-V CSR Addresses -------------------------------------------------------------------
439 
  -- -------------------------------------------------------------------------------------------
440 41 zero_gravi 
  -- read/write CSRs --
441 52 zero_gravi 
  constant csr_class_float_c    : std_ulogic_vector(07 downto 0) := x"00"; -- floating point
442 
  constant csr_fflags_c         : std_ulogic_vector(11 downto 0) := x"001";
443 
  constant csr_frm_c            : std_ulogic_vector(11 downto 0) := x"002";
444 
  constant csr_fcsr_c           : std_ulogic_vector(11 downto 0) := x"003";
445 
  --
446 
  constant csr_setup_c          : std_ulogic_vector(07 downto 0) := x"30"; -- trap setup
447 42 zero_gravi 
  constant csr_mstatus_c        : std_ulogic_vector(11 downto 0) := x"300";
448 
  constant csr_misa_c           : std_ulogic_vector(11 downto 0) := x"301";
449 
  constant csr_mie_c            : std_ulogic_vector(11 downto 0) := x"304";
450 
  constant csr_mtvec_c          : std_ulogic_vector(11 downto 0) := x"305";
451 
  constant csr_mcounteren_c     : std_ulogic_vector(11 downto 0) := x"306";
452 52 zero_gravi 
  --
453 42 zero_gravi 
  constant csr_mstatush_c       : std_ulogic_vector(11 downto 0) := x"310";
454 29 zero_gravi 
  --
455 42 zero_gravi 
  constant csr_mcountinhibit_c  : std_ulogic_vector(11 downto 0) := x"320";
456 29 zero_gravi 
  --
457 42 zero_gravi 
  constant csr_mhpmevent3_c     : std_ulogic_vector(11 downto 0) := x"323";
458 
  constant csr_mhpmevent4_c     : std_ulogic_vector(11 downto 0) := x"324";
459 
  constant csr_mhpmevent5_c     : std_ulogic_vector(11 downto 0) := x"325";
460 
  constant csr_mhpmevent6_c     : std_ulogic_vector(11 downto 0) := x"326";
461 
  constant csr_mhpmevent7_c     : std_ulogic_vector(11 downto 0) := x"327";
462 
  constant csr_mhpmevent8_c     : std_ulogic_vector(11 downto 0) := x"328";
463 
  constant csr_mhpmevent9_c     : std_ulogic_vector(11 downto 0) := x"329";
464 
  constant csr_mhpmevent10_c    : std_ulogic_vector(11 downto 0) := x"32a";
465 
  constant csr_mhpmevent11_c    : std_ulogic_vector(11 downto 0) := x"32b";
466 
  constant csr_mhpmevent12_c    : std_ulogic_vector(11 downto 0) := x"32c";
467 
  constant csr_mhpmevent13_c    : std_ulogic_vector(11 downto 0) := x"32d";
468 
  constant csr_mhpmevent14_c    : std_ulogic_vector(11 downto 0) := x"32e";
469 
  constant csr_mhpmevent15_c    : std_ulogic_vector(11 downto 0) := x"32f";
470 
  constant csr_mhpmevent16_c    : std_ulogic_vector(11 downto 0) := x"330";
471 
  constant csr_mhpmevent17_c    : std_ulogic_vector(11 downto 0) := x"331";
472 
  constant csr_mhpmevent18_c    : std_ulogic_vector(11 downto 0) := x"332";
473 
  constant csr_mhpmevent19_c    : std_ulogic_vector(11 downto 0) := x"333";
474 
  constant csr_mhpmevent20_c    : std_ulogic_vector(11 downto 0) := x"334";
475 
  constant csr_mhpmevent21_c    : std_ulogic_vector(11 downto 0) := x"335";
476 
  constant csr_mhpmevent22_c    : std_ulogic_vector(11 downto 0) := x"336";
477 
  constant csr_mhpmevent23_c    : std_ulogic_vector(11 downto 0) := x"337";
478 
  constant csr_mhpmevent24_c    : std_ulogic_vector(11 downto 0) := x"338";
479 
  constant csr_mhpmevent25_c    : std_ulogic_vector(11 downto 0) := x"339";
480 
  constant csr_mhpmevent26_c    : std_ulogic_vector(11 downto 0) := x"33a";
481 
  constant csr_mhpmevent27_c    : std_ulogic_vector(11 downto 0) := x"33b";
482 
  constant csr_mhpmevent28_c    : std_ulogic_vector(11 downto 0) := x"33c";
483 
  constant csr_mhpmevent29_c    : std_ulogic_vector(11 downto 0) := x"33d";
484 
  constant csr_mhpmevent30_c    : std_ulogic_vector(11 downto 0) := x"33e";
485 
  constant csr_mhpmevent31_c    : std_ulogic_vector(11 downto 0) := x"33f";
486 29 zero_gravi 
  --
487 52 zero_gravi 
  constant csr_class_trap_c     : std_ulogic_vector(07 downto 0) := x"34"; -- machine trap handling
488 42 zero_gravi 
  constant csr_mscratch_c       : std_ulogic_vector(11 downto 0) := x"340";
489 
  constant csr_mepc_c           : std_ulogic_vector(11 downto 0) := x"341";
490 
  constant csr_mcause_c         : std_ulogic_vector(11 downto 0) := x"342";
491 
  constant csr_mtval_c          : std_ulogic_vector(11 downto 0) := x"343";
492 
  constant csr_mip_c            : std_ulogic_vector(11 downto 0) := x"344";
493 29 zero_gravi 
  --
494 52 zero_gravi 
  constant csr_class_pmpcfg_c   : std_ulogic_vector(07 downto 0) := x"3a"; -- pmp configuration
495 42 zero_gravi 
  constant csr_pmpcfg0_c        : std_ulogic_vector(11 downto 0) := x"3a0";
496 
  constant csr_pmpcfg1_c        : std_ulogic_vector(11 downto 0) := x"3a1";
497 
  constant csr_pmpcfg2_c        : std_ulogic_vector(11 downto 0) := x"3a2";
498 
  constant csr_pmpcfg3_c        : std_ulogic_vector(11 downto 0) := x"3a3";
499 
  constant csr_pmpcfg4_c        : std_ulogic_vector(11 downto 0) := x"3a4";
500 
  constant csr_pmpcfg5_c        : std_ulogic_vector(11 downto 0) := x"3a5";
501 
  constant csr_pmpcfg6_c        : std_ulogic_vector(11 downto 0) := x"3a6";
502 
  constant csr_pmpcfg7_c        : std_ulogic_vector(11 downto 0) := x"3a7";
503 
  constant csr_pmpcfg8_c        : std_ulogic_vector(11 downto 0) := x"3a8";
504 
  constant csr_pmpcfg9_c        : std_ulogic_vector(11 downto 0) := x"3a9";
505 
  constant csr_pmpcfg10_c       : std_ulogic_vector(11 downto 0) := x"3aa";
506 
  constant csr_pmpcfg11_c       : std_ulogic_vector(11 downto 0) := x"3ab";
507 
  constant csr_pmpcfg12_c       : std_ulogic_vector(11 downto 0) := x"3ac";
508 
  constant csr_pmpcfg13_c       : std_ulogic_vector(11 downto 0) := x"3ad";
509 
  constant csr_pmpcfg14_c       : std_ulogic_vector(11 downto 0) := x"3ae";
510 
  constant csr_pmpcfg15_c       : std_ulogic_vector(11 downto 0) := x"3af";
511 29 zero_gravi 
  --
512 42 zero_gravi 
  constant csr_pmpaddr0_c       : std_ulogic_vector(11 downto 0) := x"3b0";
513 
  constant csr_pmpaddr1_c       : std_ulogic_vector(11 downto 0) := x"3b1";
514 
  constant csr_pmpaddr2_c       : std_ulogic_vector(11 downto 0) := x"3b2";
515 
  constant csr_pmpaddr3_c       : std_ulogic_vector(11 downto 0) := x"3b3";
516 
  constant csr_pmpaddr4_c       : std_ulogic_vector(11 downto 0) := x"3b4";
517 
  constant csr_pmpaddr5_c       : std_ulogic_vector(11 downto 0) := x"3b5";
518 
  constant csr_pmpaddr6_c       : std_ulogic_vector(11 downto 0) := x"3b6";
519 
  constant csr_pmpaddr7_c       : std_ulogic_vector(11 downto 0) := x"3b7";
520 
  constant csr_pmpaddr8_c       : std_ulogic_vector(11 downto 0) := x"3b8";
521 
  constant csr_pmpaddr9_c       : std_ulogic_vector(11 downto 0) := x"3b9";
522 
  constant csr_pmpaddr10_c      : std_ulogic_vector(11 downto 0) := x"3ba";
523 
  constant csr_pmpaddr11_c      : std_ulogic_vector(11 downto 0) := x"3bb";
524 
  constant csr_pmpaddr12_c      : std_ulogic_vector(11 downto 0) := x"3bc";
525 
  constant csr_pmpaddr13_c      : std_ulogic_vector(11 downto 0) := x"3bd";
526 
  constant csr_pmpaddr14_c      : std_ulogic_vector(11 downto 0) := x"3be";
527 
  constant csr_pmpaddr15_c      : std_ulogic_vector(11 downto 0) := x"3bf";
528 
  constant csr_pmpaddr16_c      : std_ulogic_vector(11 downto 0) := x"3c0";
529 
  constant csr_pmpaddr17_c      : std_ulogic_vector(11 downto 0) := x"3c1";
530 
  constant csr_pmpaddr18_c      : std_ulogic_vector(11 downto 0) := x"3c2";
531 
  constant csr_pmpaddr19_c      : std_ulogic_vector(11 downto 0) := x"3c3";
532 
  constant csr_pmpaddr20_c      : std_ulogic_vector(11 downto 0) := x"3c4";
533 
  constant csr_pmpaddr21_c      : std_ulogic_vector(11 downto 0) := x"3c5";
534 
  constant csr_pmpaddr22_c      : std_ulogic_vector(11 downto 0) := x"3c6";
535 
  constant csr_pmpaddr23_c      : std_ulogic_vector(11 downto 0) := x"3c7";
536 
  constant csr_pmpaddr24_c      : std_ulogic_vector(11 downto 0) := x"3c8";
537 
  constant csr_pmpaddr25_c      : std_ulogic_vector(11 downto 0) := x"3c9";
538 
  constant csr_pmpaddr26_c      : std_ulogic_vector(11 downto 0) := x"3ca";
539 
  constant csr_pmpaddr27_c      : std_ulogic_vector(11 downto 0) := x"3cb";
540 
  constant csr_pmpaddr28_c      : std_ulogic_vector(11 downto 0) := x"3cc";
541 
  constant csr_pmpaddr29_c      : std_ulogic_vector(11 downto 0) := x"3cd";
542 
  constant csr_pmpaddr30_c      : std_ulogic_vector(11 downto 0) := x"3ce";
543 
  constant csr_pmpaddr31_c      : std_ulogic_vector(11 downto 0) := x"3cf";
544 
  constant csr_pmpaddr32_c      : std_ulogic_vector(11 downto 0) := x"3d0";
545 
  constant csr_pmpaddr33_c      : std_ulogic_vector(11 downto 0) := x"3d1";
546 
  constant csr_pmpaddr34_c      : std_ulogic_vector(11 downto 0) := x"3d2";
547 
  constant csr_pmpaddr35_c      : std_ulogic_vector(11 downto 0) := x"3d3";
548 
  constant csr_pmpaddr36_c      : std_ulogic_vector(11 downto 0) := x"3d4";
549 
  constant csr_pmpaddr37_c      : std_ulogic_vector(11 downto 0) := x"3d5";
550 
  constant csr_pmpaddr38_c      : std_ulogic_vector(11 downto 0) := x"3d6";
551 
  constant csr_pmpaddr39_c      : std_ulogic_vector(11 downto 0) := x"3d7";
552 
  constant csr_pmpaddr40_c      : std_ulogic_vector(11 downto 0) := x"3d8";
553 
  constant csr_pmpaddr41_c      : std_ulogic_vector(11 downto 0) := x"3d9";
554 
  constant csr_pmpaddr42_c      : std_ulogic_vector(11 downto 0) := x"3da";
555 
  constant csr_pmpaddr43_c      : std_ulogic_vector(11 downto 0) := x"3db";
556 
  constant csr_pmpaddr44_c      : std_ulogic_vector(11 downto 0) := x"3dc";
557 
  constant csr_pmpaddr45_c      : std_ulogic_vector(11 downto 0) := x"3dd";
558 
  constant csr_pmpaddr46_c      : std_ulogic_vector(11 downto 0) := x"3de";
559 
  constant csr_pmpaddr47_c      : std_ulogic_vector(11 downto 0) := x"3df";
560 
  constant csr_pmpaddr48_c      : std_ulogic_vector(11 downto 0) := x"3e0";
561 
  constant csr_pmpaddr49_c      : std_ulogic_vector(11 downto 0) := x"3e1";
562 
  constant csr_pmpaddr50_c      : std_ulogic_vector(11 downto 0) := x"3e2";
563 
  constant csr_pmpaddr51_c      : std_ulogic_vector(11 downto 0) := x"3e3";
564 
  constant csr_pmpaddr52_c      : std_ulogic_vector(11 downto 0) := x"3e4";
565 
  constant csr_pmpaddr53_c      : std_ulogic_vector(11 downto 0) := x"3e5";
566 
  constant csr_pmpaddr54_c      : std_ulogic_vector(11 downto 0) := x"3e6";
567 
  constant csr_pmpaddr55_c      : std_ulogic_vector(11 downto 0) := x"3e7";
568 
  constant csr_pmpaddr56_c      : std_ulogic_vector(11 downto 0) := x"3e8";
569 
  constant csr_pmpaddr57_c      : std_ulogic_vector(11 downto 0) := x"3e9";
570 
  constant csr_pmpaddr58_c      : std_ulogic_vector(11 downto 0) := x"3ea";
571 
  constant csr_pmpaddr59_c      : std_ulogic_vector(11 downto 0) := x"3eb";
572 
  constant csr_pmpaddr60_c      : std_ulogic_vector(11 downto 0) := x"3ec";
573 
  constant csr_pmpaddr61_c      : std_ulogic_vector(11 downto 0) := x"3ed";
574 
  constant csr_pmpaddr62_c      : std_ulogic_vector(11 downto 0) := x"3ee";
575 
  constant csr_pmpaddr63_c      : std_ulogic_vector(11 downto 0) := x"3ef";
576 29 zero_gravi 
  --
577 42 zero_gravi 
  constant csr_mcycle_c         : std_ulogic_vector(11 downto 0) := x"b00";
578 
  constant csr_minstret_c       : std_ulogic_vector(11 downto 0) := x"b02";
579 
  --
580 
  constant csr_mhpmcounter3_c   : std_ulogic_vector(11 downto 0) := x"b03";
581 
  constant csr_mhpmcounter4_c   : std_ulogic_vector(11 downto 0) := x"b04";
582 
  constant csr_mhpmcounter5_c   : std_ulogic_vector(11 downto 0) := x"b05";
583 
  constant csr_mhpmcounter6_c   : std_ulogic_vector(11 downto 0) := x"b06";
584 
  constant csr_mhpmcounter7_c   : std_ulogic_vector(11 downto 0) := x"b07";
585 
  constant csr_mhpmcounter8_c   : std_ulogic_vector(11 downto 0) := x"b08";
586 
  constant csr_mhpmcounter9_c   : std_ulogic_vector(11 downto 0) := x"b09";
587 
  constant csr_mhpmcounter10_c  : std_ulogic_vector(11 downto 0) := x"b0a";
588 
  constant csr_mhpmcounter11_c  : std_ulogic_vector(11 downto 0) := x"b0b";
589 
  constant csr_mhpmcounter12_c  : std_ulogic_vector(11 downto 0) := x"b0c";
590 
  constant csr_mhpmcounter13_c  : std_ulogic_vector(11 downto 0) := x"b0d";
591 
  constant csr_mhpmcounter14_c  : std_ulogic_vector(11 downto 0) := x"b0e";
592 
  constant csr_mhpmcounter15_c  : std_ulogic_vector(11 downto 0) := x"b0f";
593 
  constant csr_mhpmcounter16_c  : std_ulogic_vector(11 downto 0) := x"b10";
594 
  constant csr_mhpmcounter17_c  : std_ulogic_vector(11 downto 0) := x"b11";
595 
  constant csr_mhpmcounter18_c  : std_ulogic_vector(11 downto 0) := x"b12";
596 
  constant csr_mhpmcounter19_c  : std_ulogic_vector(11 downto 0) := x"b13";
597 
  constant csr_mhpmcounter20_c  : std_ulogic_vector(11 downto 0) := x"b14";
598 
  constant csr_mhpmcounter21_c  : std_ulogic_vector(11 downto 0) := x"b15";
599 
  constant csr_mhpmcounter22_c  : std_ulogic_vector(11 downto 0) := x"b16";
600 
  constant csr_mhpmcounter23_c  : std_ulogic_vector(11 downto 0) := x"b17";
601 
  constant csr_mhpmcounter24_c  : std_ulogic_vector(11 downto 0) := x"b18";
602 
  constant csr_mhpmcounter25_c  : std_ulogic_vector(11 downto 0) := x"b19";
603 
  constant csr_mhpmcounter26_c  : std_ulogic_vector(11 downto 0) := x"b1a";
604 
  constant csr_mhpmcounter27_c  : std_ulogic_vector(11 downto 0) := x"b1b";
605 
  constant csr_mhpmcounter28_c  : std_ulogic_vector(11 downto 0) := x"b1c";
606 
  constant csr_mhpmcounter29_c  : std_ulogic_vector(11 downto 0) := x"b1d";
607 
  constant csr_mhpmcounter30_c  : std_ulogic_vector(11 downto 0) := x"b1e";
608 
  constant csr_mhpmcounter31_c  : std_ulogic_vector(11 downto 0) := x"b1f";
609 
  --
610 
  constant csr_mcycleh_c        : std_ulogic_vector(11 downto 0) := x"b80";
611 
  constant csr_minstreth_c      : std_ulogic_vector(11 downto 0) := x"b82";
612 
  --
613 
  constant csr_mhpmcounter3h_c  : std_ulogic_vector(11 downto 0) := x"b83";
614 
  constant csr_mhpmcounter4h_c  : std_ulogic_vector(11 downto 0) := x"b84";
615 
  constant csr_mhpmcounter5h_c  : std_ulogic_vector(11 downto 0) := x"b85";
616 
  constant csr_mhpmcounter6h_c  : std_ulogic_vector(11 downto 0) := x"b86";
617 
  constant csr_mhpmcounter7h_c  : std_ulogic_vector(11 downto 0) := x"b87";
618 
  constant csr_mhpmcounter8h_c  : std_ulogic_vector(11 downto 0) := x"b88";
619 
  constant csr_mhpmcounter9h_c  : std_ulogic_vector(11 downto 0) := x"b89";
620 
  constant csr_mhpmcounter10h_c : std_ulogic_vector(11 downto 0) := x"b8a";
621 
  constant csr_mhpmcounter11h_c : std_ulogic_vector(11 downto 0) := x"b8b";
622 
  constant csr_mhpmcounter12h_c : std_ulogic_vector(11 downto 0) := x"b8c";
623 
  constant csr_mhpmcounter13h_c : std_ulogic_vector(11 downto 0) := x"b8d";
624 
  constant csr_mhpmcounter14h_c : std_ulogic_vector(11 downto 0) := x"b8e";
625 
  constant csr_mhpmcounter15h_c : std_ulogic_vector(11 downto 0) := x"b8f";
626 
  constant csr_mhpmcounter16h_c : std_ulogic_vector(11 downto 0) := x"b90";
627 
  constant csr_mhpmcounter17h_c : std_ulogic_vector(11 downto 0) := x"b91";
628 
  constant csr_mhpmcounter18h_c : std_ulogic_vector(11 downto 0) := x"b92";
629 
  constant csr_mhpmcounter19h_c : std_ulogic_vector(11 downto 0) := x"b93";
630 
  constant csr_mhpmcounter20h_c : std_ulogic_vector(11 downto 0) := x"b94";
631 
  constant csr_mhpmcounter21h_c : std_ulogic_vector(11 downto 0) := x"b95";
632 
  constant csr_mhpmcounter22h_c : std_ulogic_vector(11 downto 0) := x"b96";
633 
  constant csr_mhpmcounter23h_c : std_ulogic_vector(11 downto 0) := x"b97";
634 
  constant csr_mhpmcounter24h_c : std_ulogic_vector(11 downto 0) := x"b98";
635 
  constant csr_mhpmcounter25h_c : std_ulogic_vector(11 downto 0) := x"b99";
636 
  constant csr_mhpmcounter26h_c : std_ulogic_vector(11 downto 0) := x"b9a";
637 
  constant csr_mhpmcounter27h_c : std_ulogic_vector(11 downto 0) := x"b9b";
638 
  constant csr_mhpmcounter28h_c : std_ulogic_vector(11 downto 0) := x"b9c";
639 
  constant csr_mhpmcounter29h_c : std_ulogic_vector(11 downto 0) := x"b9d";
640 
  constant csr_mhpmcounter30h_c : std_ulogic_vector(11 downto 0) := x"b9e";
641 
  constant csr_mhpmcounter31h_c : std_ulogic_vector(11 downto 0) := x"b9f";
642 
 
643 41 zero_gravi 
  -- read-only CSRs --
644 42 zero_gravi 
  constant csr_cycle_c          : std_ulogic_vector(11 downto 0) := x"c00";
645 
  constant csr_time_c           : std_ulogic_vector(11 downto 0) := x"c01";
646 
  constant csr_instret_c        : std_ulogic_vector(11 downto 0) := x"c02";
647 29 zero_gravi 
  --
648 42 zero_gravi 
  constant csr_hpmcounter3_c    : std_ulogic_vector(11 downto 0) := x"c03";
649 
  constant csr_hpmcounter4_c    : std_ulogic_vector(11 downto 0) := x"c04";
650 
  constant csr_hpmcounter5_c    : std_ulogic_vector(11 downto 0) := x"c05";
651 
  constant csr_hpmcounter6_c    : std_ulogic_vector(11 downto 0) := x"c06";
652 
  constant csr_hpmcounter7_c    : std_ulogic_vector(11 downto 0) := x"c07";
653 
  constant csr_hpmcounter8_c    : std_ulogic_vector(11 downto 0) := x"c08";
654 
  constant csr_hpmcounter9_c    : std_ulogic_vector(11 downto 0) := x"c09";
655 
  constant csr_hpmcounter10_c   : std_ulogic_vector(11 downto 0) := x"c0a";
656 
  constant csr_hpmcounter11_c   : std_ulogic_vector(11 downto 0) := x"c0b";
657 
  constant csr_hpmcounter12_c   : std_ulogic_vector(11 downto 0) := x"c0c";
658 
  constant csr_hpmcounter13_c   : std_ulogic_vector(11 downto 0) := x"c0d";
659 
  constant csr_hpmcounter14_c   : std_ulogic_vector(11 downto 0) := x"c0e";
660 
  constant csr_hpmcounter15_c   : std_ulogic_vector(11 downto 0) := x"c0f";
661 
  constant csr_hpmcounter16_c   : std_ulogic_vector(11 downto 0) := x"c10";
662 
  constant csr_hpmcounter17_c   : std_ulogic_vector(11 downto 0) := x"c11";
663 
  constant csr_hpmcounter18_c   : std_ulogic_vector(11 downto 0) := x"c12";
664 
  constant csr_hpmcounter19_c   : std_ulogic_vector(11 downto 0) := x"c13";
665 
  constant csr_hpmcounter20_c   : std_ulogic_vector(11 downto 0) := x"c14";
666 
  constant csr_hpmcounter21_c   : std_ulogic_vector(11 downto 0) := x"c15";
667 
  constant csr_hpmcounter22_c   : std_ulogic_vector(11 downto 0) := x"c16";
668 
  constant csr_hpmcounter23_c   : std_ulogic_vector(11 downto 0) := x"c17";
669 
  constant csr_hpmcounter24_c   : std_ulogic_vector(11 downto 0) := x"c18";
670 
  constant csr_hpmcounter25_c   : std_ulogic_vector(11 downto 0) := x"c19";
671 
  constant csr_hpmcounter26_c   : std_ulogic_vector(11 downto 0) := x"c1a";
672 
  constant csr_hpmcounter27_c   : std_ulogic_vector(11 downto 0) := x"c1b";
673 
  constant csr_hpmcounter28_c   : std_ulogic_vector(11 downto 0) := x"c1c";
674 
  constant csr_hpmcounter29_c   : std_ulogic_vector(11 downto 0) := x"c1d";
675 
  constant csr_hpmcounter30_c   : std_ulogic_vector(11 downto 0) := x"c1e";
676 
  constant csr_hpmcounter31_c   : std_ulogic_vector(11 downto 0) := x"c1f";
677 29 zero_gravi 
  --
678 42 zero_gravi 
  constant csr_cycleh_c         : std_ulogic_vector(11 downto 0) := x"c80";
679 
  constant csr_timeh_c          : std_ulogic_vector(11 downto 0) := x"c81";
680 
  constant csr_instreth_c       : std_ulogic_vector(11 downto 0) := x"c82";
681 29 zero_gravi 
  --
682 42 zero_gravi 
  constant csr_hpmcounter3h_c   : std_ulogic_vector(11 downto 0) := x"c83";
683 
  constant csr_hpmcounter4h_c   : std_ulogic_vector(11 downto 0) := x"c84";
684 
  constant csr_hpmcounter5h_c   : std_ulogic_vector(11 downto 0) := x"c85";
685 
  constant csr_hpmcounter6h_c   : std_ulogic_vector(11 downto 0) := x"c86";
686 
  constant csr_hpmcounter7h_c   : std_ulogic_vector(11 downto 0) := x"c87";
687 
  constant csr_hpmcounter8h_c   : std_ulogic_vector(11 downto 0) := x"c88";
688 
  constant csr_hpmcounter9h_c   : std_ulogic_vector(11 downto 0) := x"c89";
689 
  constant csr_hpmcounter10h_c  : std_ulogic_vector(11 downto 0) := x"c8a";
690 
  constant csr_hpmcounter11h_c  : std_ulogic_vector(11 downto 0) := x"c8b";
691 
  constant csr_hpmcounter12h_c  : std_ulogic_vector(11 downto 0) := x"c8c";
692 
  constant csr_hpmcounter13h_c  : std_ulogic_vector(11 downto 0) := x"c8d";
693 
  constant csr_hpmcounter14h_c  : std_ulogic_vector(11 downto 0) := x"c8e";
694 
  constant csr_hpmcounter15h_c  : std_ulogic_vector(11 downto 0) := x"c8f";
695 
  constant csr_hpmcounter16h_c  : std_ulogic_vector(11 downto 0) := x"c90";
696 
  constant csr_hpmcounter17h_c  : std_ulogic_vector(11 downto 0) := x"c91";
697 
  constant csr_hpmcounter18h_c  : std_ulogic_vector(11 downto 0) := x"c92";
698 
  constant csr_hpmcounter19h_c  : std_ulogic_vector(11 downto 0) := x"c93";
699 
  constant csr_hpmcounter20h_c  : std_ulogic_vector(11 downto 0) := x"c94";
700 
  constant csr_hpmcounter21h_c  : std_ulogic_vector(11 downto 0) := x"c95";
701 
  constant csr_hpmcounter22h_c  : std_ulogic_vector(11 downto 0) := x"c96";
702 
  constant csr_hpmcounter23h_c  : std_ulogic_vector(11 downto 0) := x"c97";
703 
  constant csr_hpmcounter24h_c  : std_ulogic_vector(11 downto 0) := x"c98";
704 
  constant csr_hpmcounter25h_c  : std_ulogic_vector(11 downto 0) := x"c99";
705 
  constant csr_hpmcounter26h_c  : std_ulogic_vector(11 downto 0) := x"c9a";
706 
  constant csr_hpmcounter27h_c  : std_ulogic_vector(11 downto 0) := x"c9b";
707 
  constant csr_hpmcounter28h_c  : std_ulogic_vector(11 downto 0) := x"c9c";
708 
  constant csr_hpmcounter29h_c  : std_ulogic_vector(11 downto 0) := x"c9d";
709 
  constant csr_hpmcounter30h_c  : std_ulogic_vector(11 downto 0) := x"c9e";
710 
  constant csr_hpmcounter31h_c  : std_ulogic_vector(11 downto 0) := x"c9f";
711 
  --
712 
  constant csr_mvendorid_c      : std_ulogic_vector(11 downto 0) := x"f11";
713 
  constant csr_marchid_c        : std_ulogic_vector(11 downto 0) := x"f12";
714 
  constant csr_mimpid_c         : std_ulogic_vector(11 downto 0) := x"f13";
715 
  constant csr_mhartid_c        : std_ulogic_vector(11 downto 0) := x"f14";
716 29 zero_gravi 
 
717 42 zero_gravi 
  -- custom read-only CSRs --
718 
  constant csr_mzext_c          : std_ulogic_vector(11 downto 0) := x"fc0";
719 
 
720 44 zero_gravi 
  -- Co-Processor IDs -----------------------------------------------------------------------
721 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
722 49 zero_gravi 
  constant cp_sel_muldiv_c   : std_ulogic_vector(2 downto 0) := "000"; -- multiplication/division operations ('M' extension)
723 
  constant cp_sel_atomic_c   : std_ulogic_vector(2 downto 0) := "001"; -- atomic operations; success/failure evaluation ('A' extension)
724 
  constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- bit manipulation ('B' extension)
725 
  constant cp_sel_csr_rd_c   : std_ulogic_vector(2 downto 0) := "011"; -- CSR read access ('Zicsr' extension)
726 53 zero_gravi 
  constant cp_sel_fpu_c      : std_ulogic_vector(2 downto 0) := "100"; -- loating-point unit ('Zfinx' extension)
727 
--constant cp_sel_crypto_c   : std_ulogic_vector(2 downto 0) := "101"; -- crypto operations ('K' extension)
728 52 zero_gravi 
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "110"; -- reserved
729 
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "111"; -- reserved
730 2 zero_gravi 
 
731 
  -- ALU Function Codes ---------------------------------------------------------------------
732 
  -- -------------------------------------------------------------------------------------------
733 39 zero_gravi 
  -- arithmetic core --
734 
  constant alu_arith_cmd_addsub_c : std_ulogic := '0'; -- r.arith <= A +/- B
735 
  constant alu_arith_cmd_slt_c    : std_ulogic := '1'; -- r.arith <= A < B
736 
  -- logic core --
737 
  constant alu_logic_cmd_movb_c   : std_ulogic_vector(1 downto 0) := "00"; -- r.logic <= B
738 
  constant alu_logic_cmd_xor_c    : std_ulogic_vector(1 downto 0) := "01"; -- r.logic <= A xor B
739 
  constant alu_logic_cmd_or_c     : std_ulogic_vector(1 downto 0) := "10"; -- r.logic <= A or B
740 
  constant alu_logic_cmd_and_c    : std_ulogic_vector(1 downto 0) := "11"; -- r.logic <= A and B
741 
  -- function select (actual alu result) --
742 
  constant alu_func_cmd_arith_c   : std_ulogic_vector(1 downto 0) := "00"; -- r <= r.arith
743 
  constant alu_func_cmd_logic_c   : std_ulogic_vector(1 downto 0) := "01"; -- r <= r.logic
744 
  constant alu_func_cmd_shift_c   : std_ulogic_vector(1 downto 0) := "10"; -- r <= A <</>> B (iterative)
745 
  constant alu_func_cmd_copro_c   : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (iterative)
746 2 zero_gravi 
 
747 12 zero_gravi 
  -- Trap ID Codes --------------------------------------------------------------------------
748 
  -- -------------------------------------------------------------------------------------------
749 48 zero_gravi 
  -- RISC-V compliant sync. exceptions --
750 
  constant trap_ima_c    : std_ulogic_vector(5 downto 0) := "0" & "00000"; -- 0.0:  instruction misaligned
751 
  constant trap_iba_c    : std_ulogic_vector(5 downto 0) := "0" & "00001"; -- 0.1:  instruction access fault
752 
  constant trap_iil_c    : std_ulogic_vector(5 downto 0) := "0" & "00010"; -- 0.2:  illegal instruction
753 
  constant trap_brk_c    : std_ulogic_vector(5 downto 0) := "0" & "00011"; -- 0.3:  breakpoint
754 
  constant trap_lma_c    : std_ulogic_vector(5 downto 0) := "0" & "00100"; -- 0.4:  load address misaligned
755 
  constant trap_lbe_c    : std_ulogic_vector(5 downto 0) := "0" & "00101"; -- 0.5:  load access fault
756 
  constant trap_sma_c    : std_ulogic_vector(5 downto 0) := "0" & "00110"; -- 0.6:  store address misaligned
757 
  constant trap_sbe_c    : std_ulogic_vector(5 downto 0) := "0" & "00111"; -- 0.7:  store access fault
758 
  constant trap_uenv_c   : std_ulogic_vector(5 downto 0) := "0" & "01000"; -- 0.8:  environment call from u-mode
759 
  constant trap_menv_c   : std_ulogic_vector(5 downto 0) := "0" & "01011"; -- 0.11: environment call from m-mode
760 
  -- RISC-V compliant interrupts (async. exceptions) --
761 
  constant trap_msi_c    : std_ulogic_vector(5 downto 0) := "1" & "00011"; -- 1.3:  machine software interrupt
762 
  constant trap_mti_c    : std_ulogic_vector(5 downto 0) := "1" & "00111"; -- 1.7:  machine timer interrupt
763 
  constant trap_mei_c    : std_ulogic_vector(5 downto 0) := "1" & "01011"; -- 1.11: machine external interrupt
764 
  -- NEORV32-specific (custom) interrupts (async. exceptions) --
765 
  constant trap_reset_c  : std_ulogic_vector(5 downto 0) := "1" & "00000"; -- 1.0:  hardware reset
766 
  constant trap_firq0_c  : std_ulogic_vector(5 downto 0) := "1" & "10000"; -- 1.16: fast interrupt 0
767 
  constant trap_firq1_c  : std_ulogic_vector(5 downto 0) := "1" & "10001"; -- 1.17: fast interrupt 1
768 
  constant trap_firq2_c  : std_ulogic_vector(5 downto 0) := "1" & "10010"; -- 1.18: fast interrupt 2
769 
  constant trap_firq3_c  : std_ulogic_vector(5 downto 0) := "1" & "10011"; -- 1.19: fast interrupt 3
770 
  constant trap_firq4_c  : std_ulogic_vector(5 downto 0) := "1" & "10100"; -- 1.20: fast interrupt 4
771 
  constant trap_firq5_c  : std_ulogic_vector(5 downto 0) := "1" & "10101"; -- 1.21: fast interrupt 5
772 
  constant trap_firq6_c  : std_ulogic_vector(5 downto 0) := "1" & "10110"; -- 1.22: fast interrupt 6
773 
  constant trap_firq7_c  : std_ulogic_vector(5 downto 0) := "1" & "10111"; -- 1.23: fast interrupt 7
774 
  constant trap_firq8_c  : std_ulogic_vector(5 downto 0) := "1" & "11000"; -- 1.24: fast interrupt 8
775 
  constant trap_firq9_c  : std_ulogic_vector(5 downto 0) := "1" & "11001"; -- 1.25: fast interrupt 9
776 
  constant trap_firq10_c : std_ulogic_vector(5 downto 0) := "1" & "11010"; -- 1.26: fast interrupt 10
777 
  constant trap_firq11_c : std_ulogic_vector(5 downto 0) := "1" & "11011"; -- 1.27: fast interrupt 11
778 
  constant trap_firq12_c : std_ulogic_vector(5 downto 0) := "1" & "11100"; -- 1.28: fast interrupt 12
779 
  constant trap_firq13_c : std_ulogic_vector(5 downto 0) := "1" & "11101"; -- 1.29: fast interrupt 13
780 
  constant trap_firq14_c : std_ulogic_vector(5 downto 0) := "1" & "11110"; -- 1.30: fast interrupt 14
781 
  constant trap_firq15_c : std_ulogic_vector(5 downto 0) := "1" & "11111"; -- 1.31: fast interrupt 15
782 12 zero_gravi 
 
783 2 zero_gravi 
  -- CPU Control Exception System -----------------------------------------------------------
784 
  -- -------------------------------------------------------------------------------------------
785 
  -- exception source bits --
786 47 zero_gravi 
  constant exception_iaccess_c   : natural :=  0; -- instrution access fault
787 
  constant exception_iillegal_c  : natural :=  1; -- illegal instrution
788 
  constant exception_ialign_c    : natural :=  2; -- instrution address misaligned
789 
  constant exception_m_envcall_c : natural :=  3; -- ENV call from m-mode
790 
  constant exception_u_envcall_c : natural :=  4; -- ENV call from u-mode
791 
  constant exception_break_c     : natural :=  5; -- breakpoint
792 
  constant exception_salign_c    : natural :=  6; -- store address misaligned
793 
  constant exception_lalign_c    : natural :=  7; -- load address misaligned
794 
  constant exception_saccess_c   : natural :=  8; -- store access fault
795 
  constant exception_laccess_c   : natural :=  9; -- load access fault
796 14 zero_gravi 
  --
797 40 zero_gravi 
  constant exception_width_c     : natural := 10; -- length of this list in bits
798 2 zero_gravi 
  -- interrupt source bits --
799 47 zero_gravi 
  constant interrupt_msw_irq_c   : natural :=  0; -- machine software interrupt
800 
  constant interrupt_mtime_irq_c : natural :=  1; -- machine timer interrupt
801 
  constant interrupt_mext_irq_c  : natural :=  2; -- machine external interrupt
802 
  constant interrupt_firq_0_c    : natural :=  3; -- fast interrupt channel 0
803 
  constant interrupt_firq_1_c    : natural :=  4; -- fast interrupt channel 1
804 
  constant interrupt_firq_2_c    : natural :=  5; -- fast interrupt channel 2
805 
  constant interrupt_firq_3_c    : natural :=  6; -- fast interrupt channel 3
806 
  constant interrupt_firq_4_c    : natural :=  7; -- fast interrupt channel 4
807 
  constant interrupt_firq_5_c    : natural :=  8; -- fast interrupt channel 5
808 
  constant interrupt_firq_6_c    : natural :=  9; -- fast interrupt channel 6
809 
  constant interrupt_firq_7_c    : natural := 10; -- fast interrupt channel 7
810 48 zero_gravi 
  constant interrupt_firq_8_c    : natural := 11; -- fast interrupt channel 8
811 
  constant interrupt_firq_9_c    : natural := 12; -- fast interrupt channel 9
812 
  constant interrupt_firq_10_c   : natural := 13; -- fast interrupt channel 10
813 
  constant interrupt_firq_11_c   : natural := 14; -- fast interrupt channel 11
814 
  constant interrupt_firq_12_c   : natural := 15; -- fast interrupt channel 12
815 
  constant interrupt_firq_13_c   : natural := 16; -- fast interrupt channel 13
816 
  constant interrupt_firq_14_c   : natural := 17; -- fast interrupt channel 14
817 
  constant interrupt_firq_15_c   : natural := 18; -- fast interrupt channel 15
818 14 zero_gravi 
  --
819 48 zero_gravi 
  constant interrupt_width_c     : natural := 19; -- length of this list in bits
820 2 zero_gravi 
 
821 15 zero_gravi 
  -- CPU Privilege Modes --------------------------------------------------------------------
822 
  -- -------------------------------------------------------------------------------------------
823 29 zero_gravi 
  constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
824 
  constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
825 15 zero_gravi 
 
826 42 zero_gravi 
  -- HPM Event System -----------------------------------------------------------------------
827 
  -- -------------------------------------------------------------------------------------------
828 
  constant hpmcnt_event_cy_c      : natural := 0;  -- Active cycle
829 
  constant hpmcnt_event_never_c   : natural := 1;
830 
  constant hpmcnt_event_ir_c      : natural := 2;  -- Retired instruction
831 
  constant hpmcnt_event_cir_c     : natural := 3;  -- Retired compressed instruction
832 
  constant hpmcnt_event_wait_if_c : natural := 4;  -- Instruction fetch memory wait cycle
833 
  constant hpmcnt_event_wait_ii_c : natural := 5;  -- Instruction issue wait cycle
834 45 zero_gravi 
  constant hpmcnt_event_wait_mc_c : natural := 6;  -- Multi-cycle ALU-operation wait cycle
835 
  constant hpmcnt_event_load_c    : natural := 7;  -- Load operation
836 
  constant hpmcnt_event_store_c   : natural := 8;  -- Store operation
837 
  constant hpmcnt_event_wait_ls_c : natural := 9;  -- Load/store memory wait cycle
838 
  constant hpmcnt_event_jump_c    : natural := 10; -- Unconditional jump
839 
  constant hpmcnt_event_branch_c  : natural := 11; -- Conditional branch (taken or not taken)
840 
  constant hpmcnt_event_tbranch_c : natural := 12; -- Conditional taken branch
841 
  constant hpmcnt_event_trap_c    : natural := 13; -- Entered trap
842 
  constant hpmcnt_event_illegal_c : natural := 14; -- Illegal instruction exception
843 42 zero_gravi 
  --
844 45 zero_gravi 
  constant hpmcnt_event_size_c    : natural := 15; -- length of this list
845 42 zero_gravi 
 
846 39 zero_gravi 
  -- Clock Generator ------------------------------------------------------------------------
847 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
848 
  constant clk_div2_c    : natural := 0;
849 
  constant clk_div4_c    : natural := 1;
850 
  constant clk_div8_c    : natural := 2;
851 
  constant clk_div64_c   : natural := 3;
852 
  constant clk_div128_c  : natural := 4;
853 
  constant clk_div1024_c : natural := 5;
854 
  constant clk_div2048_c : natural := 6;
855 
  constant clk_div4096_c : natural := 7;
856 
 
857 
  -- Component: NEORV32 Processor Top Entity ------------------------------------------------
858 
  -- -------------------------------------------------------------------------------------------
859 
  component neorv32_top
860 
    generic (
861 
      -- General --
862 12 zero_gravi 
      CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz
863 44 zero_gravi 
      BOOTLOADER_EN                : boolean := true;   -- implement processor-internal bootloader?
864 12 zero_gravi 
      USER_CODE                    : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
865 49 zero_gravi 
      HW_THREAD_ID                 : natural := 0;      -- hardware thread id (32-bit)
866 2 zero_gravi 
      -- RISC-V CPU Extensions --
867 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false;  -- implement atomic extension?
868 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false;  -- implement bit manipulation extensions?
869 18 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?
870 8 zero_gravi 
      CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
871 18 zero_gravi 
      CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement muld/div extension?
872 
      CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?
873 8 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?
874 39 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false;  -- implement instruction stream sync.?
875 19 zero_gravi 
      -- Extension Options --
876 34 zero_gravi 
      FAST_MUL_EN                  : boolean := false;  -- use DSPs for M extension's multiplier
877 
      FAST_SHIFT_EN                : boolean := false;  -- use barrel shifter for shift operations
878 15 zero_gravi 
      -- Physical Memory Protection (PMP) --
879 42 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0;      -- number of regions (0..64)
880 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
881 
      -- Hardware Performance Monitors (HPM) --
882 47 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0;      -- number of implemented HPM counters (0..29)
883 23 zero_gravi 
      -- Internal Instruction memory --
884 44 zero_gravi 
      MEM_INT_IMEM_EN              : boolean := true;   -- implement processor-internal instruction memory
885 8 zero_gravi 
      MEM_INT_IMEM_SIZE            : natural := 16*1024; -- size of processor-internal instruction memory in bytes
886 34 zero_gravi 
      MEM_INT_IMEM_ROM             : boolean := false;  -- implement processor-internal instruction memory as ROM
887 23 zero_gravi 
      -- Internal Data memory --
888 44 zero_gravi 
      MEM_INT_DMEM_EN              : boolean := true;   -- implement processor-internal data memory
889 8 zero_gravi 
      MEM_INT_DMEM_SIZE            : natural := 8*1024; -- size of processor-internal data memory in bytes
890 41 zero_gravi 
      -- Internal Cache memory --
891 44 zero_gravi 
      ICACHE_EN                    : boolean := false;  -- implement instruction cache
892 41 zero_gravi 
      ICACHE_NUM_BLOCKS            : natural := 4;      -- i-cache: number of blocks (min 1), has to be a power of 2
893 
      ICACHE_BLOCK_SIZE            : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
894 45 zero_gravi 
      ICACHE_ASSOCIATIVITY         : natural := 1;      -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
895 23 zero_gravi 
      -- External memory interface --
896 44 zero_gravi 
      MEM_EXT_EN                   : boolean := false;  -- implement external memory bus interface?
897 2 zero_gravi 
      -- Processor peripherals --
898 44 zero_gravi 
      IO_GPIO_EN                   : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
899 
      IO_MTIME_EN                  : boolean := true;   -- implement machine system timer (MTIME)?
900 50 zero_gravi 
      IO_UART0_EN                  : boolean := true;   -- implement primary universal asynchronous receiver/transmitter (UART0)?
901 
      IO_UART1_EN                  : boolean := true;   -- implement secondary universal asynchronous receiver/transmitter (UART1)?
902 44 zero_gravi 
      IO_SPI_EN                    : boolean := true;   -- implement serial peripheral interface (SPI)?
903 
      IO_TWI_EN                    : boolean := true;   -- implement two-wire interface (TWI)?
904 
      IO_PWM_EN                    : boolean := true;   -- implement pulse-width modulation unit (PWM)?
905 
      IO_WDT_EN                    : boolean := true;   -- implement watch dog timer (WDT)?
906 
      IO_TRNG_EN                   : boolean := false;  -- implement true random number generator (TRNG)?
907 47 zero_gravi 
      IO_CFS_EN                    : boolean := false;  -- implement custom functions subsystem (CFS)?
908 52 zero_gravi 
      IO_CFS_CONFIG                : std_ulogic_vector(31 downto 0); -- custom CFS configuration generic
909 
      IO_CFS_IN_SIZE               : positive := 32;    -- size of CFS input conduit in bits
910 
      IO_CFS_OUT_SIZE              : positive := 32;    -- size of CFS output conduit in bits
911 
      IO_NCO_EN                    : boolean := true;   -- implement numerically-controlled oscillator (NCO)?
912 
      IO_NEOLED_EN                 : boolean := true    -- implement NeoPixel-compatible smart LED interface (NEOLED)?
913 2 zero_gravi 
    );
914 
    port (
915 
      -- Global control --
916 34 zero_gravi 
      clk_i       : in  std_ulogic := '0'; -- global clock, rising edge
917 
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
918 49 zero_gravi 
      -- Wishbone bus interface (available if MEM_EXT_EN = true) --
919 53 zero_gravi 
      wb_tag_o    : out std_ulogic_vector(03 downto 0); -- request tag
920 34 zero_gravi 
      wb_adr_o    : out std_ulogic_vector(31 downto 0); -- address
921 
      wb_dat_i    : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
922 
      wb_dat_o    : out std_ulogic_vector(31 downto 0); -- write data
923 
      wb_we_o     : out std_ulogic; -- read/write
924 
      wb_sel_o    : out std_ulogic_vector(03 downto 0); -- byte enable
925 
      wb_stb_o    : out std_ulogic; -- strobe
926 
      wb_cyc_o    : out std_ulogic; -- valid cycle
927 53 zero_gravi 
      wb_tag_i    : in  std_ulogic; -- response tag
928 34 zero_gravi 
      wb_ack_i    : in  std_ulogic := '0'; -- transfer acknowledge
929 
      wb_err_i    : in  std_ulogic := '0'; -- transfer error
930 44 zero_gravi 
      -- Advanced memory control signals (available if MEM_EXT_EN = true) --
931 34 zero_gravi 
      fence_o     : out std_ulogic; -- indicates an executed FENCE operation
932 
      fencei_o    : out std_ulogic; -- indicates an executed FENCEI operation
933 49 zero_gravi 
      -- GPIO (available if IO_GPIO_EN = true) --
934 34 zero_gravi 
      gpio_o      : out std_ulogic_vector(31 downto 0); -- parallel output
935 
      gpio_i      : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
936 50 zero_gravi 
      -- primary UART0 (available if IO_UART0_EN = true) --
937 
      uart0_txd_o : out std_ulogic; -- UART0 send data
938 
      uart0_rxd_i : in  std_ulogic := '0'; -- UART0 receive data
939 51 zero_gravi 
      uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
940 
      uart0_cts_i : in  std_ulogic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
941 50 zero_gravi 
      -- secondary UART1 (available if IO_UART1_EN = true) --
942 
      uart1_txd_o : out std_ulogic; -- UART1 send data
943 
      uart1_rxd_i : in  std_ulogic := '0'; -- UART1 receive data
944 51 zero_gravi 
      uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
945 
      uart1_cts_i : in  std_ulogic := '0'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
946 49 zero_gravi 
      -- SPI (available if IO_SPI_EN = true) --
947 34 zero_gravi 
      spi_sck_o   : out std_ulogic; -- SPI serial clock
948 
      spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
949 
      spi_sdi_i   : in  std_ulogic := '0'; -- controller data in, peripheral data out
950 
      spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
951 49 zero_gravi 
      -- TWI (available if IO_TWI_EN = true) --
952 35 zero_gravi 
      twi_sda_io  : inout std_logic; -- twi serial data line
953 
      twi_scl_io  : inout std_logic; -- twi serial clock line
954 49 zero_gravi 
      -- PWM (available if IO_PWM_EN = true) --
955 40 zero_gravi 
      pwm_o       : out std_ulogic_vector(03 downto 0); -- pwm channels
956 47 zero_gravi 
      -- Custom Functions Subsystem IO --
957 52 zero_gravi 
      cfs_in_i    : in  std_ulogic_vector(IO_CFS_IN_SIZE-1  downto 0); -- custom CFS inputs conduit
958 
      cfs_out_o   : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
959 49 zero_gravi 
      -- NCO output (available if IO_NCO_EN = true) --
960 
      nco_o       : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
961 52 zero_gravi 
      -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
962 
      neoled_o    : out std_ulogic; -- async serial data line
963 44 zero_gravi 
      -- system time input from external MTIME (available if IO_MTIME_EN = false) --
964 40 zero_gravi 
      mtime_i     : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
965 2 zero_gravi 
      -- Interrupts --
966 50 zero_gravi 
      soc_firq_i  : in  std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
967 44 zero_gravi 
      mtime_irq_i : in  std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
968 34 zero_gravi 
      msw_irq_i   : in  std_ulogic := '0'; -- machine software interrupt
969 
      mext_irq_i  : in  std_ulogic := '0'  -- machine external interrupt
970 2 zero_gravi 
    );
971 
  end component;
972 
 
973 4 zero_gravi 
  -- Component: CPU Top Entity --------------------------------------------------------------
974 
  -- -------------------------------------------------------------------------------------------
975 
  component neorv32_cpu
976 
    generic (
977 
      -- General --
978 49 zero_gravi 
      HW_THREAD_ID                 : natural := 0;     -- hardware thread id (32-bit)
979 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu boot address
980 41 zero_gravi 
      BUS_TIMEOUT                  : natural := 63;    -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
981 4 zero_gravi 
      -- RISC-V CPU Extensions --
982 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
983 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
984 12 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
985 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
986 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
987 15 zero_gravi 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
988 53 zero_gravi 
      CPU_EXTENSION_RISCV_Zfinx    : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
989 12 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
990 49 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
991 19 zero_gravi 
      -- Extension Options --
992 
      FAST_MUL_EN                  : boolean := false; -- use DSPs for M extension's multiplier
993 34 zero_gravi 
      FAST_SHIFT_EN                : boolean := false; -- use barrel shifter for shift operations
994 15 zero_gravi 
      -- Physical Memory Protection (PMP) --
995 52 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0;     -- number of regions (0..64)
996 42 zero_gravi 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
997 
      -- Hardware Performance Monitors (HPM) --
998 47 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0      -- number of implemented HPM counters (0..29)
999 4 zero_gravi 
    );
1000 
    port (
1001 
      -- global control --
1002 14 zero_gravi 
      clk_i          : in  std_ulogic := '0'; -- global clock, rising edge
1003 
      rstn_i         : in  std_ulogic := '0'; -- global reset, low-active, async
1004 47 zero_gravi 
      sleep_o        : out std_ulogic; -- cpu is in sleep mode when set
1005 12 zero_gravi 
      -- instruction bus interface --
1006 
      i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1007 14 zero_gravi 
      i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
1008 12 zero_gravi 
      i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1009 
      i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1010 
      i_bus_we_o     : out std_ulogic; -- write enable
1011 
      i_bus_re_o     : out std_ulogic; -- read enable
1012 53 zero_gravi 
      i_bus_cancel_o : out std_ulogic := '0'; -- cancel current bus transaction
1013 14 zero_gravi 
      i_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
1014 
      i_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
1015 12 zero_gravi 
      i_bus_fence_o  : out std_ulogic; -- executed FENCEI operation
1016 35 zero_gravi 
      i_bus_priv_o   : out std_ulogic_vector(1 downto 0); -- privilege level
1017 12 zero_gravi 
      -- data bus interface --
1018 
      d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1019 14 zero_gravi 
      d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
1020 12 zero_gravi 
      d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1021 
      d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1022 
      d_bus_we_o     : out std_ulogic; -- write enable
1023 
      d_bus_re_o     : out std_ulogic; -- read enable
1024 
      d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
1025 14 zero_gravi 
      d_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
1026 
      d_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
1027 12 zero_gravi 
      d_bus_fence_o  : out std_ulogic; -- executed FENCE operation
1028 35 zero_gravi 
      d_bus_priv_o   : out std_ulogic_vector(1 downto 0); -- privilege level
1029 53 zero_gravi 
      d_bus_excl_o   : out std_ulogic; -- exclusive access
1030 
      d_bus_excl_i   : in  std_ulogic; -- state of exclusiv access (set if success)
1031 11 zero_gravi 
      -- system time input from MTIME --
1032 14 zero_gravi 
      time_i         : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
1033 
      -- interrupts (risc-v compliant) --
1034 
      msw_irq_i      : in  std_ulogic := '0'; -- machine software interrupt
1035 
      mext_irq_i     : in  std_ulogic := '0'; -- machine external interrupt
1036 
      mtime_irq_i    : in  std_ulogic := '0'; -- machine timer interrupt
1037 
      -- fast interrupts (custom) --
1038 48 zero_gravi 
      firq_i         : in  std_ulogic_vector(15 downto 0) := (others => '0');
1039 
      firq_ack_o     : out std_ulogic_vector(15 downto 0)
1040 4 zero_gravi 
    );
1041 
  end component;
1042 
 
1043 2 zero_gravi 
  -- Component: CPU Control -----------------------------------------------------------------
1044 
  -- -------------------------------------------------------------------------------------------
1045 
  component neorv32_cpu_control
1046 
    generic (
1047 
      -- General --
1048 49 zero_gravi 
      HW_THREAD_ID                 : natural := 0;     -- hardware thread id (32-bit)
1049 12 zero_gravi 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
1050 2 zero_gravi 
      -- RISC-V CPU Extensions --
1051 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
1052 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
1053 12 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
1054 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
1055 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
1056 15 zero_gravi 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
1057 53 zero_gravi 
      CPU_EXTENSION_RISCV_Zfinx    : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
1058 12 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
1059 49 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
1060 15 zero_gravi 
      -- Physical memory protection (PMP) --
1061 52 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0;     -- number of regions (0..64)
1062 42 zero_gravi 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
1063 
      -- Hardware Performance Monitors (HPM) --
1064 47 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0      -- number of implemented HPM counters (0..29)
1065 2 zero_gravi 
    );
1066 
    port (
1067 
      -- global control --
1068 
      clk_i         : in  std_ulogic; -- global clock, rising edge
1069 
      rstn_i        : in  std_ulogic; -- global reset, low-active, async
1070 
      ctrl_o        : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1071 
      -- status input --
1072 
      alu_wait_i    : in  std_ulogic; -- wait for ALU
1073 12 zero_gravi 
      bus_i_wait_i  : in  std_ulogic; -- wait for bus
1074 
      bus_d_wait_i  : in  std_ulogic; -- wait for bus
1075 2 zero_gravi 
      -- data input --
1076 
      instr_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- instruction
1077 
      cmp_i         : in  std_ulogic_vector(1 downto 0); -- comparator status
1078 36 zero_gravi 
      alu_add_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result
1079 52 zero_gravi 
      rs1_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1080 2 zero_gravi 
      -- data output --
1081 
      imm_o         : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
1082 6 zero_gravi 
      fetch_pc_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
1083 
      curr_pc_o     : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
1084 2 zero_gravi 
      csr_rdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
1085 52 zero_gravi 
      -- FPU interface --
1086 
      fpu_rm_o      : out std_ulogic_vector(02 downto 0); -- rounding mode
1087 
      fpu_flags_i   : in  std_ulogic_vector(04 downto 0); -- exception flags
1088 14 zero_gravi 
      -- interrupts (risc-v compliant) --
1089 
      msw_irq_i     : in  std_ulogic; -- machine software interrupt
1090 
      mext_irq_i    : in  std_ulogic; -- machine external interrupt
1091 2 zero_gravi 
      mtime_irq_i   : in  std_ulogic; -- machine timer interrupt
1092 14 zero_gravi 
      -- fast interrupts (custom) --
1093 48 zero_gravi 
      firq_i        : in  std_ulogic_vector(15 downto 0);
1094 
      firq_ack_o    : out std_ulogic_vector(15 downto 0);
1095 11 zero_gravi 
      -- system time input from MTIME --
1096 
      time_i        : in  std_ulogic_vector(63 downto 0); -- current system time
1097 15 zero_gravi 
      -- physical memory protection --
1098 
      pmp_addr_o    : out pmp_addr_if_t; -- addresses
1099 
      pmp_ctrl_o    : out pmp_ctrl_if_t; -- configs
1100 2 zero_gravi 
      -- bus access exceptions --
1101 
      mar_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
1102 
      ma_instr_i    : in  std_ulogic; -- misaligned instruction address
1103 
      ma_load_i     : in  std_ulogic; -- misaligned load data address
1104 
      ma_store_i    : in  std_ulogic; -- misaligned store data address
1105 
      be_instr_i    : in  std_ulogic; -- bus error on instruction access
1106 
      be_load_i     : in  std_ulogic; -- bus error on load data access
1107 12 zero_gravi 
      be_store_i    : in  std_ulogic  -- bus error on store data access
1108 2 zero_gravi 
    );
1109 
  end component;
1110 
 
1111 
  -- Component: CPU Register File -----------------------------------------------------------
1112 
  -- -------------------------------------------------------------------------------------------
1113 
  component neorv32_cpu_regfile
1114 
    generic (
1115 
      CPU_EXTENSION_RISCV_E : boolean := false -- implement embedded RF extension?
1116 
    );
1117 
    port (
1118 
      -- global control --
1119 
      clk_i  : in  std_ulogic; -- global clock, rising edge
1120 
      ctrl_i : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1121 
      -- data input --
1122 
      mem_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
1123 
      alu_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
1124 
      -- data output --
1125 
      rs1_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
1126 47 zero_gravi 
      rs2_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 2
1127 
      cmp_o  : out std_ulogic_vector(1 downto 0) -- comparator status
1128 2 zero_gravi 
    );
1129 
  end component;
1130 
 
1131 
  -- Component: CPU ALU ---------------------------------------------------------------------
1132 
  -- -------------------------------------------------------------------------------------------
1133 
  component neorv32_cpu_alu
1134 11 zero_gravi 
    generic (
1135 34 zero_gravi 
      CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
1136 
      FAST_SHIFT_EN         : boolean := false -- use barrel shifter for shift operations
1137 11 zero_gravi 
    );
1138 2 zero_gravi 
    port (
1139 
      -- global control --
1140 
      clk_i       : in  std_ulogic; -- global clock, rising edge
1141 
      rstn_i      : in  std_ulogic; -- global reset, low-active, async
1142 
      ctrl_i      : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1143 
      -- data input --
1144 
      rs1_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1145 
      rs2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1146 
      pc2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
1147 
      imm_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- immediate
1148 
      -- data output --
1149 
      res_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
1150 36 zero_gravi 
      add_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
1151 2 zero_gravi 
      -- co-processor interface --
1152 49 zero_gravi 
      cp_start_o  : out std_ulogic_vector(7 downto 0); -- trigger co-processor i
1153 
      cp_valid_i  : in  std_ulogic_vector(7 downto 0); -- co-processor i done
1154 
      cp_result_i : in  cp_data_if_t; -- co-processor result
1155 2 zero_gravi 
      -- status --
1156 
      wait_o      : out std_ulogic -- busy due to iterative processing units
1157 
    );
1158 
  end component;
1159 
 
1160 44 zero_gravi 
  -- Component: CPU Co-Processor MULDIV ('M' extension) -------------------------------------
1161 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1162 
  component neorv32_cpu_cp_muldiv
1163 19 zero_gravi 
    generic (
1164 
      FAST_MUL_EN : boolean := false -- use DSPs for faster multiplication
1165 
    );
1166 2 zero_gravi 
    port (
1167 
      -- global control --
1168 
      clk_i   : in  std_ulogic; -- global clock, rising edge
1169 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
1170 
      ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1171 36 zero_gravi 
      start_i : in  std_ulogic; -- trigger operation
1172 2 zero_gravi 
      -- data input --
1173 
      rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1174 
      rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1175 
      -- result and status --
1176 
      res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1177 
      valid_o : out std_ulogic -- data output valid
1178 
    );
1179 
  end component;
1180 
 
1181 44 zero_gravi 
  -- Component: CPU Co-Processor Bit Manipulation ('B' extension) ---------------------------
1182 
  -- -------------------------------------------------------------------------------------------
1183 
  component neorv32_cpu_cp_bitmanip
1184 
    port (
1185 
      -- global control --
1186 
      clk_i   : in  std_ulogic; -- global clock, rising edge
1187 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
1188 
      ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1189 
      start_i : in  std_ulogic; -- trigger operation
1190 
      -- data input --
1191 
      cmp_i   : in  std_ulogic_vector(1 downto 0); -- comparator status
1192 
      rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1193 
      rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1194 
      -- result and status --
1195 
      res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1196 
      valid_o : out std_ulogic -- data output valid
1197 
    );
1198 
  end component;
1199 
 
1200 53 zero_gravi 
  -- Component: CPU Co-Processor 32-bit FPU ('Zfinx' extension) -----------------------------
1201 52 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1202 
  component neorv32_cpu_cp_fpu
1203 
    port (
1204 
      -- global control --
1205 53 zero_gravi 
      clk_i    : in  std_ulogic; -- global clock, rising edge
1206 
      rstn_i   : in  std_ulogic; -- global reset, low-active, async
1207 
      ctrl_i   : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1208 
      start_i  : in  std_ulogic; -- trigger operation
1209 52 zero_gravi 
      -- data input --
1210 53 zero_gravi 
      frm_i    : in  std_ulogic_vector(2 downto 0); -- rounding mode
1211 
      rs1_i    : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1212 
      rs2_i    : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1213 52 zero_gravi 
      -- result and status --
1214 53 zero_gravi 
      res_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1215 
      fflags_o : out std_ulogic_vector(4 downto 0); -- exception flags
1216 
      valid_o  : out std_ulogic -- data output valid
1217 52 zero_gravi 
    );
1218 
  end component;
1219 
 
1220 2 zero_gravi 
  -- Component: CPU Bus Interface -----------------------------------------------------------
1221 
  -- -------------------------------------------------------------------------------------------
1222 
  component neorv32_cpu_bus
1223 
    generic (
1224 53 zero_gravi 
      CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
1225 40 zero_gravi 
      CPU_EXTENSION_RISCV_C : boolean := true;  -- implement compressed extension?
1226 15 zero_gravi 
      -- Physical memory protection (PMP) --
1227 42 zero_gravi 
      PMP_NUM_REGIONS       : natural := 0;       -- number of regions (0..64)
1228 
      PMP_MIN_GRANULARITY   : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
1229 41 zero_gravi 
      -- Bus Timeout --
1230 
      BUS_TIMEOUT           : natural := 63     -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
1231 2 zero_gravi 
    );
1232 
    port (
1233 
      -- global control --
1234 12 zero_gravi 
      clk_i          : in  std_ulogic; -- global clock, rising edge
1235 38 zero_gravi 
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
1236 12 zero_gravi 
      ctrl_i         : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1237 
      -- cpu instruction fetch interface --
1238 
      fetch_pc_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
1239 
      instr_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
1240 
      i_wait_o       : out std_ulogic; -- wait for fetch to complete
1241 
      --
1242 
      ma_instr_o     : out std_ulogic; -- misaligned instruction address
1243 
      be_instr_o     : out std_ulogic; -- bus error on instruction access
1244 
      -- cpu data access interface --
1245 
      addr_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
1246 
      wdata_i        : in  std_ulogic_vector(data_width_c-1 downto 0); -- write data
1247 
      rdata_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
1248 
      mar_o          : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
1249 
      d_wait_o       : out std_ulogic; -- wait for access to complete
1250 
      --
1251 53 zero_gravi 
      bus_excl_ok_o  : out std_ulogic; -- bus exclusive access successful
1252 12 zero_gravi 
      ma_load_o      : out std_ulogic; -- misaligned load data address
1253 
      ma_store_o     : out std_ulogic; -- misaligned store data address
1254 
      be_load_o      : out std_ulogic; -- bus error on load data access
1255 
      be_store_o     : out std_ulogic; -- bus error on store data access
1256 15 zero_gravi 
      -- physical memory protection --
1257 
      pmp_addr_i     : in  pmp_addr_if_t; -- addresses
1258 
      pmp_ctrl_i     : in  pmp_ctrl_if_t; -- configs
1259 12 zero_gravi 
      -- instruction bus --
1260 
      i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1261 
      i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1262 
      i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1263 
      i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1264 
      i_bus_we_o     : out std_ulogic; -- write enable
1265 
      i_bus_re_o     : out std_ulogic; -- read enable
1266 
      i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
1267 
      i_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
1268 
      i_bus_err_i    : in  std_ulogic; -- bus transfer error
1269 
      i_bus_fence_o  : out std_ulogic; -- fence operation
1270 
      -- data bus --
1271 
      d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1272 
      d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1273 
      d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1274 
      d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1275 
      d_bus_we_o     : out std_ulogic; -- write enable
1276 
      d_bus_re_o     : out std_ulogic; -- read enable
1277 
      d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
1278 
      d_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
1279 
      d_bus_err_i    : in  std_ulogic; -- bus transfer error
1280 39 zero_gravi 
      d_bus_fence_o  : out std_ulogic; -- fence operation
1281 53 zero_gravi 
      d_bus_excl_o   : out std_ulogic; -- exclusive access request
1282 
      d_bus_excl_i   : in  std_ulogic  -- state of exclusiv access (set if success)
1283 2 zero_gravi 
    );
1284 
  end component;
1285 
 
1286 45 zero_gravi 
  -- Component: CPU Instruction Cache -------------------------------------------------------
1287 41 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1288 45 zero_gravi 
  component neorv32_icache
1289 41 zero_gravi 
    generic (
1290 47 zero_gravi 
      ICACHE_NUM_BLOCKS : natural := 4;  -- number of blocks (min 1), has to be a power of 2
1291 
      ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2
1292 
      ICACHE_NUM_SETS   : natural := 1   -- associativity / number of sets (1=direct_mapped), has to be a power of 2
1293 41 zero_gravi 
    );
1294 
    port (
1295 
      -- global control --
1296 
      clk_i         : in  std_ulogic; -- global clock, rising edge
1297 
      rstn_i        : in  std_ulogic; -- global reset, low-active, async
1298 
      clear_i       : in  std_ulogic; -- cache clear
1299 
      -- host controller interface --
1300 
      host_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1301 
      host_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1302 
      host_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1303 
      host_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1304 
      host_we_i     : in  std_ulogic; -- write enable
1305 
      host_re_i     : in  std_ulogic; -- read enable
1306 
      host_cancel_i : in  std_ulogic; -- cancel current bus transaction
1307 
      host_ack_o    : out std_ulogic; -- bus transfer acknowledge
1308 
      host_err_o    : out std_ulogic; -- bus transfer error
1309 
      -- peripheral bus interface --
1310 
      bus_addr_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1311 
      bus_rdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1312 
      bus_wdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1313 
      bus_ben_o     : out std_ulogic_vector(03 downto 0); -- byte enable
1314 
      bus_we_o      : out std_ulogic; -- write enable
1315 
      bus_re_o      : out std_ulogic; -- read enable
1316 
      bus_cancel_o  : out std_ulogic; -- cancel current bus transaction
1317 
      bus_ack_i     : in  std_ulogic; -- bus transfer acknowledge
1318 
      bus_err_i     : in  std_ulogic  -- bus transfer error
1319 
    );
1320 
  end component;
1321 
 
1322 12 zero_gravi 
  -- Component: CPU Bus Switch --------------------------------------------------------------
1323 
  -- -------------------------------------------------------------------------------------------
1324 
  component neorv32_busswitch
1325 
    generic (
1326 
      PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only
1327 
      PORT_CB_READ_ONLY : boolean := false  -- set if controller port B is read-only
1328 
    );
1329 
    port (
1330 
      -- global control --
1331 
      clk_i           : in  std_ulogic; -- global clock, rising edge
1332 
      rstn_i          : in  std_ulogic; -- global reset, low-active, async
1333 
      -- controller interface a --
1334 
      ca_bus_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1335 
      ca_bus_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1336 
      ca_bus_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1337 
      ca_bus_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1338 
      ca_bus_we_i     : in  std_ulogic; -- write enable
1339 
      ca_bus_re_i     : in  std_ulogic; -- read enable
1340 
      ca_bus_cancel_i : in  std_ulogic; -- cancel current bus transaction
1341 53 zero_gravi 
      ca_bus_excl_i   : in  std_ulogic; -- exclusive access
1342 12 zero_gravi 
      ca_bus_ack_o    : out std_ulogic; -- bus transfer acknowledge
1343 
      ca_bus_err_o    : out std_ulogic; -- bus transfer error
1344 
      -- controller interface b --
1345 
      cb_bus_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1346 
      cb_bus_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1347 
      cb_bus_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1348 
      cb_bus_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1349 
      cb_bus_we_i     : in  std_ulogic; -- write enable
1350 
      cb_bus_re_i     : in  std_ulogic; -- read enable
1351 
      cb_bus_cancel_i : in  std_ulogic; -- cancel current bus transaction
1352 53 zero_gravi 
      cb_bus_excl_i   : in  std_ulogic; -- exclusive access
1353 12 zero_gravi 
      cb_bus_ack_o    : out std_ulogic; -- bus transfer acknowledge
1354 
      cb_bus_err_o    : out std_ulogic; -- bus transfer error
1355 
      -- peripheral bus --
1356 36 zero_gravi 
      p_bus_src_o     : out std_ulogic; -- access source: 0 = A, 1 = B
1357 12 zero_gravi 
      p_bus_addr_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1358 
      p_bus_rdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1359 
      p_bus_wdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1360 
      p_bus_ben_o     : out std_ulogic_vector(03 downto 0); -- byte enable
1361 
      p_bus_we_o      : out std_ulogic; -- write enable
1362 
      p_bus_re_o      : out std_ulogic; -- read enable
1363 
      p_bus_cancel_o  : out std_ulogic; -- cancel current bus transaction
1364 53 zero_gravi 
      p_bus_excl_o    : out std_ulogic; -- exclusive access
1365 12 zero_gravi 
      p_bus_ack_i     : in  std_ulogic; -- bus transfer acknowledge
1366 
      p_bus_err_i     : in  std_ulogic  -- bus transfer error
1367 
    );
1368 
  end component;
1369 
 
1370 2 zero_gravi 
  -- Component: CPU Compressed Instructions Decompressor ------------------------------------
1371 
  -- -------------------------------------------------------------------------------------------
1372 
  component neorv32_cpu_decompressor
1373 
    port (
1374 
      -- instruction input --
1375 
      ci_instr16_i : in  std_ulogic_vector(15 downto 0); -- compressed instruction input
1376 
      -- instruction output --
1377 
      ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
1378 
      ci_instr32_o : out std_ulogic_vector(31 downto 0)  -- 32-bit decompressed instruction
1379 
    );
1380 
  end component;
1381 
 
1382 
  -- Component: Processor-internal instruction memory (IMEM) --------------------------------
1383 
  -- -------------------------------------------------------------------------------------------
1384 
  component neorv32_imem
1385 
    generic (
1386 
      IMEM_BASE      : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
1387 
      IMEM_SIZE      : natural := 4*1024; -- processor-internal instruction memory size in bytes
1388 
      IMEM_AS_ROM    : boolean := false;  -- implement IMEM as read-only memory?
1389 44 zero_gravi 
      BOOTLOADER_EN  : boolean := true    -- implement and use bootloader?
1390 2 zero_gravi 
    );
1391 
    port (
1392 
      clk_i  : in  std_ulogic; -- global clock line
1393 
      rden_i : in  std_ulogic; -- read enable
1394 
      wren_i : in  std_ulogic; -- write enable
1395 
      ben_i  : in  std_ulogic_vector(03 downto 0); -- byte write enable
1396 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1397 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1398 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1399 
      ack_o  : out std_ulogic -- transfer acknowledge
1400 
    );
1401 
  end component;
1402 
 
1403 
  -- Component: Processor-internal data memory (DMEM) ---------------------------------------
1404 
  -- -------------------------------------------------------------------------------------------
1405 
  component neorv32_dmem
1406 
    generic (
1407 
      DMEM_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- memory base address
1408 
      DMEM_SIZE : natural := 4*1024  -- processor-internal instruction memory size in bytes
1409 
    );
1410 
    port (
1411 
      clk_i  : in  std_ulogic; -- global clock line
1412 
      rden_i : in  std_ulogic; -- read enable
1413 
      wren_i : in  std_ulogic; -- write enable
1414 
      ben_i  : in  std_ulogic_vector(03 downto 0); -- byte write enable
1415 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1416 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1417 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1418 
      ack_o  : out std_ulogic -- transfer acknowledge
1419 
    );
1420 
  end component;
1421 
 
1422 
  -- Component: Processor-internal bootloader ROM (BOOTROM) ---------------------------------
1423 
  -- -------------------------------------------------------------------------------------------
1424 
  component neorv32_boot_rom
1425 23 zero_gravi 
    generic (
1426 
      BOOTROM_BASE : std_ulogic_vector(31 downto 0) := x"FFFF0000"; -- boot ROM base address
1427 
      BOOTROM_SIZE : natural := 4*1024  -- processor-internal boot ROM memory size in bytes
1428 
    );
1429 2 zero_gravi 
    port (
1430 
      clk_i  : in  std_ulogic; -- global clock line
1431 
      rden_i : in  std_ulogic; -- read enable
1432 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1433 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1434 
      ack_o  : out std_ulogic -- transfer acknowledge
1435 
    );
1436 
  end component;
1437 
 
1438 
  -- Component: Machine System Timer (mtime) ------------------------------------------------
1439 
  -- -------------------------------------------------------------------------------------------
1440 
  component neorv32_mtime
1441 
    port (
1442 
      -- host access --
1443 
      clk_i     : in  std_ulogic; -- global clock line
1444 4 zero_gravi 
      rstn_i    : in  std_ulogic := '0'; -- global reset, low-active, async
1445 2 zero_gravi 
      addr_i    : in  std_ulogic_vector(31 downto 0); -- address
1446 
      rden_i    : in  std_ulogic; -- read enable
1447 
      wren_i    : in  std_ulogic; -- write enable
1448 
      data_i    : in  std_ulogic_vector(31 downto 0); -- data in
1449 
      data_o    : out std_ulogic_vector(31 downto 0); -- data out
1450 
      ack_o     : out std_ulogic; -- transfer acknowledge
1451 11 zero_gravi 
      -- time output for CPU --
1452 
      time_o    : out std_ulogic_vector(63 downto 0); -- current system time
1453 2 zero_gravi 
      -- interrupt --
1454 
      irq_o     : out std_ulogic  -- interrupt request
1455 
    );
1456 
  end component;
1457 
 
1458 
  -- Component: General Purpose Input/Output Port (GPIO) ------------------------------------
1459 
  -- -------------------------------------------------------------------------------------------
1460 
  component neorv32_gpio
1461 
    port (
1462 
      -- host access --
1463 
      clk_i  : in  std_ulogic; -- global clock line
1464 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1465 
      rden_i : in  std_ulogic; -- read enable
1466 
      wren_i : in  std_ulogic; -- write enable
1467 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1468 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1469 
      ack_o  : out std_ulogic; -- transfer acknowledge
1470 
      -- parallel io --
1471 22 zero_gravi 
      gpio_o : out std_ulogic_vector(31 downto 0);
1472 
      gpio_i : in  std_ulogic_vector(31 downto 0);
1473 2 zero_gravi 
      -- interrupt --
1474 
      irq_o  : out std_ulogic
1475 
    );
1476 
  end component;
1477 
 
1478 
  -- Component: Watchdog Timer (WDT) --------------------------------------------------------
1479 
  -- -------------------------------------------------------------------------------------------
1480 
  component neorv32_wdt
1481 
    port (
1482 
      -- host access --
1483 
      clk_i       : in  std_ulogic; -- global clock line
1484 
      rstn_i      : in  std_ulogic; -- global reset line, low-active
1485 
      rden_i      : in  std_ulogic; -- read enable
1486 
      wren_i      : in  std_ulogic; -- write enable
1487 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1488 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1489 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1490 
      ack_o       : out std_ulogic; -- transfer acknowledge
1491 
      -- clock generator --
1492 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1493 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1494 
      -- timeout event --
1495 
      irq_o       : out std_ulogic; -- timeout IRQ
1496 
      rstn_o      : out std_ulogic  -- timeout reset, low_active, use it as async!
1497 
    );
1498 
  end component;
1499 
 
1500 
  -- Component: Universal Asynchronous Receiver and Transmitter (UART) ----------------------
1501 
  -- -------------------------------------------------------------------------------------------
1502 
  component neorv32_uart
1503 50 zero_gravi 
    generic (
1504 
      UART_PRIMARY : boolean := true -- true = primary UART (UART0), false = secondary UART (UART1)
1505 
    );
1506 2 zero_gravi 
    port (
1507 
      -- host access --
1508 
      clk_i       : in  std_ulogic; -- global clock line
1509 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1510 
      rden_i      : in  std_ulogic; -- read enable
1511 
      wren_i      : in  std_ulogic; -- write enable
1512 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1513 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1514 
      ack_o       : out std_ulogic; -- transfer acknowledge
1515 
      -- clock generator --
1516 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1517 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1518 
      -- com lines --
1519 
      uart_txd_o  : out std_ulogic;
1520 
      uart_rxd_i  : in  std_ulogic;
1521 51 zero_gravi 
      -- hardware flow control --
1522 
      uart_rts_o  : out std_ulogic; -- UART.RX ready to receive ("RTR"), low-active, optional
1523 
      uart_cts_i  : in  std_ulogic; -- UART.TX allowed to transmit, low-active, optional
1524 2 zero_gravi 
      -- interrupts --
1525 48 zero_gravi 
      irq_rxd_o   : out std_ulogic; -- uart data received interrupt
1526 
      irq_txd_o   : out std_ulogic  -- uart transmission done interrupt
1527 2 zero_gravi 
    );
1528 
  end component;
1529 
 
1530 
  -- Component: Serial Peripheral Interface (SPI) -------------------------------------------
1531 
  -- -------------------------------------------------------------------------------------------
1532 
  component neorv32_spi
1533 
    port (
1534 
      -- host access --
1535 
      clk_i       : in  std_ulogic; -- global clock line
1536 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1537 
      rden_i      : in  std_ulogic; -- read enable
1538 
      wren_i      : in  std_ulogic; -- write enable
1539 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1540 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1541 
      ack_o       : out std_ulogic; -- transfer acknowledge
1542 
      -- clock generator --
1543 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1544 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1545 
      -- com lines --
1546 6 zero_gravi 
      spi_sck_o   : out std_ulogic; -- SPI serial clock
1547 
      spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
1548 
      spi_sdi_i   : in  std_ulogic; -- controller data in, peripheral data out
1549 2 zero_gravi 
      spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
1550 
      -- interrupt --
1551 48 zero_gravi 
      irq_o       : out std_ulogic -- transmission done interrupt
1552 2 zero_gravi 
    );
1553 
  end component;
1554 
 
1555 
  -- Component: Two-Wire Interface (TWI) ----------------------------------------------------
1556 
  -- -------------------------------------------------------------------------------------------
1557 
  component neorv32_twi
1558 
    port (
1559 
      -- host access --
1560 
      clk_i       : in  std_ulogic; -- global clock line
1561 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1562 
      rden_i      : in  std_ulogic; -- read enable
1563 
      wren_i      : in  std_ulogic; -- write enable
1564 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1565 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1566 
      ack_o       : out std_ulogic; -- transfer acknowledge
1567 
      -- clock generator --
1568 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1569 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1570 
      -- com lines --
1571 
      twi_sda_io  : inout std_logic; -- serial data line
1572 
      twi_scl_io  : inout std_logic; -- serial clock line
1573 
      -- interrupt --
1574 48 zero_gravi 
      irq_o       : out std_ulogic -- transfer done IRQ
1575 2 zero_gravi 
    );
1576 
  end component;
1577 
 
1578 
  -- Component: Pulse-Width Modulation Controller (PWM) -------------------------------------
1579 
  -- -------------------------------------------------------------------------------------------
1580 
  component neorv32_pwm
1581 
    port (
1582 
      -- host access --
1583 
      clk_i       : in  std_ulogic; -- global clock line
1584 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1585 
      rden_i      : in  std_ulogic; -- read enable
1586 
      wren_i      : in  std_ulogic; -- write enable
1587 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1588 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1589 
      ack_o       : out std_ulogic; -- transfer acknowledge
1590 
      -- clock generator --
1591 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1592 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1593 
      -- pwm output channels --
1594 
      pwm_o       : out std_ulogic_vector(03 downto 0)
1595 
    );
1596 
  end component;
1597 
 
1598 
  -- Component: True Random Number Generator (TRNG) -----------------------------------------
1599 
  -- -------------------------------------------------------------------------------------------
1600 
  component neorv32_trng
1601 
    port (
1602 
      -- host access --
1603 
      clk_i  : in  std_ulogic; -- global clock line
1604 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1605 
      rden_i : in  std_ulogic; -- read enable
1606 
      wren_i : in  std_ulogic; -- write enable
1607 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1608 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1609 
      ack_o  : out std_ulogic  -- transfer acknowledge
1610 
    );
1611 
  end component;
1612 
 
1613 
  -- Component: Wishbone Bus Gateway (WISHBONE) ---------------------------------------------
1614 
  -- -------------------------------------------------------------------------------------------
1615 
  component neorv32_wishbone
1616 
    generic (
1617 35 zero_gravi 
      WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
1618 23 zero_gravi 
      -- Internal instruction memory --
1619 44 zero_gravi 
      MEM_INT_IMEM_EN   : boolean := true;   -- implement processor-internal instruction memory
1620 35 zero_gravi 
      MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
1621 23 zero_gravi 
      -- Internal data memory --
1622 44 zero_gravi 
      MEM_INT_DMEM_EN   : boolean := true;   -- implement processor-internal data memory
1623 35 zero_gravi 
      MEM_INT_DMEM_SIZE : natural := 4*1024  -- size of processor-internal data memory in bytes
1624 2 zero_gravi 
    );
1625 
    port (
1626 
      -- global control --
1627 53 zero_gravi 
      clk_i    : in  std_ulogic; -- global clock line
1628 
      rstn_i   : in  std_ulogic; -- global reset line, low-active
1629 2 zero_gravi 
      -- host access --
1630 53 zero_gravi 
      src_i    : in  std_ulogic; -- access type (0: data, 1:instruction)
1631 
      addr_i   : in  std_ulogic_vector(31 downto 0); -- address
1632 
      rden_i   : in  std_ulogic; -- read enable
1633 
      wren_i   : in  std_ulogic; -- write enable
1634 
      ben_i    : in  std_ulogic_vector(03 downto 0); -- byte write enable
1635 
      data_i   : in  std_ulogic_vector(31 downto 0); -- data in
1636 
      data_o   : out std_ulogic_vector(31 downto 0); -- data out
1637 
      cancel_i : in  std_ulogic; -- cancel current bus transaction
1638 
      excl_i   : in  std_ulogic; -- exclusive access request
1639 
      excl_o   : out std_ulogic; -- state of exclusiv access (set if success)
1640 
      ack_o    : out std_ulogic; -- transfer acknowledge
1641 
      err_o    : out std_ulogic; -- transfer error
1642 
      priv_i   : in  std_ulogic_vector(01 downto 0); -- current CPU privilege level
1643 2 zero_gravi 
      -- wishbone interface --
1644 53 zero_gravi 
      wb_tag_o : out std_ulogic_vector(03 downto 0); -- request tag
1645 
      wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
1646 
      wb_dat_i : in  std_ulogic_vector(31 downto 0); -- read data
1647 
      wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
1648 
      wb_we_o  : out std_ulogic; -- read/write
1649 
      wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
1650 
      wb_stb_o : out std_ulogic; -- strobe
1651 
      wb_cyc_o : out std_ulogic; -- valid cycle
1652 
      wb_tag_i : in  std_ulogic; -- response tag
1653 
      wb_ack_i : in  std_ulogic; -- transfer acknowledge
1654 
      wb_err_i : in  std_ulogic  -- transfer error
1655 2 zero_gravi 
    );
1656 
  end component;
1657 
 
1658 47 zero_gravi 
  -- Component: Custom Functions Subsystem (CFS) --------------------------------------------
1659 23 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1660 47 zero_gravi 
  component neorv32_cfs
1661 
    generic (
1662 52 zero_gravi 
      CFS_CONFIG   : std_ulogic_vector(31 downto 0); -- custom CFS configuration generic
1663 
      CFS_IN_SIZE  : positive := 32;  -- size of CFS input conduit in bits
1664 
      CFS_OUT_SIZE : positive := 32   -- size of CFS output conduit in bits
1665 23 zero_gravi 
    );
1666 34 zero_gravi 
    port (
1667 
      -- host access --
1668 
      clk_i       : in  std_ulogic; -- global clock line
1669 
      rstn_i      : in  std_ulogic; -- global reset line, low-active, use as async
1670 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1671 
      rden_i      : in  std_ulogic; -- read enable
1672 47 zero_gravi 
      wren_i      : in  std_ulogic; -- word write enable
1673 34 zero_gravi 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1674 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1675 
      ack_o       : out std_ulogic; -- transfer acknowledge
1676 
      -- clock generator --
1677 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1678 47 zero_gravi 
      clkgen_i    : in  std_ulogic_vector(07 downto 0); -- "clock" inputs
1679 
      -- CPU state --
1680 
      sleep_i     : in  std_ulogic; -- set if cpu is in sleep mode
1681 
      -- interrupt --
1682 
      irq_o       : out std_ulogic; -- interrupt request
1683 
      irq_ack_i   : in  std_ulogic; -- interrupt acknowledge
1684 
      -- custom io (conduit) --
1685 52 zero_gravi 
      cfs_in_i    : in  std_ulogic_vector(CFS_IN_SIZE-1 downto 0);  -- custom inputs
1686 
      cfs_out_o   : out std_ulogic_vector(CFS_OUT_SIZE-1 downto 0)  -- custom outputs
1687 34 zero_gravi 
    );
1688 
  end component;
1689 
 
1690 49 zero_gravi 
  -- Component: Numerically-Controlled Oscillator (NCO) -------------------------------------
1691 
  -- -------------------------------------------------------------------------------------------
1692 
  component neorv32_nco
1693 
    port (
1694 
      -- host access --
1695 
      clk_i       : in  std_ulogic; -- global clock line
1696 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1697 
      rden_i      : in  std_ulogic; -- read enable
1698 
      wren_i      : in  std_ulogic; -- write enable
1699 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1700 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1701 
      ack_o       : out std_ulogic; -- transfer acknowledge
1702 
      -- clock generator --
1703 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1704 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1705 
      -- NCO output --
1706 
      nco_o       : out std_ulogic_vector(02 downto 0)
1707 
    );
1708 
  end component;
1709 
 
1710 52 zero_gravi 
  -- Component: Smart LED (WS2811/WS2812) Interface (NEOLED) --------------------------------
1711 
  -- -------------------------------------------------------------------------------------------
1712 
  component neorv32_neoled
1713 
    port (
1714 
      -- host access --
1715 
      clk_i       : in  std_ulogic; -- global clock line
1716 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1717 
      rden_i      : in  std_ulogic; -- read enable
1718 
      wren_i      : in  std_ulogic; -- write enable
1719 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1720 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1721 
      ack_o       : out std_ulogic; -- transfer acknowledge
1722 
      -- clock generator --
1723 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1724 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1725 
      -- interrupt --
1726 
      irq_o       : out std_ulogic; -- interrupt request
1727 
      -- NEOLED output --
1728 
      neoled_o    : out std_ulogic -- serial async data line
1729 
    );
1730 
  end component;
1731 
 
1732 23 zero_gravi 
  -- Component: System Configuration Information Memory (SYSINFO) ---------------------------
1733 
  -- -------------------------------------------------------------------------------------------
1734 12 zero_gravi 
  component neorv32_sysinfo
1735 
    generic (
1736 
      -- General --
1737 41 zero_gravi 
      CLOCK_FREQUENCY      : natural := 0;      -- clock frequency of clk_i in Hz
1738 44 zero_gravi 
      BOOTLOADER_EN        : boolean := true;   -- implement processor-internal bootloader?
1739 41 zero_gravi 
      USER_CODE            : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
1740 23 zero_gravi 
      -- Internal Instruction memory --
1741 44 zero_gravi 
      MEM_INT_IMEM_EN      : boolean := true;   -- implement processor-internal instruction memory
1742 41 zero_gravi 
      MEM_INT_IMEM_SIZE    : natural := 8*1024; -- size of processor-internal instruction memory in bytes
1743 
      MEM_INT_IMEM_ROM     : boolean := false;  -- implement processor-internal instruction memory as ROM
1744 23 zero_gravi 
      -- Internal Data memory --
1745 44 zero_gravi 
      MEM_INT_DMEM_EN      : boolean := true;   -- implement processor-internal data memory
1746 41 zero_gravi 
      MEM_INT_DMEM_SIZE    : natural := 4*1024; -- size of processor-internal data memory in bytes
1747 
      -- Internal Cache memory --
1748 44 zero_gravi 
      ICACHE_EN            : boolean := true;   -- implement instruction cache
1749 41 zero_gravi 
      ICACHE_NUM_BLOCKS    : natural := 4;      -- i-cache: number of blocks (min 2), has to be a power of 2
1750 
      ICACHE_BLOCK_SIZE    : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
1751 
      ICACHE_ASSOCIATIVITY : natural := 1;      -- i-cache: associativity (min 1), has to be a power 2
1752 23 zero_gravi 
      -- External memory interface --
1753 44 zero_gravi 
      MEM_EXT_EN           : boolean := false;  -- implement external memory bus interface?
1754 12 zero_gravi 
      -- Processor peripherals --
1755 44 zero_gravi 
      IO_GPIO_EN           : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
1756 
      IO_MTIME_EN          : boolean := true;   -- implement machine system timer (MTIME)?
1757 50 zero_gravi 
      IO_UART0_EN          : boolean := true;   -- implement primary universal asynchronous receiver/transmitter (UART0)?
1758 
      IO_UART1_EN          : boolean := true;   -- implement secondary universal asynchronous receiver/transmitter (UART1)?
1759 44 zero_gravi 
      IO_SPI_EN            : boolean := true;   -- implement serial peripheral interface (SPI)?
1760 
      IO_TWI_EN            : boolean := true;   -- implement two-wire interface (TWI)?
1761 
      IO_PWM_EN            : boolean := true;   -- implement pulse-width modulation unit (PWM)?
1762 
      IO_WDT_EN            : boolean := true;   -- implement watch dog timer (WDT)?
1763 
      IO_TRNG_EN           : boolean := true;   -- implement true random number generator (TRNG)?
1764 49 zero_gravi 
      IO_CFS_EN            : boolean := true;   -- implement custom functions subsystem (CFS)?
1765 52 zero_gravi 
      IO_NCO_EN            : boolean := true;   -- implement numerically-controlled oscillator (NCO)?
1766 
      IO_NEOLED_EN         : boolean := true    -- implement NeoPixel-compatible smart LED interface (NEOLED)?
1767 12 zero_gravi 
    );
1768 
    port (
1769 
      -- host access --
1770 
      clk_i  : in  std_ulogic; -- global clock line
1771 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1772 
      rden_i : in  std_ulogic; -- read enable
1773 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1774 
      ack_o  : out std_ulogic  -- transfer acknowledge
1775 
    );
1776 
  end component;
1777 
 
1778 2 zero_gravi 
end neorv32_package;
1779 
 
1780 
package body neorv32_package is
1781 
 
1782 41 zero_gravi 
  -- Function: Minimal required number of bits to represent input number --------------------
1783 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1784 
  function index_size_f(input : natural) return natural is
1785 
  begin
1786 
    for i in 0 to natural'high loop
1787 
      if (2**i >= input) then
1788 
        return i;
1789 
      end if;
1790 
    end loop; -- i
1791 
    return 0;
1792 
  end function index_size_f;
1793 
 
1794 
  -- Function: Conditional select natural ---------------------------------------------------
1795 
  -- -------------------------------------------------------------------------------------------
1796 
  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural is
1797 
  begin
1798 
    if (cond = true) then
1799 
      return val_t;
1800 
    else
1801 
      return val_f;
1802 
    end if;
1803 
  end function cond_sel_natural_f;
1804 
 
1805 
  -- Function: Conditional select std_ulogic_vector -----------------------------------------
1806 
  -- -------------------------------------------------------------------------------------------
1807 
  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector is
1808 
  begin
1809 
    if (cond = true) then
1810 
      return val_t;
1811 
    else
1812 
      return val_f;
1813 
    end if;
1814 
  end function cond_sel_stdulogicvector_f;
1815 
 
1816 50 zero_gravi 
  -- Function: Conditional select string ----------------------------------------------------
1817 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1818 50 zero_gravi 
  function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string is
1819 
  begin
1820 
    if (cond = true) then
1821 
      return val_t;
1822 
    else
1823 
      return val_f;
1824 
    end if;
1825 
  end function cond_sel_string_f;
1826 
 
1827 
  -- Function: Convert bool to std_ulogic ---------------------------------------------------
1828 
  -- -------------------------------------------------------------------------------------------
1829 2 zero_gravi 
  function bool_to_ulogic_f(cond : boolean) return std_ulogic is
1830 
  begin
1831 
    if (cond = true) then
1832 
      return '1';
1833 
    else
1834 
      return '0';
1835 
    end if;
1836 
  end function bool_to_ulogic_f;
1837 
 
1838 
  -- Function: OR all bits ------------------------------------------------------------------
1839 
  -- -------------------------------------------------------------------------------------------
1840 
  function or_all_f(a : std_ulogic_vector) return std_ulogic is
1841 
    variable tmp_v : std_ulogic;
1842 
  begin
1843 
    tmp_v := a(a'low);
1844 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1845 
      for i in a'low+1 to a'high loop
1846 
        tmp_v := tmp_v or a(i);
1847 
      end loop; -- i
1848 
    end if;
1849 2 zero_gravi 
    return tmp_v;
1850 
  end function or_all_f;
1851 
 
1852 
  -- Function: AND all bits -----------------------------------------------------------------
1853 
  -- -------------------------------------------------------------------------------------------
1854 
  function and_all_f(a : std_ulogic_vector) return std_ulogic is
1855 
    variable tmp_v : std_ulogic;
1856 
  begin
1857 
    tmp_v := a(a'low);
1858 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1859 
      for i in a'low+1 to a'high loop
1860 
        tmp_v := tmp_v and a(i);
1861 
      end loop; -- i
1862 
    end if;
1863 2 zero_gravi 
    return tmp_v;
1864 
  end function and_all_f;
1865 
 
1866 
  -- Function: XOR all bits -----------------------------------------------------------------
1867 
  -- -------------------------------------------------------------------------------------------
1868 
  function xor_all_f(a : std_ulogic_vector) return std_ulogic is
1869 
    variable tmp_v : std_ulogic;
1870 
  begin
1871 
    tmp_v := a(a'low);
1872 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1873 
      for i in a'low+1 to a'high loop
1874 
        tmp_v := tmp_v xor a(i);
1875 
      end loop; -- i
1876 
    end if;
1877 2 zero_gravi 
    return tmp_v;
1878 
  end function xor_all_f;
1879 
 
1880 
  -- Function: XNOR all bits ----------------------------------------------------------------
1881 
  -- -------------------------------------------------------------------------------------------
1882 
  function xnor_all_f(a : std_ulogic_vector) return std_ulogic is
1883 
    variable tmp_v : std_ulogic;
1884 
  begin
1885 
    tmp_v := a(a'low);
1886 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1887 
      for i in a'low+1 to a'high loop
1888 
        tmp_v := tmp_v xnor a(i);
1889 
      end loop; -- i
1890 
    end if;
1891 2 zero_gravi 
    return tmp_v;
1892 
  end function xnor_all_f;
1893 
 
1894 40 zero_gravi 
  -- Function: Convert std_ulogic_vector to hex char ----------------------------------------
1895 6 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1896 
  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character is
1897 
    variable output_v : character;
1898 
  begin
1899 
    case input is
1900 7 zero_gravi 
      when x"0"   => output_v := '0';
1901 
      when x"1"   => output_v := '1';
1902 
      when x"2"   => output_v := '2';
1903 
      when x"3"   => output_v := '3';
1904 
      when x"4"   => output_v := '4';
1905 
      when x"5"   => output_v := '5';
1906 
      when x"6"   => output_v := '6';
1907 
      when x"7"   => output_v := '7';
1908 
      when x"8"   => output_v := '8';
1909 
      when x"9"   => output_v := '9';
1910 
      when x"a"   => output_v := 'a';
1911 
      when x"b"   => output_v := 'b';
1912 
      when x"c"   => output_v := 'c';
1913 
      when x"d"   => output_v := 'd';
1914 
      when x"e"   => output_v := 'e';
1915 
      when x"f"   => output_v := 'f';
1916 6 zero_gravi 
      when others => output_v := '?';
1917 
    end case;
1918 
    return output_v;
1919 
  end function to_hexchar_f;
1920 
 
1921 40 zero_gravi 
  -- Function: Convert hex char to std_ulogic_vector ----------------------------------------
1922 
  -- -------------------------------------------------------------------------------------------
1923 
  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector is
1924 
    variable hex_value_v : std_ulogic_vector(3 downto 0);
1925 
  begin
1926 
    case input is
1927 
      when '0'       => hex_value_v := x"0";
1928 
      when '1'       => hex_value_v := x"1";
1929 
      when '2'       => hex_value_v := x"2";
1930 
      when '3'       => hex_value_v := x"3";
1931 
      when '4'       => hex_value_v := x"4";
1932 
      when '5'       => hex_value_v := x"5";
1933 
      when '6'       => hex_value_v := x"6";
1934 
      when '7'       => hex_value_v := x"7";
1935 
      when '8'       => hex_value_v := x"8";
1936 
      when '9'       => hex_value_v := x"9";
1937 
      when 'a' | 'A' => hex_value_v := x"a";
1938 
      when 'b' | 'B' => hex_value_v := x"b";
1939 
      when 'c' | 'C' => hex_value_v := x"c";
1940 
      when 'd' | 'D' => hex_value_v := x"d";
1941 
      when 'e' | 'E' => hex_value_v := x"e";
1942 
      when 'f' | 'F' => hex_value_v := x"f";
1943 
      when others    => hex_value_v := (others => 'X');
1944 
    end case;
1945 
    return hex_value_v;
1946 
  end function hexchar_to_stdulogicvector_f;
1947 
 
1948 32 zero_gravi 
  -- Function: Bit reversal -----------------------------------------------------------------
1949 
  -- -------------------------------------------------------------------------------------------
1950 
  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector is
1951 
    variable output_v : std_ulogic_vector(input'range);
1952 
  begin
1953 
    for i in 0 to input'length-1 loop
1954 
      output_v(input'length-i-1) := input(i);
1955 
    end loop; -- i
1956 
    return output_v;
1957 
  end function bit_rev_f;
1958 
 
1959 36 zero_gravi 
  -- Function: Test if input number is a power of two ---------------------------------------
1960 
  -- -------------------------------------------------------------------------------------------
1961 
  function is_power_of_two_f(input : natural) return boolean is
1962 
  begin
1963 38 zero_gravi 
    if (input = 1) then -- 2^0
1964 36 zero_gravi 
      return true;
1965 38 zero_gravi 
    elsif ((input / 2) /= 0) and ((input mod 2) = 0) then
1966 
      return true;
1967 36 zero_gravi 
    else
1968 
      return false;
1969 
    end if;
1970 
  end function is_power_of_two_f;
1971 
 
1972 40 zero_gravi 
  -- Function: Swap all bytes of a 32-bit word (endianness conversion) ----------------------
1973 
  -- -------------------------------------------------------------------------------------------
1974 
  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector is
1975 
    variable output_v : std_ulogic_vector(input'range);
1976 
  begin
1977 
    output_v(07 downto 00) := input(31 downto 24);
1978 
    output_v(15 downto 08) := input(23 downto 16);
1979 
    output_v(23 downto 16) := input(15 downto 08);
1980 
    output_v(31 downto 24) := input(07 downto 00);
1981 
    return output_v;
1982 
  end function bswap32_f;
1983 
 
1984 2 zero_gravi 
end neorv32_package;

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