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1 2 zero_gravi 
-- #################################################################################################
2 
-- # << NEORV32 - Main VHDL package file >>                                                        #
3 
-- # ********************************************************************************************* #
4 
-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
6 42 zero_gravi 
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
7 2 zero_gravi 
-- #                                                                                               #
8 
-- # Redistribution and use in source and binary forms, with or without modification, are          #
9 
-- # permitted provided that the following conditions are met:                                     #
10 
-- #                                                                                               #
11 
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
12 
-- #    conditions and the following disclaimer.                                                   #
13 
-- #                                                                                               #
14 
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
15 
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
16 
-- #    provided with the distribution.                                                            #
17 
-- #                                                                                               #
18 
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
20 
-- #    permission.                                                                                #
21 
-- #                                                                                               #
22 
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
23 
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
24 
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
25 
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
26 
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
27 
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
28 
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
29 
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
30 
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
32 
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
33 
-- #################################################################################################
34 
 
35 
library ieee;
36 
use ieee.std_logic_1164.all;
37 
use ieee.numeric_std.all;
38 
 
39 
package neorv32_package is
40 
 
41 36 zero_gravi 
  -- Architecture Configuration -------------------------------------------------------------
42 
  -- -------------------------------------------------------------------------------------------
43 40 zero_gravi 
  -- address space --
44 
  constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
45 
  constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
46 36 zero_gravi 
 
47 40 zero_gravi 
  -- (external) bus interface --
48 41 zero_gravi 
  constant bus_timeout_c     : natural := 127; -- cycles after which an *unacknowledged* bus access will timeout and trigger a bus fault exception (min 2)
49 40 zero_gravi 
  constant wb_pipe_mode_c    : boolean := false; -- *external* bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode
50 
  constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian
51 
 
52 
  -- CPU core --
53 55 zero_gravi 
  constant ipb_entries_c   : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
54 
  constant cp_timeout_en_c : boolean := false; -- auto-terminate pending co-processor operations after 256 cycles (for debugging only), default = false
55 40 zero_gravi 
 
56 54 zero_gravi 
  -- "critical" number of implemented PMP regions --
57 
  -- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
58 
  -- increasing instruction fetch & data access latency by +1 cycle but also reducing critical path length
59 
  constant pmp_num_regions_critical_c : natural := 8; -- default=8
60 47 zero_gravi 
 
61 48 zero_gravi 
  -- Architecture Constants (do not modify!) ------------------------------------------------
62 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
63 47 zero_gravi 
  constant data_width_c   : natural := 32; -- native data path width - do not change!
64 55 zero_gravi 
  constant hw_version_c   : std_ulogic_vector(31 downto 0) := x"01050302"; -- no touchy!
65 40 zero_gravi 
  constant pmp_max_r_c    : natural := 8; -- max PMP regions - FIXED!
66 
  constant archid_c       : natural := 19; -- official NEORV32 architecture ID - hands off!
67 42 zero_gravi 
  constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
68 27 zero_gravi 
 
69 12 zero_gravi 
  -- Helper Functions -----------------------------------------------------------------------
70 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
71 
  function index_size_f(input : natural) return natural;
72 
  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
73 
  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
74 50 zero_gravi 
  function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string;
75 2 zero_gravi 
  function bool_to_ulogic_f(cond : boolean) return std_ulogic;
76 15 zero_gravi 
  function or_all_f(a : std_ulogic_vector) return std_ulogic;
77 
  function and_all_f(a : std_ulogic_vector) return std_ulogic;
78 
  function xor_all_f(a : std_ulogic_vector) return std_ulogic;
79 2 zero_gravi 
  function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
80 6 zero_gravi 
  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
81 40 zero_gravi 
  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector;
82 32 zero_gravi 
  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector;
83 36 zero_gravi 
  function is_power_of_two_f(input : natural) return boolean;
84 40 zero_gravi 
  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;
85 2 zero_gravi 
 
86 15 zero_gravi 
  -- Internal Types -------------------------------------------------------------------------
87 
  -- -------------------------------------------------------------------------------------------
88 42 zero_gravi 
  type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);
89 
  type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0);
90 49 zero_gravi 
  type cp_data_if_t  is array (0 to 7)  of std_ulogic_vector(data_width_c-1 downto 0);
91 15 zero_gravi 
 
92 23 zero_gravi 
  -- Processor-Internal Address Space Layout ------------------------------------------------
93 
  -- -------------------------------------------------------------------------------------------
94 34 zero_gravi 
  -- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
95 39 zero_gravi 
  constant imem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
96 
  constant dmem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
97 42 zero_gravi 
  --> internal data/instruction memory sizes are configured via top's generics
98 2 zero_gravi 
 
99 23 zero_gravi 
  -- Internal Bootloader ROM --
100 
  constant boot_rom_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!
101 47 zero_gravi 
  constant boot_rom_size_c      : natural := 4*1024; -- module's address space in bytes
102 
  constant boot_rom_max_size_c  : natural := 32*1024; -- max module's address space in bytes, fixed!
103 23 zero_gravi 
 
104 2 zero_gravi 
  -- IO: Peripheral Devices ("IO") Area --
105 
  -- Control register(s) (including the device-enable) should be located at the base address of each device
106 47 zero_gravi 
  constant io_base_c            : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00";
107 
  constant io_size_c            : natural := 64*4; -- module's address space in bytes, fixed!
108 2 zero_gravi 
 
109 47 zero_gravi 
  -- Custom Functions Subsystem (CFS) --
110 
  constant cfs_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00"; -- base address
111 
  constant cfs_size_c           : natural := 32*4; -- module's address space in bytes
112 
  constant cfs_reg0_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00";
113 
  constant cfs_reg1_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF04";
114 
  constant cfs_reg2_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF08";
115 
  constant cfs_reg3_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF0C";
116 
  constant cfs_reg4_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF10";
117 
  constant cfs_reg5_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF14";
118 
  constant cfs_reg6_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF18";
119 
  constant cfs_reg7_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF1C";
120 
  constant cfs_reg8_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF20";
121 
  constant cfs_reg9_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF24";
122 
  constant cfs_reg10_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF28";
123 
  constant cfs_reg11_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF2C";
124 
  constant cfs_reg12_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF30";
125 
  constant cfs_reg13_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF34";
126 
  constant cfs_reg14_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF38";
127 
  constant cfs_reg15_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF3C";
128 
  constant cfs_reg16_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF40";
129 
  constant cfs_reg17_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF44";
130 
  constant cfs_reg18_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF48";
131 
  constant cfs_reg19_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF4C";
132 
  constant cfs_reg20_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF50";
133 
  constant cfs_reg21_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF54";
134 
  constant cfs_reg22_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF58";
135 
  constant cfs_reg23_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF5C";
136 
  constant cfs_reg24_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF60";
137 
  constant cfs_reg25_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF64";
138 
  constant cfs_reg26_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF68";
139 
  constant cfs_reg27_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF6C";
140 
  constant cfs_reg28_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF70";
141 
  constant cfs_reg29_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF74";
142 
  constant cfs_reg30_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF78";
143 
  constant cfs_reg31_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF7C";
144 
 
145 2 zero_gravi 
  -- General Purpose Input/Output Unit (GPIO) --
146 47 zero_gravi 
  constant gpio_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address
147 
  constant gpio_size_c          : natural := 2*4; -- module's address space in bytes
148 23 zero_gravi 
  constant gpio_in_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80";
149 
  constant gpio_out_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF84";
150 2 zero_gravi 
 
151 30 zero_gravi 
  -- True Random Number Generator (TRNG) --
152 47 zero_gravi 
  constant trng_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address
153 
  constant trng_size_c          : natural := 1*4; -- module's address space in bytes
154 30 zero_gravi 
  constant trng_ctrl_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88";
155 2 zero_gravi 
 
156 
  -- Watch Dog Timer (WDT) --
157 47 zero_gravi 
  constant wdt_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address
158 
  constant wdt_size_c           : natural := 1*4; -- module's address space in bytes
159 23 zero_gravi 
  constant wdt_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C";
160 2 zero_gravi 
 
161 
  -- Machine System Timer (MTIME) --
162 47 zero_gravi 
  constant mtime_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90"; -- base address
163 
  constant mtime_size_c         : natural := 4*4; -- module's address space in bytes
164 23 zero_gravi 
  constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90";
165 
  constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF94";
166 
  constant mtime_cmp_lo_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF98";
167 
  constant mtime_cmp_hi_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF9C";
168 2 zero_gravi 
 
169 50 zero_gravi 
  -- Universal Asynchronous Receiver/Transmitter 0 (UART0), primary UART --
170 
  constant uart0_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address
171 
  constant uart0_size_c         : natural := 2*4; -- module's address space in bytes
172 
  constant uart0_ctrl_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0";
173 
  constant uart0_rtx_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA4";
174 2 zero_gravi 
 
175 
  -- Serial Peripheral Interface (SPI) --
176 47 zero_gravi 
  constant spi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address
177 
  constant spi_size_c           : natural := 2*4; -- module's address space in bytes
178 23 zero_gravi 
  constant spi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8";
179 
  constant spi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFAC";
180 2 zero_gravi 
 
181 
  -- Two Wire Interface (TWI) --
182 47 zero_gravi 
  constant twi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0"; -- base address
183 
  constant twi_size_c           : natural := 2*4; -- module's address space in bytes
184 23 zero_gravi 
  constant twi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0";
185 
  constant twi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB4";
186 2 zero_gravi 
 
187 
  -- Pulse-Width Modulation Controller (PWM) --
188 47 zero_gravi 
  constant pwm_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address
189 
  constant pwm_size_c           : natural := 2*4; -- module's address space in bytes
190 23 zero_gravi 
  constant pwm_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8";
191 
  constant pwm_duty_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFBC";
192 2 zero_gravi 
 
193 49 zero_gravi 
  -- Numerically-Controlled Oscillator (NCO) --
194 
  constant nco_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address
195 
  constant nco_size_c           : natural := 4*4; -- module's address space in bytes
196 
  constant nco_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0";
197 
  constant nco_ch0_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC4";
198 
  constant nco_ch1_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8";
199 
  constant nco_ch2_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC";
200 
 
201 50 zero_gravi 
  -- Universal Asynchronous Receiver/Transmitter 1 (UART1), secondary UART --
202 
  constant uart1_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address
203 
  constant uart1_size_c         : natural := 2*4; -- module's address space in bytes
204 
  constant uart1_ctrl_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0";
205 
  constant uart1_rtx_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD4";
206 
 
207 52 zero_gravi 
  -- Smart LED (WS2811/WS2812) Interface (NEOLED) --
208 
  constant neoled_base_c        : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD8"; -- base address
209 
  constant neoled_size_c        : natural := 2*4; -- module's address space in bytes
210 
  constant neoled_ctrl_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD8";
211 
  constant neoled_data_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFDC";
212 12 zero_gravi 
 
213 23 zero_gravi 
  -- System Information Memory (SYSINFO) --
214 47 zero_gravi 
  constant sysinfo_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address
215 
  constant sysinfo_size_c       : natural := 8*4; -- module's address space in bytes
216 12 zero_gravi 
 
217 2 zero_gravi 
  -- Main Control Bus -----------------------------------------------------------------------
218 
  -- -------------------------------------------------------------------------------------------
219 
  -- register file --
220 49 zero_gravi 
  constant ctrl_rf_in_mux_c     : natural :=  0; -- input source select lsb (0=MEM, 1=ALU)
221 
  constant ctrl_rf_rs1_adr0_c   : natural :=  1; -- source register 1 address bit 0
222 
  constant ctrl_rf_rs1_adr1_c   : natural :=  2; -- source register 1 address bit 1
223 
  constant ctrl_rf_rs1_adr2_c   : natural :=  3; -- source register 1 address bit 2
224 
  constant ctrl_rf_rs1_adr3_c   : natural :=  4; -- source register 1 address bit 3
225 
  constant ctrl_rf_rs1_adr4_c   : natural :=  5; -- source register 1 address bit 4
226 
  constant ctrl_rf_rs2_adr0_c   : natural :=  6; -- source register 2 address bit 0
227 
  constant ctrl_rf_rs2_adr1_c   : natural :=  7; -- source register 2 address bit 1
228 
  constant ctrl_rf_rs2_adr2_c   : natural :=  8; -- source register 2 address bit 2
229 
  constant ctrl_rf_rs2_adr3_c   : natural :=  9; -- source register 2 address bit 3
230 
  constant ctrl_rf_rs2_adr4_c   : natural := 10; -- source register 2 address bit 4
231 
  constant ctrl_rf_rd_adr0_c    : natural := 11; -- destiantion register address bit 0
232 
  constant ctrl_rf_rd_adr1_c    : natural := 12; -- destiantion register address bit 1
233 
  constant ctrl_rf_rd_adr2_c    : natural := 13; -- destiantion register address bit 2
234 
  constant ctrl_rf_rd_adr3_c    : natural := 14; -- destiantion register address bit 3
235 
  constant ctrl_rf_rd_adr4_c    : natural := 15; -- destiantion register address bit 4
236 
  constant ctrl_rf_wb_en_c      : natural := 16; -- write back enable
237 
  constant ctrl_rf_r0_we_c      : natural := 17; -- force write access and force rd=r0
238 2 zero_gravi 
  -- alu --
239 49 zero_gravi 
  constant ctrl_alu_arith_c     : natural := 18; -- ALU arithmetic command
240 
  constant ctrl_alu_logic0_c    : natural := 19; -- ALU logic command bit 0
241 
  constant ctrl_alu_logic1_c    : natural := 20; -- ALU logic command bit 1
242 
  constant ctrl_alu_func0_c     : natural := 21; -- ALU function select command bit 0
243 
  constant ctrl_alu_func1_c     : natural := 22; -- ALU function select command bit 1
244 
  constant ctrl_alu_addsub_c    : natural := 23; -- 0=ADD, 1=SUB
245 
  constant ctrl_alu_opa_mux_c   : natural := 24; -- operand A select (0=rs1, 1=PC)
246 
  constant ctrl_alu_opb_mux_c   : natural := 25; -- operand B select (0=rs2, 1=IMM)
247 
  constant ctrl_alu_unsigned_c  : natural := 26; -- is unsigned ALU operation
248 
  constant ctrl_alu_shift_dir_c : natural := 27; -- shift direction (0=left, 1=right)
249 
  constant ctrl_alu_shift_ar_c  : natural := 28; -- is arithmetic shift
250 2 zero_gravi 
  -- bus interface --
251 49 zero_gravi 
  constant ctrl_bus_size_lsb_c  : natural := 29; -- transfer size lsb (00=byte, 01=half-word)
252 
  constant ctrl_bus_size_msb_c  : natural := 30; -- transfer size msb (10=word, 11=?)
253 
  constant ctrl_bus_rd_c        : natural := 31; -- read data request
254 
  constant ctrl_bus_wr_c        : natural := 32; -- write data request
255 
  constant ctrl_bus_if_c        : natural := 33; -- instruction fetch request
256 
  constant ctrl_bus_mo_we_c     : natural := 34; -- memory address and data output register write enable
257 
  constant ctrl_bus_mi_we_c     : natural := 35; -- memory data input register write enable
258 53 zero_gravi 
  constant ctrl_bus_unsigned_c  : natural := 36; -- is unsigned load
259 
  constant ctrl_bus_ierr_ack_c  : natural := 37; -- acknowledge instruction fetch bus exceptions
260 
  constant ctrl_bus_derr_ack_c  : natural := 38; -- acknowledge data access bus exceptions
261 
  constant ctrl_bus_fence_c     : natural := 39; -- executed fence operation
262 
  constant ctrl_bus_fencei_c    : natural := 40; -- executed fencei operation
263 
  constant ctrl_bus_excl_c      : natural := 41; -- exclusive bus access
264 26 zero_gravi 
  -- co-processors --
265 53 zero_gravi 
  constant ctrl_cp_id_lsb_c     : natural := 42; -- cp select ID lsb
266 
  constant ctrl_cp_id_hsb_c     : natural := 43; -- cp select ID hsb
267 
  constant ctrl_cp_id_msb_c     : natural := 44; -- cp select ID msb
268 36 zero_gravi 
  -- current privilege level --
269 53 zero_gravi 
  constant ctrl_priv_lvl_lsb_c  : natural := 45; -- privilege level lsb
270 
  constant ctrl_priv_lvl_msb_c  : natural := 46; -- privilege level msb
271 44 zero_gravi 
  -- instruction's control blocks (used by cpu co-processors) --
272 53 zero_gravi 
  constant ctrl_ir_funct3_0_c   : natural := 47; -- funct3 bit 0
273 
  constant ctrl_ir_funct3_1_c   : natural := 48; -- funct3 bit 1
274 
  constant ctrl_ir_funct3_2_c   : natural := 49; -- funct3 bit 2
275 
  constant ctrl_ir_funct12_0_c  : natural := 50; -- funct12 bit 0
276 
  constant ctrl_ir_funct12_1_c  : natural := 51; -- funct12 bit 1
277 
  constant ctrl_ir_funct12_2_c  : natural := 52; -- funct12 bit 2
278 
  constant ctrl_ir_funct12_3_c  : natural := 53; -- funct12 bit 3
279 
  constant ctrl_ir_funct12_4_c  : natural := 54; -- funct12 bit 4
280 
  constant ctrl_ir_funct12_5_c  : natural := 55; -- funct12 bit 5
281 
  constant ctrl_ir_funct12_6_c  : natural := 56; -- funct12 bit 6
282 
  constant ctrl_ir_funct12_7_c  : natural := 57; -- funct12 bit 7
283 
  constant ctrl_ir_funct12_8_c  : natural := 58; -- funct12 bit 8
284 
  constant ctrl_ir_funct12_9_c  : natural := 59; -- funct12 bit 9
285 
  constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10
286 
  constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11
287 
  constant ctrl_ir_opcode7_0_c  : natural := 62; -- opcode7 bit 0
288 
  constant ctrl_ir_opcode7_1_c  : natural := 63; -- opcode7 bit 1
289 
  constant ctrl_ir_opcode7_2_c  : natural := 64; -- opcode7 bit 2
290 
  constant ctrl_ir_opcode7_3_c  : natural := 65; -- opcode7 bit 3
291 
  constant ctrl_ir_opcode7_4_c  : natural := 66; -- opcode7 bit 4
292 
  constant ctrl_ir_opcode7_5_c  : natural := 67; -- opcode7 bit 5
293 
  constant ctrl_ir_opcode7_6_c  : natural := 68; -- opcode7 bit 6
294 47 zero_gravi 
  -- CPU status --
295 53 zero_gravi 
  constant ctrl_sleep_c         : natural := 69; -- set when CPU is in sleep mode
296 2 zero_gravi 
  -- control bus size --
297 53 zero_gravi 
  constant ctrl_width_c         : natural := 70; -- control bus size
298 2 zero_gravi 
 
299 47 zero_gravi 
  -- Comparator Bus -------------------------------------------------------------------------
300 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
301 47 zero_gravi 
  constant cmp_equal_c : natural := 0;
302 
  constant cmp_less_c  : natural := 1; -- for signed and unsigned comparisons
303 2 zero_gravi 
 
304 
  -- RISC-V Opcode Layout -------------------------------------------------------------------
305 
  -- -------------------------------------------------------------------------------------------
306 
  constant instr_opcode_lsb_c  : natural :=  0; -- opcode bit 0
307 
  constant instr_opcode_msb_c  : natural :=  6; -- opcode bit 6
308 
  constant instr_rd_lsb_c      : natural :=  7; -- destination register address bit 0
309 
  constant instr_rd_msb_c      : natural := 11; -- destination register address bit 4
310 
  constant instr_funct3_lsb_c  : natural := 12; -- funct3 bit 0
311 
  constant instr_funct3_msb_c  : natural := 14; -- funct3 bit 2
312 
  constant instr_rs1_lsb_c     : natural := 15; -- source register 1 address bit 0
313 
  constant instr_rs1_msb_c     : natural := 19; -- source register 1 address bit 4
314 
  constant instr_rs2_lsb_c     : natural := 20; -- source register 2 address bit 0
315 
  constant instr_rs2_msb_c     : natural := 24; -- source register 2 address bit 4
316 
  constant instr_funct7_lsb_c  : natural := 25; -- funct7 bit 0
317 
  constant instr_funct7_msb_c  : natural := 31; -- funct7 bit 6
318 
  constant instr_funct12_lsb_c : natural := 20; -- funct12 bit 0
319 
  constant instr_funct12_msb_c : natural := 31; -- funct12 bit 11
320 
  constant instr_imm12_lsb_c   : natural := 20; -- immediate12 bit 0
321 
  constant instr_imm12_msb_c   : natural := 31; -- immediate12 bit 11
322 
  constant instr_imm20_lsb_c   : natural := 12; -- immediate20 bit 0
323 
  constant instr_imm20_msb_c   : natural := 31; -- immediate20 bit 21
324 
  constant instr_csr_id_lsb_c  : natural := 20; -- csr select bit 0
325 
  constant instr_csr_id_msb_c  : natural := 31; -- csr select bit 11
326 39 zero_gravi 
  constant instr_funct5_lsb_c  : natural := 27; -- funct5 select bit 0
327 
  constant instr_funct5_msb_c  : natural := 31; -- funct5 select bit 4
328 2 zero_gravi 
 
329 
  -- RISC-V Opcodes -------------------------------------------------------------------------
330 
  -- -------------------------------------------------------------------------------------------
331 
  -- alu --
332 
  constant opcode_lui_c    : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate
333 
  constant opcode_auipc_c  : std_ulogic_vector(6 downto 0) := "0010111"; -- add upper immediate to PC
334 
  constant opcode_alui_c   : std_ulogic_vector(6 downto 0) := "0010011"; -- ALU operation with immediate (operation via funct3 and funct7)
335 
  constant opcode_alu_c    : std_ulogic_vector(6 downto 0) := "0110011"; -- ALU operation (operation via funct3 and funct7)
336 
  -- control flow --
337 
  constant opcode_jal_c    : std_ulogic_vector(6 downto 0) := "1101111"; -- jump and link
338 29 zero_gravi 
  constant opcode_jalr_c   : std_ulogic_vector(6 downto 0) := "1100111"; -- jump and link with register
339 2 zero_gravi 
  constant opcode_branch_c : std_ulogic_vector(6 downto 0) := "1100011"; -- branch (condition set via funct3)
340 
  -- memory access --
341 
  constant opcode_load_c   : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)
342 
  constant opcode_store_c  : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)
343 
  -- system/csr --
344 8 zero_gravi 
  constant opcode_fence_c  : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
345 2 zero_gravi 
  constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
346 52 zero_gravi 
  -- atomic memory access (A) --
347 39 zero_gravi 
  constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)
348 53 zero_gravi 
  -- floating point operations (Zfinx-only) (F/D/H/Q) --
349 
  constant opcode_fop_c    : std_ulogic_vector(6 downto 0) := "1010011"; -- dual/single opearand instruction
350 2 zero_gravi 
 
351 
  -- RISC-V Funct3 --------------------------------------------------------------------------
352 
  -- -------------------------------------------------------------------------------------------
353 
  -- control flow --
354 
  constant funct3_beq_c    : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
355 
  constant funct3_bne_c    : std_ulogic_vector(2 downto 0) := "001"; -- branch if not equal
356 
  constant funct3_blt_c    : std_ulogic_vector(2 downto 0) := "100"; -- branch if less than
357 
  constant funct3_bge_c    : std_ulogic_vector(2 downto 0) := "101"; -- branch if greater than or equal
358 
  constant funct3_bltu_c   : std_ulogic_vector(2 downto 0) := "110"; -- branch if less than (unsigned)
359 
  constant funct3_bgeu_c   : std_ulogic_vector(2 downto 0) := "111"; -- branch if greater than or equal (unsigned)
360 
  -- memory access --
361 
  constant funct3_lb_c     : std_ulogic_vector(2 downto 0) := "000"; -- load byte
362 
  constant funct3_lh_c     : std_ulogic_vector(2 downto 0) := "001"; -- load half word
363 
  constant funct3_lw_c     : std_ulogic_vector(2 downto 0) := "010"; -- load word
364 
  constant funct3_lbu_c    : std_ulogic_vector(2 downto 0) := "100"; -- load byte (unsigned)
365 
  constant funct3_lhu_c    : std_ulogic_vector(2 downto 0) := "101"; -- load half word (unsigned)
366 
  constant funct3_sb_c     : std_ulogic_vector(2 downto 0) := "000"; -- store byte
367 
  constant funct3_sh_c     : std_ulogic_vector(2 downto 0) := "001"; -- store half word
368 
  constant funct3_sw_c     : std_ulogic_vector(2 downto 0) := "010"; -- store word
369 
  -- alu --
370 
  constant funct3_subadd_c : std_ulogic_vector(2 downto 0) := "000"; -- sub/add via funct7
371 
  constant funct3_sll_c    : std_ulogic_vector(2 downto 0) := "001"; -- shift logical left
372 
  constant funct3_slt_c    : std_ulogic_vector(2 downto 0) := "010"; -- set on less
373 
  constant funct3_sltu_c   : std_ulogic_vector(2 downto 0) := "011"; -- set on less unsigned
374 
  constant funct3_xor_c    : std_ulogic_vector(2 downto 0) := "100"; -- xor
375 
  constant funct3_sr_c     : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7
376 
  constant funct3_or_c     : std_ulogic_vector(2 downto 0) := "110"; -- or
377 
  constant funct3_and_c    : std_ulogic_vector(2 downto 0) := "111"; -- and
378 
  -- system/csr --
379 
  constant funct3_env_c    : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi
380 
  constant funct3_csrrw_c  : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w
381 
  constant funct3_csrrs_c  : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit
382 
  constant funct3_csrrc_c  : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit
383 
  constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate
384 
  constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate
385 
  constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
386 8 zero_gravi 
  -- fence --
387 
  constant funct3_fence_c  : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
388 
  constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync
389 2 zero_gravi 
 
390 39 zero_gravi 
  -- RISC-V Funct12 -------------------------------------------------------------------------
391 11 zero_gravi 
  -- -------------------------------------------------------------------------------------------
392 
  -- system --
393 
  constant funct12_ecall_c  : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
394 
  constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
395 
  constant funct12_mret_c   : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
396 
  constant funct12_wfi_c    : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
397 
 
398 39 zero_gravi 
  -- RISC-V Funct5 --------------------------------------------------------------------------
399 
  -- -------------------------------------------------------------------------------------------
400 
  -- atomic operations --
401 
  constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR
402 
  constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC
403 
 
404 54 zero_gravi 
  -- RISC-V Floating-Point Stuff ------------------------------------------------------------
405 52 zero_gravi 
  -- -------------------------------------------------------------------------------------------
406 54 zero_gravi 
  -- formats --
407 
  constant float_single_c : std_ulogic_vector(1 downto 0) := "00"; -- single-precision (32-bit)
408 
  constant float_double_c : std_ulogic_vector(1 downto 0) := "01"; -- double-precision (64-bit)
409 
  constant float_half_c   : std_ulogic_vector(1 downto 0) := "10"; -- half-precision (16-bit)
410 
  constant float_quad_c   : std_ulogic_vector(1 downto 0) := "11"; -- quad-precision (128-bit)
411 52 zero_gravi 
 
412 54 zero_gravi 
  -- number class flags --
413 
  constant fp_class_neg_inf_c    : natural := 0; -- negative infinity
414 
  constant fp_class_neg_norm_c   : natural := 1; -- negative normal number
415 
  constant fp_class_neg_denorm_c : natural := 2; -- negative subnormal number
416 
  constant fp_class_neg_zero_c   : natural := 3; -- negative zero
417 
  constant fp_class_pos_zero_c   : natural := 4; -- positive zero
418 
  constant fp_class_pos_denorm_c : natural := 5; -- positive subnormal number
419 
  constant fp_class_pos_norm_c   : natural := 6; -- positive normal number
420 
  constant fp_class_pos_inf_c    : natural := 7; -- positive infinity
421 
  constant fp_class_snan_c       : natural := 8; -- signaling NaN (sNaN)
422 
  constant fp_class_qnan_c       : natural := 9; -- quiet NaN (qNaN)
423 
 
424 
  -- exception flags --
425 
  constant fp_exc_nv_c : natural := 0; -- invalid operation
426 
  constant fp_exc_dz_c : natural := 1; -- divide by zero
427 
  constant fp_exc_of_c : natural := 2; -- overflow
428 
  constant fp_exc_uf_c : natural := 3; -- underflow
429 
  constant fp_exc_nx_c : natural := 4; -- inexact
430 
 
431 
  -- special values (single-precision) --
432 
  constant fp_single_qnan_c     : std_ulogic_vector(31 downto 0) := x"7fc00000"; -- quiet NaN
433 
  constant fp_single_snan_c     : std_ulogic_vector(31 downto 0) := x"7fa00000"; -- signaling NaN
434 
  constant fp_single_pos_inf_c  : std_ulogic_vector(31 downto 0) := x"7f800000"; -- positive infinity
435 
  constant fp_single_neg_inf_c  : std_ulogic_vector(31 downto 0) := x"ff800000"; -- negative infinity
436 
  constant fp_single_pos_zero_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- positive zero
437 
  constant fp_single_neg_zero_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- negative zero
438 
 
439 29 zero_gravi 
  -- RISC-V CSR Addresses -------------------------------------------------------------------
440 
  -- -------------------------------------------------------------------------------------------
441 41 zero_gravi 
  -- read/write CSRs --
442 52 zero_gravi 
  constant csr_class_float_c    : std_ulogic_vector(07 downto 0) := x"00"; -- floating point
443 
  constant csr_fflags_c         : std_ulogic_vector(11 downto 0) := x"001";
444 
  constant csr_frm_c            : std_ulogic_vector(11 downto 0) := x"002";
445 
  constant csr_fcsr_c           : std_ulogic_vector(11 downto 0) := x"003";
446 
  --
447 
  constant csr_setup_c          : std_ulogic_vector(07 downto 0) := x"30"; -- trap setup
448 42 zero_gravi 
  constant csr_mstatus_c        : std_ulogic_vector(11 downto 0) := x"300";
449 
  constant csr_misa_c           : std_ulogic_vector(11 downto 0) := x"301";
450 
  constant csr_mie_c            : std_ulogic_vector(11 downto 0) := x"304";
451 
  constant csr_mtvec_c          : std_ulogic_vector(11 downto 0) := x"305";
452 
  constant csr_mcounteren_c     : std_ulogic_vector(11 downto 0) := x"306";
453 52 zero_gravi 
  --
454 42 zero_gravi 
  constant csr_mstatush_c       : std_ulogic_vector(11 downto 0) := x"310";
455 29 zero_gravi 
  --
456 42 zero_gravi 
  constant csr_mcountinhibit_c  : std_ulogic_vector(11 downto 0) := x"320";
457 29 zero_gravi 
  --
458 42 zero_gravi 
  constant csr_mhpmevent3_c     : std_ulogic_vector(11 downto 0) := x"323";
459 
  constant csr_mhpmevent4_c     : std_ulogic_vector(11 downto 0) := x"324";
460 
  constant csr_mhpmevent5_c     : std_ulogic_vector(11 downto 0) := x"325";
461 
  constant csr_mhpmevent6_c     : std_ulogic_vector(11 downto 0) := x"326";
462 
  constant csr_mhpmevent7_c     : std_ulogic_vector(11 downto 0) := x"327";
463 
  constant csr_mhpmevent8_c     : std_ulogic_vector(11 downto 0) := x"328";
464 
  constant csr_mhpmevent9_c     : std_ulogic_vector(11 downto 0) := x"329";
465 
  constant csr_mhpmevent10_c    : std_ulogic_vector(11 downto 0) := x"32a";
466 
  constant csr_mhpmevent11_c    : std_ulogic_vector(11 downto 0) := x"32b";
467 
  constant csr_mhpmevent12_c    : std_ulogic_vector(11 downto 0) := x"32c";
468 
  constant csr_mhpmevent13_c    : std_ulogic_vector(11 downto 0) := x"32d";
469 
  constant csr_mhpmevent14_c    : std_ulogic_vector(11 downto 0) := x"32e";
470 
  constant csr_mhpmevent15_c    : std_ulogic_vector(11 downto 0) := x"32f";
471 
  constant csr_mhpmevent16_c    : std_ulogic_vector(11 downto 0) := x"330";
472 
  constant csr_mhpmevent17_c    : std_ulogic_vector(11 downto 0) := x"331";
473 
  constant csr_mhpmevent18_c    : std_ulogic_vector(11 downto 0) := x"332";
474 
  constant csr_mhpmevent19_c    : std_ulogic_vector(11 downto 0) := x"333";
475 
  constant csr_mhpmevent20_c    : std_ulogic_vector(11 downto 0) := x"334";
476 
  constant csr_mhpmevent21_c    : std_ulogic_vector(11 downto 0) := x"335";
477 
  constant csr_mhpmevent22_c    : std_ulogic_vector(11 downto 0) := x"336";
478 
  constant csr_mhpmevent23_c    : std_ulogic_vector(11 downto 0) := x"337";
479 
  constant csr_mhpmevent24_c    : std_ulogic_vector(11 downto 0) := x"338";
480 
  constant csr_mhpmevent25_c    : std_ulogic_vector(11 downto 0) := x"339";
481 
  constant csr_mhpmevent26_c    : std_ulogic_vector(11 downto 0) := x"33a";
482 
  constant csr_mhpmevent27_c    : std_ulogic_vector(11 downto 0) := x"33b";
483 
  constant csr_mhpmevent28_c    : std_ulogic_vector(11 downto 0) := x"33c";
484 
  constant csr_mhpmevent29_c    : std_ulogic_vector(11 downto 0) := x"33d";
485 
  constant csr_mhpmevent30_c    : std_ulogic_vector(11 downto 0) := x"33e";
486 
  constant csr_mhpmevent31_c    : std_ulogic_vector(11 downto 0) := x"33f";
487 29 zero_gravi 
  --
488 52 zero_gravi 
  constant csr_class_trap_c     : std_ulogic_vector(07 downto 0) := x"34"; -- machine trap handling
489 42 zero_gravi 
  constant csr_mscratch_c       : std_ulogic_vector(11 downto 0) := x"340";
490 
  constant csr_mepc_c           : std_ulogic_vector(11 downto 0) := x"341";
491 
  constant csr_mcause_c         : std_ulogic_vector(11 downto 0) := x"342";
492 
  constant csr_mtval_c          : std_ulogic_vector(11 downto 0) := x"343";
493 
  constant csr_mip_c            : std_ulogic_vector(11 downto 0) := x"344";
494 29 zero_gravi 
  --
495 52 zero_gravi 
  constant csr_class_pmpcfg_c   : std_ulogic_vector(07 downto 0) := x"3a"; -- pmp configuration
496 42 zero_gravi 
  constant csr_pmpcfg0_c        : std_ulogic_vector(11 downto 0) := x"3a0";
497 
  constant csr_pmpcfg1_c        : std_ulogic_vector(11 downto 0) := x"3a1";
498 
  constant csr_pmpcfg2_c        : std_ulogic_vector(11 downto 0) := x"3a2";
499 
  constant csr_pmpcfg3_c        : std_ulogic_vector(11 downto 0) := x"3a3";
500 
  constant csr_pmpcfg4_c        : std_ulogic_vector(11 downto 0) := x"3a4";
501 
  constant csr_pmpcfg5_c        : std_ulogic_vector(11 downto 0) := x"3a5";
502 
  constant csr_pmpcfg6_c        : std_ulogic_vector(11 downto 0) := x"3a6";
503 
  constant csr_pmpcfg7_c        : std_ulogic_vector(11 downto 0) := x"3a7";
504 
  constant csr_pmpcfg8_c        : std_ulogic_vector(11 downto 0) := x"3a8";
505 
  constant csr_pmpcfg9_c        : std_ulogic_vector(11 downto 0) := x"3a9";
506 
  constant csr_pmpcfg10_c       : std_ulogic_vector(11 downto 0) := x"3aa";
507 
  constant csr_pmpcfg11_c       : std_ulogic_vector(11 downto 0) := x"3ab";
508 
  constant csr_pmpcfg12_c       : std_ulogic_vector(11 downto 0) := x"3ac";
509 
  constant csr_pmpcfg13_c       : std_ulogic_vector(11 downto 0) := x"3ad";
510 
  constant csr_pmpcfg14_c       : std_ulogic_vector(11 downto 0) := x"3ae";
511 
  constant csr_pmpcfg15_c       : std_ulogic_vector(11 downto 0) := x"3af";
512 29 zero_gravi 
  --
513 42 zero_gravi 
  constant csr_pmpaddr0_c       : std_ulogic_vector(11 downto 0) := x"3b0";
514 
  constant csr_pmpaddr1_c       : std_ulogic_vector(11 downto 0) := x"3b1";
515 
  constant csr_pmpaddr2_c       : std_ulogic_vector(11 downto 0) := x"3b2";
516 
  constant csr_pmpaddr3_c       : std_ulogic_vector(11 downto 0) := x"3b3";
517 
  constant csr_pmpaddr4_c       : std_ulogic_vector(11 downto 0) := x"3b4";
518 
  constant csr_pmpaddr5_c       : std_ulogic_vector(11 downto 0) := x"3b5";
519 
  constant csr_pmpaddr6_c       : std_ulogic_vector(11 downto 0) := x"3b6";
520 
  constant csr_pmpaddr7_c       : std_ulogic_vector(11 downto 0) := x"3b7";
521 
  constant csr_pmpaddr8_c       : std_ulogic_vector(11 downto 0) := x"3b8";
522 
  constant csr_pmpaddr9_c       : std_ulogic_vector(11 downto 0) := x"3b9";
523 
  constant csr_pmpaddr10_c      : std_ulogic_vector(11 downto 0) := x"3ba";
524 
  constant csr_pmpaddr11_c      : std_ulogic_vector(11 downto 0) := x"3bb";
525 
  constant csr_pmpaddr12_c      : std_ulogic_vector(11 downto 0) := x"3bc";
526 
  constant csr_pmpaddr13_c      : std_ulogic_vector(11 downto 0) := x"3bd";
527 
  constant csr_pmpaddr14_c      : std_ulogic_vector(11 downto 0) := x"3be";
528 
  constant csr_pmpaddr15_c      : std_ulogic_vector(11 downto 0) := x"3bf";
529 
  constant csr_pmpaddr16_c      : std_ulogic_vector(11 downto 0) := x"3c0";
530 
  constant csr_pmpaddr17_c      : std_ulogic_vector(11 downto 0) := x"3c1";
531 
  constant csr_pmpaddr18_c      : std_ulogic_vector(11 downto 0) := x"3c2";
532 
  constant csr_pmpaddr19_c      : std_ulogic_vector(11 downto 0) := x"3c3";
533 
  constant csr_pmpaddr20_c      : std_ulogic_vector(11 downto 0) := x"3c4";
534 
  constant csr_pmpaddr21_c      : std_ulogic_vector(11 downto 0) := x"3c5";
535 
  constant csr_pmpaddr22_c      : std_ulogic_vector(11 downto 0) := x"3c6";
536 
  constant csr_pmpaddr23_c      : std_ulogic_vector(11 downto 0) := x"3c7";
537 
  constant csr_pmpaddr24_c      : std_ulogic_vector(11 downto 0) := x"3c8";
538 
  constant csr_pmpaddr25_c      : std_ulogic_vector(11 downto 0) := x"3c9";
539 
  constant csr_pmpaddr26_c      : std_ulogic_vector(11 downto 0) := x"3ca";
540 
  constant csr_pmpaddr27_c      : std_ulogic_vector(11 downto 0) := x"3cb";
541 
  constant csr_pmpaddr28_c      : std_ulogic_vector(11 downto 0) := x"3cc";
542 
  constant csr_pmpaddr29_c      : std_ulogic_vector(11 downto 0) := x"3cd";
543 
  constant csr_pmpaddr30_c      : std_ulogic_vector(11 downto 0) := x"3ce";
544 
  constant csr_pmpaddr31_c      : std_ulogic_vector(11 downto 0) := x"3cf";
545 
  constant csr_pmpaddr32_c      : std_ulogic_vector(11 downto 0) := x"3d0";
546 
  constant csr_pmpaddr33_c      : std_ulogic_vector(11 downto 0) := x"3d1";
547 
  constant csr_pmpaddr34_c      : std_ulogic_vector(11 downto 0) := x"3d2";
548 
  constant csr_pmpaddr35_c      : std_ulogic_vector(11 downto 0) := x"3d3";
549 
  constant csr_pmpaddr36_c      : std_ulogic_vector(11 downto 0) := x"3d4";
550 
  constant csr_pmpaddr37_c      : std_ulogic_vector(11 downto 0) := x"3d5";
551 
  constant csr_pmpaddr38_c      : std_ulogic_vector(11 downto 0) := x"3d6";
552 
  constant csr_pmpaddr39_c      : std_ulogic_vector(11 downto 0) := x"3d7";
553 
  constant csr_pmpaddr40_c      : std_ulogic_vector(11 downto 0) := x"3d8";
554 
  constant csr_pmpaddr41_c      : std_ulogic_vector(11 downto 0) := x"3d9";
555 
  constant csr_pmpaddr42_c      : std_ulogic_vector(11 downto 0) := x"3da";
556 
  constant csr_pmpaddr43_c      : std_ulogic_vector(11 downto 0) := x"3db";
557 
  constant csr_pmpaddr44_c      : std_ulogic_vector(11 downto 0) := x"3dc";
558 
  constant csr_pmpaddr45_c      : std_ulogic_vector(11 downto 0) := x"3dd";
559 
  constant csr_pmpaddr46_c      : std_ulogic_vector(11 downto 0) := x"3de";
560 
  constant csr_pmpaddr47_c      : std_ulogic_vector(11 downto 0) := x"3df";
561 
  constant csr_pmpaddr48_c      : std_ulogic_vector(11 downto 0) := x"3e0";
562 
  constant csr_pmpaddr49_c      : std_ulogic_vector(11 downto 0) := x"3e1";
563 
  constant csr_pmpaddr50_c      : std_ulogic_vector(11 downto 0) := x"3e2";
564 
  constant csr_pmpaddr51_c      : std_ulogic_vector(11 downto 0) := x"3e3";
565 
  constant csr_pmpaddr52_c      : std_ulogic_vector(11 downto 0) := x"3e4";
566 
  constant csr_pmpaddr53_c      : std_ulogic_vector(11 downto 0) := x"3e5";
567 
  constant csr_pmpaddr54_c      : std_ulogic_vector(11 downto 0) := x"3e6";
568 
  constant csr_pmpaddr55_c      : std_ulogic_vector(11 downto 0) := x"3e7";
569 
  constant csr_pmpaddr56_c      : std_ulogic_vector(11 downto 0) := x"3e8";
570 
  constant csr_pmpaddr57_c      : std_ulogic_vector(11 downto 0) := x"3e9";
571 
  constant csr_pmpaddr58_c      : std_ulogic_vector(11 downto 0) := x"3ea";
572 
  constant csr_pmpaddr59_c      : std_ulogic_vector(11 downto 0) := x"3eb";
573 
  constant csr_pmpaddr60_c      : std_ulogic_vector(11 downto 0) := x"3ec";
574 
  constant csr_pmpaddr61_c      : std_ulogic_vector(11 downto 0) := x"3ed";
575 
  constant csr_pmpaddr62_c      : std_ulogic_vector(11 downto 0) := x"3ee";
576 
  constant csr_pmpaddr63_c      : std_ulogic_vector(11 downto 0) := x"3ef";
577 29 zero_gravi 
  --
578 42 zero_gravi 
  constant csr_mcycle_c         : std_ulogic_vector(11 downto 0) := x"b00";
579 
  constant csr_minstret_c       : std_ulogic_vector(11 downto 0) := x"b02";
580 
  --
581 
  constant csr_mhpmcounter3_c   : std_ulogic_vector(11 downto 0) := x"b03";
582 
  constant csr_mhpmcounter4_c   : std_ulogic_vector(11 downto 0) := x"b04";
583 
  constant csr_mhpmcounter5_c   : std_ulogic_vector(11 downto 0) := x"b05";
584 
  constant csr_mhpmcounter6_c   : std_ulogic_vector(11 downto 0) := x"b06";
585 
  constant csr_mhpmcounter7_c   : std_ulogic_vector(11 downto 0) := x"b07";
586 
  constant csr_mhpmcounter8_c   : std_ulogic_vector(11 downto 0) := x"b08";
587 
  constant csr_mhpmcounter9_c   : std_ulogic_vector(11 downto 0) := x"b09";
588 
  constant csr_mhpmcounter10_c  : std_ulogic_vector(11 downto 0) := x"b0a";
589 
  constant csr_mhpmcounter11_c  : std_ulogic_vector(11 downto 0) := x"b0b";
590 
  constant csr_mhpmcounter12_c  : std_ulogic_vector(11 downto 0) := x"b0c";
591 
  constant csr_mhpmcounter13_c  : std_ulogic_vector(11 downto 0) := x"b0d";
592 
  constant csr_mhpmcounter14_c  : std_ulogic_vector(11 downto 0) := x"b0e";
593 
  constant csr_mhpmcounter15_c  : std_ulogic_vector(11 downto 0) := x"b0f";
594 
  constant csr_mhpmcounter16_c  : std_ulogic_vector(11 downto 0) := x"b10";
595 
  constant csr_mhpmcounter17_c  : std_ulogic_vector(11 downto 0) := x"b11";
596 
  constant csr_mhpmcounter18_c  : std_ulogic_vector(11 downto 0) := x"b12";
597 
  constant csr_mhpmcounter19_c  : std_ulogic_vector(11 downto 0) := x"b13";
598 
  constant csr_mhpmcounter20_c  : std_ulogic_vector(11 downto 0) := x"b14";
599 
  constant csr_mhpmcounter21_c  : std_ulogic_vector(11 downto 0) := x"b15";
600 
  constant csr_mhpmcounter22_c  : std_ulogic_vector(11 downto 0) := x"b16";
601 
  constant csr_mhpmcounter23_c  : std_ulogic_vector(11 downto 0) := x"b17";
602 
  constant csr_mhpmcounter24_c  : std_ulogic_vector(11 downto 0) := x"b18";
603 
  constant csr_mhpmcounter25_c  : std_ulogic_vector(11 downto 0) := x"b19";
604 
  constant csr_mhpmcounter26_c  : std_ulogic_vector(11 downto 0) := x"b1a";
605 
  constant csr_mhpmcounter27_c  : std_ulogic_vector(11 downto 0) := x"b1b";
606 
  constant csr_mhpmcounter28_c  : std_ulogic_vector(11 downto 0) := x"b1c";
607 
  constant csr_mhpmcounter29_c  : std_ulogic_vector(11 downto 0) := x"b1d";
608 
  constant csr_mhpmcounter30_c  : std_ulogic_vector(11 downto 0) := x"b1e";
609 
  constant csr_mhpmcounter31_c  : std_ulogic_vector(11 downto 0) := x"b1f";
610 
  --
611 
  constant csr_mcycleh_c        : std_ulogic_vector(11 downto 0) := x"b80";
612 
  constant csr_minstreth_c      : std_ulogic_vector(11 downto 0) := x"b82";
613 
  --
614 
  constant csr_mhpmcounter3h_c  : std_ulogic_vector(11 downto 0) := x"b83";
615 
  constant csr_mhpmcounter4h_c  : std_ulogic_vector(11 downto 0) := x"b84";
616 
  constant csr_mhpmcounter5h_c  : std_ulogic_vector(11 downto 0) := x"b85";
617 
  constant csr_mhpmcounter6h_c  : std_ulogic_vector(11 downto 0) := x"b86";
618 
  constant csr_mhpmcounter7h_c  : std_ulogic_vector(11 downto 0) := x"b87";
619 
  constant csr_mhpmcounter8h_c  : std_ulogic_vector(11 downto 0) := x"b88";
620 
  constant csr_mhpmcounter9h_c  : std_ulogic_vector(11 downto 0) := x"b89";
621 
  constant csr_mhpmcounter10h_c : std_ulogic_vector(11 downto 0) := x"b8a";
622 
  constant csr_mhpmcounter11h_c : std_ulogic_vector(11 downto 0) := x"b8b";
623 
  constant csr_mhpmcounter12h_c : std_ulogic_vector(11 downto 0) := x"b8c";
624 
  constant csr_mhpmcounter13h_c : std_ulogic_vector(11 downto 0) := x"b8d";
625 
  constant csr_mhpmcounter14h_c : std_ulogic_vector(11 downto 0) := x"b8e";
626 
  constant csr_mhpmcounter15h_c : std_ulogic_vector(11 downto 0) := x"b8f";
627 
  constant csr_mhpmcounter16h_c : std_ulogic_vector(11 downto 0) := x"b90";
628 
  constant csr_mhpmcounter17h_c : std_ulogic_vector(11 downto 0) := x"b91";
629 
  constant csr_mhpmcounter18h_c : std_ulogic_vector(11 downto 0) := x"b92";
630 
  constant csr_mhpmcounter19h_c : std_ulogic_vector(11 downto 0) := x"b93";
631 
  constant csr_mhpmcounter20h_c : std_ulogic_vector(11 downto 0) := x"b94";
632 
  constant csr_mhpmcounter21h_c : std_ulogic_vector(11 downto 0) := x"b95";
633 
  constant csr_mhpmcounter22h_c : std_ulogic_vector(11 downto 0) := x"b96";
634 
  constant csr_mhpmcounter23h_c : std_ulogic_vector(11 downto 0) := x"b97";
635 
  constant csr_mhpmcounter24h_c : std_ulogic_vector(11 downto 0) := x"b98";
636 
  constant csr_mhpmcounter25h_c : std_ulogic_vector(11 downto 0) := x"b99";
637 
  constant csr_mhpmcounter26h_c : std_ulogic_vector(11 downto 0) := x"b9a";
638 
  constant csr_mhpmcounter27h_c : std_ulogic_vector(11 downto 0) := x"b9b";
639 
  constant csr_mhpmcounter28h_c : std_ulogic_vector(11 downto 0) := x"b9c";
640 
  constant csr_mhpmcounter29h_c : std_ulogic_vector(11 downto 0) := x"b9d";
641 
  constant csr_mhpmcounter30h_c : std_ulogic_vector(11 downto 0) := x"b9e";
642 
  constant csr_mhpmcounter31h_c : std_ulogic_vector(11 downto 0) := x"b9f";
643 
 
644 41 zero_gravi 
  -- read-only CSRs --
645 42 zero_gravi 
  constant csr_cycle_c          : std_ulogic_vector(11 downto 0) := x"c00";
646 
  constant csr_time_c           : std_ulogic_vector(11 downto 0) := x"c01";
647 
  constant csr_instret_c        : std_ulogic_vector(11 downto 0) := x"c02";
648 29 zero_gravi 
  --
649 42 zero_gravi 
  constant csr_hpmcounter3_c    : std_ulogic_vector(11 downto 0) := x"c03";
650 
  constant csr_hpmcounter4_c    : std_ulogic_vector(11 downto 0) := x"c04";
651 
  constant csr_hpmcounter5_c    : std_ulogic_vector(11 downto 0) := x"c05";
652 
  constant csr_hpmcounter6_c    : std_ulogic_vector(11 downto 0) := x"c06";
653 
  constant csr_hpmcounter7_c    : std_ulogic_vector(11 downto 0) := x"c07";
654 
  constant csr_hpmcounter8_c    : std_ulogic_vector(11 downto 0) := x"c08";
655 
  constant csr_hpmcounter9_c    : std_ulogic_vector(11 downto 0) := x"c09";
656 
  constant csr_hpmcounter10_c   : std_ulogic_vector(11 downto 0) := x"c0a";
657 
  constant csr_hpmcounter11_c   : std_ulogic_vector(11 downto 0) := x"c0b";
658 
  constant csr_hpmcounter12_c   : std_ulogic_vector(11 downto 0) := x"c0c";
659 
  constant csr_hpmcounter13_c   : std_ulogic_vector(11 downto 0) := x"c0d";
660 
  constant csr_hpmcounter14_c   : std_ulogic_vector(11 downto 0) := x"c0e";
661 
  constant csr_hpmcounter15_c   : std_ulogic_vector(11 downto 0) := x"c0f";
662 
  constant csr_hpmcounter16_c   : std_ulogic_vector(11 downto 0) := x"c10";
663 
  constant csr_hpmcounter17_c   : std_ulogic_vector(11 downto 0) := x"c11";
664 
  constant csr_hpmcounter18_c   : std_ulogic_vector(11 downto 0) := x"c12";
665 
  constant csr_hpmcounter19_c   : std_ulogic_vector(11 downto 0) := x"c13";
666 
  constant csr_hpmcounter20_c   : std_ulogic_vector(11 downto 0) := x"c14";
667 
  constant csr_hpmcounter21_c   : std_ulogic_vector(11 downto 0) := x"c15";
668 
  constant csr_hpmcounter22_c   : std_ulogic_vector(11 downto 0) := x"c16";
669 
  constant csr_hpmcounter23_c   : std_ulogic_vector(11 downto 0) := x"c17";
670 
  constant csr_hpmcounter24_c   : std_ulogic_vector(11 downto 0) := x"c18";
671 
  constant csr_hpmcounter25_c   : std_ulogic_vector(11 downto 0) := x"c19";
672 
  constant csr_hpmcounter26_c   : std_ulogic_vector(11 downto 0) := x"c1a";
673 
  constant csr_hpmcounter27_c   : std_ulogic_vector(11 downto 0) := x"c1b";
674 
  constant csr_hpmcounter28_c   : std_ulogic_vector(11 downto 0) := x"c1c";
675 
  constant csr_hpmcounter29_c   : std_ulogic_vector(11 downto 0) := x"c1d";
676 
  constant csr_hpmcounter30_c   : std_ulogic_vector(11 downto 0) := x"c1e";
677 
  constant csr_hpmcounter31_c   : std_ulogic_vector(11 downto 0) := x"c1f";
678 29 zero_gravi 
  --
679 42 zero_gravi 
  constant csr_cycleh_c         : std_ulogic_vector(11 downto 0) := x"c80";
680 
  constant csr_timeh_c          : std_ulogic_vector(11 downto 0) := x"c81";
681 
  constant csr_instreth_c       : std_ulogic_vector(11 downto 0) := x"c82";
682 29 zero_gravi 
  --
683 42 zero_gravi 
  constant csr_hpmcounter3h_c   : std_ulogic_vector(11 downto 0) := x"c83";
684 
  constant csr_hpmcounter4h_c   : std_ulogic_vector(11 downto 0) := x"c84";
685 
  constant csr_hpmcounter5h_c   : std_ulogic_vector(11 downto 0) := x"c85";
686 
  constant csr_hpmcounter6h_c   : std_ulogic_vector(11 downto 0) := x"c86";
687 
  constant csr_hpmcounter7h_c   : std_ulogic_vector(11 downto 0) := x"c87";
688 
  constant csr_hpmcounter8h_c   : std_ulogic_vector(11 downto 0) := x"c88";
689 
  constant csr_hpmcounter9h_c   : std_ulogic_vector(11 downto 0) := x"c89";
690 
  constant csr_hpmcounter10h_c  : std_ulogic_vector(11 downto 0) := x"c8a";
691 
  constant csr_hpmcounter11h_c  : std_ulogic_vector(11 downto 0) := x"c8b";
692 
  constant csr_hpmcounter12h_c  : std_ulogic_vector(11 downto 0) := x"c8c";
693 
  constant csr_hpmcounter13h_c  : std_ulogic_vector(11 downto 0) := x"c8d";
694 
  constant csr_hpmcounter14h_c  : std_ulogic_vector(11 downto 0) := x"c8e";
695 
  constant csr_hpmcounter15h_c  : std_ulogic_vector(11 downto 0) := x"c8f";
696 
  constant csr_hpmcounter16h_c  : std_ulogic_vector(11 downto 0) := x"c90";
697 
  constant csr_hpmcounter17h_c  : std_ulogic_vector(11 downto 0) := x"c91";
698 
  constant csr_hpmcounter18h_c  : std_ulogic_vector(11 downto 0) := x"c92";
699 
  constant csr_hpmcounter19h_c  : std_ulogic_vector(11 downto 0) := x"c93";
700 
  constant csr_hpmcounter20h_c  : std_ulogic_vector(11 downto 0) := x"c94";
701 
  constant csr_hpmcounter21h_c  : std_ulogic_vector(11 downto 0) := x"c95";
702 
  constant csr_hpmcounter22h_c  : std_ulogic_vector(11 downto 0) := x"c96";
703 
  constant csr_hpmcounter23h_c  : std_ulogic_vector(11 downto 0) := x"c97";
704 
  constant csr_hpmcounter24h_c  : std_ulogic_vector(11 downto 0) := x"c98";
705 
  constant csr_hpmcounter25h_c  : std_ulogic_vector(11 downto 0) := x"c99";
706 
  constant csr_hpmcounter26h_c  : std_ulogic_vector(11 downto 0) := x"c9a";
707 
  constant csr_hpmcounter27h_c  : std_ulogic_vector(11 downto 0) := x"c9b";
708 
  constant csr_hpmcounter28h_c  : std_ulogic_vector(11 downto 0) := x"c9c";
709 
  constant csr_hpmcounter29h_c  : std_ulogic_vector(11 downto 0) := x"c9d";
710 
  constant csr_hpmcounter30h_c  : std_ulogic_vector(11 downto 0) := x"c9e";
711 
  constant csr_hpmcounter31h_c  : std_ulogic_vector(11 downto 0) := x"c9f";
712 
  --
713 
  constant csr_mvendorid_c      : std_ulogic_vector(11 downto 0) := x"f11";
714 
  constant csr_marchid_c        : std_ulogic_vector(11 downto 0) := x"f12";
715 
  constant csr_mimpid_c         : std_ulogic_vector(11 downto 0) := x"f13";
716 
  constant csr_mhartid_c        : std_ulogic_vector(11 downto 0) := x"f14";
717 29 zero_gravi 
 
718 42 zero_gravi 
  -- custom read-only CSRs --
719 
  constant csr_mzext_c          : std_ulogic_vector(11 downto 0) := x"fc0";
720 
 
721 44 zero_gravi 
  -- Co-Processor IDs -----------------------------------------------------------------------
722 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
723 49 zero_gravi 
  constant cp_sel_muldiv_c   : std_ulogic_vector(2 downto 0) := "000"; -- multiplication/division operations ('M' extension)
724 
  constant cp_sel_atomic_c   : std_ulogic_vector(2 downto 0) := "001"; -- atomic operations; success/failure evaluation ('A' extension)
725 
  constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- bit manipulation ('B' extension)
726 
  constant cp_sel_csr_rd_c   : std_ulogic_vector(2 downto 0) := "011"; -- CSR read access ('Zicsr' extension)
727 53 zero_gravi 
  constant cp_sel_fpu_c      : std_ulogic_vector(2 downto 0) := "100"; -- loating-point unit ('Zfinx' extension)
728 
--constant cp_sel_crypto_c   : std_ulogic_vector(2 downto 0) := "101"; -- crypto operations ('K' extension)
729 52 zero_gravi 
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "110"; -- reserved
730 
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "111"; -- reserved
731 2 zero_gravi 
 
732 
  -- ALU Function Codes ---------------------------------------------------------------------
733 
  -- -------------------------------------------------------------------------------------------
734 39 zero_gravi 
  -- arithmetic core --
735 
  constant alu_arith_cmd_addsub_c : std_ulogic := '0'; -- r.arith <= A +/- B
736 
  constant alu_arith_cmd_slt_c    : std_ulogic := '1'; -- r.arith <= A < B
737 
  -- logic core --
738 
  constant alu_logic_cmd_movb_c   : std_ulogic_vector(1 downto 0) := "00"; -- r.logic <= B
739 
  constant alu_logic_cmd_xor_c    : std_ulogic_vector(1 downto 0) := "01"; -- r.logic <= A xor B
740 
  constant alu_logic_cmd_or_c     : std_ulogic_vector(1 downto 0) := "10"; -- r.logic <= A or B
741 
  constant alu_logic_cmd_and_c    : std_ulogic_vector(1 downto 0) := "11"; -- r.logic <= A and B
742 
  -- function select (actual alu result) --
743 
  constant alu_func_cmd_arith_c   : std_ulogic_vector(1 downto 0) := "00"; -- r <= r.arith
744 
  constant alu_func_cmd_logic_c   : std_ulogic_vector(1 downto 0) := "01"; -- r <= r.logic
745 
  constant alu_func_cmd_shift_c   : std_ulogic_vector(1 downto 0) := "10"; -- r <= A <</>> B (iterative)
746 
  constant alu_func_cmd_copro_c   : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (iterative)
747 2 zero_gravi 
 
748 12 zero_gravi 
  -- Trap ID Codes --------------------------------------------------------------------------
749 
  -- -------------------------------------------------------------------------------------------
750 48 zero_gravi 
  -- RISC-V compliant sync. exceptions --
751 
  constant trap_ima_c    : std_ulogic_vector(5 downto 0) := "0" & "00000"; -- 0.0:  instruction misaligned
752 
  constant trap_iba_c    : std_ulogic_vector(5 downto 0) := "0" & "00001"; -- 0.1:  instruction access fault
753 
  constant trap_iil_c    : std_ulogic_vector(5 downto 0) := "0" & "00010"; -- 0.2:  illegal instruction
754 
  constant trap_brk_c    : std_ulogic_vector(5 downto 0) := "0" & "00011"; -- 0.3:  breakpoint
755 
  constant trap_lma_c    : std_ulogic_vector(5 downto 0) := "0" & "00100"; -- 0.4:  load address misaligned
756 
  constant trap_lbe_c    : std_ulogic_vector(5 downto 0) := "0" & "00101"; -- 0.5:  load access fault
757 
  constant trap_sma_c    : std_ulogic_vector(5 downto 0) := "0" & "00110"; -- 0.6:  store address misaligned
758 
  constant trap_sbe_c    : std_ulogic_vector(5 downto 0) := "0" & "00111"; -- 0.7:  store access fault
759 
  constant trap_uenv_c   : std_ulogic_vector(5 downto 0) := "0" & "01000"; -- 0.8:  environment call from u-mode
760 
  constant trap_menv_c   : std_ulogic_vector(5 downto 0) := "0" & "01011"; -- 0.11: environment call from m-mode
761 
  -- RISC-V compliant interrupts (async. exceptions) --
762 
  constant trap_msi_c    : std_ulogic_vector(5 downto 0) := "1" & "00011"; -- 1.3:  machine software interrupt
763 
  constant trap_mti_c    : std_ulogic_vector(5 downto 0) := "1" & "00111"; -- 1.7:  machine timer interrupt
764 
  constant trap_mei_c    : std_ulogic_vector(5 downto 0) := "1" & "01011"; -- 1.11: machine external interrupt
765 
  -- NEORV32-specific (custom) interrupts (async. exceptions) --
766 
  constant trap_reset_c  : std_ulogic_vector(5 downto 0) := "1" & "00000"; -- 1.0:  hardware reset
767 
  constant trap_firq0_c  : std_ulogic_vector(5 downto 0) := "1" & "10000"; -- 1.16: fast interrupt 0
768 
  constant trap_firq1_c  : std_ulogic_vector(5 downto 0) := "1" & "10001"; -- 1.17: fast interrupt 1
769 
  constant trap_firq2_c  : std_ulogic_vector(5 downto 0) := "1" & "10010"; -- 1.18: fast interrupt 2
770 
  constant trap_firq3_c  : std_ulogic_vector(5 downto 0) := "1" & "10011"; -- 1.19: fast interrupt 3
771 
  constant trap_firq4_c  : std_ulogic_vector(5 downto 0) := "1" & "10100"; -- 1.20: fast interrupt 4
772 
  constant trap_firq5_c  : std_ulogic_vector(5 downto 0) := "1" & "10101"; -- 1.21: fast interrupt 5
773 
  constant trap_firq6_c  : std_ulogic_vector(5 downto 0) := "1" & "10110"; -- 1.22: fast interrupt 6
774 
  constant trap_firq7_c  : std_ulogic_vector(5 downto 0) := "1" & "10111"; -- 1.23: fast interrupt 7
775 
  constant trap_firq8_c  : std_ulogic_vector(5 downto 0) := "1" & "11000"; -- 1.24: fast interrupt 8
776 
  constant trap_firq9_c  : std_ulogic_vector(5 downto 0) := "1" & "11001"; -- 1.25: fast interrupt 9
777 
  constant trap_firq10_c : std_ulogic_vector(5 downto 0) := "1" & "11010"; -- 1.26: fast interrupt 10
778 
  constant trap_firq11_c : std_ulogic_vector(5 downto 0) := "1" & "11011"; -- 1.27: fast interrupt 11
779 
  constant trap_firq12_c : std_ulogic_vector(5 downto 0) := "1" & "11100"; -- 1.28: fast interrupt 12
780 
  constant trap_firq13_c : std_ulogic_vector(5 downto 0) := "1" & "11101"; -- 1.29: fast interrupt 13
781 
  constant trap_firq14_c : std_ulogic_vector(5 downto 0) := "1" & "11110"; -- 1.30: fast interrupt 14
782 
  constant trap_firq15_c : std_ulogic_vector(5 downto 0) := "1" & "11111"; -- 1.31: fast interrupt 15
783 12 zero_gravi 
 
784 2 zero_gravi 
  -- CPU Control Exception System -----------------------------------------------------------
785 
  -- -------------------------------------------------------------------------------------------
786 
  -- exception source bits --
787 47 zero_gravi 
  constant exception_iaccess_c   : natural :=  0; -- instrution access fault
788 
  constant exception_iillegal_c  : natural :=  1; -- illegal instrution
789 
  constant exception_ialign_c    : natural :=  2; -- instrution address misaligned
790 
  constant exception_m_envcall_c : natural :=  3; -- ENV call from m-mode
791 
  constant exception_u_envcall_c : natural :=  4; -- ENV call from u-mode
792 
  constant exception_break_c     : natural :=  5; -- breakpoint
793 
  constant exception_salign_c    : natural :=  6; -- store address misaligned
794 
  constant exception_lalign_c    : natural :=  7; -- load address misaligned
795 
  constant exception_saccess_c   : natural :=  8; -- store access fault
796 
  constant exception_laccess_c   : natural :=  9; -- load access fault
797 14 zero_gravi 
  --
798 40 zero_gravi 
  constant exception_width_c     : natural := 10; -- length of this list in bits
799 2 zero_gravi 
  -- interrupt source bits --
800 47 zero_gravi 
  constant interrupt_msw_irq_c   : natural :=  0; -- machine software interrupt
801 
  constant interrupt_mtime_irq_c : natural :=  1; -- machine timer interrupt
802 
  constant interrupt_mext_irq_c  : natural :=  2; -- machine external interrupt
803 
  constant interrupt_firq_0_c    : natural :=  3; -- fast interrupt channel 0
804 
  constant interrupt_firq_1_c    : natural :=  4; -- fast interrupt channel 1
805 
  constant interrupt_firq_2_c    : natural :=  5; -- fast interrupt channel 2
806 
  constant interrupt_firq_3_c    : natural :=  6; -- fast interrupt channel 3
807 
  constant interrupt_firq_4_c    : natural :=  7; -- fast interrupt channel 4
808 
  constant interrupt_firq_5_c    : natural :=  8; -- fast interrupt channel 5
809 
  constant interrupt_firq_6_c    : natural :=  9; -- fast interrupt channel 6
810 
  constant interrupt_firq_7_c    : natural := 10; -- fast interrupt channel 7
811 48 zero_gravi 
  constant interrupt_firq_8_c    : natural := 11; -- fast interrupt channel 8
812 
  constant interrupt_firq_9_c    : natural := 12; -- fast interrupt channel 9
813 
  constant interrupt_firq_10_c   : natural := 13; -- fast interrupt channel 10
814 
  constant interrupt_firq_11_c   : natural := 14; -- fast interrupt channel 11
815 
  constant interrupt_firq_12_c   : natural := 15; -- fast interrupt channel 12
816 
  constant interrupt_firq_13_c   : natural := 16; -- fast interrupt channel 13
817 
  constant interrupt_firq_14_c   : natural := 17; -- fast interrupt channel 14
818 
  constant interrupt_firq_15_c   : natural := 18; -- fast interrupt channel 15
819 14 zero_gravi 
  --
820 48 zero_gravi 
  constant interrupt_width_c     : natural := 19; -- length of this list in bits
821 2 zero_gravi 
 
822 15 zero_gravi 
  -- CPU Privilege Modes --------------------------------------------------------------------
823 
  -- -------------------------------------------------------------------------------------------
824 29 zero_gravi 
  constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
825 
  constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
826 15 zero_gravi 
 
827 42 zero_gravi 
  -- HPM Event System -----------------------------------------------------------------------
828 
  -- -------------------------------------------------------------------------------------------
829 
  constant hpmcnt_event_cy_c      : natural := 0;  -- Active cycle
830 
  constant hpmcnt_event_never_c   : natural := 1;
831 
  constant hpmcnt_event_ir_c      : natural := 2;  -- Retired instruction
832 
  constant hpmcnt_event_cir_c     : natural := 3;  -- Retired compressed instruction
833 
  constant hpmcnt_event_wait_if_c : natural := 4;  -- Instruction fetch memory wait cycle
834 
  constant hpmcnt_event_wait_ii_c : natural := 5;  -- Instruction issue wait cycle
835 45 zero_gravi 
  constant hpmcnt_event_wait_mc_c : natural := 6;  -- Multi-cycle ALU-operation wait cycle
836 
  constant hpmcnt_event_load_c    : natural := 7;  -- Load operation
837 
  constant hpmcnt_event_store_c   : natural := 8;  -- Store operation
838 
  constant hpmcnt_event_wait_ls_c : natural := 9;  -- Load/store memory wait cycle
839 
  constant hpmcnt_event_jump_c    : natural := 10; -- Unconditional jump
840 
  constant hpmcnt_event_branch_c  : natural := 11; -- Conditional branch (taken or not taken)
841 
  constant hpmcnt_event_tbranch_c : natural := 12; -- Conditional taken branch
842 
  constant hpmcnt_event_trap_c    : natural := 13; -- Entered trap
843 
  constant hpmcnt_event_illegal_c : natural := 14; -- Illegal instruction exception
844 42 zero_gravi 
  --
845 45 zero_gravi 
  constant hpmcnt_event_size_c    : natural := 15; -- length of this list
846 42 zero_gravi 
 
847 39 zero_gravi 
  -- Clock Generator ------------------------------------------------------------------------
848 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
849 
  constant clk_div2_c    : natural := 0;
850 
  constant clk_div4_c    : natural := 1;
851 
  constant clk_div8_c    : natural := 2;
852 
  constant clk_div64_c   : natural := 3;
853 
  constant clk_div128_c  : natural := 4;
854 
  constant clk_div1024_c : natural := 5;
855 
  constant clk_div2048_c : natural := 6;
856 
  constant clk_div4096_c : natural := 7;
857 
 
858 
  -- Component: NEORV32 Processor Top Entity ------------------------------------------------
859 
  -- -------------------------------------------------------------------------------------------
860 
  component neorv32_top
861 
    generic (
862 
      -- General --
863 12 zero_gravi 
      CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz
864 44 zero_gravi 
      BOOTLOADER_EN                : boolean := true;   -- implement processor-internal bootloader?
865 12 zero_gravi 
      USER_CODE                    : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
866 49 zero_gravi 
      HW_THREAD_ID                 : natural := 0;      -- hardware thread id (32-bit)
867 2 zero_gravi 
      -- RISC-V CPU Extensions --
868 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false;  -- implement atomic extension?
869 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false;  -- implement bit manipulation extensions?
870 18 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?
871 8 zero_gravi 
      CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
872 18 zero_gravi 
      CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement muld/div extension?
873 
      CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?
874 55 zero_gravi 
      CPU_EXTENSION_RISCV_Zfinx    : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
875 8 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?
876 39 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false;  -- implement instruction stream sync.?
877 19 zero_gravi 
      -- Extension Options --
878 34 zero_gravi 
      FAST_MUL_EN                  : boolean := false;  -- use DSPs for M extension's multiplier
879 
      FAST_SHIFT_EN                : boolean := false;  -- use barrel shifter for shift operations
880 15 zero_gravi 
      -- Physical Memory Protection (PMP) --
881 42 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0;      -- number of regions (0..64)
882 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
883 
      -- Hardware Performance Monitors (HPM) --
884 47 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0;      -- number of implemented HPM counters (0..29)
885 23 zero_gravi 
      -- Internal Instruction memory --
886 44 zero_gravi 
      MEM_INT_IMEM_EN              : boolean := true;   -- implement processor-internal instruction memory
887 8 zero_gravi 
      MEM_INT_IMEM_SIZE            : natural := 16*1024; -- size of processor-internal instruction memory in bytes
888 34 zero_gravi 
      MEM_INT_IMEM_ROM             : boolean := false;  -- implement processor-internal instruction memory as ROM
889 23 zero_gravi 
      -- Internal Data memory --
890 44 zero_gravi 
      MEM_INT_DMEM_EN              : boolean := true;   -- implement processor-internal data memory
891 8 zero_gravi 
      MEM_INT_DMEM_SIZE            : natural := 8*1024; -- size of processor-internal data memory in bytes
892 41 zero_gravi 
      -- Internal Cache memory --
893 44 zero_gravi 
      ICACHE_EN                    : boolean := false;  -- implement instruction cache
894 41 zero_gravi 
      ICACHE_NUM_BLOCKS            : natural := 4;      -- i-cache: number of blocks (min 1), has to be a power of 2
895 
      ICACHE_BLOCK_SIZE            : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
896 45 zero_gravi 
      ICACHE_ASSOCIATIVITY         : natural := 1;      -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
897 23 zero_gravi 
      -- External memory interface --
898 44 zero_gravi 
      MEM_EXT_EN                   : boolean := false;  -- implement external memory bus interface?
899 2 zero_gravi 
      -- Processor peripherals --
900 44 zero_gravi 
      IO_GPIO_EN                   : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
901 
      IO_MTIME_EN                  : boolean := true;   -- implement machine system timer (MTIME)?
902 50 zero_gravi 
      IO_UART0_EN                  : boolean := true;   -- implement primary universal asynchronous receiver/transmitter (UART0)?
903 
      IO_UART1_EN                  : boolean := true;   -- implement secondary universal asynchronous receiver/transmitter (UART1)?
904 44 zero_gravi 
      IO_SPI_EN                    : boolean := true;   -- implement serial peripheral interface (SPI)?
905 
      IO_TWI_EN                    : boolean := true;   -- implement two-wire interface (TWI)?
906 
      IO_PWM_EN                    : boolean := true;   -- implement pulse-width modulation unit (PWM)?
907 
      IO_WDT_EN                    : boolean := true;   -- implement watch dog timer (WDT)?
908 
      IO_TRNG_EN                   : boolean := false;  -- implement true random number generator (TRNG)?
909 47 zero_gravi 
      IO_CFS_EN                    : boolean := false;  -- implement custom functions subsystem (CFS)?
910 52 zero_gravi 
      IO_CFS_CONFIG                : std_ulogic_vector(31 downto 0); -- custom CFS configuration generic
911 
      IO_CFS_IN_SIZE               : positive := 32;    -- size of CFS input conduit in bits
912 
      IO_CFS_OUT_SIZE              : positive := 32;    -- size of CFS output conduit in bits
913 
      IO_NCO_EN                    : boolean := true;   -- implement numerically-controlled oscillator (NCO)?
914 
      IO_NEOLED_EN                 : boolean := true    -- implement NeoPixel-compatible smart LED interface (NEOLED)?
915 2 zero_gravi 
    );
916 
    port (
917 
      -- Global control --
918 34 zero_gravi 
      clk_i       : in  std_ulogic := '0'; -- global clock, rising edge
919 
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
920 49 zero_gravi 
      -- Wishbone bus interface (available if MEM_EXT_EN = true) --
921 53 zero_gravi 
      wb_tag_o    : out std_ulogic_vector(03 downto 0); -- request tag
922 34 zero_gravi 
      wb_adr_o    : out std_ulogic_vector(31 downto 0); -- address
923 
      wb_dat_i    : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
924 
      wb_dat_o    : out std_ulogic_vector(31 downto 0); -- write data
925 
      wb_we_o     : out std_ulogic; -- read/write
926 
      wb_sel_o    : out std_ulogic_vector(03 downto 0); -- byte enable
927 
      wb_stb_o    : out std_ulogic; -- strobe
928 
      wb_cyc_o    : out std_ulogic; -- valid cycle
929 53 zero_gravi 
      wb_tag_i    : in  std_ulogic; -- response tag
930 34 zero_gravi 
      wb_ack_i    : in  std_ulogic := '0'; -- transfer acknowledge
931 
      wb_err_i    : in  std_ulogic := '0'; -- transfer error
932 44 zero_gravi 
      -- Advanced memory control signals (available if MEM_EXT_EN = true) --
933 34 zero_gravi 
      fence_o     : out std_ulogic; -- indicates an executed FENCE operation
934 
      fencei_o    : out std_ulogic; -- indicates an executed FENCEI operation
935 49 zero_gravi 
      -- GPIO (available if IO_GPIO_EN = true) --
936 34 zero_gravi 
      gpio_o      : out std_ulogic_vector(31 downto 0); -- parallel output
937 
      gpio_i      : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
938 50 zero_gravi 
      -- primary UART0 (available if IO_UART0_EN = true) --
939 
      uart0_txd_o : out std_ulogic; -- UART0 send data
940 
      uart0_rxd_i : in  std_ulogic := '0'; -- UART0 receive data
941 51 zero_gravi 
      uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
942 
      uart0_cts_i : in  std_ulogic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
943 50 zero_gravi 
      -- secondary UART1 (available if IO_UART1_EN = true) --
944 
      uart1_txd_o : out std_ulogic; -- UART1 send data
945 
      uart1_rxd_i : in  std_ulogic := '0'; -- UART1 receive data
946 51 zero_gravi 
      uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
947 
      uart1_cts_i : in  std_ulogic := '0'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
948 49 zero_gravi 
      -- SPI (available if IO_SPI_EN = true) --
949 34 zero_gravi 
      spi_sck_o   : out std_ulogic; -- SPI serial clock
950 
      spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
951 
      spi_sdi_i   : in  std_ulogic := '0'; -- controller data in, peripheral data out
952 
      spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
953 49 zero_gravi 
      -- TWI (available if IO_TWI_EN = true) --
954 35 zero_gravi 
      twi_sda_io  : inout std_logic; -- twi serial data line
955 
      twi_scl_io  : inout std_logic; -- twi serial clock line
956 49 zero_gravi 
      -- PWM (available if IO_PWM_EN = true) --
957 40 zero_gravi 
      pwm_o       : out std_ulogic_vector(03 downto 0); -- pwm channels
958 47 zero_gravi 
      -- Custom Functions Subsystem IO --
959 52 zero_gravi 
      cfs_in_i    : in  std_ulogic_vector(IO_CFS_IN_SIZE-1  downto 0); -- custom CFS inputs conduit
960 
      cfs_out_o   : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
961 49 zero_gravi 
      -- NCO output (available if IO_NCO_EN = true) --
962 
      nco_o       : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
963 52 zero_gravi 
      -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
964 
      neoled_o    : out std_ulogic; -- async serial data line
965 44 zero_gravi 
      -- system time input from external MTIME (available if IO_MTIME_EN = false) --
966 40 zero_gravi 
      mtime_i     : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
967 2 zero_gravi 
      -- Interrupts --
968 50 zero_gravi 
      soc_firq_i  : in  std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
969 44 zero_gravi 
      mtime_irq_i : in  std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
970 34 zero_gravi 
      msw_irq_i   : in  std_ulogic := '0'; -- machine software interrupt
971 
      mext_irq_i  : in  std_ulogic := '0'  -- machine external interrupt
972 2 zero_gravi 
    );
973 
  end component;
974 
 
975 4 zero_gravi 
  -- Component: CPU Top Entity --------------------------------------------------------------
976 
  -- -------------------------------------------------------------------------------------------
977 
  component neorv32_cpu
978 
    generic (
979 
      -- General --
980 49 zero_gravi 
      HW_THREAD_ID                 : natural := 0;     -- hardware thread id (32-bit)
981 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu boot address
982 41 zero_gravi 
      BUS_TIMEOUT                  : natural := 63;    -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
983 4 zero_gravi 
      -- RISC-V CPU Extensions --
984 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
985 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
986 12 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
987 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
988 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
989 15 zero_gravi 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
990 53 zero_gravi 
      CPU_EXTENSION_RISCV_Zfinx    : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
991 12 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
992 49 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
993 19 zero_gravi 
      -- Extension Options --
994 
      FAST_MUL_EN                  : boolean := false; -- use DSPs for M extension's multiplier
995 34 zero_gravi 
      FAST_SHIFT_EN                : boolean := false; -- use barrel shifter for shift operations
996 15 zero_gravi 
      -- Physical Memory Protection (PMP) --
997 52 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0;     -- number of regions (0..64)
998 42 zero_gravi 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
999 
      -- Hardware Performance Monitors (HPM) --
1000 47 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0      -- number of implemented HPM counters (0..29)
1001 4 zero_gravi 
    );
1002 
    port (
1003 
      -- global control --
1004 14 zero_gravi 
      clk_i          : in  std_ulogic := '0'; -- global clock, rising edge
1005 
      rstn_i         : in  std_ulogic := '0'; -- global reset, low-active, async
1006 47 zero_gravi 
      sleep_o        : out std_ulogic; -- cpu is in sleep mode when set
1007 12 zero_gravi 
      -- instruction bus interface --
1008 
      i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1009 14 zero_gravi 
      i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
1010 12 zero_gravi 
      i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1011 
      i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1012 
      i_bus_we_o     : out std_ulogic; -- write enable
1013 
      i_bus_re_o     : out std_ulogic; -- read enable
1014 53 zero_gravi 
      i_bus_cancel_o : out std_ulogic := '0'; -- cancel current bus transaction
1015 14 zero_gravi 
      i_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
1016 
      i_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
1017 12 zero_gravi 
      i_bus_fence_o  : out std_ulogic; -- executed FENCEI operation
1018 35 zero_gravi 
      i_bus_priv_o   : out std_ulogic_vector(1 downto 0); -- privilege level
1019 12 zero_gravi 
      -- data bus interface --
1020 
      d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1021 14 zero_gravi 
      d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
1022 12 zero_gravi 
      d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1023 
      d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1024 
      d_bus_we_o     : out std_ulogic; -- write enable
1025 
      d_bus_re_o     : out std_ulogic; -- read enable
1026 
      d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
1027 14 zero_gravi 
      d_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
1028 
      d_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
1029 12 zero_gravi 
      d_bus_fence_o  : out std_ulogic; -- executed FENCE operation
1030 35 zero_gravi 
      d_bus_priv_o   : out std_ulogic_vector(1 downto 0); -- privilege level
1031 53 zero_gravi 
      d_bus_excl_o   : out std_ulogic; -- exclusive access
1032 
      d_bus_excl_i   : in  std_ulogic; -- state of exclusiv access (set if success)
1033 11 zero_gravi 
      -- system time input from MTIME --
1034 14 zero_gravi 
      time_i         : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
1035 
      -- interrupts (risc-v compliant) --
1036 
      msw_irq_i      : in  std_ulogic := '0'; -- machine software interrupt
1037 
      mext_irq_i     : in  std_ulogic := '0'; -- machine external interrupt
1038 
      mtime_irq_i    : in  std_ulogic := '0'; -- machine timer interrupt
1039 
      -- fast interrupts (custom) --
1040 48 zero_gravi 
      firq_i         : in  std_ulogic_vector(15 downto 0) := (others => '0');
1041 
      firq_ack_o     : out std_ulogic_vector(15 downto 0)
1042 4 zero_gravi 
    );
1043 
  end component;
1044 
 
1045 2 zero_gravi 
  -- Component: CPU Control -----------------------------------------------------------------
1046 
  -- -------------------------------------------------------------------------------------------
1047 
  component neorv32_cpu_control
1048 
    generic (
1049 
      -- General --
1050 49 zero_gravi 
      HW_THREAD_ID                 : natural := 0;     -- hardware thread id (32-bit)
1051 12 zero_gravi 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
1052 2 zero_gravi 
      -- RISC-V CPU Extensions --
1053 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
1054 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
1055 12 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
1056 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
1057 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
1058 15 zero_gravi 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
1059 53 zero_gravi 
      CPU_EXTENSION_RISCV_Zfinx    : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
1060 12 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
1061 49 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
1062 15 zero_gravi 
      -- Physical memory protection (PMP) --
1063 52 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0;     -- number of regions (0..64)
1064 42 zero_gravi 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
1065 
      -- Hardware Performance Monitors (HPM) --
1066 47 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0      -- number of implemented HPM counters (0..29)
1067 2 zero_gravi 
    );
1068 
    port (
1069 
      -- global control --
1070 
      clk_i         : in  std_ulogic; -- global clock, rising edge
1071 
      rstn_i        : in  std_ulogic; -- global reset, low-active, async
1072 
      ctrl_o        : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1073 
      -- status input --
1074 
      alu_wait_i    : in  std_ulogic; -- wait for ALU
1075 12 zero_gravi 
      bus_i_wait_i  : in  std_ulogic; -- wait for bus
1076 
      bus_d_wait_i  : in  std_ulogic; -- wait for bus
1077 2 zero_gravi 
      -- data input --
1078 
      instr_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- instruction
1079 
      cmp_i         : in  std_ulogic_vector(1 downto 0); -- comparator status
1080 36 zero_gravi 
      alu_add_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result
1081 52 zero_gravi 
      rs1_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1082 2 zero_gravi 
      -- data output --
1083 
      imm_o         : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
1084 6 zero_gravi 
      fetch_pc_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
1085 
      curr_pc_o     : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
1086 2 zero_gravi 
      csr_rdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
1087 52 zero_gravi 
      -- FPU interface --
1088 
      fpu_rm_o      : out std_ulogic_vector(02 downto 0); -- rounding mode
1089 
      fpu_flags_i   : in  std_ulogic_vector(04 downto 0); -- exception flags
1090 14 zero_gravi 
      -- interrupts (risc-v compliant) --
1091 
      msw_irq_i     : in  std_ulogic; -- machine software interrupt
1092 
      mext_irq_i    : in  std_ulogic; -- machine external interrupt
1093 2 zero_gravi 
      mtime_irq_i   : in  std_ulogic; -- machine timer interrupt
1094 14 zero_gravi 
      -- fast interrupts (custom) --
1095 48 zero_gravi 
      firq_i        : in  std_ulogic_vector(15 downto 0);
1096 
      firq_ack_o    : out std_ulogic_vector(15 downto 0);
1097 11 zero_gravi 
      -- system time input from MTIME --
1098 
      time_i        : in  std_ulogic_vector(63 downto 0); -- current system time
1099 15 zero_gravi 
      -- physical memory protection --
1100 
      pmp_addr_o    : out pmp_addr_if_t; -- addresses
1101 
      pmp_ctrl_o    : out pmp_ctrl_if_t; -- configs
1102 2 zero_gravi 
      -- bus access exceptions --
1103 
      mar_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
1104 
      ma_instr_i    : in  std_ulogic; -- misaligned instruction address
1105 
      ma_load_i     : in  std_ulogic; -- misaligned load data address
1106 
      ma_store_i    : in  std_ulogic; -- misaligned store data address
1107 
      be_instr_i    : in  std_ulogic; -- bus error on instruction access
1108 
      be_load_i     : in  std_ulogic; -- bus error on load data access
1109 12 zero_gravi 
      be_store_i    : in  std_ulogic  -- bus error on store data access
1110 2 zero_gravi 
    );
1111 
  end component;
1112 
 
1113 
  -- Component: CPU Register File -----------------------------------------------------------
1114 
  -- -------------------------------------------------------------------------------------------
1115 
  component neorv32_cpu_regfile
1116 
    generic (
1117 
      CPU_EXTENSION_RISCV_E : boolean := false -- implement embedded RF extension?
1118 
    );
1119 
    port (
1120 
      -- global control --
1121 
      clk_i  : in  std_ulogic; -- global clock, rising edge
1122 
      ctrl_i : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1123 
      -- data input --
1124 
      mem_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
1125 
      alu_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
1126 
      -- data output --
1127 
      rs1_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
1128 47 zero_gravi 
      rs2_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 2
1129 
      cmp_o  : out std_ulogic_vector(1 downto 0) -- comparator status
1130 2 zero_gravi 
    );
1131 
  end component;
1132 
 
1133 
  -- Component: CPU ALU ---------------------------------------------------------------------
1134 
  -- -------------------------------------------------------------------------------------------
1135 
  component neorv32_cpu_alu
1136 11 zero_gravi 
    generic (
1137 34 zero_gravi 
      CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
1138 
      FAST_SHIFT_EN         : boolean := false -- use barrel shifter for shift operations
1139 11 zero_gravi 
    );
1140 2 zero_gravi 
    port (
1141 
      -- global control --
1142 
      clk_i       : in  std_ulogic; -- global clock, rising edge
1143 
      rstn_i      : in  std_ulogic; -- global reset, low-active, async
1144 
      ctrl_i      : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1145 
      -- data input --
1146 
      rs1_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1147 
      rs2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1148 
      pc2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
1149 
      imm_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- immediate
1150 
      -- data output --
1151 
      res_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
1152 36 zero_gravi 
      add_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
1153 2 zero_gravi 
      -- co-processor interface --
1154 49 zero_gravi 
      cp_start_o  : out std_ulogic_vector(7 downto 0); -- trigger co-processor i
1155 
      cp_valid_i  : in  std_ulogic_vector(7 downto 0); -- co-processor i done
1156 
      cp_result_i : in  cp_data_if_t; -- co-processor result
1157 2 zero_gravi 
      -- status --
1158 
      wait_o      : out std_ulogic -- busy due to iterative processing units
1159 
    );
1160 
  end component;
1161 
 
1162 44 zero_gravi 
  -- Component: CPU Co-Processor MULDIV ('M' extension) -------------------------------------
1163 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1164 
  component neorv32_cpu_cp_muldiv
1165 19 zero_gravi 
    generic (
1166 
      FAST_MUL_EN : boolean := false -- use DSPs for faster multiplication
1167 
    );
1168 2 zero_gravi 
    port (
1169 
      -- global control --
1170 
      clk_i   : in  std_ulogic; -- global clock, rising edge
1171 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
1172 
      ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1173 36 zero_gravi 
      start_i : in  std_ulogic; -- trigger operation
1174 2 zero_gravi 
      -- data input --
1175 
      rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1176 
      rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1177 
      -- result and status --
1178 
      res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1179 
      valid_o : out std_ulogic -- data output valid
1180 
    );
1181 
  end component;
1182 
 
1183 44 zero_gravi 
  -- Component: CPU Co-Processor Bit Manipulation ('B' extension) ---------------------------
1184 
  -- -------------------------------------------------------------------------------------------
1185 
  component neorv32_cpu_cp_bitmanip
1186 
    port (
1187 
      -- global control --
1188 
      clk_i   : in  std_ulogic; -- global clock, rising edge
1189 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
1190 
      ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1191 
      start_i : in  std_ulogic; -- trigger operation
1192 
      -- data input --
1193 
      cmp_i   : in  std_ulogic_vector(1 downto 0); -- comparator status
1194 
      rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1195 
      rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1196 
      -- result and status --
1197 
      res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1198 
      valid_o : out std_ulogic -- data output valid
1199 
    );
1200 
  end component;
1201 
 
1202 53 zero_gravi 
  -- Component: CPU Co-Processor 32-bit FPU ('Zfinx' extension) -----------------------------
1203 52 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1204 
  component neorv32_cpu_cp_fpu
1205 
    port (
1206 
      -- global control --
1207 53 zero_gravi 
      clk_i    : in  std_ulogic; -- global clock, rising edge
1208 
      rstn_i   : in  std_ulogic; -- global reset, low-active, async
1209 
      ctrl_i   : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1210 
      start_i  : in  std_ulogic; -- trigger operation
1211 52 zero_gravi 
      -- data input --
1212 53 zero_gravi 
      frm_i    : in  std_ulogic_vector(2 downto 0); -- rounding mode
1213 
      rs1_i    : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1214 
      rs2_i    : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1215 52 zero_gravi 
      -- result and status --
1216 53 zero_gravi 
      res_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1217 
      fflags_o : out std_ulogic_vector(4 downto 0); -- exception flags
1218 
      valid_o  : out std_ulogic -- data output valid
1219 52 zero_gravi 
    );
1220 
  end component;
1221 
 
1222 2 zero_gravi 
  -- Component: CPU Bus Interface -----------------------------------------------------------
1223 
  -- -------------------------------------------------------------------------------------------
1224 
  component neorv32_cpu_bus
1225 
    generic (
1226 53 zero_gravi 
      CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
1227 40 zero_gravi 
      CPU_EXTENSION_RISCV_C : boolean := true;  -- implement compressed extension?
1228 15 zero_gravi 
      -- Physical memory protection (PMP) --
1229 42 zero_gravi 
      PMP_NUM_REGIONS       : natural := 0;       -- number of regions (0..64)
1230 
      PMP_MIN_GRANULARITY   : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
1231 41 zero_gravi 
      -- Bus Timeout --
1232 
      BUS_TIMEOUT           : natural := 63     -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
1233 2 zero_gravi 
    );
1234 
    port (
1235 
      -- global control --
1236 12 zero_gravi 
      clk_i          : in  std_ulogic; -- global clock, rising edge
1237 38 zero_gravi 
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
1238 12 zero_gravi 
      ctrl_i         : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1239 
      -- cpu instruction fetch interface --
1240 
      fetch_pc_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
1241 
      instr_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
1242 
      i_wait_o       : out std_ulogic; -- wait for fetch to complete
1243 
      --
1244 
      ma_instr_o     : out std_ulogic; -- misaligned instruction address
1245 
      be_instr_o     : out std_ulogic; -- bus error on instruction access
1246 
      -- cpu data access interface --
1247 
      addr_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
1248 
      wdata_i        : in  std_ulogic_vector(data_width_c-1 downto 0); -- write data
1249 
      rdata_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
1250 
      mar_o          : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
1251 
      d_wait_o       : out std_ulogic; -- wait for access to complete
1252 
      --
1253 53 zero_gravi 
      bus_excl_ok_o  : out std_ulogic; -- bus exclusive access successful
1254 12 zero_gravi 
      ma_load_o      : out std_ulogic; -- misaligned load data address
1255 
      ma_store_o     : out std_ulogic; -- misaligned store data address
1256 
      be_load_o      : out std_ulogic; -- bus error on load data access
1257 
      be_store_o     : out std_ulogic; -- bus error on store data access
1258 15 zero_gravi 
      -- physical memory protection --
1259 
      pmp_addr_i     : in  pmp_addr_if_t; -- addresses
1260 
      pmp_ctrl_i     : in  pmp_ctrl_if_t; -- configs
1261 12 zero_gravi 
      -- instruction bus --
1262 
      i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1263 
      i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1264 
      i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1265 
      i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1266 
      i_bus_we_o     : out std_ulogic; -- write enable
1267 
      i_bus_re_o     : out std_ulogic; -- read enable
1268 
      i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
1269 
      i_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
1270 
      i_bus_err_i    : in  std_ulogic; -- bus transfer error
1271 
      i_bus_fence_o  : out std_ulogic; -- fence operation
1272 
      -- data bus --
1273 
      d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1274 
      d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1275 
      d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1276 
      d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1277 
      d_bus_we_o     : out std_ulogic; -- write enable
1278 
      d_bus_re_o     : out std_ulogic; -- read enable
1279 
      d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
1280 
      d_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
1281 
      d_bus_err_i    : in  std_ulogic; -- bus transfer error
1282 39 zero_gravi 
      d_bus_fence_o  : out std_ulogic; -- fence operation
1283 53 zero_gravi 
      d_bus_excl_o   : out std_ulogic; -- exclusive access request
1284 
      d_bus_excl_i   : in  std_ulogic  -- state of exclusiv access (set if success)
1285 2 zero_gravi 
    );
1286 
  end component;
1287 
 
1288 45 zero_gravi 
  -- Component: CPU Instruction Cache -------------------------------------------------------
1289 41 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1290 45 zero_gravi 
  component neorv32_icache
1291 41 zero_gravi 
    generic (
1292 47 zero_gravi 
      ICACHE_NUM_BLOCKS : natural := 4;  -- number of blocks (min 1), has to be a power of 2
1293 
      ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2
1294 
      ICACHE_NUM_SETS   : natural := 1   -- associativity / number of sets (1=direct_mapped), has to be a power of 2
1295 41 zero_gravi 
    );
1296 
    port (
1297 
      -- global control --
1298 
      clk_i         : in  std_ulogic; -- global clock, rising edge
1299 
      rstn_i        : in  std_ulogic; -- global reset, low-active, async
1300 
      clear_i       : in  std_ulogic; -- cache clear
1301 
      -- host controller interface --
1302 
      host_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1303 
      host_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1304 
      host_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1305 
      host_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1306 
      host_we_i     : in  std_ulogic; -- write enable
1307 
      host_re_i     : in  std_ulogic; -- read enable
1308 
      host_cancel_i : in  std_ulogic; -- cancel current bus transaction
1309 
      host_ack_o    : out std_ulogic; -- bus transfer acknowledge
1310 
      host_err_o    : out std_ulogic; -- bus transfer error
1311 
      -- peripheral bus interface --
1312 
      bus_addr_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1313 
      bus_rdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1314 
      bus_wdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1315 
      bus_ben_o     : out std_ulogic_vector(03 downto 0); -- byte enable
1316 
      bus_we_o      : out std_ulogic; -- write enable
1317 
      bus_re_o      : out std_ulogic; -- read enable
1318 
      bus_cancel_o  : out std_ulogic; -- cancel current bus transaction
1319 
      bus_ack_i     : in  std_ulogic; -- bus transfer acknowledge
1320 
      bus_err_i     : in  std_ulogic  -- bus transfer error
1321 
    );
1322 
  end component;
1323 
 
1324 12 zero_gravi 
  -- Component: CPU Bus Switch --------------------------------------------------------------
1325 
  -- -------------------------------------------------------------------------------------------
1326 
  component neorv32_busswitch
1327 
    generic (
1328 
      PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only
1329 
      PORT_CB_READ_ONLY : boolean := false  -- set if controller port B is read-only
1330 
    );
1331 
    port (
1332 
      -- global control --
1333 
      clk_i           : in  std_ulogic; -- global clock, rising edge
1334 
      rstn_i          : in  std_ulogic; -- global reset, low-active, async
1335 
      -- controller interface a --
1336 
      ca_bus_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1337 
      ca_bus_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1338 
      ca_bus_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1339 
      ca_bus_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1340 
      ca_bus_we_i     : in  std_ulogic; -- write enable
1341 
      ca_bus_re_i     : in  std_ulogic; -- read enable
1342 
      ca_bus_cancel_i : in  std_ulogic; -- cancel current bus transaction
1343 53 zero_gravi 
      ca_bus_excl_i   : in  std_ulogic; -- exclusive access
1344 12 zero_gravi 
      ca_bus_ack_o    : out std_ulogic; -- bus transfer acknowledge
1345 
      ca_bus_err_o    : out std_ulogic; -- bus transfer error
1346 
      -- controller interface b --
1347 
      cb_bus_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1348 
      cb_bus_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1349 
      cb_bus_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1350 
      cb_bus_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1351 
      cb_bus_we_i     : in  std_ulogic; -- write enable
1352 
      cb_bus_re_i     : in  std_ulogic; -- read enable
1353 
      cb_bus_cancel_i : in  std_ulogic; -- cancel current bus transaction
1354 53 zero_gravi 
      cb_bus_excl_i   : in  std_ulogic; -- exclusive access
1355 12 zero_gravi 
      cb_bus_ack_o    : out std_ulogic; -- bus transfer acknowledge
1356 
      cb_bus_err_o    : out std_ulogic; -- bus transfer error
1357 
      -- peripheral bus --
1358 36 zero_gravi 
      p_bus_src_o     : out std_ulogic; -- access source: 0 = A, 1 = B
1359 12 zero_gravi 
      p_bus_addr_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1360 
      p_bus_rdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1361 
      p_bus_wdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1362 
      p_bus_ben_o     : out std_ulogic_vector(03 downto 0); -- byte enable
1363 
      p_bus_we_o      : out std_ulogic; -- write enable
1364 
      p_bus_re_o      : out std_ulogic; -- read enable
1365 
      p_bus_cancel_o  : out std_ulogic; -- cancel current bus transaction
1366 53 zero_gravi 
      p_bus_excl_o    : out std_ulogic; -- exclusive access
1367 12 zero_gravi 
      p_bus_ack_i     : in  std_ulogic; -- bus transfer acknowledge
1368 
      p_bus_err_i     : in  std_ulogic  -- bus transfer error
1369 
    );
1370 
  end component;
1371 
 
1372 2 zero_gravi 
  -- Component: CPU Compressed Instructions Decompressor ------------------------------------
1373 
  -- -------------------------------------------------------------------------------------------
1374 
  component neorv32_cpu_decompressor
1375 
    port (
1376 
      -- instruction input --
1377 
      ci_instr16_i : in  std_ulogic_vector(15 downto 0); -- compressed instruction input
1378 
      -- instruction output --
1379 
      ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
1380 
      ci_instr32_o : out std_ulogic_vector(31 downto 0)  -- 32-bit decompressed instruction
1381 
    );
1382 
  end component;
1383 
 
1384 
  -- Component: Processor-internal instruction memory (IMEM) --------------------------------
1385 
  -- -------------------------------------------------------------------------------------------
1386 
  component neorv32_imem
1387 
    generic (
1388 
      IMEM_BASE      : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
1389 
      IMEM_SIZE      : natural := 4*1024; -- processor-internal instruction memory size in bytes
1390 
      IMEM_AS_ROM    : boolean := false;  -- implement IMEM as read-only memory?
1391 44 zero_gravi 
      BOOTLOADER_EN  : boolean := true    -- implement and use bootloader?
1392 2 zero_gravi 
    );
1393 
    port (
1394 
      clk_i  : in  std_ulogic; -- global clock line
1395 
      rden_i : in  std_ulogic; -- read enable
1396 
      wren_i : in  std_ulogic; -- write enable
1397 
      ben_i  : in  std_ulogic_vector(03 downto 0); -- byte write enable
1398 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1399 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1400 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1401 
      ack_o  : out std_ulogic -- transfer acknowledge
1402 
    );
1403 
  end component;
1404 
 
1405 
  -- Component: Processor-internal data memory (DMEM) ---------------------------------------
1406 
  -- -------------------------------------------------------------------------------------------
1407 
  component neorv32_dmem
1408 
    generic (
1409 
      DMEM_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- memory base address
1410 
      DMEM_SIZE : natural := 4*1024  -- processor-internal instruction memory size in bytes
1411 
    );
1412 
    port (
1413 
      clk_i  : in  std_ulogic; -- global clock line
1414 
      rden_i : in  std_ulogic; -- read enable
1415 
      wren_i : in  std_ulogic; -- write enable
1416 
      ben_i  : in  std_ulogic_vector(03 downto 0); -- byte write enable
1417 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1418 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1419 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1420 
      ack_o  : out std_ulogic -- transfer acknowledge
1421 
    );
1422 
  end component;
1423 
 
1424 
  -- Component: Processor-internal bootloader ROM (BOOTROM) ---------------------------------
1425 
  -- -------------------------------------------------------------------------------------------
1426 
  component neorv32_boot_rom
1427 23 zero_gravi 
    generic (
1428 
      BOOTROM_BASE : std_ulogic_vector(31 downto 0) := x"FFFF0000"; -- boot ROM base address
1429 
      BOOTROM_SIZE : natural := 4*1024  -- processor-internal boot ROM memory size in bytes
1430 
    );
1431 2 zero_gravi 
    port (
1432 
      clk_i  : in  std_ulogic; -- global clock line
1433 
      rden_i : in  std_ulogic; -- read enable
1434 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1435 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1436 
      ack_o  : out std_ulogic -- transfer acknowledge
1437 
    );
1438 
  end component;
1439 
 
1440 
  -- Component: Machine System Timer (mtime) ------------------------------------------------
1441 
  -- -------------------------------------------------------------------------------------------
1442 
  component neorv32_mtime
1443 
    port (
1444 
      -- host access --
1445 
      clk_i     : in  std_ulogic; -- global clock line
1446 4 zero_gravi 
      rstn_i    : in  std_ulogic := '0'; -- global reset, low-active, async
1447 2 zero_gravi 
      addr_i    : in  std_ulogic_vector(31 downto 0); -- address
1448 
      rden_i    : in  std_ulogic; -- read enable
1449 
      wren_i    : in  std_ulogic; -- write enable
1450 
      data_i    : in  std_ulogic_vector(31 downto 0); -- data in
1451 
      data_o    : out std_ulogic_vector(31 downto 0); -- data out
1452 
      ack_o     : out std_ulogic; -- transfer acknowledge
1453 11 zero_gravi 
      -- time output for CPU --
1454 
      time_o    : out std_ulogic_vector(63 downto 0); -- current system time
1455 2 zero_gravi 
      -- interrupt --
1456 
      irq_o     : out std_ulogic  -- interrupt request
1457 
    );
1458 
  end component;
1459 
 
1460 
  -- Component: General Purpose Input/Output Port (GPIO) ------------------------------------
1461 
  -- -------------------------------------------------------------------------------------------
1462 
  component neorv32_gpio
1463 
    port (
1464 
      -- host access --
1465 
      clk_i  : in  std_ulogic; -- global clock line
1466 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1467 
      rden_i : in  std_ulogic; -- read enable
1468 
      wren_i : in  std_ulogic; -- write enable
1469 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1470 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1471 
      ack_o  : out std_ulogic; -- transfer acknowledge
1472 
      -- parallel io --
1473 22 zero_gravi 
      gpio_o : out std_ulogic_vector(31 downto 0);
1474 
      gpio_i : in  std_ulogic_vector(31 downto 0);
1475 2 zero_gravi 
      -- interrupt --
1476 
      irq_o  : out std_ulogic
1477 
    );
1478 
  end component;
1479 
 
1480 
  -- Component: Watchdog Timer (WDT) --------------------------------------------------------
1481 
  -- -------------------------------------------------------------------------------------------
1482 
  component neorv32_wdt
1483 
    port (
1484 
      -- host access --
1485 
      clk_i       : in  std_ulogic; -- global clock line
1486 
      rstn_i      : in  std_ulogic; -- global reset line, low-active
1487 
      rden_i      : in  std_ulogic; -- read enable
1488 
      wren_i      : in  std_ulogic; -- write enable
1489 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1490 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1491 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1492 
      ack_o       : out std_ulogic; -- transfer acknowledge
1493 
      -- clock generator --
1494 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1495 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1496 
      -- timeout event --
1497 
      irq_o       : out std_ulogic; -- timeout IRQ
1498 
      rstn_o      : out std_ulogic  -- timeout reset, low_active, use it as async!
1499 
    );
1500 
  end component;
1501 
 
1502 
  -- Component: Universal Asynchronous Receiver and Transmitter (UART) ----------------------
1503 
  -- -------------------------------------------------------------------------------------------
1504 
  component neorv32_uart
1505 50 zero_gravi 
    generic (
1506 
      UART_PRIMARY : boolean := true -- true = primary UART (UART0), false = secondary UART (UART1)
1507 
    );
1508 2 zero_gravi 
    port (
1509 
      -- host access --
1510 
      clk_i       : in  std_ulogic; -- global clock line
1511 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1512 
      rden_i      : in  std_ulogic; -- read enable
1513 
      wren_i      : in  std_ulogic; -- write enable
1514 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1515 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1516 
      ack_o       : out std_ulogic; -- transfer acknowledge
1517 
      -- clock generator --
1518 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1519 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1520 
      -- com lines --
1521 
      uart_txd_o  : out std_ulogic;
1522 
      uart_rxd_i  : in  std_ulogic;
1523 51 zero_gravi 
      -- hardware flow control --
1524 
      uart_rts_o  : out std_ulogic; -- UART.RX ready to receive ("RTR"), low-active, optional
1525 
      uart_cts_i  : in  std_ulogic; -- UART.TX allowed to transmit, low-active, optional
1526 2 zero_gravi 
      -- interrupts --
1527 48 zero_gravi 
      irq_rxd_o   : out std_ulogic; -- uart data received interrupt
1528 
      irq_txd_o   : out std_ulogic  -- uart transmission done interrupt
1529 2 zero_gravi 
    );
1530 
  end component;
1531 
 
1532 
  -- Component: Serial Peripheral Interface (SPI) -------------------------------------------
1533 
  -- -------------------------------------------------------------------------------------------
1534 
  component neorv32_spi
1535 
    port (
1536 
      -- host access --
1537 
      clk_i       : in  std_ulogic; -- global clock line
1538 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1539 
      rden_i      : in  std_ulogic; -- read enable
1540 
      wren_i      : in  std_ulogic; -- write enable
1541 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1542 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1543 
      ack_o       : out std_ulogic; -- transfer acknowledge
1544 
      -- clock generator --
1545 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1546 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1547 
      -- com lines --
1548 6 zero_gravi 
      spi_sck_o   : out std_ulogic; -- SPI serial clock
1549 
      spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
1550 
      spi_sdi_i   : in  std_ulogic; -- controller data in, peripheral data out
1551 2 zero_gravi 
      spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
1552 
      -- interrupt --
1553 48 zero_gravi 
      irq_o       : out std_ulogic -- transmission done interrupt
1554 2 zero_gravi 
    );
1555 
  end component;
1556 
 
1557 
  -- Component: Two-Wire Interface (TWI) ----------------------------------------------------
1558 
  -- -------------------------------------------------------------------------------------------
1559 
  component neorv32_twi
1560 
    port (
1561 
      -- host access --
1562 
      clk_i       : in  std_ulogic; -- global clock line
1563 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1564 
      rden_i      : in  std_ulogic; -- read enable
1565 
      wren_i      : in  std_ulogic; -- write enable
1566 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1567 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1568 
      ack_o       : out std_ulogic; -- transfer acknowledge
1569 
      -- clock generator --
1570 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1571 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1572 
      -- com lines --
1573 
      twi_sda_io  : inout std_logic; -- serial data line
1574 
      twi_scl_io  : inout std_logic; -- serial clock line
1575 
      -- interrupt --
1576 48 zero_gravi 
      irq_o       : out std_ulogic -- transfer done IRQ
1577 2 zero_gravi 
    );
1578 
  end component;
1579 
 
1580 
  -- Component: Pulse-Width Modulation Controller (PWM) -------------------------------------
1581 
  -- -------------------------------------------------------------------------------------------
1582 
  component neorv32_pwm
1583 
    port (
1584 
      -- host access --
1585 
      clk_i       : in  std_ulogic; -- global clock line
1586 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1587 
      rden_i      : in  std_ulogic; -- read enable
1588 
      wren_i      : in  std_ulogic; -- write enable
1589 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1590 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1591 
      ack_o       : out std_ulogic; -- transfer acknowledge
1592 
      -- clock generator --
1593 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1594 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1595 
      -- pwm output channels --
1596 
      pwm_o       : out std_ulogic_vector(03 downto 0)
1597 
    );
1598 
  end component;
1599 
 
1600 
  -- Component: True Random Number Generator (TRNG) -----------------------------------------
1601 
  -- -------------------------------------------------------------------------------------------
1602 
  component neorv32_trng
1603 
    port (
1604 
      -- host access --
1605 
      clk_i  : in  std_ulogic; -- global clock line
1606 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1607 
      rden_i : in  std_ulogic; -- read enable
1608 
      wren_i : in  std_ulogic; -- write enable
1609 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1610 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1611 
      ack_o  : out std_ulogic  -- transfer acknowledge
1612 
    );
1613 
  end component;
1614 
 
1615 
  -- Component: Wishbone Bus Gateway (WISHBONE) ---------------------------------------------
1616 
  -- -------------------------------------------------------------------------------------------
1617 
  component neorv32_wishbone
1618 
    generic (
1619 35 zero_gravi 
      WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
1620 23 zero_gravi 
      -- Internal instruction memory --
1621 44 zero_gravi 
      MEM_INT_IMEM_EN   : boolean := true;   -- implement processor-internal instruction memory
1622 35 zero_gravi 
      MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
1623 23 zero_gravi 
      -- Internal data memory --
1624 44 zero_gravi 
      MEM_INT_DMEM_EN   : boolean := true;   -- implement processor-internal data memory
1625 35 zero_gravi 
      MEM_INT_DMEM_SIZE : natural := 4*1024  -- size of processor-internal data memory in bytes
1626 2 zero_gravi 
    );
1627 
    port (
1628 
      -- global control --
1629 53 zero_gravi 
      clk_i    : in  std_ulogic; -- global clock line
1630 
      rstn_i   : in  std_ulogic; -- global reset line, low-active
1631 2 zero_gravi 
      -- host access --
1632 53 zero_gravi 
      src_i    : in  std_ulogic; -- access type (0: data, 1:instruction)
1633 
      addr_i   : in  std_ulogic_vector(31 downto 0); -- address
1634 
      rden_i   : in  std_ulogic; -- read enable
1635 
      wren_i   : in  std_ulogic; -- write enable
1636 
      ben_i    : in  std_ulogic_vector(03 downto 0); -- byte write enable
1637 
      data_i   : in  std_ulogic_vector(31 downto 0); -- data in
1638 
      data_o   : out std_ulogic_vector(31 downto 0); -- data out
1639 
      cancel_i : in  std_ulogic; -- cancel current bus transaction
1640 
      excl_i   : in  std_ulogic; -- exclusive access request
1641 
      excl_o   : out std_ulogic; -- state of exclusiv access (set if success)
1642 
      ack_o    : out std_ulogic; -- transfer acknowledge
1643 
      err_o    : out std_ulogic; -- transfer error
1644 
      priv_i   : in  std_ulogic_vector(01 downto 0); -- current CPU privilege level
1645 2 zero_gravi 
      -- wishbone interface --
1646 53 zero_gravi 
      wb_tag_o : out std_ulogic_vector(03 downto 0); -- request tag
1647 
      wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
1648 
      wb_dat_i : in  std_ulogic_vector(31 downto 0); -- read data
1649 
      wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
1650 
      wb_we_o  : out std_ulogic; -- read/write
1651 
      wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
1652 
      wb_stb_o : out std_ulogic; -- strobe
1653 
      wb_cyc_o : out std_ulogic; -- valid cycle
1654 
      wb_tag_i : in  std_ulogic; -- response tag
1655 
      wb_ack_i : in  std_ulogic; -- transfer acknowledge
1656 
      wb_err_i : in  std_ulogic  -- transfer error
1657 2 zero_gravi 
    );
1658 
  end component;
1659 
 
1660 47 zero_gravi 
  -- Component: Custom Functions Subsystem (CFS) --------------------------------------------
1661 23 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1662 47 zero_gravi 
  component neorv32_cfs
1663 
    generic (
1664 52 zero_gravi 
      CFS_CONFIG   : std_ulogic_vector(31 downto 0); -- custom CFS configuration generic
1665 
      CFS_IN_SIZE  : positive := 32;  -- size of CFS input conduit in bits
1666 
      CFS_OUT_SIZE : positive := 32   -- size of CFS output conduit in bits
1667 23 zero_gravi 
    );
1668 34 zero_gravi 
    port (
1669 
      -- host access --
1670 
      clk_i       : in  std_ulogic; -- global clock line
1671 
      rstn_i      : in  std_ulogic; -- global reset line, low-active, use as async
1672 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1673 
      rden_i      : in  std_ulogic; -- read enable
1674 47 zero_gravi 
      wren_i      : in  std_ulogic; -- word write enable
1675 34 zero_gravi 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1676 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1677 
      ack_o       : out std_ulogic; -- transfer acknowledge
1678 
      -- clock generator --
1679 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1680 47 zero_gravi 
      clkgen_i    : in  std_ulogic_vector(07 downto 0); -- "clock" inputs
1681 
      -- CPU state --
1682 
      sleep_i     : in  std_ulogic; -- set if cpu is in sleep mode
1683 
      -- interrupt --
1684 
      irq_o       : out std_ulogic; -- interrupt request
1685 
      irq_ack_i   : in  std_ulogic; -- interrupt acknowledge
1686 
      -- custom io (conduit) --
1687 52 zero_gravi 
      cfs_in_i    : in  std_ulogic_vector(CFS_IN_SIZE-1 downto 0);  -- custom inputs
1688 
      cfs_out_o   : out std_ulogic_vector(CFS_OUT_SIZE-1 downto 0)  -- custom outputs
1689 34 zero_gravi 
    );
1690 
  end component;
1691 
 
1692 49 zero_gravi 
  -- Component: Numerically-Controlled Oscillator (NCO) -------------------------------------
1693 
  -- -------------------------------------------------------------------------------------------
1694 
  component neorv32_nco
1695 
    port (
1696 
      -- host access --
1697 
      clk_i       : in  std_ulogic; -- global clock line
1698 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1699 
      rden_i      : in  std_ulogic; -- read enable
1700 
      wren_i      : in  std_ulogic; -- write enable
1701 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1702 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1703 
      ack_o       : out std_ulogic; -- transfer acknowledge
1704 
      -- clock generator --
1705 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1706 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1707 
      -- NCO output --
1708 
      nco_o       : out std_ulogic_vector(02 downto 0)
1709 
    );
1710 
  end component;
1711 
 
1712 52 zero_gravi 
  -- Component: Smart LED (WS2811/WS2812) Interface (NEOLED) --------------------------------
1713 
  -- -------------------------------------------------------------------------------------------
1714 
  component neorv32_neoled
1715 
    port (
1716 
      -- host access --
1717 
      clk_i       : in  std_ulogic; -- global clock line
1718 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1719 
      rden_i      : in  std_ulogic; -- read enable
1720 
      wren_i      : in  std_ulogic; -- write enable
1721 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1722 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1723 
      ack_o       : out std_ulogic; -- transfer acknowledge
1724 
      -- clock generator --
1725 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1726 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1727 
      -- interrupt --
1728 
      irq_o       : out std_ulogic; -- interrupt request
1729 
      -- NEOLED output --
1730 
      neoled_o    : out std_ulogic -- serial async data line
1731 
    );
1732 
  end component;
1733 
 
1734 23 zero_gravi 
  -- Component: System Configuration Information Memory (SYSINFO) ---------------------------
1735 
  -- -------------------------------------------------------------------------------------------
1736 12 zero_gravi 
  component neorv32_sysinfo
1737 
    generic (
1738 
      -- General --
1739 41 zero_gravi 
      CLOCK_FREQUENCY      : natural := 0;      -- clock frequency of clk_i in Hz
1740 44 zero_gravi 
      BOOTLOADER_EN        : boolean := true;   -- implement processor-internal bootloader?
1741 41 zero_gravi 
      USER_CODE            : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
1742 23 zero_gravi 
      -- Internal Instruction memory --
1743 44 zero_gravi 
      MEM_INT_IMEM_EN      : boolean := true;   -- implement processor-internal instruction memory
1744 41 zero_gravi 
      MEM_INT_IMEM_SIZE    : natural := 8*1024; -- size of processor-internal instruction memory in bytes
1745 
      MEM_INT_IMEM_ROM     : boolean := false;  -- implement processor-internal instruction memory as ROM
1746 23 zero_gravi 
      -- Internal Data memory --
1747 44 zero_gravi 
      MEM_INT_DMEM_EN      : boolean := true;   -- implement processor-internal data memory
1748 41 zero_gravi 
      MEM_INT_DMEM_SIZE    : natural := 4*1024; -- size of processor-internal data memory in bytes
1749 
      -- Internal Cache memory --
1750 44 zero_gravi 
      ICACHE_EN            : boolean := true;   -- implement instruction cache
1751 41 zero_gravi 
      ICACHE_NUM_BLOCKS    : natural := 4;      -- i-cache: number of blocks (min 2), has to be a power of 2
1752 
      ICACHE_BLOCK_SIZE    : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
1753 
      ICACHE_ASSOCIATIVITY : natural := 1;      -- i-cache: associativity (min 1), has to be a power 2
1754 23 zero_gravi 
      -- External memory interface --
1755 44 zero_gravi 
      MEM_EXT_EN           : boolean := false;  -- implement external memory bus interface?
1756 12 zero_gravi 
      -- Processor peripherals --
1757 44 zero_gravi 
      IO_GPIO_EN           : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
1758 
      IO_MTIME_EN          : boolean := true;   -- implement machine system timer (MTIME)?
1759 50 zero_gravi 
      IO_UART0_EN          : boolean := true;   -- implement primary universal asynchronous receiver/transmitter (UART0)?
1760 
      IO_UART1_EN          : boolean := true;   -- implement secondary universal asynchronous receiver/transmitter (UART1)?
1761 44 zero_gravi 
      IO_SPI_EN            : boolean := true;   -- implement serial peripheral interface (SPI)?
1762 
      IO_TWI_EN            : boolean := true;   -- implement two-wire interface (TWI)?
1763 
      IO_PWM_EN            : boolean := true;   -- implement pulse-width modulation unit (PWM)?
1764 
      IO_WDT_EN            : boolean := true;   -- implement watch dog timer (WDT)?
1765 
      IO_TRNG_EN           : boolean := true;   -- implement true random number generator (TRNG)?
1766 49 zero_gravi 
      IO_CFS_EN            : boolean := true;   -- implement custom functions subsystem (CFS)?
1767 52 zero_gravi 
      IO_NCO_EN            : boolean := true;   -- implement numerically-controlled oscillator (NCO)?
1768 
      IO_NEOLED_EN         : boolean := true    -- implement NeoPixel-compatible smart LED interface (NEOLED)?
1769 12 zero_gravi 
    );
1770 
    port (
1771 
      -- host access --
1772 
      clk_i  : in  std_ulogic; -- global clock line
1773 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1774 
      rden_i : in  std_ulogic; -- read enable
1775 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1776 
      ack_o  : out std_ulogic  -- transfer acknowledge
1777 
    );
1778 
  end component;
1779 
 
1780 2 zero_gravi 
end neorv32_package;
1781 
 
1782 
package body neorv32_package is
1783 
 
1784 41 zero_gravi 
  -- Function: Minimal required number of bits to represent input number --------------------
1785 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1786 
  function index_size_f(input : natural) return natural is
1787 
  begin
1788 
    for i in 0 to natural'high loop
1789 
      if (2**i >= input) then
1790 
        return i;
1791 
      end if;
1792 
    end loop; -- i
1793 
    return 0;
1794 
  end function index_size_f;
1795 
 
1796 
  -- Function: Conditional select natural ---------------------------------------------------
1797 
  -- -------------------------------------------------------------------------------------------
1798 
  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural is
1799 
  begin
1800 
    if (cond = true) then
1801 
      return val_t;
1802 
    else
1803 
      return val_f;
1804 
    end if;
1805 
  end function cond_sel_natural_f;
1806 
 
1807 
  -- Function: Conditional select std_ulogic_vector -----------------------------------------
1808 
  -- -------------------------------------------------------------------------------------------
1809 
  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector is
1810 
  begin
1811 
    if (cond = true) then
1812 
      return val_t;
1813 
    else
1814 
      return val_f;
1815 
    end if;
1816 
  end function cond_sel_stdulogicvector_f;
1817 
 
1818 50 zero_gravi 
  -- Function: Conditional select string ----------------------------------------------------
1819 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1820 50 zero_gravi 
  function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string is
1821 
  begin
1822 
    if (cond = true) then
1823 
      return val_t;
1824 
    else
1825 
      return val_f;
1826 
    end if;
1827 
  end function cond_sel_string_f;
1828 
 
1829 
  -- Function: Convert bool to std_ulogic ---------------------------------------------------
1830 
  -- -------------------------------------------------------------------------------------------
1831 2 zero_gravi 
  function bool_to_ulogic_f(cond : boolean) return std_ulogic is
1832 
  begin
1833 
    if (cond = true) then
1834 
      return '1';
1835 
    else
1836 
      return '0';
1837 
    end if;
1838 
  end function bool_to_ulogic_f;
1839 
 
1840 
  -- Function: OR all bits ------------------------------------------------------------------
1841 
  -- -------------------------------------------------------------------------------------------
1842 
  function or_all_f(a : std_ulogic_vector) return std_ulogic is
1843 
    variable tmp_v : std_ulogic;
1844 
  begin
1845 
    tmp_v := a(a'low);
1846 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1847 
      for i in a'low+1 to a'high loop
1848 
        tmp_v := tmp_v or a(i);
1849 
      end loop; -- i
1850 
    end if;
1851 2 zero_gravi 
    return tmp_v;
1852 
  end function or_all_f;
1853 
 
1854 
  -- Function: AND all bits -----------------------------------------------------------------
1855 
  -- -------------------------------------------------------------------------------------------
1856 
  function and_all_f(a : std_ulogic_vector) return std_ulogic is
1857 
    variable tmp_v : std_ulogic;
1858 
  begin
1859 
    tmp_v := a(a'low);
1860 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1861 
      for i in a'low+1 to a'high loop
1862 
        tmp_v := tmp_v and a(i);
1863 
      end loop; -- i
1864 
    end if;
1865 2 zero_gravi 
    return tmp_v;
1866 
  end function and_all_f;
1867 
 
1868 
  -- Function: XOR all bits -----------------------------------------------------------------
1869 
  -- -------------------------------------------------------------------------------------------
1870 
  function xor_all_f(a : std_ulogic_vector) return std_ulogic is
1871 
    variable tmp_v : std_ulogic;
1872 
  begin
1873 
    tmp_v := a(a'low);
1874 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1875 
      for i in a'low+1 to a'high loop
1876 
        tmp_v := tmp_v xor a(i);
1877 
      end loop; -- i
1878 
    end if;
1879 2 zero_gravi 
    return tmp_v;
1880 
  end function xor_all_f;
1881 
 
1882 
  -- Function: XNOR all bits ----------------------------------------------------------------
1883 
  -- -------------------------------------------------------------------------------------------
1884 
  function xnor_all_f(a : std_ulogic_vector) return std_ulogic is
1885 
    variable tmp_v : std_ulogic;
1886 
  begin
1887 
    tmp_v := a(a'low);
1888 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1889 
      for i in a'low+1 to a'high loop
1890 
        tmp_v := tmp_v xnor a(i);
1891 
      end loop; -- i
1892 
    end if;
1893 2 zero_gravi 
    return tmp_v;
1894 
  end function xnor_all_f;
1895 
 
1896 40 zero_gravi 
  -- Function: Convert std_ulogic_vector to hex char ----------------------------------------
1897 6 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1898 
  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character is
1899 
    variable output_v : character;
1900 
  begin
1901 
    case input is
1902 7 zero_gravi 
      when x"0"   => output_v := '0';
1903 
      when x"1"   => output_v := '1';
1904 
      when x"2"   => output_v := '2';
1905 
      when x"3"   => output_v := '3';
1906 
      when x"4"   => output_v := '4';
1907 
      when x"5"   => output_v := '5';
1908 
      when x"6"   => output_v := '6';
1909 
      when x"7"   => output_v := '7';
1910 
      when x"8"   => output_v := '8';
1911 
      when x"9"   => output_v := '9';
1912 
      when x"a"   => output_v := 'a';
1913 
      when x"b"   => output_v := 'b';
1914 
      when x"c"   => output_v := 'c';
1915 
      when x"d"   => output_v := 'd';
1916 
      when x"e"   => output_v := 'e';
1917 
      when x"f"   => output_v := 'f';
1918 6 zero_gravi 
      when others => output_v := '?';
1919 
    end case;
1920 
    return output_v;
1921 
  end function to_hexchar_f;
1922 
 
1923 40 zero_gravi 
  -- Function: Convert hex char to std_ulogic_vector ----------------------------------------
1924 
  -- -------------------------------------------------------------------------------------------
1925 
  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector is
1926 
    variable hex_value_v : std_ulogic_vector(3 downto 0);
1927 
  begin
1928 
    case input is
1929 
      when '0'       => hex_value_v := x"0";
1930 
      when '1'       => hex_value_v := x"1";
1931 
      when '2'       => hex_value_v := x"2";
1932 
      when '3'       => hex_value_v := x"3";
1933 
      when '4'       => hex_value_v := x"4";
1934 
      when '5'       => hex_value_v := x"5";
1935 
      when '6'       => hex_value_v := x"6";
1936 
      when '7'       => hex_value_v := x"7";
1937 
      when '8'       => hex_value_v := x"8";
1938 
      when '9'       => hex_value_v := x"9";
1939 
      when 'a' | 'A' => hex_value_v := x"a";
1940 
      when 'b' | 'B' => hex_value_v := x"b";
1941 
      when 'c' | 'C' => hex_value_v := x"c";
1942 
      when 'd' | 'D' => hex_value_v := x"d";
1943 
      when 'e' | 'E' => hex_value_v := x"e";
1944 
      when 'f' | 'F' => hex_value_v := x"f";
1945 
      when others    => hex_value_v := (others => 'X');
1946 
    end case;
1947 
    return hex_value_v;
1948 
  end function hexchar_to_stdulogicvector_f;
1949 
 
1950 32 zero_gravi 
  -- Function: Bit reversal -----------------------------------------------------------------
1951 
  -- -------------------------------------------------------------------------------------------
1952 
  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector is
1953 
    variable output_v : std_ulogic_vector(input'range);
1954 
  begin
1955 
    for i in 0 to input'length-1 loop
1956 
      output_v(input'length-i-1) := input(i);
1957 
    end loop; -- i
1958 
    return output_v;
1959 
  end function bit_rev_f;
1960 
 
1961 36 zero_gravi 
  -- Function: Test if input number is a power of two ---------------------------------------
1962 
  -- -------------------------------------------------------------------------------------------
1963 
  function is_power_of_two_f(input : natural) return boolean is
1964 
  begin
1965 38 zero_gravi 
    if (input = 1) then -- 2^0
1966 36 zero_gravi 
      return true;
1967 38 zero_gravi 
    elsif ((input / 2) /= 0) and ((input mod 2) = 0) then
1968 
      return true;
1969 36 zero_gravi 
    else
1970 
      return false;
1971 
    end if;
1972 
  end function is_power_of_two_f;
1973 
 
1974 40 zero_gravi 
  -- Function: Swap all bytes of a 32-bit word (endianness conversion) ----------------------
1975 
  -- -------------------------------------------------------------------------------------------
1976 
  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector is
1977 
    variable output_v : std_ulogic_vector(input'range);
1978 
  begin
1979 
    output_v(07 downto 00) := input(31 downto 24);
1980 
    output_v(15 downto 08) := input(23 downto 16);
1981 
    output_v(23 downto 16) := input(15 downto 08);
1982 
    output_v(31 downto 24) := input(07 downto 00);
1983 
    return output_v;
1984 
  end function bswap32_f;
1985 
 
1986 2 zero_gravi 
end neorv32_package;

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