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1 2 zero_gravi 
-- #################################################################################################
2 
-- # << NEORV32 - Main VHDL package file >>                                                        #
3 
-- # ********************************************************************************************* #
4 
-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
6 42 zero_gravi 
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
7 2 zero_gravi 
-- #                                                                                               #
8 
-- # Redistribution and use in source and binary forms, with or without modification, are          #
9 
-- # permitted provided that the following conditions are met:                                     #
10 
-- #                                                                                               #
11 
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
12 
-- #    conditions and the following disclaimer.                                                   #
13 
-- #                                                                                               #
14 
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
15 
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
16 
-- #    provided with the distribution.                                                            #
17 
-- #                                                                                               #
18 
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
20 
-- #    permission.                                                                                #
21 
-- #                                                                                               #
22 
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
23 
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
24 
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
26 
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
27 
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
28 
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
29 
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
30 
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
32 
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
33 
-- #################################################################################################
34 
 
35 
library ieee;
36 
use ieee.std_logic_1164.all;
37 
use ieee.numeric_std.all;
38 
 
39 
package neorv32_package is
40 
 
41 36 zero_gravi 
  -- Architecture Configuration -------------------------------------------------------------
42 
  -- -------------------------------------------------------------------------------------------
43 40 zero_gravi 
  -- address space --
44 
  constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
45 
  constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
46 36 zero_gravi 
 
47 40 zero_gravi 
  -- (external) bus interface --
48 
  constant wb_pipe_mode_c    : boolean := false; -- *external* bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode
49 
  constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian
50 
 
51 
  -- CPU core --
52 57 zero_gravi 
  constant ipb_entries_c     : natural := 4; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
53 56 zero_gravi 
  constant cp_timeout_en_c   : boolean := false; -- auto-terminate pending co-processor operations after 256 cycles (for debugging only), default = false
54 
  constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value)
55 40 zero_gravi 
 
56 54 zero_gravi 
  -- "critical" number of implemented PMP regions --
57 
  -- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
58 
  -- increasing instruction fetch & data access latency by +1 cycle but also reducing critical path length
59 
  constant pmp_num_regions_critical_c : natural := 8; -- default=8
60 47 zero_gravi 
 
61 57 zero_gravi 
  -- "response time window" for processor-internal memories and IO devices
62 
  constant max_proc_int_response_time_c : natural := 15; -- cycles after which an *unacknowledged* internal bus access will timeout and trigger a bus fault exception (min 2)
63 
 
64 12 zero_gravi 
  -- Helper Functions -----------------------------------------------------------------------
65 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
66 
  function index_size_f(input : natural) return natural;
67 
  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
68 56 zero_gravi 
  function cond_sel_int_f(cond : boolean; val_t : integer; val_f : integer) return integer;
69 2 zero_gravi 
  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
70 56 zero_gravi 
  function cond_sel_stdulogic_f(cond : boolean; val_t : std_ulogic; val_f : std_ulogic) return std_ulogic;
71 50 zero_gravi 
  function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string;
72 2 zero_gravi 
  function bool_to_ulogic_f(cond : boolean) return std_ulogic;
73 15 zero_gravi 
  function or_all_f(a : std_ulogic_vector) return std_ulogic;
74 
  function and_all_f(a : std_ulogic_vector) return std_ulogic;
75 
  function xor_all_f(a : std_ulogic_vector) return std_ulogic;
76 2 zero_gravi 
  function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
77 6 zero_gravi 
  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
78 40 zero_gravi 
  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector;
79 32 zero_gravi 
  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector;
80 36 zero_gravi 
  function is_power_of_two_f(input : natural) return boolean;
81 40 zero_gravi 
  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;
82 2 zero_gravi 
 
83 56 zero_gravi 
  -- Architecture Constants (do not modify!) ------------------------------------------------
84 
  -- -------------------------------------------------------------------------------------------
85 
  constant data_width_c   : natural := 32; -- native data path width - do not change!
86 57 zero_gravi 
  constant hw_version_c   : std_ulogic_vector(31 downto 0) := x"01050408"; -- no touchy!
87 56 zero_gravi 
  constant archid_c       : natural := 19; -- official NEORV32 architecture ID - hands off!
88 
  constant rf_r0_is_reg_c : boolean := true; -- x0 is a *physical register* that has to be initialized to zero by the CPU
89 
  constant def_rst_val_c  : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-');
90 
 
91 15 zero_gravi 
  -- Internal Types -------------------------------------------------------------------------
92 
  -- -------------------------------------------------------------------------------------------
93 42 zero_gravi 
  type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);
94 
  type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0);
95 49 zero_gravi 
  type cp_data_if_t  is array (0 to 7)  of std_ulogic_vector(data_width_c-1 downto 0);
96 15 zero_gravi 
 
97 23 zero_gravi 
  -- Processor-Internal Address Space Layout ------------------------------------------------
98 
  -- -------------------------------------------------------------------------------------------
99 34 zero_gravi 
  -- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
100 39 zero_gravi 
  constant imem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
101 
  constant dmem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
102 42 zero_gravi 
  --> internal data/instruction memory sizes are configured via top's generics
103 2 zero_gravi 
 
104 23 zero_gravi 
  -- Internal Bootloader ROM --
105 56 zero_gravi 
  constant boot_rom_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffff0000"; -- bootloader base address, fixed!
106 47 zero_gravi 
  constant boot_rom_size_c      : natural := 4*1024; -- module's address space in bytes
107 
  constant boot_rom_max_size_c  : natural := 32*1024; -- max module's address space in bytes, fixed!
108 23 zero_gravi 
 
109 2 zero_gravi 
  -- IO: Peripheral Devices ("IO") Area --
110 
  -- Control register(s) (including the device-enable) should be located at the base address of each device
111 56 zero_gravi 
  constant io_base_c            : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00";
112 47 zero_gravi 
  constant io_size_c            : natural := 64*4; -- module's address space in bytes, fixed!
113 2 zero_gravi 
 
114 47 zero_gravi 
  -- Custom Functions Subsystem (CFS) --
115 56 zero_gravi 
  constant cfs_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00"; -- base address
116 47 zero_gravi 
  constant cfs_size_c           : natural := 32*4; -- module's address space in bytes
117 56 zero_gravi 
  constant cfs_reg0_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00";
118 
  constant cfs_reg1_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff04";
119 
  constant cfs_reg2_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff08";
120 
  constant cfs_reg3_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff0c";
121 
  constant cfs_reg4_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff10";
122 
  constant cfs_reg5_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff14";
123 
  constant cfs_reg6_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff18";
124 
  constant cfs_reg7_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff1c";
125 
  constant cfs_reg8_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff20";
126 
  constant cfs_reg9_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff24";
127 
  constant cfs_reg10_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff28";
128 
  constant cfs_reg11_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff2c";
129 
  constant cfs_reg12_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff30";
130 
  constant cfs_reg13_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff34";
131 
  constant cfs_reg14_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff38";
132 
  constant cfs_reg15_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff3c";
133 
  constant cfs_reg16_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff40";
134 
  constant cfs_reg17_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff44";
135 
  constant cfs_reg18_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff48";
136 
  constant cfs_reg19_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff4c";
137 
  constant cfs_reg20_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff50";
138 
  constant cfs_reg21_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff54";
139 
  constant cfs_reg22_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff58";
140 
  constant cfs_reg23_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff5c";
141 
  constant cfs_reg24_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff60";
142 
  constant cfs_reg25_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff64";
143 
  constant cfs_reg26_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff68";
144 
  constant cfs_reg27_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff6c";
145 
  constant cfs_reg28_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff70";
146 
  constant cfs_reg29_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff74";
147 
  constant cfs_reg30_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff78";
148 
  constant cfs_reg31_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff7c";
149 47 zero_gravi 
 
150 2 zero_gravi 
  -- General Purpose Input/Output Unit (GPIO) --
151 56 zero_gravi 
  constant gpio_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80"; -- base address
152 47 zero_gravi 
  constant gpio_size_c          : natural := 2*4; -- module's address space in bytes
153 56 zero_gravi 
  constant gpio_in_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80";
154 
  constant gpio_out_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff84";
155 2 zero_gravi 
 
156 30 zero_gravi 
  -- True Random Number Generator (TRNG) --
157 56 zero_gravi 
  constant trng_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff88"; -- base address
158 47 zero_gravi 
  constant trng_size_c          : natural := 1*4; -- module's address space in bytes
159 56 zero_gravi 
  constant trng_ctrl_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff88";
160 2 zero_gravi 
 
161 
  -- Watch Dog Timer (WDT) --
162 56 zero_gravi 
  constant wdt_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff8c"; -- base address
163 47 zero_gravi 
  constant wdt_size_c           : natural := 1*4; -- module's address space in bytes
164 56 zero_gravi 
  constant wdt_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff8c";
165 2 zero_gravi 
 
166 
  -- Machine System Timer (MTIME) --
167 56 zero_gravi 
  constant mtime_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff90"; -- base address
168 47 zero_gravi 
  constant mtime_size_c         : natural := 4*4; -- module's address space in bytes
169 56 zero_gravi 
  constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff90";
170 
  constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff94";
171 
  constant mtime_cmp_lo_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff98";
172 
  constant mtime_cmp_hi_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff9c";
173 2 zero_gravi 
 
174 50 zero_gravi 
  -- Universal Asynchronous Receiver/Transmitter 0 (UART0), primary UART --
175 56 zero_gravi 
  constant uart0_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0"; -- base address
176 50 zero_gravi 
  constant uart0_size_c         : natural := 2*4; -- module's address space in bytes
177 56 zero_gravi 
  constant uart0_ctrl_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0";
178 
  constant uart0_rtx_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa4";
179 2 zero_gravi 
 
180 
  -- Serial Peripheral Interface (SPI) --
181 56 zero_gravi 
  constant spi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa8"; -- base address
182 47 zero_gravi 
  constant spi_size_c           : natural := 2*4; -- module's address space in bytes
183 56 zero_gravi 
  constant spi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa8";
184 
  constant spi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffac";
185 2 zero_gravi 
 
186 
  -- Two Wire Interface (TWI) --
187 56 zero_gravi 
  constant twi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb0"; -- base address
188 47 zero_gravi 
  constant twi_size_c           : natural := 2*4; -- module's address space in bytes
189 56 zero_gravi 
  constant twi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb0";
190 
  constant twi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb4";
191 2 zero_gravi 
 
192 
  -- Pulse-Width Modulation Controller (PWM) --
193 56 zero_gravi 
  constant pwm_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb8"; -- base address
194 47 zero_gravi 
  constant pwm_size_c           : natural := 2*4; -- module's address space in bytes
195 56 zero_gravi 
  constant pwm_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb8";
196 
  constant pwm_duty_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffbc";
197 2 zero_gravi 
 
198 49 zero_gravi 
  -- Numerically-Controlled Oscillator (NCO) --
199 56 zero_gravi 
  constant nco_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0"; -- base address
200 49 zero_gravi 
  constant nco_size_c           : natural := 4*4; -- module's address space in bytes
201 56 zero_gravi 
  constant nco_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0";
202 
  constant nco_ch0_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc4";
203 
  constant nco_ch1_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc8";
204 
  constant nco_ch2_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffcc";
205 49 zero_gravi 
 
206 50 zero_gravi 
  -- Universal Asynchronous Receiver/Transmitter 1 (UART1), secondary UART --
207 56 zero_gravi 
  constant uart1_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0"; -- base address
208 50 zero_gravi 
  constant uart1_size_c         : natural := 2*4; -- module's address space in bytes
209 56 zero_gravi 
  constant uart1_ctrl_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0";
210 
  constant uart1_rtx_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd4";
211 50 zero_gravi 
 
212 52 zero_gravi 
  -- Smart LED (WS2811/WS2812) Interface (NEOLED) --
213 56 zero_gravi 
  constant neoled_base_c        : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd8"; -- base address
214 52 zero_gravi 
  constant neoled_size_c        : natural := 2*4; -- module's address space in bytes
215 56 zero_gravi 
  constant neoled_ctrl_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd8";
216 
  constant neoled_data_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffdc";
217 12 zero_gravi 
 
218 23 zero_gravi 
  -- System Information Memory (SYSINFO) --
219 56 zero_gravi 
  constant sysinfo_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffe0"; -- base address
220 47 zero_gravi 
  constant sysinfo_size_c       : natural := 8*4; -- module's address space in bytes
221 12 zero_gravi 
 
222 2 zero_gravi 
  -- Main Control Bus -----------------------------------------------------------------------
223 
  -- -------------------------------------------------------------------------------------------
224 
  -- register file --
225 49 zero_gravi 
  constant ctrl_rf_in_mux_c     : natural :=  0; -- input source select lsb (0=MEM, 1=ALU)
226 
  constant ctrl_rf_rs1_adr0_c   : natural :=  1; -- source register 1 address bit 0
227 
  constant ctrl_rf_rs1_adr1_c   : natural :=  2; -- source register 1 address bit 1
228 
  constant ctrl_rf_rs1_adr2_c   : natural :=  3; -- source register 1 address bit 2
229 
  constant ctrl_rf_rs1_adr3_c   : natural :=  4; -- source register 1 address bit 3
230 
  constant ctrl_rf_rs1_adr4_c   : natural :=  5; -- source register 1 address bit 4
231 
  constant ctrl_rf_rs2_adr0_c   : natural :=  6; -- source register 2 address bit 0
232 
  constant ctrl_rf_rs2_adr1_c   : natural :=  7; -- source register 2 address bit 1
233 
  constant ctrl_rf_rs2_adr2_c   : natural :=  8; -- source register 2 address bit 2
234 
  constant ctrl_rf_rs2_adr3_c   : natural :=  9; -- source register 2 address bit 3
235 
  constant ctrl_rf_rs2_adr4_c   : natural := 10; -- source register 2 address bit 4
236 
  constant ctrl_rf_rd_adr0_c    : natural := 11; -- destiantion register address bit 0
237 
  constant ctrl_rf_rd_adr1_c    : natural := 12; -- destiantion register address bit 1
238 
  constant ctrl_rf_rd_adr2_c    : natural := 13; -- destiantion register address bit 2
239 
  constant ctrl_rf_rd_adr3_c    : natural := 14; -- destiantion register address bit 3
240 
  constant ctrl_rf_rd_adr4_c    : natural := 15; -- destiantion register address bit 4
241 
  constant ctrl_rf_wb_en_c      : natural := 16; -- write back enable
242 
  constant ctrl_rf_r0_we_c      : natural := 17; -- force write access and force rd=r0
243 2 zero_gravi 
  -- alu --
244 49 zero_gravi 
  constant ctrl_alu_arith_c     : natural := 18; -- ALU arithmetic command
245 
  constant ctrl_alu_logic0_c    : natural := 19; -- ALU logic command bit 0
246 
  constant ctrl_alu_logic1_c    : natural := 20; -- ALU logic command bit 1
247 
  constant ctrl_alu_func0_c     : natural := 21; -- ALU function select command bit 0
248 
  constant ctrl_alu_func1_c     : natural := 22; -- ALU function select command bit 1
249 
  constant ctrl_alu_addsub_c    : natural := 23; -- 0=ADD, 1=SUB
250 
  constant ctrl_alu_opa_mux_c   : natural := 24; -- operand A select (0=rs1, 1=PC)
251 
  constant ctrl_alu_opb_mux_c   : natural := 25; -- operand B select (0=rs2, 1=IMM)
252 
  constant ctrl_alu_unsigned_c  : natural := 26; -- is unsigned ALU operation
253 
  constant ctrl_alu_shift_dir_c : natural := 27; -- shift direction (0=left, 1=right)
254 
  constant ctrl_alu_shift_ar_c  : natural := 28; -- is arithmetic shift
255 2 zero_gravi 
  -- bus interface --
256 49 zero_gravi 
  constant ctrl_bus_size_lsb_c  : natural := 29; -- transfer size lsb (00=byte, 01=half-word)
257 
  constant ctrl_bus_size_msb_c  : natural := 30; -- transfer size msb (10=word, 11=?)
258 
  constant ctrl_bus_rd_c        : natural := 31; -- read data request
259 
  constant ctrl_bus_wr_c        : natural := 32; -- write data request
260 
  constant ctrl_bus_if_c        : natural := 33; -- instruction fetch request
261 
  constant ctrl_bus_mo_we_c     : natural := 34; -- memory address and data output register write enable
262 
  constant ctrl_bus_mi_we_c     : natural := 35; -- memory data input register write enable
263 53 zero_gravi 
  constant ctrl_bus_unsigned_c  : natural := 36; -- is unsigned load
264 
  constant ctrl_bus_ierr_ack_c  : natural := 37; -- acknowledge instruction fetch bus exceptions
265 
  constant ctrl_bus_derr_ack_c  : natural := 38; -- acknowledge data access bus exceptions
266 
  constant ctrl_bus_fence_c     : natural := 39; -- executed fence operation
267 
  constant ctrl_bus_fencei_c    : natural := 40; -- executed fencei operation
268 57 zero_gravi 
  constant ctrl_bus_lock_c      : natural := 41; -- make atomic/exclusive access lock
269 
  constant ctrl_bus_de_lock_c   : natural := 42; -- remove atomic/exclusive access
270 
  constant ctrl_bus_ch_lock_c   : natural := 43; -- evaluate atomic/exclusive lock (SC operation)
271 26 zero_gravi 
  -- co-processors --
272 57 zero_gravi 
  constant ctrl_cp_id_lsb_c     : natural := 44; -- cp select ID lsb
273 
  constant ctrl_cp_id_hsb_c     : natural := 45; -- cp select ID
274 
  constant ctrl_cp_id_msb_c     : natural := 46; -- cp select ID msb
275 44 zero_gravi 
  -- instruction's control blocks (used by cpu co-processors) --
276 53 zero_gravi 
  constant ctrl_ir_funct3_0_c   : natural := 47; -- funct3 bit 0
277 
  constant ctrl_ir_funct3_1_c   : natural := 48; -- funct3 bit 1
278 
  constant ctrl_ir_funct3_2_c   : natural := 49; -- funct3 bit 2
279 
  constant ctrl_ir_funct12_0_c  : natural := 50; -- funct12 bit 0
280 
  constant ctrl_ir_funct12_1_c  : natural := 51; -- funct12 bit 1
281 
  constant ctrl_ir_funct12_2_c  : natural := 52; -- funct12 bit 2
282 
  constant ctrl_ir_funct12_3_c  : natural := 53; -- funct12 bit 3
283 
  constant ctrl_ir_funct12_4_c  : natural := 54; -- funct12 bit 4
284 
  constant ctrl_ir_funct12_5_c  : natural := 55; -- funct12 bit 5
285 
  constant ctrl_ir_funct12_6_c  : natural := 56; -- funct12 bit 6
286 
  constant ctrl_ir_funct12_7_c  : natural := 57; -- funct12 bit 7
287 
  constant ctrl_ir_funct12_8_c  : natural := 58; -- funct12 bit 8
288 
  constant ctrl_ir_funct12_9_c  : natural := 59; -- funct12 bit 9
289 
  constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10
290 
  constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11
291 
  constant ctrl_ir_opcode7_0_c  : natural := 62; -- opcode7 bit 0
292 
  constant ctrl_ir_opcode7_1_c  : natural := 63; -- opcode7 bit 1
293 
  constant ctrl_ir_opcode7_2_c  : natural := 64; -- opcode7 bit 2
294 
  constant ctrl_ir_opcode7_3_c  : natural := 65; -- opcode7 bit 3
295 
  constant ctrl_ir_opcode7_4_c  : natural := 66; -- opcode7 bit 4
296 
  constant ctrl_ir_opcode7_5_c  : natural := 67; -- opcode7 bit 5
297 
  constant ctrl_ir_opcode7_6_c  : natural := 68; -- opcode7 bit 6
298 47 zero_gravi 
  -- CPU status --
299 57 zero_gravi 
  constant ctrl_priv_lvl_lsb_c  : natural := 69; -- privilege level lsb
300 
  constant ctrl_priv_lvl_msb_c  : natural := 70; -- privilege level msb
301 
  constant ctrl_sleep_c         : natural := 71; -- set when CPU is in sleep mode
302 
  constant ctrl_trap_c          : natural := 72; -- set when CPU is entering trap execution
303 2 zero_gravi 
  -- control bus size --
304 57 zero_gravi 
  constant ctrl_width_c         : natural := 73; -- control bus size
305 2 zero_gravi 
 
306 47 zero_gravi 
  -- Comparator Bus -------------------------------------------------------------------------
307 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
308 47 zero_gravi 
  constant cmp_equal_c : natural := 0;
309 
  constant cmp_less_c  : natural := 1; -- for signed and unsigned comparisons
310 2 zero_gravi 
 
311 
  -- RISC-V Opcode Layout -------------------------------------------------------------------
312 
  -- -------------------------------------------------------------------------------------------
313 
  constant instr_opcode_lsb_c  : natural :=  0; -- opcode bit 0
314 
  constant instr_opcode_msb_c  : natural :=  6; -- opcode bit 6
315 
  constant instr_rd_lsb_c      : natural :=  7; -- destination register address bit 0
316 
  constant instr_rd_msb_c      : natural := 11; -- destination register address bit 4
317 
  constant instr_funct3_lsb_c  : natural := 12; -- funct3 bit 0
318 
  constant instr_funct3_msb_c  : natural := 14; -- funct3 bit 2
319 
  constant instr_rs1_lsb_c     : natural := 15; -- source register 1 address bit 0
320 
  constant instr_rs1_msb_c     : natural := 19; -- source register 1 address bit 4
321 
  constant instr_rs2_lsb_c     : natural := 20; -- source register 2 address bit 0
322 
  constant instr_rs2_msb_c     : natural := 24; -- source register 2 address bit 4
323 
  constant instr_funct7_lsb_c  : natural := 25; -- funct7 bit 0
324 
  constant instr_funct7_msb_c  : natural := 31; -- funct7 bit 6
325 
  constant instr_funct12_lsb_c : natural := 20; -- funct12 bit 0
326 
  constant instr_funct12_msb_c : natural := 31; -- funct12 bit 11
327 
  constant instr_imm12_lsb_c   : natural := 20; -- immediate12 bit 0
328 
  constant instr_imm12_msb_c   : natural := 31; -- immediate12 bit 11
329 
  constant instr_imm20_lsb_c   : natural := 12; -- immediate20 bit 0
330 
  constant instr_imm20_msb_c   : natural := 31; -- immediate20 bit 21
331 
  constant instr_csr_id_lsb_c  : natural := 20; -- csr select bit 0
332 
  constant instr_csr_id_msb_c  : natural := 31; -- csr select bit 11
333 39 zero_gravi 
  constant instr_funct5_lsb_c  : natural := 27; -- funct5 select bit 0
334 
  constant instr_funct5_msb_c  : natural := 31; -- funct5 select bit 4
335 2 zero_gravi 
 
336 
  -- RISC-V Opcodes -------------------------------------------------------------------------
337 
  -- -------------------------------------------------------------------------------------------
338 
  -- alu --
339 
  constant opcode_lui_c    : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate
340 
  constant opcode_auipc_c  : std_ulogic_vector(6 downto 0) := "0010111"; -- add upper immediate to PC
341 
  constant opcode_alui_c   : std_ulogic_vector(6 downto 0) := "0010011"; -- ALU operation with immediate (operation via funct3 and funct7)
342 
  constant opcode_alu_c    : std_ulogic_vector(6 downto 0) := "0110011"; -- ALU operation (operation via funct3 and funct7)
343 
  -- control flow --
344 
  constant opcode_jal_c    : std_ulogic_vector(6 downto 0) := "1101111"; -- jump and link
345 29 zero_gravi 
  constant opcode_jalr_c   : std_ulogic_vector(6 downto 0) := "1100111"; -- jump and link with register
346 2 zero_gravi 
  constant opcode_branch_c : std_ulogic_vector(6 downto 0) := "1100011"; -- branch (condition set via funct3)
347 
  -- memory access --
348 
  constant opcode_load_c   : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)
349 
  constant opcode_store_c  : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)
350 
  -- system/csr --
351 8 zero_gravi 
  constant opcode_fence_c  : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
352 2 zero_gravi 
  constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
353 52 zero_gravi 
  -- atomic memory access (A) --
354 39 zero_gravi 
  constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)
355 53 zero_gravi 
  -- floating point operations (Zfinx-only) (F/D/H/Q) --
356 
  constant opcode_fop_c    : std_ulogic_vector(6 downto 0) := "1010011"; -- dual/single opearand instruction
357 2 zero_gravi 
 
358 
  -- RISC-V Funct3 --------------------------------------------------------------------------
359 
  -- -------------------------------------------------------------------------------------------
360 
  -- control flow --
361 
  constant funct3_beq_c    : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
362 
  constant funct3_bne_c    : std_ulogic_vector(2 downto 0) := "001"; -- branch if not equal
363 
  constant funct3_blt_c    : std_ulogic_vector(2 downto 0) := "100"; -- branch if less than
364 
  constant funct3_bge_c    : std_ulogic_vector(2 downto 0) := "101"; -- branch if greater than or equal
365 
  constant funct3_bltu_c   : std_ulogic_vector(2 downto 0) := "110"; -- branch if less than (unsigned)
366 
  constant funct3_bgeu_c   : std_ulogic_vector(2 downto 0) := "111"; -- branch if greater than or equal (unsigned)
367 
  -- memory access --
368 
  constant funct3_lb_c     : std_ulogic_vector(2 downto 0) := "000"; -- load byte
369 
  constant funct3_lh_c     : std_ulogic_vector(2 downto 0) := "001"; -- load half word
370 
  constant funct3_lw_c     : std_ulogic_vector(2 downto 0) := "010"; -- load word
371 
  constant funct3_lbu_c    : std_ulogic_vector(2 downto 0) := "100"; -- load byte (unsigned)
372 
  constant funct3_lhu_c    : std_ulogic_vector(2 downto 0) := "101"; -- load half word (unsigned)
373 
  constant funct3_sb_c     : std_ulogic_vector(2 downto 0) := "000"; -- store byte
374 
  constant funct3_sh_c     : std_ulogic_vector(2 downto 0) := "001"; -- store half word
375 
  constant funct3_sw_c     : std_ulogic_vector(2 downto 0) := "010"; -- store word
376 
  -- alu --
377 
  constant funct3_subadd_c : std_ulogic_vector(2 downto 0) := "000"; -- sub/add via funct7
378 
  constant funct3_sll_c    : std_ulogic_vector(2 downto 0) := "001"; -- shift logical left
379 
  constant funct3_slt_c    : std_ulogic_vector(2 downto 0) := "010"; -- set on less
380 
  constant funct3_sltu_c   : std_ulogic_vector(2 downto 0) := "011"; -- set on less unsigned
381 
  constant funct3_xor_c    : std_ulogic_vector(2 downto 0) := "100"; -- xor
382 
  constant funct3_sr_c     : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7
383 
  constant funct3_or_c     : std_ulogic_vector(2 downto 0) := "110"; -- or
384 
  constant funct3_and_c    : std_ulogic_vector(2 downto 0) := "111"; -- and
385 
  -- system/csr --
386 
  constant funct3_env_c    : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi
387 
  constant funct3_csrrw_c  : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w
388 
  constant funct3_csrrs_c  : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit
389 
  constant funct3_csrrc_c  : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit
390 
  constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate
391 
  constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate
392 
  constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
393 8 zero_gravi 
  -- fence --
394 
  constant funct3_fence_c  : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
395 
  constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync
396 2 zero_gravi 
 
397 39 zero_gravi 
  -- RISC-V Funct12 -------------------------------------------------------------------------
398 11 zero_gravi 
  -- -------------------------------------------------------------------------------------------
399 
  -- system --
400 
  constant funct12_ecall_c  : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
401 
  constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
402 
  constant funct12_mret_c   : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
403 
  constant funct12_wfi_c    : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
404 
 
405 39 zero_gravi 
  -- RISC-V Funct5 --------------------------------------------------------------------------
406 
  -- -------------------------------------------------------------------------------------------
407 
  -- atomic operations --
408 
  constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR
409 
  constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC
410 
 
411 54 zero_gravi 
  -- RISC-V Floating-Point Stuff ------------------------------------------------------------
412 52 zero_gravi 
  -- -------------------------------------------------------------------------------------------
413 54 zero_gravi 
  -- formats --
414 
  constant float_single_c : std_ulogic_vector(1 downto 0) := "00"; -- single-precision (32-bit)
415 
  constant float_double_c : std_ulogic_vector(1 downto 0) := "01"; -- double-precision (64-bit)
416 
  constant float_half_c   : std_ulogic_vector(1 downto 0) := "10"; -- half-precision (16-bit)
417 
  constant float_quad_c   : std_ulogic_vector(1 downto 0) := "11"; -- quad-precision (128-bit)
418 52 zero_gravi 
 
419 54 zero_gravi 
  -- number class flags --
420 
  constant fp_class_neg_inf_c    : natural := 0; -- negative infinity
421 
  constant fp_class_neg_norm_c   : natural := 1; -- negative normal number
422 
  constant fp_class_neg_denorm_c : natural := 2; -- negative subnormal number
423 
  constant fp_class_neg_zero_c   : natural := 3; -- negative zero
424 
  constant fp_class_pos_zero_c   : natural := 4; -- positive zero
425 
  constant fp_class_pos_denorm_c : natural := 5; -- positive subnormal number
426 
  constant fp_class_pos_norm_c   : natural := 6; -- positive normal number
427 
  constant fp_class_pos_inf_c    : natural := 7; -- positive infinity
428 
  constant fp_class_snan_c       : natural := 8; -- signaling NaN (sNaN)
429 
  constant fp_class_qnan_c       : natural := 9; -- quiet NaN (qNaN)
430 
 
431 
  -- exception flags --
432 
  constant fp_exc_nv_c : natural := 0; -- invalid operation
433 
  constant fp_exc_dz_c : natural := 1; -- divide by zero
434 
  constant fp_exc_of_c : natural := 2; -- overflow
435 
  constant fp_exc_uf_c : natural := 3; -- underflow
436 
  constant fp_exc_nx_c : natural := 4; -- inexact
437 
 
438 
  -- special values (single-precision) --
439 
  constant fp_single_qnan_c     : std_ulogic_vector(31 downto 0) := x"7fc00000"; -- quiet NaN
440 
  constant fp_single_snan_c     : std_ulogic_vector(31 downto 0) := x"7fa00000"; -- signaling NaN
441 
  constant fp_single_pos_inf_c  : std_ulogic_vector(31 downto 0) := x"7f800000"; -- positive infinity
442 
  constant fp_single_neg_inf_c  : std_ulogic_vector(31 downto 0) := x"ff800000"; -- negative infinity
443 
  constant fp_single_pos_zero_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- positive zero
444 
  constant fp_single_neg_zero_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- negative zero
445 
 
446 29 zero_gravi 
  -- RISC-V CSR Addresses -------------------------------------------------------------------
447 
  -- -------------------------------------------------------------------------------------------
448 56 zero_gravi 
  -- <<< standard read/write CSRs >>> --
449 
  -- user floating-point CSRs --
450 52 zero_gravi 
  constant csr_class_float_c    : std_ulogic_vector(07 downto 0) := x"00"; -- floating point
451 
  constant csr_fflags_c         : std_ulogic_vector(11 downto 0) := x"001";
452 
  constant csr_frm_c            : std_ulogic_vector(11 downto 0) := x"002";
453 
  constant csr_fcsr_c           : std_ulogic_vector(11 downto 0) := x"003";
454 56 zero_gravi 
  -- machine trap setup --
455 
  constant csr_class_setup_c    : std_ulogic_vector(07 downto 0) := x"30"; -- trap setup
456 42 zero_gravi 
  constant csr_mstatus_c        : std_ulogic_vector(11 downto 0) := x"300";
457 
  constant csr_misa_c           : std_ulogic_vector(11 downto 0) := x"301";
458 
  constant csr_mie_c            : std_ulogic_vector(11 downto 0) := x"304";
459 
  constant csr_mtvec_c          : std_ulogic_vector(11 downto 0) := x"305";
460 
  constant csr_mcounteren_c     : std_ulogic_vector(11 downto 0) := x"306";
461 
  constant csr_mstatush_c       : std_ulogic_vector(11 downto 0) := x"310";
462 56 zero_gravi 
  -- machine counter setup --
463 
  constant csr_cnt_setup_c      : std_ulogic_vector(06 downto 0) := x"3" & "001"; -- counter setup
464 42 zero_gravi 
  constant csr_mcountinhibit_c  : std_ulogic_vector(11 downto 0) := x"320";
465 
  constant csr_mhpmevent3_c     : std_ulogic_vector(11 downto 0) := x"323";
466 
  constant csr_mhpmevent4_c     : std_ulogic_vector(11 downto 0) := x"324";
467 
  constant csr_mhpmevent5_c     : std_ulogic_vector(11 downto 0) := x"325";
468 
  constant csr_mhpmevent6_c     : std_ulogic_vector(11 downto 0) := x"326";
469 
  constant csr_mhpmevent7_c     : std_ulogic_vector(11 downto 0) := x"327";
470 
  constant csr_mhpmevent8_c     : std_ulogic_vector(11 downto 0) := x"328";
471 
  constant csr_mhpmevent9_c     : std_ulogic_vector(11 downto 0) := x"329";
472 
  constant csr_mhpmevent10_c    : std_ulogic_vector(11 downto 0) := x"32a";
473 
  constant csr_mhpmevent11_c    : std_ulogic_vector(11 downto 0) := x"32b";
474 
  constant csr_mhpmevent12_c    : std_ulogic_vector(11 downto 0) := x"32c";
475 
  constant csr_mhpmevent13_c    : std_ulogic_vector(11 downto 0) := x"32d";
476 
  constant csr_mhpmevent14_c    : std_ulogic_vector(11 downto 0) := x"32e";
477 
  constant csr_mhpmevent15_c    : std_ulogic_vector(11 downto 0) := x"32f";
478 
  constant csr_mhpmevent16_c    : std_ulogic_vector(11 downto 0) := x"330";
479 
  constant csr_mhpmevent17_c    : std_ulogic_vector(11 downto 0) := x"331";
480 
  constant csr_mhpmevent18_c    : std_ulogic_vector(11 downto 0) := x"332";
481 
  constant csr_mhpmevent19_c    : std_ulogic_vector(11 downto 0) := x"333";
482 
  constant csr_mhpmevent20_c    : std_ulogic_vector(11 downto 0) := x"334";
483 
  constant csr_mhpmevent21_c    : std_ulogic_vector(11 downto 0) := x"335";
484 
  constant csr_mhpmevent22_c    : std_ulogic_vector(11 downto 0) := x"336";
485 
  constant csr_mhpmevent23_c    : std_ulogic_vector(11 downto 0) := x"337";
486 
  constant csr_mhpmevent24_c    : std_ulogic_vector(11 downto 0) := x"338";
487 
  constant csr_mhpmevent25_c    : std_ulogic_vector(11 downto 0) := x"339";
488 
  constant csr_mhpmevent26_c    : std_ulogic_vector(11 downto 0) := x"33a";
489 
  constant csr_mhpmevent27_c    : std_ulogic_vector(11 downto 0) := x"33b";
490 
  constant csr_mhpmevent28_c    : std_ulogic_vector(11 downto 0) := x"33c";
491 
  constant csr_mhpmevent29_c    : std_ulogic_vector(11 downto 0) := x"33d";
492 
  constant csr_mhpmevent30_c    : std_ulogic_vector(11 downto 0) := x"33e";
493 
  constant csr_mhpmevent31_c    : std_ulogic_vector(11 downto 0) := x"33f";
494 56 zero_gravi 
  -- machine trap handling --
495 52 zero_gravi 
  constant csr_class_trap_c     : std_ulogic_vector(07 downto 0) := x"34"; -- machine trap handling
496 42 zero_gravi 
  constant csr_mscratch_c       : std_ulogic_vector(11 downto 0) := x"340";
497 
  constant csr_mepc_c           : std_ulogic_vector(11 downto 0) := x"341";
498 
  constant csr_mcause_c         : std_ulogic_vector(11 downto 0) := x"342";
499 
  constant csr_mtval_c          : std_ulogic_vector(11 downto 0) := x"343";
500 
  constant csr_mip_c            : std_ulogic_vector(11 downto 0) := x"344";
501 56 zero_gravi 
  -- physical memory protection - configuration --
502 52 zero_gravi 
  constant csr_class_pmpcfg_c   : std_ulogic_vector(07 downto 0) := x"3a"; -- pmp configuration
503 42 zero_gravi 
  constant csr_pmpcfg0_c        : std_ulogic_vector(11 downto 0) := x"3a0";
504 
  constant csr_pmpcfg1_c        : std_ulogic_vector(11 downto 0) := x"3a1";
505 
  constant csr_pmpcfg2_c        : std_ulogic_vector(11 downto 0) := x"3a2";
506 
  constant csr_pmpcfg3_c        : std_ulogic_vector(11 downto 0) := x"3a3";
507 
  constant csr_pmpcfg4_c        : std_ulogic_vector(11 downto 0) := x"3a4";
508 
  constant csr_pmpcfg5_c        : std_ulogic_vector(11 downto 0) := x"3a5";
509 
  constant csr_pmpcfg6_c        : std_ulogic_vector(11 downto 0) := x"3a6";
510 
  constant csr_pmpcfg7_c        : std_ulogic_vector(11 downto 0) := x"3a7";
511 
  constant csr_pmpcfg8_c        : std_ulogic_vector(11 downto 0) := x"3a8";
512 
  constant csr_pmpcfg9_c        : std_ulogic_vector(11 downto 0) := x"3a9";
513 
  constant csr_pmpcfg10_c       : std_ulogic_vector(11 downto 0) := x"3aa";
514 
  constant csr_pmpcfg11_c       : std_ulogic_vector(11 downto 0) := x"3ab";
515 
  constant csr_pmpcfg12_c       : std_ulogic_vector(11 downto 0) := x"3ac";
516 
  constant csr_pmpcfg13_c       : std_ulogic_vector(11 downto 0) := x"3ad";
517 
  constant csr_pmpcfg14_c       : std_ulogic_vector(11 downto 0) := x"3ae";
518 
  constant csr_pmpcfg15_c       : std_ulogic_vector(11 downto 0) := x"3af";
519 56 zero_gravi 
  -- physical memory protection - address --
520 42 zero_gravi 
  constant csr_pmpaddr0_c       : std_ulogic_vector(11 downto 0) := x"3b0";
521 
  constant csr_pmpaddr1_c       : std_ulogic_vector(11 downto 0) := x"3b1";
522 
  constant csr_pmpaddr2_c       : std_ulogic_vector(11 downto 0) := x"3b2";
523 
  constant csr_pmpaddr3_c       : std_ulogic_vector(11 downto 0) := x"3b3";
524 
  constant csr_pmpaddr4_c       : std_ulogic_vector(11 downto 0) := x"3b4";
525 
  constant csr_pmpaddr5_c       : std_ulogic_vector(11 downto 0) := x"3b5";
526 
  constant csr_pmpaddr6_c       : std_ulogic_vector(11 downto 0) := x"3b6";
527 
  constant csr_pmpaddr7_c       : std_ulogic_vector(11 downto 0) := x"3b7";
528 
  constant csr_pmpaddr8_c       : std_ulogic_vector(11 downto 0) := x"3b8";
529 
  constant csr_pmpaddr9_c       : std_ulogic_vector(11 downto 0) := x"3b9";
530 
  constant csr_pmpaddr10_c      : std_ulogic_vector(11 downto 0) := x"3ba";
531 
  constant csr_pmpaddr11_c      : std_ulogic_vector(11 downto 0) := x"3bb";
532 
  constant csr_pmpaddr12_c      : std_ulogic_vector(11 downto 0) := x"3bc";
533 
  constant csr_pmpaddr13_c      : std_ulogic_vector(11 downto 0) := x"3bd";
534 
  constant csr_pmpaddr14_c      : std_ulogic_vector(11 downto 0) := x"3be";
535 
  constant csr_pmpaddr15_c      : std_ulogic_vector(11 downto 0) := x"3bf";
536 
  constant csr_pmpaddr16_c      : std_ulogic_vector(11 downto 0) := x"3c0";
537 
  constant csr_pmpaddr17_c      : std_ulogic_vector(11 downto 0) := x"3c1";
538 
  constant csr_pmpaddr18_c      : std_ulogic_vector(11 downto 0) := x"3c2";
539 
  constant csr_pmpaddr19_c      : std_ulogic_vector(11 downto 0) := x"3c3";
540 
  constant csr_pmpaddr20_c      : std_ulogic_vector(11 downto 0) := x"3c4";
541 
  constant csr_pmpaddr21_c      : std_ulogic_vector(11 downto 0) := x"3c5";
542 
  constant csr_pmpaddr22_c      : std_ulogic_vector(11 downto 0) := x"3c6";
543 
  constant csr_pmpaddr23_c      : std_ulogic_vector(11 downto 0) := x"3c7";
544 
  constant csr_pmpaddr24_c      : std_ulogic_vector(11 downto 0) := x"3c8";
545 
  constant csr_pmpaddr25_c      : std_ulogic_vector(11 downto 0) := x"3c9";
546 
  constant csr_pmpaddr26_c      : std_ulogic_vector(11 downto 0) := x"3ca";
547 
  constant csr_pmpaddr27_c      : std_ulogic_vector(11 downto 0) := x"3cb";
548 
  constant csr_pmpaddr28_c      : std_ulogic_vector(11 downto 0) := x"3cc";
549 
  constant csr_pmpaddr29_c      : std_ulogic_vector(11 downto 0) := x"3cd";
550 
  constant csr_pmpaddr30_c      : std_ulogic_vector(11 downto 0) := x"3ce";
551 
  constant csr_pmpaddr31_c      : std_ulogic_vector(11 downto 0) := x"3cf";
552 
  constant csr_pmpaddr32_c      : std_ulogic_vector(11 downto 0) := x"3d0";
553 
  constant csr_pmpaddr33_c      : std_ulogic_vector(11 downto 0) := x"3d1";
554 
  constant csr_pmpaddr34_c      : std_ulogic_vector(11 downto 0) := x"3d2";
555 
  constant csr_pmpaddr35_c      : std_ulogic_vector(11 downto 0) := x"3d3";
556 
  constant csr_pmpaddr36_c      : std_ulogic_vector(11 downto 0) := x"3d4";
557 
  constant csr_pmpaddr37_c      : std_ulogic_vector(11 downto 0) := x"3d5";
558 
  constant csr_pmpaddr38_c      : std_ulogic_vector(11 downto 0) := x"3d6";
559 
  constant csr_pmpaddr39_c      : std_ulogic_vector(11 downto 0) := x"3d7";
560 
  constant csr_pmpaddr40_c      : std_ulogic_vector(11 downto 0) := x"3d8";
561 
  constant csr_pmpaddr41_c      : std_ulogic_vector(11 downto 0) := x"3d9";
562 
  constant csr_pmpaddr42_c      : std_ulogic_vector(11 downto 0) := x"3da";
563 
  constant csr_pmpaddr43_c      : std_ulogic_vector(11 downto 0) := x"3db";
564 
  constant csr_pmpaddr44_c      : std_ulogic_vector(11 downto 0) := x"3dc";
565 
  constant csr_pmpaddr45_c      : std_ulogic_vector(11 downto 0) := x"3dd";
566 
  constant csr_pmpaddr46_c      : std_ulogic_vector(11 downto 0) := x"3de";
567 
  constant csr_pmpaddr47_c      : std_ulogic_vector(11 downto 0) := x"3df";
568 
  constant csr_pmpaddr48_c      : std_ulogic_vector(11 downto 0) := x"3e0";
569 
  constant csr_pmpaddr49_c      : std_ulogic_vector(11 downto 0) := x"3e1";
570 
  constant csr_pmpaddr50_c      : std_ulogic_vector(11 downto 0) := x"3e2";
571 
  constant csr_pmpaddr51_c      : std_ulogic_vector(11 downto 0) := x"3e3";
572 
  constant csr_pmpaddr52_c      : std_ulogic_vector(11 downto 0) := x"3e4";
573 
  constant csr_pmpaddr53_c      : std_ulogic_vector(11 downto 0) := x"3e5";
574 
  constant csr_pmpaddr54_c      : std_ulogic_vector(11 downto 0) := x"3e6";
575 
  constant csr_pmpaddr55_c      : std_ulogic_vector(11 downto 0) := x"3e7";
576 
  constant csr_pmpaddr56_c      : std_ulogic_vector(11 downto 0) := x"3e8";
577 
  constant csr_pmpaddr57_c      : std_ulogic_vector(11 downto 0) := x"3e9";
578 
  constant csr_pmpaddr58_c      : std_ulogic_vector(11 downto 0) := x"3ea";
579 
  constant csr_pmpaddr59_c      : std_ulogic_vector(11 downto 0) := x"3eb";
580 
  constant csr_pmpaddr60_c      : std_ulogic_vector(11 downto 0) := x"3ec";
581 
  constant csr_pmpaddr61_c      : std_ulogic_vector(11 downto 0) := x"3ed";
582 
  constant csr_pmpaddr62_c      : std_ulogic_vector(11 downto 0) := x"3ee";
583 
  constant csr_pmpaddr63_c      : std_ulogic_vector(11 downto 0) := x"3ef";
584 56 zero_gravi 
  -- machine counters/timers --
585 42 zero_gravi 
  constant csr_mcycle_c         : std_ulogic_vector(11 downto 0) := x"b00";
586 
  constant csr_minstret_c       : std_ulogic_vector(11 downto 0) := x"b02";
587 
  --
588 
  constant csr_mhpmcounter3_c   : std_ulogic_vector(11 downto 0) := x"b03";
589 
  constant csr_mhpmcounter4_c   : std_ulogic_vector(11 downto 0) := x"b04";
590 
  constant csr_mhpmcounter5_c   : std_ulogic_vector(11 downto 0) := x"b05";
591 
  constant csr_mhpmcounter6_c   : std_ulogic_vector(11 downto 0) := x"b06";
592 
  constant csr_mhpmcounter7_c   : std_ulogic_vector(11 downto 0) := x"b07";
593 
  constant csr_mhpmcounter8_c   : std_ulogic_vector(11 downto 0) := x"b08";
594 
  constant csr_mhpmcounter9_c   : std_ulogic_vector(11 downto 0) := x"b09";
595 
  constant csr_mhpmcounter10_c  : std_ulogic_vector(11 downto 0) := x"b0a";
596 
  constant csr_mhpmcounter11_c  : std_ulogic_vector(11 downto 0) := x"b0b";
597 
  constant csr_mhpmcounter12_c  : std_ulogic_vector(11 downto 0) := x"b0c";
598 
  constant csr_mhpmcounter13_c  : std_ulogic_vector(11 downto 0) := x"b0d";
599 
  constant csr_mhpmcounter14_c  : std_ulogic_vector(11 downto 0) := x"b0e";
600 
  constant csr_mhpmcounter15_c  : std_ulogic_vector(11 downto 0) := x"b0f";
601 
  constant csr_mhpmcounter16_c  : std_ulogic_vector(11 downto 0) := x"b10";
602 
  constant csr_mhpmcounter17_c  : std_ulogic_vector(11 downto 0) := x"b11";
603 
  constant csr_mhpmcounter18_c  : std_ulogic_vector(11 downto 0) := x"b12";
604 
  constant csr_mhpmcounter19_c  : std_ulogic_vector(11 downto 0) := x"b13";
605 
  constant csr_mhpmcounter20_c  : std_ulogic_vector(11 downto 0) := x"b14";
606 
  constant csr_mhpmcounter21_c  : std_ulogic_vector(11 downto 0) := x"b15";
607 
  constant csr_mhpmcounter22_c  : std_ulogic_vector(11 downto 0) := x"b16";
608 
  constant csr_mhpmcounter23_c  : std_ulogic_vector(11 downto 0) := x"b17";
609 
  constant csr_mhpmcounter24_c  : std_ulogic_vector(11 downto 0) := x"b18";
610 
  constant csr_mhpmcounter25_c  : std_ulogic_vector(11 downto 0) := x"b19";
611 
  constant csr_mhpmcounter26_c  : std_ulogic_vector(11 downto 0) := x"b1a";
612 
  constant csr_mhpmcounter27_c  : std_ulogic_vector(11 downto 0) := x"b1b";
613 
  constant csr_mhpmcounter28_c  : std_ulogic_vector(11 downto 0) := x"b1c";
614 
  constant csr_mhpmcounter29_c  : std_ulogic_vector(11 downto 0) := x"b1d";
615 
  constant csr_mhpmcounter30_c  : std_ulogic_vector(11 downto 0) := x"b1e";
616 
  constant csr_mhpmcounter31_c  : std_ulogic_vector(11 downto 0) := x"b1f";
617 
  --
618 
  constant csr_mcycleh_c        : std_ulogic_vector(11 downto 0) := x"b80";
619 
  constant csr_minstreth_c      : std_ulogic_vector(11 downto 0) := x"b82";
620 
  --
621 
  constant csr_mhpmcounter3h_c  : std_ulogic_vector(11 downto 0) := x"b83";
622 
  constant csr_mhpmcounter4h_c  : std_ulogic_vector(11 downto 0) := x"b84";
623 
  constant csr_mhpmcounter5h_c  : std_ulogic_vector(11 downto 0) := x"b85";
624 
  constant csr_mhpmcounter6h_c  : std_ulogic_vector(11 downto 0) := x"b86";
625 
  constant csr_mhpmcounter7h_c  : std_ulogic_vector(11 downto 0) := x"b87";
626 
  constant csr_mhpmcounter8h_c  : std_ulogic_vector(11 downto 0) := x"b88";
627 
  constant csr_mhpmcounter9h_c  : std_ulogic_vector(11 downto 0) := x"b89";
628 
  constant csr_mhpmcounter10h_c : std_ulogic_vector(11 downto 0) := x"b8a";
629 
  constant csr_mhpmcounter11h_c : std_ulogic_vector(11 downto 0) := x"b8b";
630 
  constant csr_mhpmcounter12h_c : std_ulogic_vector(11 downto 0) := x"b8c";
631 
  constant csr_mhpmcounter13h_c : std_ulogic_vector(11 downto 0) := x"b8d";
632 
  constant csr_mhpmcounter14h_c : std_ulogic_vector(11 downto 0) := x"b8e";
633 
  constant csr_mhpmcounter15h_c : std_ulogic_vector(11 downto 0) := x"b8f";
634 
  constant csr_mhpmcounter16h_c : std_ulogic_vector(11 downto 0) := x"b90";
635 
  constant csr_mhpmcounter17h_c : std_ulogic_vector(11 downto 0) := x"b91";
636 
  constant csr_mhpmcounter18h_c : std_ulogic_vector(11 downto 0) := x"b92";
637 
  constant csr_mhpmcounter19h_c : std_ulogic_vector(11 downto 0) := x"b93";
638 
  constant csr_mhpmcounter20h_c : std_ulogic_vector(11 downto 0) := x"b94";
639 
  constant csr_mhpmcounter21h_c : std_ulogic_vector(11 downto 0) := x"b95";
640 
  constant csr_mhpmcounter22h_c : std_ulogic_vector(11 downto 0) := x"b96";
641 
  constant csr_mhpmcounter23h_c : std_ulogic_vector(11 downto 0) := x"b97";
642 
  constant csr_mhpmcounter24h_c : std_ulogic_vector(11 downto 0) := x"b98";
643 
  constant csr_mhpmcounter25h_c : std_ulogic_vector(11 downto 0) := x"b99";
644 
  constant csr_mhpmcounter26h_c : std_ulogic_vector(11 downto 0) := x"b9a";
645 
  constant csr_mhpmcounter27h_c : std_ulogic_vector(11 downto 0) := x"b9b";
646 
  constant csr_mhpmcounter28h_c : std_ulogic_vector(11 downto 0) := x"b9c";
647 
  constant csr_mhpmcounter29h_c : std_ulogic_vector(11 downto 0) := x"b9d";
648 
  constant csr_mhpmcounter30h_c : std_ulogic_vector(11 downto 0) := x"b9e";
649 
  constant csr_mhpmcounter31h_c : std_ulogic_vector(11 downto 0) := x"b9f";
650 
 
651 56 zero_gravi 
  -- <<< standard read-only CSRs >>> --
652 
  -- user counters/timers --
653 42 zero_gravi 
  constant csr_cycle_c          : std_ulogic_vector(11 downto 0) := x"c00";
654 
  constant csr_time_c           : std_ulogic_vector(11 downto 0) := x"c01";
655 
  constant csr_instret_c        : std_ulogic_vector(11 downto 0) := x"c02";
656 29 zero_gravi 
  --
657 42 zero_gravi 
  constant csr_hpmcounter3_c    : std_ulogic_vector(11 downto 0) := x"c03";
658 
  constant csr_hpmcounter4_c    : std_ulogic_vector(11 downto 0) := x"c04";
659 
  constant csr_hpmcounter5_c    : std_ulogic_vector(11 downto 0) := x"c05";
660 
  constant csr_hpmcounter6_c    : std_ulogic_vector(11 downto 0) := x"c06";
661 
  constant csr_hpmcounter7_c    : std_ulogic_vector(11 downto 0) := x"c07";
662 
  constant csr_hpmcounter8_c    : std_ulogic_vector(11 downto 0) := x"c08";
663 
  constant csr_hpmcounter9_c    : std_ulogic_vector(11 downto 0) := x"c09";
664 
  constant csr_hpmcounter10_c   : std_ulogic_vector(11 downto 0) := x"c0a";
665 
  constant csr_hpmcounter11_c   : std_ulogic_vector(11 downto 0) := x"c0b";
666 
  constant csr_hpmcounter12_c   : std_ulogic_vector(11 downto 0) := x"c0c";
667 
  constant csr_hpmcounter13_c   : std_ulogic_vector(11 downto 0) := x"c0d";
668 
  constant csr_hpmcounter14_c   : std_ulogic_vector(11 downto 0) := x"c0e";
669 
  constant csr_hpmcounter15_c   : std_ulogic_vector(11 downto 0) := x"c0f";
670 
  constant csr_hpmcounter16_c   : std_ulogic_vector(11 downto 0) := x"c10";
671 
  constant csr_hpmcounter17_c   : std_ulogic_vector(11 downto 0) := x"c11";
672 
  constant csr_hpmcounter18_c   : std_ulogic_vector(11 downto 0) := x"c12";
673 
  constant csr_hpmcounter19_c   : std_ulogic_vector(11 downto 0) := x"c13";
674 
  constant csr_hpmcounter20_c   : std_ulogic_vector(11 downto 0) := x"c14";
675 
  constant csr_hpmcounter21_c   : std_ulogic_vector(11 downto 0) := x"c15";
676 
  constant csr_hpmcounter22_c   : std_ulogic_vector(11 downto 0) := x"c16";
677 
  constant csr_hpmcounter23_c   : std_ulogic_vector(11 downto 0) := x"c17";
678 
  constant csr_hpmcounter24_c   : std_ulogic_vector(11 downto 0) := x"c18";
679 
  constant csr_hpmcounter25_c   : std_ulogic_vector(11 downto 0) := x"c19";
680 
  constant csr_hpmcounter26_c   : std_ulogic_vector(11 downto 0) := x"c1a";
681 
  constant csr_hpmcounter27_c   : std_ulogic_vector(11 downto 0) := x"c1b";
682 
  constant csr_hpmcounter28_c   : std_ulogic_vector(11 downto 0) := x"c1c";
683 
  constant csr_hpmcounter29_c   : std_ulogic_vector(11 downto 0) := x"c1d";
684 
  constant csr_hpmcounter30_c   : std_ulogic_vector(11 downto 0) := x"c1e";
685 
  constant csr_hpmcounter31_c   : std_ulogic_vector(11 downto 0) := x"c1f";
686 29 zero_gravi 
  --
687 42 zero_gravi 
  constant csr_cycleh_c         : std_ulogic_vector(11 downto 0) := x"c80";
688 
  constant csr_timeh_c          : std_ulogic_vector(11 downto 0) := x"c81";
689 
  constant csr_instreth_c       : std_ulogic_vector(11 downto 0) := x"c82";
690 29 zero_gravi 
  --
691 42 zero_gravi 
  constant csr_hpmcounter3h_c   : std_ulogic_vector(11 downto 0) := x"c83";
692 
  constant csr_hpmcounter4h_c   : std_ulogic_vector(11 downto 0) := x"c84";
693 
  constant csr_hpmcounter5h_c   : std_ulogic_vector(11 downto 0) := x"c85";
694 
  constant csr_hpmcounter6h_c   : std_ulogic_vector(11 downto 0) := x"c86";
695 
  constant csr_hpmcounter7h_c   : std_ulogic_vector(11 downto 0) := x"c87";
696 
  constant csr_hpmcounter8h_c   : std_ulogic_vector(11 downto 0) := x"c88";
697 
  constant csr_hpmcounter9h_c   : std_ulogic_vector(11 downto 0) := x"c89";
698 
  constant csr_hpmcounter10h_c  : std_ulogic_vector(11 downto 0) := x"c8a";
699 
  constant csr_hpmcounter11h_c  : std_ulogic_vector(11 downto 0) := x"c8b";
700 
  constant csr_hpmcounter12h_c  : std_ulogic_vector(11 downto 0) := x"c8c";
701 
  constant csr_hpmcounter13h_c  : std_ulogic_vector(11 downto 0) := x"c8d";
702 
  constant csr_hpmcounter14h_c  : std_ulogic_vector(11 downto 0) := x"c8e";
703 
  constant csr_hpmcounter15h_c  : std_ulogic_vector(11 downto 0) := x"c8f";
704 
  constant csr_hpmcounter16h_c  : std_ulogic_vector(11 downto 0) := x"c90";
705 
  constant csr_hpmcounter17h_c  : std_ulogic_vector(11 downto 0) := x"c91";
706 
  constant csr_hpmcounter18h_c  : std_ulogic_vector(11 downto 0) := x"c92";
707 
  constant csr_hpmcounter19h_c  : std_ulogic_vector(11 downto 0) := x"c93";
708 
  constant csr_hpmcounter20h_c  : std_ulogic_vector(11 downto 0) := x"c94";
709 
  constant csr_hpmcounter21h_c  : std_ulogic_vector(11 downto 0) := x"c95";
710 
  constant csr_hpmcounter22h_c  : std_ulogic_vector(11 downto 0) := x"c96";
711 
  constant csr_hpmcounter23h_c  : std_ulogic_vector(11 downto 0) := x"c97";
712 
  constant csr_hpmcounter24h_c  : std_ulogic_vector(11 downto 0) := x"c98";
713 
  constant csr_hpmcounter25h_c  : std_ulogic_vector(11 downto 0) := x"c99";
714 
  constant csr_hpmcounter26h_c  : std_ulogic_vector(11 downto 0) := x"c9a";
715 
  constant csr_hpmcounter27h_c  : std_ulogic_vector(11 downto 0) := x"c9b";
716 
  constant csr_hpmcounter28h_c  : std_ulogic_vector(11 downto 0) := x"c9c";
717 
  constant csr_hpmcounter29h_c  : std_ulogic_vector(11 downto 0) := x"c9d";
718 
  constant csr_hpmcounter30h_c  : std_ulogic_vector(11 downto 0) := x"c9e";
719 
  constant csr_hpmcounter31h_c  : std_ulogic_vector(11 downto 0) := x"c9f";
720 56 zero_gravi 
  -- machine information registers --
721 42 zero_gravi 
  constant csr_mvendorid_c      : std_ulogic_vector(11 downto 0) := x"f11";
722 
  constant csr_marchid_c        : std_ulogic_vector(11 downto 0) := x"f12";
723 
  constant csr_mimpid_c         : std_ulogic_vector(11 downto 0) := x"f13";
724 
  constant csr_mhartid_c        : std_ulogic_vector(11 downto 0) := x"f14";
725 56 zero_gravi 
  -- <<< custom (NEORV32-specific) read-only CSRs >>> --
726 42 zero_gravi 
  constant csr_mzext_c          : std_ulogic_vector(11 downto 0) := x"fc0";
727 
 
728 44 zero_gravi 
  -- Co-Processor IDs -----------------------------------------------------------------------
729 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
730 57 zero_gravi 
  constant cp_sel_csr_rd_c   : std_ulogic_vector(2 downto 0) := "000"; -- CSR read access ('Zicsr' extension)
731 
  constant cp_sel_muldiv_c   : std_ulogic_vector(2 downto 0) := "001"; -- multiplication/division operations ('M' extension)
732 49 zero_gravi 
  constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- bit manipulation ('B' extension)
733 57 zero_gravi 
  constant cp_sel_fpu_c      : std_ulogic_vector(2 downto 0) := "011"; -- floating-point unit ('Zfinx' extension)
734 
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "100"; -- reserved
735 
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "101"; -- reserved
736 52 zero_gravi 
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "110"; -- reserved
737 
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "111"; -- reserved
738 2 zero_gravi 
 
739 
  -- ALU Function Codes ---------------------------------------------------------------------
740 
  -- -------------------------------------------------------------------------------------------
741 39 zero_gravi 
  -- arithmetic core --
742 
  constant alu_arith_cmd_addsub_c : std_ulogic := '0'; -- r.arith <= A +/- B
743 
  constant alu_arith_cmd_slt_c    : std_ulogic := '1'; -- r.arith <= A < B
744 
  -- logic core --
745 
  constant alu_logic_cmd_movb_c   : std_ulogic_vector(1 downto 0) := "00"; -- r.logic <= B
746 
  constant alu_logic_cmd_xor_c    : std_ulogic_vector(1 downto 0) := "01"; -- r.logic <= A xor B
747 
  constant alu_logic_cmd_or_c     : std_ulogic_vector(1 downto 0) := "10"; -- r.logic <= A or B
748 
  constant alu_logic_cmd_and_c    : std_ulogic_vector(1 downto 0) := "11"; -- r.logic <= A and B
749 
  -- function select (actual alu result) --
750 
  constant alu_func_cmd_arith_c   : std_ulogic_vector(1 downto 0) := "00"; -- r <= r.arith
751 
  constant alu_func_cmd_logic_c   : std_ulogic_vector(1 downto 0) := "01"; -- r <= r.logic
752 
  constant alu_func_cmd_shift_c   : std_ulogic_vector(1 downto 0) := "10"; -- r <= A <</>> B (iterative)
753 
  constant alu_func_cmd_copro_c   : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (iterative)
754 2 zero_gravi 
 
755 12 zero_gravi 
  -- Trap ID Codes --------------------------------------------------------------------------
756 
  -- -------------------------------------------------------------------------------------------
757 48 zero_gravi 
  -- RISC-V compliant sync. exceptions --
758 
  constant trap_ima_c    : std_ulogic_vector(5 downto 0) := "0" & "00000"; -- 0.0:  instruction misaligned
759 
  constant trap_iba_c    : std_ulogic_vector(5 downto 0) := "0" & "00001"; -- 0.1:  instruction access fault
760 
  constant trap_iil_c    : std_ulogic_vector(5 downto 0) := "0" & "00010"; -- 0.2:  illegal instruction
761 
  constant trap_brk_c    : std_ulogic_vector(5 downto 0) := "0" & "00011"; -- 0.3:  breakpoint
762 
  constant trap_lma_c    : std_ulogic_vector(5 downto 0) := "0" & "00100"; -- 0.4:  load address misaligned
763 
  constant trap_lbe_c    : std_ulogic_vector(5 downto 0) := "0" & "00101"; -- 0.5:  load access fault
764 
  constant trap_sma_c    : std_ulogic_vector(5 downto 0) := "0" & "00110"; -- 0.6:  store address misaligned
765 
  constant trap_sbe_c    : std_ulogic_vector(5 downto 0) := "0" & "00111"; -- 0.7:  store access fault
766 
  constant trap_uenv_c   : std_ulogic_vector(5 downto 0) := "0" & "01000"; -- 0.8:  environment call from u-mode
767 
  constant trap_menv_c   : std_ulogic_vector(5 downto 0) := "0" & "01011"; -- 0.11: environment call from m-mode
768 
  -- RISC-V compliant interrupts (async. exceptions) --
769 
  constant trap_msi_c    : std_ulogic_vector(5 downto 0) := "1" & "00011"; -- 1.3:  machine software interrupt
770 
  constant trap_mti_c    : std_ulogic_vector(5 downto 0) := "1" & "00111"; -- 1.7:  machine timer interrupt
771 
  constant trap_mei_c    : std_ulogic_vector(5 downto 0) := "1" & "01011"; -- 1.11: machine external interrupt
772 
  -- NEORV32-specific (custom) interrupts (async. exceptions) --
773 
  constant trap_firq0_c  : std_ulogic_vector(5 downto 0) := "1" & "10000"; -- 1.16: fast interrupt 0
774 
  constant trap_firq1_c  : std_ulogic_vector(5 downto 0) := "1" & "10001"; -- 1.17: fast interrupt 1
775 
  constant trap_firq2_c  : std_ulogic_vector(5 downto 0) := "1" & "10010"; -- 1.18: fast interrupt 2
776 
  constant trap_firq3_c  : std_ulogic_vector(5 downto 0) := "1" & "10011"; -- 1.19: fast interrupt 3
777 
  constant trap_firq4_c  : std_ulogic_vector(5 downto 0) := "1" & "10100"; -- 1.20: fast interrupt 4
778 
  constant trap_firq5_c  : std_ulogic_vector(5 downto 0) := "1" & "10101"; -- 1.21: fast interrupt 5
779 
  constant trap_firq6_c  : std_ulogic_vector(5 downto 0) := "1" & "10110"; -- 1.22: fast interrupt 6
780 
  constant trap_firq7_c  : std_ulogic_vector(5 downto 0) := "1" & "10111"; -- 1.23: fast interrupt 7
781 
  constant trap_firq8_c  : std_ulogic_vector(5 downto 0) := "1" & "11000"; -- 1.24: fast interrupt 8
782 
  constant trap_firq9_c  : std_ulogic_vector(5 downto 0) := "1" & "11001"; -- 1.25: fast interrupt 9
783 
  constant trap_firq10_c : std_ulogic_vector(5 downto 0) := "1" & "11010"; -- 1.26: fast interrupt 10
784 
  constant trap_firq11_c : std_ulogic_vector(5 downto 0) := "1" & "11011"; -- 1.27: fast interrupt 11
785 
  constant trap_firq12_c : std_ulogic_vector(5 downto 0) := "1" & "11100"; -- 1.28: fast interrupt 12
786 
  constant trap_firq13_c : std_ulogic_vector(5 downto 0) := "1" & "11101"; -- 1.29: fast interrupt 13
787 
  constant trap_firq14_c : std_ulogic_vector(5 downto 0) := "1" & "11110"; -- 1.30: fast interrupt 14
788 
  constant trap_firq15_c : std_ulogic_vector(5 downto 0) := "1" & "11111"; -- 1.31: fast interrupt 15
789 12 zero_gravi 
 
790 2 zero_gravi 
  -- CPU Control Exception System -----------------------------------------------------------
791 
  -- -------------------------------------------------------------------------------------------
792 
  -- exception source bits --
793 47 zero_gravi 
  constant exception_iaccess_c   : natural :=  0; -- instrution access fault
794 
  constant exception_iillegal_c  : natural :=  1; -- illegal instrution
795 
  constant exception_ialign_c    : natural :=  2; -- instrution address misaligned
796 
  constant exception_m_envcall_c : natural :=  3; -- ENV call from m-mode
797 
  constant exception_u_envcall_c : natural :=  4; -- ENV call from u-mode
798 
  constant exception_break_c     : natural :=  5; -- breakpoint
799 
  constant exception_salign_c    : natural :=  6; -- store address misaligned
800 
  constant exception_lalign_c    : natural :=  7; -- load address misaligned
801 
  constant exception_saccess_c   : natural :=  8; -- store access fault
802 
  constant exception_laccess_c   : natural :=  9; -- load access fault
803 14 zero_gravi 
  --
804 40 zero_gravi 
  constant exception_width_c     : natural := 10; -- length of this list in bits
805 2 zero_gravi 
  -- interrupt source bits --
806 47 zero_gravi 
  constant interrupt_msw_irq_c   : natural :=  0; -- machine software interrupt
807 
  constant interrupt_mtime_irq_c : natural :=  1; -- machine timer interrupt
808 
  constant interrupt_mext_irq_c  : natural :=  2; -- machine external interrupt
809 
  constant interrupt_firq_0_c    : natural :=  3; -- fast interrupt channel 0
810 
  constant interrupt_firq_1_c    : natural :=  4; -- fast interrupt channel 1
811 
  constant interrupt_firq_2_c    : natural :=  5; -- fast interrupt channel 2
812 
  constant interrupt_firq_3_c    : natural :=  6; -- fast interrupt channel 3
813 
  constant interrupt_firq_4_c    : natural :=  7; -- fast interrupt channel 4
814 
  constant interrupt_firq_5_c    : natural :=  8; -- fast interrupt channel 5
815 
  constant interrupt_firq_6_c    : natural :=  9; -- fast interrupt channel 6
816 
  constant interrupt_firq_7_c    : natural := 10; -- fast interrupt channel 7
817 48 zero_gravi 
  constant interrupt_firq_8_c    : natural := 11; -- fast interrupt channel 8
818 
  constant interrupt_firq_9_c    : natural := 12; -- fast interrupt channel 9
819 
  constant interrupt_firq_10_c   : natural := 13; -- fast interrupt channel 10
820 
  constant interrupt_firq_11_c   : natural := 14; -- fast interrupt channel 11
821 
  constant interrupt_firq_12_c   : natural := 15; -- fast interrupt channel 12
822 
  constant interrupt_firq_13_c   : natural := 16; -- fast interrupt channel 13
823 
  constant interrupt_firq_14_c   : natural := 17; -- fast interrupt channel 14
824 
  constant interrupt_firq_15_c   : natural := 18; -- fast interrupt channel 15
825 14 zero_gravi 
  --
826 48 zero_gravi 
  constant interrupt_width_c     : natural := 19; -- length of this list in bits
827 2 zero_gravi 
 
828 15 zero_gravi 
  -- CPU Privilege Modes --------------------------------------------------------------------
829 
  -- -------------------------------------------------------------------------------------------
830 29 zero_gravi 
  constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
831 
  constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
832 15 zero_gravi 
 
833 42 zero_gravi 
  -- HPM Event System -----------------------------------------------------------------------
834 
  -- -------------------------------------------------------------------------------------------
835 
  constant hpmcnt_event_cy_c      : natural := 0;  -- Active cycle
836 56 zero_gravi 
  constant hpmcnt_event_never_c   : natural := 1;  -- Unused / never (actually, this would be used for TIME)
837 42 zero_gravi 
  constant hpmcnt_event_ir_c      : natural := 2;  -- Retired instruction
838 
  constant hpmcnt_event_cir_c     : natural := 3;  -- Retired compressed instruction
839 
  constant hpmcnt_event_wait_if_c : natural := 4;  -- Instruction fetch memory wait cycle
840 
  constant hpmcnt_event_wait_ii_c : natural := 5;  -- Instruction issue wait cycle
841 45 zero_gravi 
  constant hpmcnt_event_wait_mc_c : natural := 6;  -- Multi-cycle ALU-operation wait cycle
842 
  constant hpmcnt_event_load_c    : natural := 7;  -- Load operation
843 
  constant hpmcnt_event_store_c   : natural := 8;  -- Store operation
844 
  constant hpmcnt_event_wait_ls_c : natural := 9;  -- Load/store memory wait cycle
845 
  constant hpmcnt_event_jump_c    : natural := 10; -- Unconditional jump
846 
  constant hpmcnt_event_branch_c  : natural := 11; -- Conditional branch (taken or not taken)
847 
  constant hpmcnt_event_tbranch_c : natural := 12; -- Conditional taken branch
848 
  constant hpmcnt_event_trap_c    : natural := 13; -- Entered trap
849 
  constant hpmcnt_event_illegal_c : natural := 14; -- Illegal instruction exception
850 42 zero_gravi 
  --
851 45 zero_gravi 
  constant hpmcnt_event_size_c    : natural := 15; -- length of this list
852 42 zero_gravi 
 
853 39 zero_gravi 
  -- Clock Generator ------------------------------------------------------------------------
854 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
855 
  constant clk_div2_c    : natural := 0;
856 
  constant clk_div4_c    : natural := 1;
857 
  constant clk_div8_c    : natural := 2;
858 
  constant clk_div64_c   : natural := 3;
859 
  constant clk_div128_c  : natural := 4;
860 
  constant clk_div1024_c : natural := 5;
861 
  constant clk_div2048_c : natural := 6;
862 
  constant clk_div4096_c : natural := 7;
863 
 
864 
  -- Component: NEORV32 Processor Top Entity ------------------------------------------------
865 
  -- -------------------------------------------------------------------------------------------
866 
  component neorv32_top
867 
    generic (
868 
      -- General --
869 12 zero_gravi 
      CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz
870 44 zero_gravi 
      BOOTLOADER_EN                : boolean := true;   -- implement processor-internal bootloader?
871 12 zero_gravi 
      USER_CODE                    : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
872 49 zero_gravi 
      HW_THREAD_ID                 : natural := 0;      -- hardware thread id (32-bit)
873 2 zero_gravi 
      -- RISC-V CPU Extensions --
874 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false;  -- implement atomic extension?
875 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false;  -- implement bit manipulation extensions?
876 18 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?
877 8 zero_gravi 
      CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
878 18 zero_gravi 
      CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement muld/div extension?
879 
      CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?
880 57 zero_gravi 
      CPU_EXTENSION_RISCV_Zfinx    : boolean := false;  -- implement 32-bit floating-point extension (using INT regs!)
881 8 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?
882 39 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false;  -- implement instruction stream sync.?
883 19 zero_gravi 
      -- Extension Options --
884 34 zero_gravi 
      FAST_MUL_EN                  : boolean := false;  -- use DSPs for M extension's multiplier
885 
      FAST_SHIFT_EN                : boolean := false;  -- use barrel shifter for shift operations
886 56 zero_gravi 
      TINY_SHIFT_EN                : boolean := false;  -- use tiny (single-bit) shifter for shift operations
887 
      CPU_CNT_WIDTH                : natural := 64;     -- total width of CPU cycle and instret counters (0..64)
888 15 zero_gravi 
      -- Physical Memory Protection (PMP) --
889 42 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0;      -- number of regions (0..64)
890 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
891 
      -- Hardware Performance Monitors (HPM) --
892 47 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0;      -- number of implemented HPM counters (0..29)
893 56 zero_gravi 
      HPM_CNT_WIDTH                : natural := 40;     -- total size of HPM counters (1..64)
894 23 zero_gravi 
      -- Internal Instruction memory --
895 44 zero_gravi 
      MEM_INT_IMEM_EN              : boolean := true;   -- implement processor-internal instruction memory
896 8 zero_gravi 
      MEM_INT_IMEM_SIZE            : natural := 16*1024; -- size of processor-internal instruction memory in bytes
897 34 zero_gravi 
      MEM_INT_IMEM_ROM             : boolean := false;  -- implement processor-internal instruction memory as ROM
898 23 zero_gravi 
      -- Internal Data memory --
899 44 zero_gravi 
      MEM_INT_DMEM_EN              : boolean := true;   -- implement processor-internal data memory
900 8 zero_gravi 
      MEM_INT_DMEM_SIZE            : natural := 8*1024; -- size of processor-internal data memory in bytes
901 41 zero_gravi 
      -- Internal Cache memory --
902 44 zero_gravi 
      ICACHE_EN                    : boolean := false;  -- implement instruction cache
903 41 zero_gravi 
      ICACHE_NUM_BLOCKS            : natural := 4;      -- i-cache: number of blocks (min 1), has to be a power of 2
904 
      ICACHE_BLOCK_SIZE            : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
905 45 zero_gravi 
      ICACHE_ASSOCIATIVITY         : natural := 1;      -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
906 23 zero_gravi 
      -- External memory interface --
907 44 zero_gravi 
      MEM_EXT_EN                   : boolean := false;  -- implement external memory bus interface?
908 57 zero_gravi 
      MEM_EXT_TIMEOUT              : natural := 255;    -- cycles after a pending bus access auto-terminates (0 = disabled)
909 2 zero_gravi 
      -- Processor peripherals --
910 44 zero_gravi 
      IO_GPIO_EN                   : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
911 
      IO_MTIME_EN                  : boolean := true;   -- implement machine system timer (MTIME)?
912 50 zero_gravi 
      IO_UART0_EN                  : boolean := true;   -- implement primary universal asynchronous receiver/transmitter (UART0)?
913 
      IO_UART1_EN                  : boolean := true;   -- implement secondary universal asynchronous receiver/transmitter (UART1)?
914 44 zero_gravi 
      IO_SPI_EN                    : boolean := true;   -- implement serial peripheral interface (SPI)?
915 
      IO_TWI_EN                    : boolean := true;   -- implement two-wire interface (TWI)?
916 
      IO_PWM_EN                    : boolean := true;   -- implement pulse-width modulation unit (PWM)?
917 
      IO_WDT_EN                    : boolean := true;   -- implement watch dog timer (WDT)?
918 
      IO_TRNG_EN                   : boolean := false;  -- implement true random number generator (TRNG)?
919 47 zero_gravi 
      IO_CFS_EN                    : boolean := false;  -- implement custom functions subsystem (CFS)?
920 56 zero_gravi 
      IO_CFS_CONFIG                : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
921 52 zero_gravi 
      IO_CFS_IN_SIZE               : positive := 32;    -- size of CFS input conduit in bits
922 
      IO_CFS_OUT_SIZE              : positive := 32;    -- size of CFS output conduit in bits
923 
      IO_NCO_EN                    : boolean := true;   -- implement numerically-controlled oscillator (NCO)?
924 
      IO_NEOLED_EN                 : boolean := true    -- implement NeoPixel-compatible smart LED interface (NEOLED)?
925 2 zero_gravi 
    );
926 
    port (
927 
      -- Global control --
928 34 zero_gravi 
      clk_i       : in  std_ulogic := '0'; -- global clock, rising edge
929 
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
930 49 zero_gravi 
      -- Wishbone bus interface (available if MEM_EXT_EN = true) --
931 57 zero_gravi 
      wb_tag_o    : out std_ulogic_vector(02 downto 0); -- request tag
932 34 zero_gravi 
      wb_adr_o    : out std_ulogic_vector(31 downto 0); -- address
933 
      wb_dat_i    : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
934 
      wb_dat_o    : out std_ulogic_vector(31 downto 0); -- write data
935 
      wb_we_o     : out std_ulogic; -- read/write
936 
      wb_sel_o    : out std_ulogic_vector(03 downto 0); -- byte enable
937 
      wb_stb_o    : out std_ulogic; -- strobe
938 
      wb_cyc_o    : out std_ulogic; -- valid cycle
939 57 zero_gravi 
      wb_lock_o   : out std_ulogic; -- exclusive access request
940 34 zero_gravi 
      wb_ack_i    : in  std_ulogic := '0'; -- transfer acknowledge
941 
      wb_err_i    : in  std_ulogic := '0'; -- transfer error
942 44 zero_gravi 
      -- Advanced memory control signals (available if MEM_EXT_EN = true) --
943 34 zero_gravi 
      fence_o     : out std_ulogic; -- indicates an executed FENCE operation
944 
      fencei_o    : out std_ulogic; -- indicates an executed FENCEI operation
945 49 zero_gravi 
      -- GPIO (available if IO_GPIO_EN = true) --
946 34 zero_gravi 
      gpio_o      : out std_ulogic_vector(31 downto 0); -- parallel output
947 
      gpio_i      : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
948 50 zero_gravi 
      -- primary UART0 (available if IO_UART0_EN = true) --
949 
      uart0_txd_o : out std_ulogic; -- UART0 send data
950 
      uart0_rxd_i : in  std_ulogic := '0'; -- UART0 receive data
951 51 zero_gravi 
      uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
952 
      uart0_cts_i : in  std_ulogic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
953 50 zero_gravi 
      -- secondary UART1 (available if IO_UART1_EN = true) --
954 
      uart1_txd_o : out std_ulogic; -- UART1 send data
955 
      uart1_rxd_i : in  std_ulogic := '0'; -- UART1 receive data
956 51 zero_gravi 
      uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
957 
      uart1_cts_i : in  std_ulogic := '0'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
958 49 zero_gravi 
      -- SPI (available if IO_SPI_EN = true) --
959 34 zero_gravi 
      spi_sck_o   : out std_ulogic; -- SPI serial clock
960 
      spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
961 
      spi_sdi_i   : in  std_ulogic := '0'; -- controller data in, peripheral data out
962 
      spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
963 49 zero_gravi 
      -- TWI (available if IO_TWI_EN = true) --
964 35 zero_gravi 
      twi_sda_io  : inout std_logic; -- twi serial data line
965 
      twi_scl_io  : inout std_logic; -- twi serial clock line
966 49 zero_gravi 
      -- PWM (available if IO_PWM_EN = true) --
967 40 zero_gravi 
      pwm_o       : out std_ulogic_vector(03 downto 0); -- pwm channels
968 47 zero_gravi 
      -- Custom Functions Subsystem IO --
969 52 zero_gravi 
      cfs_in_i    : in  std_ulogic_vector(IO_CFS_IN_SIZE-1  downto 0); -- custom CFS inputs conduit
970 
      cfs_out_o   : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
971 49 zero_gravi 
      -- NCO output (available if IO_NCO_EN = true) --
972 
      nco_o       : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
973 52 zero_gravi 
      -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
974 
      neoled_o    : out std_ulogic; -- async serial data line
975 44 zero_gravi 
      -- system time input from external MTIME (available if IO_MTIME_EN = false) --
976 40 zero_gravi 
      mtime_i     : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
977 2 zero_gravi 
      -- Interrupts --
978 50 zero_gravi 
      soc_firq_i  : in  std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
979 44 zero_gravi 
      mtime_irq_i : in  std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
980 34 zero_gravi 
      msw_irq_i   : in  std_ulogic := '0'; -- machine software interrupt
981 
      mext_irq_i  : in  std_ulogic := '0'  -- machine external interrupt
982 2 zero_gravi 
    );
983 
  end component;
984 
 
985 4 zero_gravi 
  -- Component: CPU Top Entity --------------------------------------------------------------
986 
  -- -------------------------------------------------------------------------------------------
987 
  component neorv32_cpu
988 
    generic (
989 
      -- General --
990 49 zero_gravi 
      HW_THREAD_ID                 : natural := 0;     -- hardware thread id (32-bit)
991 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu boot address
992 4 zero_gravi 
      -- RISC-V CPU Extensions --
993 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
994 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
995 12 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
996 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
997 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
998 15 zero_gravi 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
999 53 zero_gravi 
      CPU_EXTENSION_RISCV_Zfinx    : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
1000 12 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
1001 49 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
1002 19 zero_gravi 
      -- Extension Options --
1003 
      FAST_MUL_EN                  : boolean := false; -- use DSPs for M extension's multiplier
1004 34 zero_gravi 
      FAST_SHIFT_EN                : boolean := false; -- use barrel shifter for shift operations
1005 56 zero_gravi 
      TINY_SHIFT_EN                : boolean := false; -- use tiny (single-bit) shifter for shift operations
1006 
      CPU_CNT_WIDTH                : natural := 64;    -- total width of CPU cycle and instret counters (0..64)
1007 15 zero_gravi 
      -- Physical Memory Protection (PMP) --
1008 52 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0;     -- number of regions (0..64)
1009 42 zero_gravi 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
1010 
      -- Hardware Performance Monitors (HPM) --
1011 56 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0;     -- number of implemented HPM counters (0..29)
1012 
      HPM_CNT_WIDTH                : natural := 40     -- total size of HPM counters (1..64)
1013 4 zero_gravi 
    );
1014 
    port (
1015 
      -- global control --
1016 14 zero_gravi 
      clk_i          : in  std_ulogic := '0'; -- global clock, rising edge
1017 
      rstn_i         : in  std_ulogic := '0'; -- global reset, low-active, async
1018 47 zero_gravi 
      sleep_o        : out std_ulogic; -- cpu is in sleep mode when set
1019 12 zero_gravi 
      -- instruction bus interface --
1020 
      i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1021 14 zero_gravi 
      i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
1022 12 zero_gravi 
      i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1023 
      i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1024 
      i_bus_we_o     : out std_ulogic; -- write enable
1025 
      i_bus_re_o     : out std_ulogic; -- read enable
1026 57 zero_gravi 
      i_bus_lock_o   : out std_ulogic; -- exclusive access request
1027 14 zero_gravi 
      i_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
1028 
      i_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
1029 12 zero_gravi 
      i_bus_fence_o  : out std_ulogic; -- executed FENCEI operation
1030 35 zero_gravi 
      i_bus_priv_o   : out std_ulogic_vector(1 downto 0); -- privilege level
1031 12 zero_gravi 
      -- data bus interface --
1032 
      d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1033 14 zero_gravi 
      d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
1034 12 zero_gravi 
      d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1035 
      d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1036 
      d_bus_we_o     : out std_ulogic; -- write enable
1037 
      d_bus_re_o     : out std_ulogic; -- read enable
1038 57 zero_gravi 
      d_bus_lock_o   : out std_ulogic; -- exclusive access request
1039 14 zero_gravi 
      d_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
1040 
      d_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
1041 12 zero_gravi 
      d_bus_fence_o  : out std_ulogic; -- executed FENCE operation
1042 35 zero_gravi 
      d_bus_priv_o   : out std_ulogic_vector(1 downto 0); -- privilege level
1043 11 zero_gravi 
      -- system time input from MTIME --
1044 14 zero_gravi 
      time_i         : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
1045 
      -- interrupts (risc-v compliant) --
1046 
      msw_irq_i      : in  std_ulogic := '0'; -- machine software interrupt
1047 
      mext_irq_i     : in  std_ulogic := '0'; -- machine external interrupt
1048 
      mtime_irq_i    : in  std_ulogic := '0'; -- machine timer interrupt
1049 
      -- fast interrupts (custom) --
1050 48 zero_gravi 
      firq_i         : in  std_ulogic_vector(15 downto 0) := (others => '0');
1051 
      firq_ack_o     : out std_ulogic_vector(15 downto 0)
1052 4 zero_gravi 
    );
1053 
  end component;
1054 
 
1055 2 zero_gravi 
  -- Component: CPU Control -----------------------------------------------------------------
1056 
  -- -------------------------------------------------------------------------------------------
1057 
  component neorv32_cpu_control
1058 
    generic (
1059 
      -- General --
1060 49 zero_gravi 
      HW_THREAD_ID                 : natural := 0;     -- hardware thread id (32-bit)
1061 12 zero_gravi 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
1062 2 zero_gravi 
      -- RISC-V CPU Extensions --
1063 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
1064 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
1065 12 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
1066 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
1067 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
1068 15 zero_gravi 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
1069 53 zero_gravi 
      CPU_EXTENSION_RISCV_Zfinx    : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
1070 12 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
1071 49 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
1072 56 zero_gravi 
      -- Extension Options --
1073 
      CPU_CNT_WIDTH                : natural := 64; -- total width of CPU cycle and instret counters (0..64)
1074 15 zero_gravi 
      -- Physical memory protection (PMP) --
1075 52 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0;     -- number of regions (0..64)
1076 42 zero_gravi 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
1077 
      -- Hardware Performance Monitors (HPM) --
1078 56 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0;     -- number of implemented HPM counters (0..29)
1079 
      HPM_CNT_WIDTH                : natural := 40     -- total size of HPM counters (1..64)
1080 2 zero_gravi 
    );
1081 
    port (
1082 
      -- global control --
1083 
      clk_i         : in  std_ulogic; -- global clock, rising edge
1084 
      rstn_i        : in  std_ulogic; -- global reset, low-active, async
1085 
      ctrl_o        : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1086 
      -- status input --
1087 
      alu_wait_i    : in  std_ulogic; -- wait for ALU
1088 12 zero_gravi 
      bus_i_wait_i  : in  std_ulogic; -- wait for bus
1089 
      bus_d_wait_i  : in  std_ulogic; -- wait for bus
1090 57 zero_gravi 
      excl_state_i  : in  std_ulogic; -- atomic/exclusive access lock status
1091 2 zero_gravi 
      -- data input --
1092 
      instr_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- instruction
1093 
      cmp_i         : in  std_ulogic_vector(1 downto 0); -- comparator status
1094 36 zero_gravi 
      alu_add_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result
1095 52 zero_gravi 
      rs1_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1096 2 zero_gravi 
      -- data output --
1097 
      imm_o         : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
1098 6 zero_gravi 
      fetch_pc_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
1099 
      curr_pc_o     : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
1100 2 zero_gravi 
      csr_rdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
1101 52 zero_gravi 
      -- FPU interface --
1102 
      fpu_rm_o      : out std_ulogic_vector(02 downto 0); -- rounding mode
1103 
      fpu_flags_i   : in  std_ulogic_vector(04 downto 0); -- exception flags
1104 14 zero_gravi 
      -- interrupts (risc-v compliant) --
1105 
      msw_irq_i     : in  std_ulogic; -- machine software interrupt
1106 
      mext_irq_i    : in  std_ulogic; -- machine external interrupt
1107 2 zero_gravi 
      mtime_irq_i   : in  std_ulogic; -- machine timer interrupt
1108 14 zero_gravi 
      -- fast interrupts (custom) --
1109 48 zero_gravi 
      firq_i        : in  std_ulogic_vector(15 downto 0);
1110 
      firq_ack_o    : out std_ulogic_vector(15 downto 0);
1111 11 zero_gravi 
      -- system time input from MTIME --
1112 
      time_i        : in  std_ulogic_vector(63 downto 0); -- current system time
1113 15 zero_gravi 
      -- physical memory protection --
1114 
      pmp_addr_o    : out pmp_addr_if_t; -- addresses
1115 
      pmp_ctrl_o    : out pmp_ctrl_if_t; -- configs
1116 2 zero_gravi 
      -- bus access exceptions --
1117 
      mar_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
1118 
      ma_instr_i    : in  std_ulogic; -- misaligned instruction address
1119 
      ma_load_i     : in  std_ulogic; -- misaligned load data address
1120 
      ma_store_i    : in  std_ulogic; -- misaligned store data address
1121 
      be_instr_i    : in  std_ulogic; -- bus error on instruction access
1122 
      be_load_i     : in  std_ulogic; -- bus error on load data access
1123 12 zero_gravi 
      be_store_i    : in  std_ulogic  -- bus error on store data access
1124 2 zero_gravi 
    );
1125 
  end component;
1126 
 
1127 
  -- Component: CPU Register File -----------------------------------------------------------
1128 
  -- -------------------------------------------------------------------------------------------
1129 
  component neorv32_cpu_regfile
1130 
    generic (
1131 
      CPU_EXTENSION_RISCV_E : boolean := false -- implement embedded RF extension?
1132 
    );
1133 
    port (
1134 
      -- global control --
1135 
      clk_i  : in  std_ulogic; -- global clock, rising edge
1136 
      ctrl_i : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1137 
      -- data input --
1138 
      mem_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
1139 
      alu_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
1140 
      -- data output --
1141 
      rs1_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
1142 47 zero_gravi 
      rs2_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 2
1143 
      cmp_o  : out std_ulogic_vector(1 downto 0) -- comparator status
1144 2 zero_gravi 
    );
1145 
  end component;
1146 
 
1147 
  -- Component: CPU ALU ---------------------------------------------------------------------
1148 
  -- -------------------------------------------------------------------------------------------
1149 
  component neorv32_cpu_alu
1150 11 zero_gravi 
    generic (
1151 56 zero_gravi 
      CPU_EXTENSION_RISCV_M : boolean := true;  -- implement muld/div extension?
1152 
      FAST_SHIFT_EN         : boolean := false; -- use barrel shifter for shift operations
1153 
      TINY_SHIFT_EN         : boolean := false  -- use tiny (single-bit) shifter for shift operations
1154 11 zero_gravi 
    );
1155 2 zero_gravi 
    port (
1156 
      -- global control --
1157 
      clk_i       : in  std_ulogic; -- global clock, rising edge
1158 
      rstn_i      : in  std_ulogic; -- global reset, low-active, async
1159 
      ctrl_i      : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1160 
      -- data input --
1161 
      rs1_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1162 
      rs2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1163 
      pc2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
1164 
      imm_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- immediate
1165 
      -- data output --
1166 
      res_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
1167 36 zero_gravi 
      add_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
1168 2 zero_gravi 
      -- co-processor interface --
1169 49 zero_gravi 
      cp_start_o  : out std_ulogic_vector(7 downto 0); -- trigger co-processor i
1170 
      cp_valid_i  : in  std_ulogic_vector(7 downto 0); -- co-processor i done
1171 
      cp_result_i : in  cp_data_if_t; -- co-processor result
1172 2 zero_gravi 
      -- status --
1173 
      wait_o      : out std_ulogic -- busy due to iterative processing units
1174 
    );
1175 
  end component;
1176 
 
1177 44 zero_gravi 
  -- Component: CPU Co-Processor MULDIV ('M' extension) -------------------------------------
1178 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1179 
  component neorv32_cpu_cp_muldiv
1180 19 zero_gravi 
    generic (
1181 
      FAST_MUL_EN : boolean := false -- use DSPs for faster multiplication
1182 
    );
1183 2 zero_gravi 
    port (
1184 
      -- global control --
1185 
      clk_i   : in  std_ulogic; -- global clock, rising edge
1186 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
1187 
      ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1188 36 zero_gravi 
      start_i : in  std_ulogic; -- trigger operation
1189 2 zero_gravi 
      -- data input --
1190 
      rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1191 
      rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1192 
      -- result and status --
1193 
      res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1194 
      valid_o : out std_ulogic -- data output valid
1195 
    );
1196 
  end component;
1197 
 
1198 44 zero_gravi 
  -- Component: CPU Co-Processor Bit Manipulation ('B' extension) ---------------------------
1199 
  -- -------------------------------------------------------------------------------------------
1200 
  component neorv32_cpu_cp_bitmanip
1201 
    port (
1202 
      -- global control --
1203 
      clk_i   : in  std_ulogic; -- global clock, rising edge
1204 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
1205 
      ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1206 
      start_i : in  std_ulogic; -- trigger operation
1207 
      -- data input --
1208 
      cmp_i   : in  std_ulogic_vector(1 downto 0); -- comparator status
1209 
      rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1210 
      rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1211 
      -- result and status --
1212 
      res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1213 
      valid_o : out std_ulogic -- data output valid
1214 
    );
1215 
  end component;
1216 
 
1217 53 zero_gravi 
  -- Component: CPU Co-Processor 32-bit FPU ('Zfinx' extension) -----------------------------
1218 52 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1219 
  component neorv32_cpu_cp_fpu
1220 
    port (
1221 
      -- global control --
1222 53 zero_gravi 
      clk_i    : in  std_ulogic; -- global clock, rising edge
1223 
      rstn_i   : in  std_ulogic; -- global reset, low-active, async
1224 
      ctrl_i   : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1225 
      start_i  : in  std_ulogic; -- trigger operation
1226 52 zero_gravi 
      -- data input --
1227 53 zero_gravi 
      frm_i    : in  std_ulogic_vector(2 downto 0); -- rounding mode
1228 56 zero_gravi 
      cmp_i    : in  std_ulogic_vector(1 downto 0); -- comparator status
1229 53 zero_gravi 
      rs1_i    : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1230 
      rs2_i    : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1231 52 zero_gravi 
      -- result and status --
1232 53 zero_gravi 
      res_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1233 
      fflags_o : out std_ulogic_vector(4 downto 0); -- exception flags
1234 
      valid_o  : out std_ulogic -- data output valid
1235 52 zero_gravi 
    );
1236 
  end component;
1237 
 
1238 2 zero_gravi 
  -- Component: CPU Bus Interface -----------------------------------------------------------
1239 
  -- -------------------------------------------------------------------------------------------
1240 
  component neorv32_cpu_bus
1241 
    generic (
1242 57 zero_gravi 
      CPU_EXTENSION_RISCV_A : boolean := false;  -- implement atomic extension?
1243 
      CPU_EXTENSION_RISCV_C : boolean := true;   -- implement compressed extension?
1244 15 zero_gravi 
      -- Physical memory protection (PMP) --
1245 57 zero_gravi 
      PMP_NUM_REGIONS       : natural := 0;      -- number of regions (0..64)
1246 
      PMP_MIN_GRANULARITY   : natural := 64*1024 -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
1247 2 zero_gravi 
    );
1248 
    port (
1249 
      -- global control --
1250 12 zero_gravi 
      clk_i          : in  std_ulogic; -- global clock, rising edge
1251 38 zero_gravi 
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
1252 12 zero_gravi 
      ctrl_i         : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1253 
      -- cpu instruction fetch interface --
1254 
      fetch_pc_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
1255 
      instr_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
1256 
      i_wait_o       : out std_ulogic; -- wait for fetch to complete
1257 
      --
1258 
      ma_instr_o     : out std_ulogic; -- misaligned instruction address
1259 
      be_instr_o     : out std_ulogic; -- bus error on instruction access
1260 
      -- cpu data access interface --
1261 
      addr_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
1262 
      wdata_i        : in  std_ulogic_vector(data_width_c-1 downto 0); -- write data
1263 
      rdata_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
1264 
      mar_o          : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
1265 
      d_wait_o       : out std_ulogic; -- wait for access to complete
1266 
      --
1267 57 zero_gravi 
      excl_state_o   : out std_ulogic; -- atomic/exclusive access status
1268 12 zero_gravi 
      ma_load_o      : out std_ulogic; -- misaligned load data address
1269 
      ma_store_o     : out std_ulogic; -- misaligned store data address
1270 
      be_load_o      : out std_ulogic; -- bus error on load data access
1271 
      be_store_o     : out std_ulogic; -- bus error on store data access
1272 15 zero_gravi 
      -- physical memory protection --
1273 
      pmp_addr_i     : in  pmp_addr_if_t; -- addresses
1274 
      pmp_ctrl_i     : in  pmp_ctrl_if_t; -- configs
1275 12 zero_gravi 
      -- instruction bus --
1276 
      i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1277 
      i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1278 
      i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1279 
      i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1280 
      i_bus_we_o     : out std_ulogic; -- write enable
1281 
      i_bus_re_o     : out std_ulogic; -- read enable
1282 57 zero_gravi 
      i_bus_lock_o   : out std_ulogic; -- exclusive access request
1283 12 zero_gravi 
      i_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
1284 
      i_bus_err_i    : in  std_ulogic; -- bus transfer error
1285 
      i_bus_fence_o  : out std_ulogic; -- fence operation
1286 
      -- data bus --
1287 
      d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1288 
      d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1289 
      d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1290 
      d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1291 
      d_bus_we_o     : out std_ulogic; -- write enable
1292 
      d_bus_re_o     : out std_ulogic; -- read enable
1293 57 zero_gravi 
      d_bus_lock_o   : out std_ulogic; -- exclusive access request
1294 12 zero_gravi 
      d_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
1295 
      d_bus_err_i    : in  std_ulogic; -- bus transfer error
1296 57 zero_gravi 
      d_bus_fence_o  : out std_ulogic  -- fence operation
1297 2 zero_gravi 
    );
1298 
  end component;
1299 
 
1300 57 zero_gravi 
  -- Component: Bus Keeper ------------------------------------------------------------------
1301 
  -- -------------------------------------------------------------------------------------------
1302 
  component neorv32_bus_keeper is
1303 
    generic (
1304 
      -- Internal instruction memory --
1305 
      MEM_INT_IMEM_EN   : boolean := true;   -- implement processor-internal instruction memory
1306 
      MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
1307 
      -- Internal data memory --
1308 
      MEM_INT_DMEM_EN   : boolean := true;   -- implement processor-internal data memory
1309 
      MEM_INT_DMEM_SIZE : natural := 8*1024  -- size of processor-internal data memory in bytes
1310 
    );
1311 
    port (
1312 
      -- host access --
1313 
      clk_i  : in  std_ulogic; -- global clock line
1314 
      rstn_i : in  std_ulogic; -- global reset line, low-active
1315 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1316 
      rden_i : in  std_ulogic; -- read enable
1317 
      wren_i : in  std_ulogic; -- write enable
1318 
      ack_i  : in  std_ulogic; -- transfer acknowledge from bus system
1319 
      err_i  : in  std_ulogic; -- transfer error from bus system
1320 
      err_o  : out std_ulogic  -- bus error
1321 
    );
1322 
  end component;
1323 
 
1324 45 zero_gravi 
  -- Component: CPU Instruction Cache -------------------------------------------------------
1325 41 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1326 45 zero_gravi 
  component neorv32_icache
1327 41 zero_gravi 
    generic (
1328 47 zero_gravi 
      ICACHE_NUM_BLOCKS : natural := 4;  -- number of blocks (min 1), has to be a power of 2
1329 
      ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2
1330 
      ICACHE_NUM_SETS   : natural := 1   -- associativity / number of sets (1=direct_mapped), has to be a power of 2
1331 41 zero_gravi 
    );
1332 
    port (
1333 
      -- global control --
1334 
      clk_i         : in  std_ulogic; -- global clock, rising edge
1335 
      rstn_i        : in  std_ulogic; -- global reset, low-active, async
1336 
      clear_i       : in  std_ulogic; -- cache clear
1337 
      -- host controller interface --
1338 
      host_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1339 
      host_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1340 
      host_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1341 
      host_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1342 
      host_we_i     : in  std_ulogic; -- write enable
1343 
      host_re_i     : in  std_ulogic; -- read enable
1344 
      host_ack_o    : out std_ulogic; -- bus transfer acknowledge
1345 
      host_err_o    : out std_ulogic; -- bus transfer error
1346 
      -- peripheral bus interface --
1347 
      bus_addr_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1348 
      bus_rdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1349 
      bus_wdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1350 
      bus_ben_o     : out std_ulogic_vector(03 downto 0); -- byte enable
1351 
      bus_we_o      : out std_ulogic; -- write enable
1352 
      bus_re_o      : out std_ulogic; -- read enable
1353 
      bus_ack_i     : in  std_ulogic; -- bus transfer acknowledge
1354 
      bus_err_i     : in  std_ulogic  -- bus transfer error
1355 
    );
1356 
  end component;
1357 
 
1358 12 zero_gravi 
  -- Component: CPU Bus Switch --------------------------------------------------------------
1359 
  -- -------------------------------------------------------------------------------------------
1360 
  component neorv32_busswitch
1361 
    generic (
1362 
      PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only
1363 
      PORT_CB_READ_ONLY : boolean := false  -- set if controller port B is read-only
1364 
    );
1365 
    port (
1366 
      -- global control --
1367 
      clk_i           : in  std_ulogic; -- global clock, rising edge
1368 
      rstn_i          : in  std_ulogic; -- global reset, low-active, async
1369 
      -- controller interface a --
1370 
      ca_bus_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1371 
      ca_bus_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1372 
      ca_bus_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1373 
      ca_bus_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1374 
      ca_bus_we_i     : in  std_ulogic; -- write enable
1375 
      ca_bus_re_i     : in  std_ulogic; -- read enable
1376 57 zero_gravi 
      ca_bus_lock_i   : in  std_ulogic; -- exclusive access request
1377 12 zero_gravi 
      ca_bus_ack_o    : out std_ulogic; -- bus transfer acknowledge
1378 
      ca_bus_err_o    : out std_ulogic; -- bus transfer error
1379 
      -- controller interface b --
1380 
      cb_bus_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1381 
      cb_bus_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1382 
      cb_bus_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1383 
      cb_bus_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1384 
      cb_bus_we_i     : in  std_ulogic; -- write enable
1385 
      cb_bus_re_i     : in  std_ulogic; -- read enable
1386 57 zero_gravi 
      cb_bus_lock_i   : in  std_ulogic; -- exclusive access request
1387 12 zero_gravi 
      cb_bus_ack_o    : out std_ulogic; -- bus transfer acknowledge
1388 
      cb_bus_err_o    : out std_ulogic; -- bus transfer error
1389 
      -- peripheral bus --
1390 36 zero_gravi 
      p_bus_src_o     : out std_ulogic; -- access source: 0 = A, 1 = B
1391 12 zero_gravi 
      p_bus_addr_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1392 
      p_bus_rdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1393 
      p_bus_wdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1394 
      p_bus_ben_o     : out std_ulogic_vector(03 downto 0); -- byte enable
1395 
      p_bus_we_o      : out std_ulogic; -- write enable
1396 
      p_bus_re_o      : out std_ulogic; -- read enable
1397 57 zero_gravi 
      p_bus_lock_o    : out std_ulogic; -- exclusive access request
1398 12 zero_gravi 
      p_bus_ack_i     : in  std_ulogic; -- bus transfer acknowledge
1399 
      p_bus_err_i     : in  std_ulogic  -- bus transfer error
1400 
    );
1401 
  end component;
1402 
 
1403 2 zero_gravi 
  -- Component: CPU Compressed Instructions Decompressor ------------------------------------
1404 
  -- -------------------------------------------------------------------------------------------
1405 
  component neorv32_cpu_decompressor
1406 
    port (
1407 
      -- instruction input --
1408 
      ci_instr16_i : in  std_ulogic_vector(15 downto 0); -- compressed instruction input
1409 
      -- instruction output --
1410 
      ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
1411 
      ci_instr32_o : out std_ulogic_vector(31 downto 0)  -- 32-bit decompressed instruction
1412 
    );
1413 
  end component;
1414 
 
1415 
  -- Component: Processor-internal instruction memory (IMEM) --------------------------------
1416 
  -- -------------------------------------------------------------------------------------------
1417 
  component neorv32_imem
1418 
    generic (
1419 
      IMEM_BASE      : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
1420 
      IMEM_SIZE      : natural := 4*1024; -- processor-internal instruction memory size in bytes
1421 
      IMEM_AS_ROM    : boolean := false;  -- implement IMEM as read-only memory?
1422 44 zero_gravi 
      BOOTLOADER_EN  : boolean := true    -- implement and use bootloader?
1423 2 zero_gravi 
    );
1424 
    port (
1425 
      clk_i  : in  std_ulogic; -- global clock line
1426 
      rden_i : in  std_ulogic; -- read enable
1427 
      wren_i : in  std_ulogic; -- write enable
1428 
      ben_i  : in  std_ulogic_vector(03 downto 0); -- byte write enable
1429 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1430 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1431 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1432 
      ack_o  : out std_ulogic -- transfer acknowledge
1433 
    );
1434 
  end component;
1435 
 
1436 
  -- Component: Processor-internal data memory (DMEM) ---------------------------------------
1437 
  -- -------------------------------------------------------------------------------------------
1438 
  component neorv32_dmem
1439 
    generic (
1440 
      DMEM_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- memory base address
1441 
      DMEM_SIZE : natural := 4*1024  -- processor-internal instruction memory size in bytes
1442 
    );
1443 
    port (
1444 
      clk_i  : in  std_ulogic; -- global clock line
1445 
      rden_i : in  std_ulogic; -- read enable
1446 
      wren_i : in  std_ulogic; -- write enable
1447 
      ben_i  : in  std_ulogic_vector(03 downto 0); -- byte write enable
1448 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1449 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1450 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1451 
      ack_o  : out std_ulogic -- transfer acknowledge
1452 
    );
1453 
  end component;
1454 
 
1455 
  -- Component: Processor-internal bootloader ROM (BOOTROM) ---------------------------------
1456 
  -- -------------------------------------------------------------------------------------------
1457 
  component neorv32_boot_rom
1458 23 zero_gravi 
    generic (
1459 
      BOOTROM_BASE : std_ulogic_vector(31 downto 0) := x"FFFF0000"; -- boot ROM base address
1460 
      BOOTROM_SIZE : natural := 4*1024  -- processor-internal boot ROM memory size in bytes
1461 
    );
1462 2 zero_gravi 
    port (
1463 
      clk_i  : in  std_ulogic; -- global clock line
1464 
      rden_i : in  std_ulogic; -- read enable
1465 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1466 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1467 
      ack_o  : out std_ulogic -- transfer acknowledge
1468 
    );
1469 
  end component;
1470 
 
1471 
  -- Component: Machine System Timer (mtime) ------------------------------------------------
1472 
  -- -------------------------------------------------------------------------------------------
1473 
  component neorv32_mtime
1474 
    port (
1475 
      -- host access --
1476 
      clk_i     : in  std_ulogic; -- global clock line
1477 4 zero_gravi 
      rstn_i    : in  std_ulogic := '0'; -- global reset, low-active, async
1478 2 zero_gravi 
      addr_i    : in  std_ulogic_vector(31 downto 0); -- address
1479 
      rden_i    : in  std_ulogic; -- read enable
1480 
      wren_i    : in  std_ulogic; -- write enable
1481 
      data_i    : in  std_ulogic_vector(31 downto 0); -- data in
1482 
      data_o    : out std_ulogic_vector(31 downto 0); -- data out
1483 
      ack_o     : out std_ulogic; -- transfer acknowledge
1484 11 zero_gravi 
      -- time output for CPU --
1485 
      time_o    : out std_ulogic_vector(63 downto 0); -- current system time
1486 2 zero_gravi 
      -- interrupt --
1487 
      irq_o     : out std_ulogic  -- interrupt request
1488 
    );
1489 
  end component;
1490 
 
1491 
  -- Component: General Purpose Input/Output Port (GPIO) ------------------------------------
1492 
  -- -------------------------------------------------------------------------------------------
1493 
  component neorv32_gpio
1494 
    port (
1495 
      -- host access --
1496 
      clk_i  : in  std_ulogic; -- global clock line
1497 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1498 
      rden_i : in  std_ulogic; -- read enable
1499 
      wren_i : in  std_ulogic; -- write enable
1500 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1501 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1502 
      ack_o  : out std_ulogic; -- transfer acknowledge
1503 
      -- parallel io --
1504 22 zero_gravi 
      gpio_o : out std_ulogic_vector(31 downto 0);
1505 
      gpio_i : in  std_ulogic_vector(31 downto 0);
1506 2 zero_gravi 
      -- interrupt --
1507 
      irq_o  : out std_ulogic
1508 
    );
1509 
  end component;
1510 
 
1511 
  -- Component: Watchdog Timer (WDT) --------------------------------------------------------
1512 
  -- -------------------------------------------------------------------------------------------
1513 
  component neorv32_wdt
1514 
    port (
1515 
      -- host access --
1516 
      clk_i       : in  std_ulogic; -- global clock line
1517 
      rstn_i      : in  std_ulogic; -- global reset line, low-active
1518 
      rden_i      : in  std_ulogic; -- read enable
1519 
      wren_i      : in  std_ulogic; -- write enable
1520 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1521 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1522 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1523 
      ack_o       : out std_ulogic; -- transfer acknowledge
1524 
      -- clock generator --
1525 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1526 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1527 
      -- timeout event --
1528 
      irq_o       : out std_ulogic; -- timeout IRQ
1529 
      rstn_o      : out std_ulogic  -- timeout reset, low_active, use it as async!
1530 
    );
1531 
  end component;
1532 
 
1533 
  -- Component: Universal Asynchronous Receiver and Transmitter (UART) ----------------------
1534 
  -- -------------------------------------------------------------------------------------------
1535 
  component neorv32_uart
1536 50 zero_gravi 
    generic (
1537 
      UART_PRIMARY : boolean := true -- true = primary UART (UART0), false = secondary UART (UART1)
1538 
    );
1539 2 zero_gravi 
    port (
1540 
      -- host access --
1541 
      clk_i       : in  std_ulogic; -- global clock line
1542 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1543 
      rden_i      : in  std_ulogic; -- read enable
1544 
      wren_i      : in  std_ulogic; -- write enable
1545 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1546 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1547 
      ack_o       : out std_ulogic; -- transfer acknowledge
1548 
      -- clock generator --
1549 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1550 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1551 
      -- com lines --
1552 
      uart_txd_o  : out std_ulogic;
1553 
      uart_rxd_i  : in  std_ulogic;
1554 51 zero_gravi 
      -- hardware flow control --
1555 
      uart_rts_o  : out std_ulogic; -- UART.RX ready to receive ("RTR"), low-active, optional
1556 
      uart_cts_i  : in  std_ulogic; -- UART.TX allowed to transmit, low-active, optional
1557 2 zero_gravi 
      -- interrupts --
1558 48 zero_gravi 
      irq_rxd_o   : out std_ulogic; -- uart data received interrupt
1559 
      irq_txd_o   : out std_ulogic  -- uart transmission done interrupt
1560 2 zero_gravi 
    );
1561 
  end component;
1562 
 
1563 
  -- Component: Serial Peripheral Interface (SPI) -------------------------------------------
1564 
  -- -------------------------------------------------------------------------------------------
1565 
  component neorv32_spi
1566 
    port (
1567 
      -- host access --
1568 
      clk_i       : in  std_ulogic; -- global clock line
1569 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1570 
      rden_i      : in  std_ulogic; -- read enable
1571 
      wren_i      : in  std_ulogic; -- write enable
1572 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1573 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1574 
      ack_o       : out std_ulogic; -- transfer acknowledge
1575 
      -- clock generator --
1576 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1577 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1578 
      -- com lines --
1579 6 zero_gravi 
      spi_sck_o   : out std_ulogic; -- SPI serial clock
1580 
      spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
1581 
      spi_sdi_i   : in  std_ulogic; -- controller data in, peripheral data out
1582 2 zero_gravi 
      spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
1583 
      -- interrupt --
1584 48 zero_gravi 
      irq_o       : out std_ulogic -- transmission done interrupt
1585 2 zero_gravi 
    );
1586 
  end component;
1587 
 
1588 
  -- Component: Two-Wire Interface (TWI) ----------------------------------------------------
1589 
  -- -------------------------------------------------------------------------------------------
1590 
  component neorv32_twi
1591 
    port (
1592 
      -- host access --
1593 
      clk_i       : in  std_ulogic; -- global clock line
1594 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1595 
      rden_i      : in  std_ulogic; -- read enable
1596 
      wren_i      : in  std_ulogic; -- write enable
1597 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1598 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1599 
      ack_o       : out std_ulogic; -- transfer acknowledge
1600 
      -- clock generator --
1601 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1602 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1603 
      -- com lines --
1604 
      twi_sda_io  : inout std_logic; -- serial data line
1605 
      twi_scl_io  : inout std_logic; -- serial clock line
1606 
      -- interrupt --
1607 48 zero_gravi 
      irq_o       : out std_ulogic -- transfer done IRQ
1608 2 zero_gravi 
    );
1609 
  end component;
1610 
 
1611 
  -- Component: Pulse-Width Modulation Controller (PWM) -------------------------------------
1612 
  -- -------------------------------------------------------------------------------------------
1613 
  component neorv32_pwm
1614 
    port (
1615 
      -- host access --
1616 
      clk_i       : in  std_ulogic; -- global clock line
1617 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1618 
      rden_i      : in  std_ulogic; -- read enable
1619 
      wren_i      : in  std_ulogic; -- write enable
1620 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1621 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1622 
      ack_o       : out std_ulogic; -- transfer acknowledge
1623 
      -- clock generator --
1624 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1625 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1626 
      -- pwm output channels --
1627 
      pwm_o       : out std_ulogic_vector(03 downto 0)
1628 
    );
1629 
  end component;
1630 
 
1631 
  -- Component: True Random Number Generator (TRNG) -----------------------------------------
1632 
  -- -------------------------------------------------------------------------------------------
1633 
  component neorv32_trng
1634 
    port (
1635 
      -- host access --
1636 
      clk_i  : in  std_ulogic; -- global clock line
1637 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1638 
      rden_i : in  std_ulogic; -- read enable
1639 
      wren_i : in  std_ulogic; -- write enable
1640 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1641 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1642 
      ack_o  : out std_ulogic  -- transfer acknowledge
1643 
    );
1644 
  end component;
1645 
 
1646 
  -- Component: Wishbone Bus Gateway (WISHBONE) ---------------------------------------------
1647 
  -- -------------------------------------------------------------------------------------------
1648 
  component neorv32_wishbone
1649 
    generic (
1650 35 zero_gravi 
      WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
1651 23 zero_gravi 
      -- Internal instruction memory --
1652 44 zero_gravi 
      MEM_INT_IMEM_EN   : boolean := true;   -- implement processor-internal instruction memory
1653 35 zero_gravi 
      MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
1654 23 zero_gravi 
      -- Internal data memory --
1655 44 zero_gravi 
      MEM_INT_DMEM_EN   : boolean := true;   -- implement processor-internal data memory
1656 57 zero_gravi 
      MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
1657 
      -- Bus Timeout --
1658 
      BUS_TIMEOUT       : natural := 63      -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
1659 2 zero_gravi 
    );
1660 
    port (
1661 
      -- global control --
1662 57 zero_gravi 
      clk_i     : in  std_ulogic; -- global clock line
1663 
      rstn_i    : in  std_ulogic; -- global reset line, low-active
1664 2 zero_gravi 
      -- host access --
1665 57 zero_gravi 
      src_i     : in  std_ulogic; -- access type (0: data, 1:instruction)
1666 
      addr_i    : in  std_ulogic_vector(31 downto 0); -- address
1667 
      rden_i    : in  std_ulogic; -- read enable
1668 
      wren_i    : in  std_ulogic; -- write enable
1669 
      ben_i     : in  std_ulogic_vector(03 downto 0); -- byte write enable
1670 
      data_i    : in  std_ulogic_vector(31 downto 0); -- data in
1671 
      data_o    : out std_ulogic_vector(31 downto 0); -- data out
1672 
      lock_i    : in  std_ulogic; -- exclusive access request
1673 
      ack_o     : out std_ulogic; -- transfer acknowledge
1674 
      err_o     : out std_ulogic; -- transfer error
1675 
      priv_i    : in  std_ulogic_vector(01 downto 0); -- current CPU privilege level
1676 2 zero_gravi 
      -- wishbone interface --
1677 57 zero_gravi 
      wb_tag_o  : out std_ulogic_vector(02 downto 0); -- request tag
1678 
      wb_adr_o  : out std_ulogic_vector(31 downto 0); -- address
1679 
      wb_dat_i  : in  std_ulogic_vector(31 downto 0); -- read data
1680 
      wb_dat_o  : out std_ulogic_vector(31 downto 0); -- write data
1681 
      wb_we_o   : out std_ulogic; -- read/write
1682 
      wb_sel_o  : out std_ulogic_vector(03 downto 0); -- byte enable
1683 
      wb_stb_o  : out std_ulogic; -- strobe
1684 
      wb_cyc_o  : out std_ulogic; -- valid cycle
1685 
      wb_lock_o : out std_ulogic; -- exclusive access request
1686 
      wb_ack_i  : in  std_ulogic; -- transfer acknowledge
1687 
      wb_err_i  : in  std_ulogic  -- transfer error
1688 2 zero_gravi 
    );
1689 
  end component;
1690 
 
1691 47 zero_gravi 
  -- Component: Custom Functions Subsystem (CFS) --------------------------------------------
1692 23 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1693 47 zero_gravi 
  component neorv32_cfs
1694 
    generic (
1695 52 zero_gravi 
      CFS_CONFIG   : std_ulogic_vector(31 downto 0); -- custom CFS configuration generic
1696 
      CFS_IN_SIZE  : positive := 32;  -- size of CFS input conduit in bits
1697 
      CFS_OUT_SIZE : positive := 32   -- size of CFS output conduit in bits
1698 23 zero_gravi 
    );
1699 34 zero_gravi 
    port (
1700 
      -- host access --
1701 
      clk_i       : in  std_ulogic; -- global clock line
1702 
      rstn_i      : in  std_ulogic; -- global reset line, low-active, use as async
1703 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1704 
      rden_i      : in  std_ulogic; -- read enable
1705 47 zero_gravi 
      wren_i      : in  std_ulogic; -- word write enable
1706 34 zero_gravi 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1707 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1708 
      ack_o       : out std_ulogic; -- transfer acknowledge
1709 
      -- clock generator --
1710 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1711 47 zero_gravi 
      clkgen_i    : in  std_ulogic_vector(07 downto 0); -- "clock" inputs
1712 
      -- CPU state --
1713 
      sleep_i     : in  std_ulogic; -- set if cpu is in sleep mode
1714 
      -- interrupt --
1715 
      irq_o       : out std_ulogic; -- interrupt request
1716 
      irq_ack_i   : in  std_ulogic; -- interrupt acknowledge
1717 
      -- custom io (conduit) --
1718 52 zero_gravi 
      cfs_in_i    : in  std_ulogic_vector(CFS_IN_SIZE-1 downto 0);  -- custom inputs
1719 
      cfs_out_o   : out std_ulogic_vector(CFS_OUT_SIZE-1 downto 0)  -- custom outputs
1720 34 zero_gravi 
    );
1721 
  end component;
1722 
 
1723 49 zero_gravi 
  -- Component: Numerically-Controlled Oscillator (NCO) -------------------------------------
1724 
  -- -------------------------------------------------------------------------------------------
1725 
  component neorv32_nco
1726 
    port (
1727 
      -- host access --
1728 
      clk_i       : in  std_ulogic; -- global clock line
1729 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1730 
      rden_i      : in  std_ulogic; -- read enable
1731 
      wren_i      : in  std_ulogic; -- write enable
1732 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1733 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1734 
      ack_o       : out std_ulogic; -- transfer acknowledge
1735 
      -- clock generator --
1736 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1737 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1738 
      -- NCO output --
1739 
      nco_o       : out std_ulogic_vector(02 downto 0)
1740 
    );
1741 
  end component;
1742 
 
1743 52 zero_gravi 
  -- Component: Smart LED (WS2811/WS2812) Interface (NEOLED) --------------------------------
1744 
  -- -------------------------------------------------------------------------------------------
1745 
  component neorv32_neoled
1746 
    port (
1747 
      -- host access --
1748 
      clk_i       : in  std_ulogic; -- global clock line
1749 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1750 
      rden_i      : in  std_ulogic; -- read enable
1751 
      wren_i      : in  std_ulogic; -- write enable
1752 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1753 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1754 
      ack_o       : out std_ulogic; -- transfer acknowledge
1755 
      -- clock generator --
1756 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1757 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1758 
      -- interrupt --
1759 
      irq_o       : out std_ulogic; -- interrupt request
1760 
      -- NEOLED output --
1761 
      neoled_o    : out std_ulogic -- serial async data line
1762 
    );
1763 
  end component;
1764 
 
1765 23 zero_gravi 
  -- Component: System Configuration Information Memory (SYSINFO) ---------------------------
1766 
  -- -------------------------------------------------------------------------------------------
1767 12 zero_gravi 
  component neorv32_sysinfo
1768 
    generic (
1769 
      -- General --
1770 41 zero_gravi 
      CLOCK_FREQUENCY      : natural := 0;      -- clock frequency of clk_i in Hz
1771 44 zero_gravi 
      BOOTLOADER_EN        : boolean := true;   -- implement processor-internal bootloader?
1772 41 zero_gravi 
      USER_CODE            : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
1773 23 zero_gravi 
      -- Internal Instruction memory --
1774 44 zero_gravi 
      MEM_INT_IMEM_EN      : boolean := true;   -- implement processor-internal instruction memory
1775 41 zero_gravi 
      MEM_INT_IMEM_SIZE    : natural := 8*1024; -- size of processor-internal instruction memory in bytes
1776 
      MEM_INT_IMEM_ROM     : boolean := false;  -- implement processor-internal instruction memory as ROM
1777 23 zero_gravi 
      -- Internal Data memory --
1778 44 zero_gravi 
      MEM_INT_DMEM_EN      : boolean := true;   -- implement processor-internal data memory
1779 41 zero_gravi 
      MEM_INT_DMEM_SIZE    : natural := 4*1024; -- size of processor-internal data memory in bytes
1780 
      -- Internal Cache memory --
1781 44 zero_gravi 
      ICACHE_EN            : boolean := true;   -- implement instruction cache
1782 41 zero_gravi 
      ICACHE_NUM_BLOCKS    : natural := 4;      -- i-cache: number of blocks (min 2), has to be a power of 2
1783 
      ICACHE_BLOCK_SIZE    : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
1784 
      ICACHE_ASSOCIATIVITY : natural := 1;      -- i-cache: associativity (min 1), has to be a power 2
1785 23 zero_gravi 
      -- External memory interface --
1786 44 zero_gravi 
      MEM_EXT_EN           : boolean := false;  -- implement external memory bus interface?
1787 12 zero_gravi 
      -- Processor peripherals --
1788 44 zero_gravi 
      IO_GPIO_EN           : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
1789 
      IO_MTIME_EN          : boolean := true;   -- implement machine system timer (MTIME)?
1790 50 zero_gravi 
      IO_UART0_EN          : boolean := true;   -- implement primary universal asynchronous receiver/transmitter (UART0)?
1791 
      IO_UART1_EN          : boolean := true;   -- implement secondary universal asynchronous receiver/transmitter (UART1)?
1792 44 zero_gravi 
      IO_SPI_EN            : boolean := true;   -- implement serial peripheral interface (SPI)?
1793 
      IO_TWI_EN            : boolean := true;   -- implement two-wire interface (TWI)?
1794 
      IO_PWM_EN            : boolean := true;   -- implement pulse-width modulation unit (PWM)?
1795 
      IO_WDT_EN            : boolean := true;   -- implement watch dog timer (WDT)?
1796 
      IO_TRNG_EN           : boolean := true;   -- implement true random number generator (TRNG)?
1797 49 zero_gravi 
      IO_CFS_EN            : boolean := true;   -- implement custom functions subsystem (CFS)?
1798 52 zero_gravi 
      IO_NCO_EN            : boolean := true;   -- implement numerically-controlled oscillator (NCO)?
1799 
      IO_NEOLED_EN         : boolean := true    -- implement NeoPixel-compatible smart LED interface (NEOLED)?
1800 12 zero_gravi 
    );
1801 
    port (
1802 
      -- host access --
1803 
      clk_i  : in  std_ulogic; -- global clock line
1804 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1805 
      rden_i : in  std_ulogic; -- read enable
1806 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1807 
      ack_o  : out std_ulogic  -- transfer acknowledge
1808 
    );
1809 
  end component;
1810 
 
1811 2 zero_gravi 
end neorv32_package;
1812 
 
1813 
package body neorv32_package is
1814 
 
1815 41 zero_gravi 
  -- Function: Minimal required number of bits to represent input number --------------------
1816 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1817 
  function index_size_f(input : natural) return natural is
1818 
  begin
1819 
    for i in 0 to natural'high loop
1820 
      if (2**i >= input) then
1821 
        return i;
1822 
      end if;
1823 
    end loop; -- i
1824 
    return 0;
1825 
  end function index_size_f;
1826 
 
1827 
  -- Function: Conditional select natural ---------------------------------------------------
1828 
  -- -------------------------------------------------------------------------------------------
1829 
  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural is
1830 
  begin
1831 
    if (cond = true) then
1832 
      return val_t;
1833 
    else
1834 
      return val_f;
1835 
    end if;
1836 
  end function cond_sel_natural_f;
1837 
 
1838 56 zero_gravi 
  -- Function: Conditional select integer ---------------------------------------------------
1839 
  -- -------------------------------------------------------------------------------------------
1840 
  function cond_sel_int_f(cond : boolean; val_t : integer; val_f : integer) return integer is
1841 
  begin
1842 
    if (cond = true) then
1843 
      return val_t;
1844 
    else
1845 
      return val_f;
1846 
    end if;
1847 
  end function cond_sel_int_f;
1848 
 
1849 2 zero_gravi 
  -- Function: Conditional select std_ulogic_vector -----------------------------------------
1850 
  -- -------------------------------------------------------------------------------------------
1851 
  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector is
1852 
  begin
1853 
    if (cond = true) then
1854 
      return val_t;
1855 
    else
1856 
      return val_f;
1857 
    end if;
1858 
  end function cond_sel_stdulogicvector_f;
1859 
 
1860 56 zero_gravi 
  -- Function: Conditional select std_ulogic ------------------------------------------------
1861 
  -- -------------------------------------------------------------------------------------------
1862 
  function cond_sel_stdulogic_f(cond : boolean; val_t : std_ulogic; val_f : std_ulogic) return std_ulogic is
1863 
  begin
1864 
    if (cond = true) then
1865 
      return val_t;
1866 
    else
1867 
      return val_f;
1868 
    end if;
1869 
  end function cond_sel_stdulogic_f;
1870 
 
1871 50 zero_gravi 
  -- Function: Conditional select string ----------------------------------------------------
1872 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1873 50 zero_gravi 
  function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string is
1874 
  begin
1875 
    if (cond = true) then
1876 
      return val_t;
1877 
    else
1878 
      return val_f;
1879 
    end if;
1880 
  end function cond_sel_string_f;
1881 
 
1882 
  -- Function: Convert bool to std_ulogic ---------------------------------------------------
1883 
  -- -------------------------------------------------------------------------------------------
1884 2 zero_gravi 
  function bool_to_ulogic_f(cond : boolean) return std_ulogic is
1885 
  begin
1886 
    if (cond = true) then
1887 
      return '1';
1888 
    else
1889 
      return '0';
1890 
    end if;
1891 
  end function bool_to_ulogic_f;
1892 
 
1893 
  -- Function: OR all bits ------------------------------------------------------------------
1894 
  -- -------------------------------------------------------------------------------------------
1895 
  function or_all_f(a : std_ulogic_vector) return std_ulogic is
1896 
    variable tmp_v : std_ulogic;
1897 
  begin
1898 56 zero_gravi 
    tmp_v := '0';
1899 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1900 56 zero_gravi 
      for i in a'low to a'high loop
1901 15 zero_gravi 
        tmp_v := tmp_v or a(i);
1902 
      end loop; -- i
1903 
    end if;
1904 2 zero_gravi 
    return tmp_v;
1905 
  end function or_all_f;
1906 
 
1907 
  -- Function: AND all bits -----------------------------------------------------------------
1908 
  -- -------------------------------------------------------------------------------------------
1909 
  function and_all_f(a : std_ulogic_vector) return std_ulogic is
1910 
    variable tmp_v : std_ulogic;
1911 
  begin
1912 56 zero_gravi 
    tmp_v := '1';
1913 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1914 56 zero_gravi 
      for i in a'low to a'high loop
1915 15 zero_gravi 
        tmp_v := tmp_v and a(i);
1916 
      end loop; -- i
1917 
    end if;
1918 2 zero_gravi 
    return tmp_v;
1919 
  end function and_all_f;
1920 
 
1921 
  -- Function: XOR all bits -----------------------------------------------------------------
1922 
  -- -------------------------------------------------------------------------------------------
1923 
  function xor_all_f(a : std_ulogic_vector) return std_ulogic is
1924 
    variable tmp_v : std_ulogic;
1925 
  begin
1926 56 zero_gravi 
    tmp_v := '0';
1927 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1928 56 zero_gravi 
      for i in a'low to a'high loop
1929 15 zero_gravi 
        tmp_v := tmp_v xor a(i);
1930 
      end loop; -- i
1931 
    end if;
1932 2 zero_gravi 
    return tmp_v;
1933 
  end function xor_all_f;
1934 
 
1935 
  -- Function: XNOR all bits ----------------------------------------------------------------
1936 
  -- -------------------------------------------------------------------------------------------
1937 
  function xnor_all_f(a : std_ulogic_vector) return std_ulogic is
1938 
    variable tmp_v : std_ulogic;
1939 
  begin
1940 56 zero_gravi 
    tmp_v := '1';
1941 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1942 56 zero_gravi 
      for i in a'low to a'high loop
1943 15 zero_gravi 
        tmp_v := tmp_v xnor a(i);
1944 
      end loop; -- i
1945 
    end if;
1946 2 zero_gravi 
    return tmp_v;
1947 
  end function xnor_all_f;
1948 
 
1949 40 zero_gravi 
  -- Function: Convert std_ulogic_vector to hex char ----------------------------------------
1950 6 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1951 
  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character is
1952 
    variable output_v : character;
1953 
  begin
1954 
    case input is
1955 7 zero_gravi 
      when x"0"   => output_v := '0';
1956 
      when x"1"   => output_v := '1';
1957 
      when x"2"   => output_v := '2';
1958 
      when x"3"   => output_v := '3';
1959 
      when x"4"   => output_v := '4';
1960 
      when x"5"   => output_v := '5';
1961 
      when x"6"   => output_v := '6';
1962 
      when x"7"   => output_v := '7';
1963 
      when x"8"   => output_v := '8';
1964 
      when x"9"   => output_v := '9';
1965 
      when x"a"   => output_v := 'a';
1966 
      when x"b"   => output_v := 'b';
1967 
      when x"c"   => output_v := 'c';
1968 
      when x"d"   => output_v := 'd';
1969 
      when x"e"   => output_v := 'e';
1970 
      when x"f"   => output_v := 'f';
1971 6 zero_gravi 
      when others => output_v := '?';
1972 
    end case;
1973 
    return output_v;
1974 
  end function to_hexchar_f;
1975 
 
1976 40 zero_gravi 
  -- Function: Convert hex char to std_ulogic_vector ----------------------------------------
1977 
  -- -------------------------------------------------------------------------------------------
1978 
  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector is
1979 
    variable hex_value_v : std_ulogic_vector(3 downto 0);
1980 
  begin
1981 
    case input is
1982 
      when '0'       => hex_value_v := x"0";
1983 
      when '1'       => hex_value_v := x"1";
1984 
      when '2'       => hex_value_v := x"2";
1985 
      when '3'       => hex_value_v := x"3";
1986 
      when '4'       => hex_value_v := x"4";
1987 
      when '5'       => hex_value_v := x"5";
1988 
      when '6'       => hex_value_v := x"6";
1989 
      when '7'       => hex_value_v := x"7";
1990 
      when '8'       => hex_value_v := x"8";
1991 
      when '9'       => hex_value_v := x"9";
1992 
      when 'a' | 'A' => hex_value_v := x"a";
1993 
      when 'b' | 'B' => hex_value_v := x"b";
1994 
      when 'c' | 'C' => hex_value_v := x"c";
1995 
      when 'd' | 'D' => hex_value_v := x"d";
1996 
      when 'e' | 'E' => hex_value_v := x"e";
1997 
      when 'f' | 'F' => hex_value_v := x"f";
1998 
      when others    => hex_value_v := (others => 'X');
1999 
    end case;
2000 
    return hex_value_v;
2001 
  end function hexchar_to_stdulogicvector_f;
2002 
 
2003 32 zero_gravi 
  -- Function: Bit reversal -----------------------------------------------------------------
2004 
  -- -------------------------------------------------------------------------------------------
2005 
  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector is
2006 
    variable output_v : std_ulogic_vector(input'range);
2007 
  begin
2008 
    for i in 0 to input'length-1 loop
2009 
      output_v(input'length-i-1) := input(i);
2010 
    end loop; -- i
2011 
    return output_v;
2012 
  end function bit_rev_f;
2013 
 
2014 36 zero_gravi 
  -- Function: Test if input number is a power of two ---------------------------------------
2015 
  -- -------------------------------------------------------------------------------------------
2016 
  function is_power_of_two_f(input : natural) return boolean is
2017 
  begin
2018 38 zero_gravi 
    if (input = 1) then -- 2^0
2019 36 zero_gravi 
      return true;
2020 38 zero_gravi 
    elsif ((input / 2) /= 0) and ((input mod 2) = 0) then
2021 
      return true;
2022 36 zero_gravi 
    else
2023 
      return false;
2024 
    end if;
2025 
  end function is_power_of_two_f;
2026 
 
2027 40 zero_gravi 
  -- Function: Swap all bytes of a 32-bit word (endianness conversion) ----------------------
2028 
  -- -------------------------------------------------------------------------------------------
2029 
  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector is
2030 
    variable output_v : std_ulogic_vector(input'range);
2031 
  begin
2032 
    output_v(07 downto 00) := input(31 downto 24);
2033 
    output_v(15 downto 08) := input(23 downto 16);
2034 
    output_v(23 downto 16) := input(15 downto 08);
2035 
    output_v(31 downto 24) := input(07 downto 00);
2036 
    return output_v;
2037 
  end function bswap32_f;
2038 
 
2039 2 zero_gravi 
end neorv32_package;

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