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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_pwm.vhd] - Blame information for rev 66

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-- #################################################################################################
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-- # << NEORV32 - Pulse Width Modulation Controller (PWM) >>                                       #
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-- # ********************************************************************************************* #
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-- # Simple PWM controller with 8 bit resolution for the duty cycle and programmable base          #
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-- # frequency. The controller supports up to 60 PWM channels.                                     #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
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-- #                                                                                               #
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-- # Redistribution and use in source and binary forms, with or without modification, are          #
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-- # permitted provided that the following conditions are met:                                     #
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-- #                                                                                               #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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-- #    conditions and the following disclaimer.                                                   #
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-- #                                                                                               #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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-- #    conditions and the following disclaimer in the documentation and/or other materials        #
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-- #    provided with the distribution.                                                            #
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-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
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-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_pwm is
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  generic (
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    NUM_CHANNELS : natural -- number of PWM channels (0..60)
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  );
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  port (
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    -- host access --
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    clk_i       : in  std_ulogic; -- global clock line
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    addr_i      : in  std_ulogic_vector(31 downto 0); -- address
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    rden_i      : in  std_ulogic; -- read enable
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    wren_i      : in  std_ulogic; -- write enable
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    data_i      : in  std_ulogic_vector(31 downto 0); -- data in
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    data_o      : out std_ulogic_vector(31 downto 0); -- data out
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    ack_o       : out std_ulogic; -- transfer acknowledge
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    -- clock generator --
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    clkgen_en_o : out std_ulogic; -- enable clock generator
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    clkgen_i    : in  std_ulogic_vector(07 downto 0);
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    -- pwm output channels --
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    pwm_o       : out std_ulogic_vector(NUM_CHANNELS-1 downto 0)
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  );
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end neorv32_pwm;
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architecture neorv32_pwm_rtl of neorv32_pwm is
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  -- IO space: module base address --
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  constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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  constant lo_abb_c : natural := index_size_f(pwm_size_c); -- low address boundary bit
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  -- Control register bits --
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  constant ctrl_enable_c    : natural := 0; -- r/w: PWM enable
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  constant ctrl_prsc0_bit_c : natural := 1; -- r/w: prescaler select bit 0
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  constant ctrl_prsc1_bit_c : natural := 2; -- r/w: prescaler select bit 1
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  constant ctrl_prsc2_bit_c : natural := 3; -- r/w: prescaler select bit 2
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  -- access control --
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  signal acc_en : std_ulogic; -- module access enable
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  signal addr   : std_ulogic_vector(31 downto 0); -- access address
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  signal wren   : std_ulogic; -- write enable
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  signal rden   : std_ulogic; -- read enable
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  -- accessible regs --
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  type pwm_ch_t is array (0 to NUM_CHANNELS-1) of std_ulogic_vector(7 downto 0);
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  signal pwm_ch : pwm_ch_t; -- duty cycle (r/w)
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  signal enable : std_ulogic; -- enable unit (r/w)
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  signal prsc   : std_ulogic_vector(2 downto 0); -- clock prescaler (r/w)
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  type pwm_ch_rd_t is array (0 to 60-1) of std_ulogic_vector(7 downto 0);
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  signal pwm_ch_rd : pwm_ch_rd_t; -- duty cycle read-back
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  -- prescaler clock generator --
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  signal prsc_tick : std_ulogic;
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  -- pwm core counter --
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  signal pwm_cnt : std_ulogic_vector(7 downto 0);
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begin
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  -- Sanity Checks --------------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  assert not (NUM_CHANNELS > 60) report "NEORV32 PROCESSOR CONFIG ERROR! <IO.PWM> invalid number of channels! Has to be 0..60.!" severity error;
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  -- Access Control -------------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = pwm_base_c(hi_abb_c downto lo_abb_c)) else '0';
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  addr   <= pwm_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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  rden   <= acc_en and rden_i;
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  wren   <= acc_en and wren_i;
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  -- Write access ---------------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  wr_access: process(clk_i)
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  begin
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    if rising_edge(clk_i) then
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      ack_o <= rden or wren;
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      -- write access --
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      if (wren = '1') then
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        -- control register --
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        if (addr = pwm_ctrl_addr_c) then
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          enable <= data_i(ctrl_enable_c);
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          prsc   <= data_i(ctrl_prsc2_bit_c downto ctrl_prsc0_bit_c);
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        end if;
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        -- duty cycle registers --
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        for i in 0 to NUM_CHANNELS-1 loop -- channel loop
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          if (addr(5 downto 2) = std_ulogic_vector(to_unsigned((i/4)+1, 4))) then -- 4 channels per register; add ctrl reg offset
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            pwm_ch(i) <= data_i((i mod 4)*8+7 downto (i mod 4)*8+0);
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          end if;
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        end loop;
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      end if;
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      -- read access --
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      data_o <= (others => '0');
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      if (rden = '1') then
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        case addr(5 downto 2) is
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          when x"0"   => data_o(ctrl_enable_c) <= enable; data_o(ctrl_prsc2_bit_c downto ctrl_prsc0_bit_c) <= prsc;
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          when x"1"   => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(3)  & pwm_ch_rd(2)  & pwm_ch_rd(1)  & pwm_ch_rd(0);  else NULL; end if;
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          when x"2"   => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(7)  & pwm_ch_rd(6)  & pwm_ch_rd(5)  & pwm_ch_rd(4);  else NULL; end if;
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          when x"3"   => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(11) & pwm_ch_rd(10) & pwm_ch_rd(9)  & pwm_ch_rd(8);  else NULL; end if;
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          when x"4"   => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(15) & pwm_ch_rd(14) & pwm_ch_rd(13) & pwm_ch_rd(12); else NULL; end if;
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          when x"5"   => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(19) & pwm_ch_rd(18) & pwm_ch_rd(17) & pwm_ch_rd(16); else NULL; end if;
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          when x"6"   => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(23) & pwm_ch_rd(22) & pwm_ch_rd(21) & pwm_ch_rd(20); else NULL; end if;
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          when x"7"   => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(27) & pwm_ch_rd(26) & pwm_ch_rd(25) & pwm_ch_rd(24); else NULL; end if;
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          when x"8"   => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(31) & pwm_ch_rd(30) & pwm_ch_rd(29) & pwm_ch_rd(28); else NULL; end if;
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          when x"9"   => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(35) & pwm_ch_rd(34) & pwm_ch_rd(33) & pwm_ch_rd(32); else NULL; end if;
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          when x"a"   => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(39) & pwm_ch_rd(38) & pwm_ch_rd(37) & pwm_ch_rd(36); else NULL; end if;
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          when x"b"   => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(43) & pwm_ch_rd(42) & pwm_ch_rd(41) & pwm_ch_rd(40); else NULL; end if;
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          when x"c"   => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(47) & pwm_ch_rd(46) & pwm_ch_rd(45) & pwm_ch_rd(44); else NULL; end if;
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          when x"d"   => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(51) & pwm_ch_rd(50) & pwm_ch_rd(49) & pwm_ch_rd(48); else NULL; end if;
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          when x"e"   => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(55) & pwm_ch_rd(54) & pwm_ch_rd(53) & pwm_ch_rd(52); else NULL; end if;
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          when x"f"   => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(59) & pwm_ch_rd(58) & pwm_ch_rd(57) & pwm_ch_rd(56); else NULL; end if;
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          when others => NULL;
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        end case;
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      end if;
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    end if;
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  end process wr_access;
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  -- duty cycle read-back --
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  pwm_dc_rd_gen: process(pwm_ch)
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  begin
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    pwm_ch_rd <= (others => (others => '0'));
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    for i in 0 to NUM_CHANNELS-1 loop
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      pwm_ch_rd(i) <= pwm_ch(i);
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    end loop;
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  end process pwm_dc_rd_gen;
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  -- PWM clock select --
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  clkgen_en_o <= enable; -- enable clock generator
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  prsc_tick   <= clkgen_i(to_integer(unsigned(prsc)));
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175
 
176
  -- PWM Core -------------------------------------------------------------------------------
177
  -- -------------------------------------------------------------------------------------------
178
  pwm_core: process(clk_i)
179
  begin
180
    if rising_edge(clk_i) then
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      -- pwm base counter --
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      if (enable = '0') then
183
        pwm_cnt <= (others => '0');
184
      elsif (prsc_tick = '1') then
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        pwm_cnt <= std_ulogic_vector(unsigned(pwm_cnt) + 1);
186
      end if;
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      -- channels --
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      for i in 0 to NUM_CHANNELS-1 loop
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        if (unsigned(pwm_cnt) >= unsigned(pwm_ch(i))) or (enable = '0') then
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          pwm_o(i) <= '0';
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        else
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          pwm_o(i) <= '1';
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        end if;
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      end loop;
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    end if;
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  end process pwm_core;
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end neorv32_pwm_rtl;

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