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zero_gravi |
-- #################################################################################################
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-- # << NEORV32 - Stream Link Interface (SLINK) >> #
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-- # ********************************************************************************************* #
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-- # Up to 8 input (RX) and up to 8 output (TX) stream links are supported. Each stream direction #
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-- # provides a global interrupt to indicate that a RX link has received new data or that a TX #
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-- # has finished sending data. Each link is provides an internal FIFO for buffering. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_slink is
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generic (
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48 |
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SLINK_NUM_TX : natural := 8; -- number of TX links (0..8)
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SLINK_NUM_RX : natural := 8; -- number of TX links (0..8)
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SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two
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SLINK_RX_FIFO : natural := 1 -- RX fifo depth, has to be a power of two
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);
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port (
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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-- interrupt --
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irq_tx_o : out std_ulogic; -- transmission done
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irq_rx_o : out std_ulogic; -- data received
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-- TX stream interfaces --
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slink_tx_dat_o : out sdata_8x32_t; -- output data
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slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output
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slink_tx_rdy_i : in std_ulogic_vector(7 downto 0); -- ready to send
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-- RX stream interfaces --
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slink_rx_dat_i : in sdata_8x32_t; -- input data
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slink_rx_val_i : in std_ulogic_vector(7 downto 0); -- valid input
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slink_rx_rdy_o : out std_ulogic_vector(7 downto 0) -- ready to receive
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);
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end neorv32_slink;
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architecture neorv32_slink_rtl of neorv32_slink is
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-- IO space: module base address --
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant lo_abb_c : natural := index_size_f(slink_size_c); -- low address boundary bit
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-- control reg bits --
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constant ctrl_rx0_avail_c : natural := 0; -- r/-: set if TX link 0 is ready to send
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constant ctrl_rx1_avail_c : natural := 1; -- r/-: set if TX link 1 is ready to send
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constant ctrl_rx2_avail_c : natural := 2; -- r/-: set if TX link 2 is ready to send
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constant ctrl_rx3_avail_c : natural := 3; -- r/-: set if TX link 3 is ready to send
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constant ctrl_rx4_avail_c : natural := 4; -- r/-: set if TX link 4 is ready to send
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constant ctrl_rx5_avail_c : natural := 5; -- r/-: set if TX link 5 is ready to send
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constant ctrl_rx6_avail_c : natural := 6; -- r/-: set if TX link 6 is ready to send
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constant ctrl_rx7_avail_c : natural := 7; -- r/-: set if TX link 7 is ready to send
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--
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constant ctrl_tx0_free_c : natural := 8; -- r/-: set if RX link 0 data available
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constant ctrl_tx1_free_c : natural := 9; -- r/-: set if RX link 1 data available
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constant ctrl_tx2_free_c : natural := 10; -- r/-: set if RX link 2 data available
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constant ctrl_tx3_free_c : natural := 11; -- r/-: set if RX link 3 data available
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constant ctrl_tx4_free_c : natural := 12; -- r/-: set if RX link 4 data available
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constant ctrl_tx5_free_c : natural := 13; -- r/-: set if RX link 5 data available
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constant ctrl_tx6_free_c : natural := 14; -- r/-: set if RX link 6 data available
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constant ctrl_tx7_free_c : natural := 15; -- r/-: set if RX link 7 data available
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--
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constant ctrl_rx_num0_c : natural := 16; -- r/-: number of implemented RX links -1 bit 0
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constant ctrl_rx_num1_c : natural := 17; -- r/-: number of implemented RX links -1 bit 1
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constant ctrl_rx_num2_c : natural := 18; -- r/-: number of implemented RX links -1 bit 2
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constant ctrl_tx_num0_c : natural := 19; -- r/-: number of implemented TX links -1 bit 0
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105 |
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constant ctrl_tx_num1_c : natural := 20; -- r/-: number of implemented TX links -1 bit 1
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constant ctrl_tx_num2_c : natural := 21; -- r/-: number of implemented TX links -1 bit 2
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--
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constant ctrl_rx_size0_c : natural := 22; -- r/-: log2(RX FIFO size) bit 0
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109 |
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constant ctrl_rx_size1_c : natural := 23; -- r/-: log2(RX FIFO size) bit 1
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constant ctrl_rx_size2_c : natural := 24; -- r/-: log2(RX FIFO size) bit 2
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111 |
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constant ctrl_rx_size3_c : natural := 25; -- r/-: log2(RX FIFO size) bit 3
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112 |
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constant ctrl_tx_size0_c : natural := 26; -- r/-: log2(TX FIFO size) bit 0
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113 |
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constant ctrl_tx_size1_c : natural := 27; -- r/-: log2(TX FIFO size) bit 1
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114 |
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constant ctrl_tx_size2_c : natural := 28; -- r/-: log2(TX FIFO size) bit 2
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constant ctrl_tx_size3_c : natural := 29; -- r/-: log2(TX FIFO size) bit 3
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116 |
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--
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117 |
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constant ctrl_en_c : natural := 31; -- r/w: global enable
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118 |
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119 |
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-- bus access control --
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120 |
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signal ack_read : std_ulogic;
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121 |
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signal ack_write : std_ulogic;
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122 |
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signal acc_en : std_ulogic;
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signal addr : std_ulogic_vector(31 downto 0);
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124 |
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125 |
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-- control register --
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126 |
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signal enable : std_ulogic; -- global enable
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127 |
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128 |
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-- interrupt generator --
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129 |
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signal tx_fifo_free_buf : std_ulogic_vector(7 downto 0);
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130 |
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signal rx_fifo_avail_buf : std_ulogic_vector(7 downto 0);
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131 |
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132 |
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-- stream link fifo interface --
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133 |
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type fifo_data_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
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134 |
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signal rx_fifo_rdata : fifo_data_t;
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signal fifo_clear : std_ulogic;
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136 |
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signal link_sel : std_ulogic_vector(7 downto 0);
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137 |
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signal tx_fifo_we, tx_fifo_free : std_ulogic_vector(7 downto 0);
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138 |
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signal rx_fifo_re, rx_fifo_avail : std_ulogic_vector(7 downto 0);
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139 |
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140 |
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begin
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141 |
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142 |
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-- Sanity Checks --------------------------------------------------------------------------
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143 |
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-- -------------------------------------------------------------------------------------------
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144 |
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assert not (is_power_of_two_f(SLINK_TX_FIFO) = false) report "NEORV32 PROCESSOR CONFIG ERROR: SLINK <SLINK_TX_FIFO> has to be a power of two." severity error;
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145 |
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assert not (SLINK_TX_FIFO > 2**15) report "NEORV32 PROCESSOR CONFIG ERROR: SLINK <SLINK_TX_FIFO> has to be 1..32768." severity error;
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146 |
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--
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147 |
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assert not (is_power_of_two_f(SLINK_RX_FIFO) = false) report "NEORV32 PROCESSOR CONFIG ERROR: SLINK <SLINK_RX_FIFO> has to be a power of two." severity error;
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148 |
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assert not (SLINK_RX_FIFO > 2**15) report "NEORV32 PROCESSOR CONFIG ERROR: SLINK <SLINK_RX_FIFO> has to be 1..32768." severity error;
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149 |
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--
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150 |
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assert not (SLINK_NUM_RX > 8) report "NEORV32 PROCESSOR CONFIG ERROR: SLINK <SLINK_NUM_RX> has to be 0..8." severity error;
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151 |
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assert not (SLINK_NUM_TX > 8) report "NEORV32 PROCESSOR CONFIG ERROR: SLINK <SLINK_NUM_TX> has to be 0..8." severity error;
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152 |
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--
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153 |
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assert false report "NEORV32 PROCESSOR CONFIG NOTE: Implementing " & integer'image(SLINK_NUM_RX) & " RX and " &
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154 |
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integer'image(SLINK_NUM_TX) & " TX stream links." severity note;
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155 |
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156 |
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157 |
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-- Access Control -------------------------------------------------------------------------
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158 |
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-- -------------------------------------------------------------------------------------------
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159 |
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = slink_base_c(hi_abb_c downto lo_abb_c)) else '0';
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160 |
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addr <= slink_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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161 |
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162 |
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163 |
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-- Read/Write Access ----------------------------------------------------------------------
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164 |
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-- -------------------------------------------------------------------------------------------
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165 |
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rw_access: process(clk_i)
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166 |
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begin
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167 |
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if rising_edge(clk_i) then
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168 |
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-- write access --
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169 |
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ack_write <= '0';
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170 |
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if (acc_en = '1') and (wren_i = '1') then
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171 |
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if (addr(5) = '0') then -- control register
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172 |
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enable <= data_i(ctrl_en_c);
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173 |
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ack_write <= '1';
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174 |
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else -- TX links
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175 |
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ack_write <= or_reduce_f(link_sel and tx_fifo_free);
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176 |
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end if;
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177 |
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end if;
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178 |
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|
179 |
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-- read access --
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180 |
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data_o <= (others => '0');
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181 |
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ack_read <= '0';
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182 |
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if (acc_en = '1') and (rden_i = '1') then
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183 |
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if (addr(5) = '0') then -- control register
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184 |
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data_o(ctrl_rx7_avail_c downto ctrl_rx0_avail_c) <= rx_fifo_avail;
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185 |
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data_o(ctrl_tx7_free_c downto ctrl_tx0_free_c) <= tx_fifo_free;
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186 |
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data_o(ctrl_rx_num2_c downto ctrl_rx_num0_c) <= std_ulogic_vector(to_unsigned(SLINK_NUM_RX-1, 3));
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187 |
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data_o(ctrl_tx_num2_c downto ctrl_tx_num0_c) <= std_ulogic_vector(to_unsigned(SLINK_NUM_TX-1, 3));
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188 |
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data_o(ctrl_rx_size3_c downto ctrl_rx_size0_c) <= std_ulogic_vector(to_unsigned(index_size_f(SLINK_RX_FIFO), 4));
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189 |
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data_o(ctrl_tx_size3_c downto ctrl_tx_size0_c) <= std_ulogic_vector(to_unsigned(index_size_f(SLINK_TX_FIFO), 4));
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190 |
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data_o(ctrl_en_c) <= enable;
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191 |
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ack_read <= '1';
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192 |
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else -- RX links
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193 |
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data_o <= rx_fifo_rdata(to_integer(unsigned(addr(4 downto 2))));
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194 |
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ack_read <= or_reduce_f(link_sel and rx_fifo_avail);
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195 |
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end if;
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196 |
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end if;
|
197 |
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end if;
|
198 |
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end process rw_access;
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199 |
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|
200 |
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-- bus access acknowledge --
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201 |
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ack_o <= ack_write or ack_read;
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202 |
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|
203 |
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-- link fifo reset (sync) --
|
204 |
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fifo_clear <= not enable;
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205 |
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|
206 |
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|
207 |
|
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-- Interrupt Generator --------------------------------------------------------------------
|
208 |
|
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-- -------------------------------------------------------------------------------------------
|
209 |
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irq_generator: process(clk_i)
|
210 |
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begin
|
211 |
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if rising_edge(clk_i) then
|
212 |
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-- buffer status --
|
213 |
|
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tx_fifo_free_buf <= tx_fifo_free;
|
214 |
|
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rx_fifo_avail_buf <= rx_fifo_avail;
|
215 |
|
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-- rising edge detector --
|
216 |
|
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irq_tx_o <= enable and or_reduce_f(tx_fifo_free and (not tx_fifo_free_buf));
|
217 |
|
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irq_rx_o <= enable and or_reduce_f(rx_fifo_avail and (not rx_fifo_avail_buf));
|
218 |
|
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end if;
|
219 |
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end process irq_generator;
|
220 |
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|
221 |
|
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|
222 |
|
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-- Link Select ----------------------------------------------------------------------------
|
223 |
|
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-- -------------------------------------------------------------------------------------------
|
224 |
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link_select: process(addr)
|
225 |
|
|
begin
|
226 |
|
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case addr(5 downto 2) is -- MSB = data fifo access at all?
|
227 |
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when "1000" => link_sel <= "00000001";
|
228 |
|
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when "1001" => link_sel <= "00000010";
|
229 |
|
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when "1010" => link_sel <= "00000100";
|
230 |
|
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when "1011" => link_sel <= "00001000";
|
231 |
|
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when "1100" => link_sel <= "00010000";
|
232 |
|
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when "1101" => link_sel <= "00100000";
|
233 |
|
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when "1110" => link_sel <= "01000000";
|
234 |
|
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when "1111" => link_sel <= "10000000";
|
235 |
|
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when others => link_sel <= "00000000";
|
236 |
|
|
end case;
|
237 |
|
|
end process link_select;
|
238 |
|
|
|
239 |
|
|
fifo_access_gen:
|
240 |
|
|
for i in 0 to 7 generate
|
241 |
|
|
tx_fifo_we(i) <= link_sel(i) and acc_en and wren_i;
|
242 |
|
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rx_fifo_re(i) <= link_sel(i) and acc_en and rden_i;
|
243 |
|
|
end generate;
|
244 |
|
|
|
245 |
|
|
|
246 |
|
|
-- TX Link FIFOs --------------------------------------------------------------------------
|
247 |
|
|
-- -------------------------------------------------------------------------------------------
|
248 |
|
|
transmit_fifo_gen:
|
249 |
|
|
for i in 0 to SLINK_NUM_TX-1 generate
|
250 |
|
|
transmit_fifo_inst: neorv32_fifo
|
251 |
|
|
generic map (
|
252 |
|
|
FIFO_DEPTH => SLINK_TX_FIFO, -- number of fifo entries; has to be a power of two; min 1
|
253 |
|
|
FIFO_WIDTH => 32, -- size of data elements in fifo
|
254 |
|
|
FIFO_RSYNC => false, -- false = async read; true = sync read
|
255 |
|
|
FIFO_SAFE => true -- true = allow read/write only if data available
|
256 |
|
|
)
|
257 |
|
|
port map (
|
258 |
|
|
-- control --
|
259 |
|
|
clk_i => clk_i, -- clock, rising edge
|
260 |
|
|
rstn_i => '1', -- async reset, low-active
|
261 |
|
|
clear_i => fifo_clear, -- sync reset, high-active
|
262 |
|
|
-- write port --
|
263 |
|
|
wdata_i => data_i, -- write data
|
264 |
|
|
we_i => tx_fifo_we(i), -- write enable
|
265 |
|
|
free_o => tx_fifo_free(i), -- at least one entry is free when set
|
266 |
|
|
-- read port --
|
267 |
|
|
re_i => slink_tx_rdy_i(i), -- read enable
|
268 |
|
|
rdata_o => slink_tx_dat_o(i), -- read data
|
269 |
|
|
avail_o => slink_tx_val_o(i) -- data available when set
|
270 |
|
|
);
|
271 |
|
|
end generate;
|
272 |
|
|
|
273 |
|
|
-- terminate unimplemented links --
|
274 |
|
|
transmit_fifo_gen_terminate:
|
275 |
|
|
for i in SLINK_NUM_TX to 7 generate
|
276 |
|
|
tx_fifo_free(i) <= '0';
|
277 |
|
|
slink_tx_dat_o(i) <= (others => '0');
|
278 |
|
|
slink_tx_val_o(i) <= '0';
|
279 |
|
|
end generate;
|
280 |
|
|
|
281 |
|
|
|
282 |
|
|
-- RX Link FIFOs --------------------------------------------------------------------------
|
283 |
|
|
-- -------------------------------------------------------------------------------------------
|
284 |
|
|
receive_fifo_gen:
|
285 |
|
|
for i in 0 to SLINK_NUM_RX-1 generate
|
286 |
|
|
receive_fifo_inst: neorv32_fifo
|
287 |
|
|
generic map (
|
288 |
|
|
FIFO_DEPTH => SLINK_RX_FIFO, -- number of fifo entries; has to be a power of two; min 1
|
289 |
|
|
FIFO_WIDTH => 32, -- size of data elements in fifo
|
290 |
|
|
FIFO_RSYNC => false, -- false = async read; true = sync read
|
291 |
|
|
FIFO_SAFE => true -- true = allow read/write only if data available
|
292 |
|
|
)
|
293 |
|
|
port map (
|
294 |
|
|
-- control --
|
295 |
|
|
clk_i => clk_i, -- clock, rising edge
|
296 |
|
|
rstn_i => '1', -- async reset, low-active
|
297 |
|
|
clear_i => fifo_clear, -- sync reset, high-active
|
298 |
|
|
-- write port --
|
299 |
|
|
wdata_i => slink_rx_dat_i(i), -- write data
|
300 |
|
|
we_i => slink_rx_val_i(i), -- write enable
|
301 |
|
|
free_o => slink_rx_rdy_o(i), -- at least one entry is free when set
|
302 |
|
|
-- read port --
|
303 |
|
|
re_i => rx_fifo_re(i), -- read enable
|
304 |
|
|
rdata_o => rx_fifo_rdata(i), -- read data
|
305 |
|
|
avail_o => rx_fifo_avail(i) -- data available when set
|
306 |
|
|
);
|
307 |
|
|
end generate;
|
308 |
|
|
|
309 |
|
|
-- terminate unimplemented links --
|
310 |
|
|
receive_fifo_gen_terminate:
|
311 |
|
|
for i in SLINK_NUM_RX to 7 generate
|
312 |
|
|
rx_fifo_avail(i) <= '0';
|
313 |
|
|
slink_rx_rdy_o(i) <= '0';
|
314 |
|
|
rx_fifo_rdata(i) <= (others => '0');
|
315 |
|
|
end generate;
|
316 |
|
|
|
317 |
|
|
|
318 |
|
|
end neorv32_slink_rtl;
|