Subversion Repositories neorv32

-- #################################################################################################

-- # << NEORV32 - Processor Top Entity >>                                                          #

-- # ********************************************************************************************* #

-- # This is the top entity of the NEORV32 PROCESSOR. Instantiate this unit in your own project    #

-- # and define all the configuration generics according to your needs. Alternatively, you can use #

-- # one of the alternative top entities provided in the "rtl/top_templates" folder.               #

-- #                                                                                               #

-- # Check out the processor's data sheet for more information: docs/NEORV32.pdf                   #

-- # ********************************************************************************************* #

-- # BSD 3-Clause License                                                                          #

-- #                                                                                               #

-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #

-- #                                                                                               #

-- # Redistribution and use in source and binary forms, with or without modification, are          #

-- # permitted provided that the following conditions are met:                                     #

-- #                                                                                               #

-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #

-- #    conditions and the following disclaimer.                                                   #

-- #                                                                                               #

-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #

-- #    conditions and the following disclaimer in the documentation and/or other materials        #

-- #    provided with the distribution.                                                            #

-- #                                                                                               #

-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #

-- #    endorse or promote products derived from this software without specific prior written      #

-- #    permission.                                                                                #

-- #                                                                                               #

-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #

-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #

-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #

-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #

-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #

-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #

-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #

-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #

-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #

-- # ********************************************************************************************* #

-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #

-- #################################################################################################

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

library neorv32;

use neorv32.neorv32_package.all;

entity neorv32_top is

  generic (

    -- General --

    CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz

    BOOTLOADER_EN                : boolean := true;   -- implement processor-internal bootloader?

    USER_CODE                    : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code

    HW_THREAD_ID                 : natural := 0;      -- hardware thread id (32-bit)

    -- RISC-V CPU Extensions --

    CPU_EXTENSION_RISCV_A        : boolean := false;  -- implement atomic extension?

    CPU_EXTENSION_RISCV_B        : boolean := false;  -- implement bit manipulation extensions?

    CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?

    CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?

    CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement muld/div extension?

    CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?

    CPU_EXTENSION_RISCV_Zfinx    : boolean := false;  -- implement 32-bit floating-point extension (using INT reg!)

    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?

    CPU_EXTENSION_RISCV_Zifencei : boolean := false;  -- implement instruction stream sync.?

    -- Extension Options --

    FAST_MUL_EN                  : boolean := false;  -- use DSPs for M extension's multiplier

    FAST_SHIFT_EN                : boolean := false;  -- use barrel shifter for shift operations

    TINY_SHIFT_EN                : boolean := false;  -- use tiny (single-bit) shifter for shift operations

    CPU_CNT_WIDTH                : natural := 64;     -- total width of CPU cycle and instret counters (0..64)

    -- Physical Memory Protection (PMP) --

    PMP_NUM_REGIONS              : natural := 0;      -- number of regions (0..64)

    PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes

    -- Hardware Performance Monitors (HPM) --

    HPM_NUM_CNTS                 : natural := 0;      -- number of implemented HPM counters (0..29)

    HPM_CNT_WIDTH                : natural := 40;     -- total size of HPM counters (1..64)

    -- Internal Instruction memory --

    MEM_INT_IMEM_EN              : boolean := true;   -- implement processor-internal instruction memory

    MEM_INT_IMEM_SIZE            : natural := 16*1024; -- size of processor-internal instruction memory in bytes

    MEM_INT_IMEM_ROM             : boolean := false;  -- implement processor-internal instruction memory as ROM

    -- Internal Data memory --

    MEM_INT_DMEM_EN              : boolean := true;   -- implement processor-internal data memory

    MEM_INT_DMEM_SIZE            : natural := 8*1024; -- size of processor-internal data memory in bytes

    -- Internal Cache memory --

    ICACHE_EN                    : boolean := false;  -- implement instruction cache

    ICACHE_NUM_BLOCKS            : natural := 4;      -- i-cache: number of blocks (min 1), has to be a power of 2

    ICACHE_BLOCK_SIZE            : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2

    ICACHE_ASSOCIATIVITY         : natural := 1;      -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2

    -- External memory interface --

    MEM_EXT_EN                   : boolean := false;  -- implement external memory bus interface?

    -- Processor peripherals --

    IO_GPIO_EN                   : boolean := true;   -- implement general purpose input/output port unit (GPIO)?

    IO_MTIME_EN                  : boolean := true;   -- implement machine system timer (MTIME)?

    IO_UART0_EN                  : boolean := true;   -- implement primary universal asynchronous receiver/transmitter (UART0)?

    IO_UART1_EN                  : boolean := true;   -- implement secondary universal asynchronous receiver/transmitter (UART1)?

    IO_SPI_EN                    : boolean := true;   -- implement serial peripheral interface (SPI)?

    IO_TWI_EN                    : boolean := true;   -- implement two-wire interface (TWI)?

    IO_PWM_EN                    : boolean := true;   -- implement pulse-width modulation unit (PWM)?

    IO_WDT_EN                    : boolean := true;   -- implement watch dog timer (WDT)?

    IO_TRNG_EN                   : boolean := false;  -- implement true random number generator (TRNG)?

    IO_CFS_EN                    : boolean := false;  -- implement custom functions subsystem (CFS)?

    IO_CFS_CONFIG                : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic

    IO_CFS_IN_SIZE               : positive := 32;    -- size of CFS input conduit in bits

    IO_CFS_OUT_SIZE              : positive := 32;    -- size of CFS output conduit in bits

    IO_NCO_EN                    : boolean := true;   -- implement numerically-controlled oscillator (NCO)?

    IO_NEOLED_EN                 : boolean := true    -- implement NeoPixel-compatible smart LED interface (NEOLED)?

  );

  port (

    -- Global control --

    clk_i       : in  std_ulogic := '0'; -- global clock, rising edge

    rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async

    -- Wishbone bus interface (available if MEM_EXT_EN = true) --

    wb_tag_o    : out std_ulogic_vector(03 downto 0); -- request tag

    wb_adr_o    : out std_ulogic_vector(31 downto 0); -- address

    wb_dat_i    : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- read data

    wb_dat_o    : out std_ulogic_vector(31 downto 0); -- write data

    wb_we_o     : out std_ulogic; -- read/write

    wb_sel_o    : out std_ulogic_vector(03 downto 0); -- byte enable

    wb_stb_o    : out std_ulogic; -- strobe

    wb_cyc_o    : out std_ulogic; -- valid cycle

    wb_tag_i    : in  std_ulogic := '0'; -- response tag

    wb_ack_i    : in  std_ulogic := '0'; -- transfer acknowledge

    wb_err_i    : in  std_ulogic := '0'; -- transfer error

    -- Advanced memory control signals (available if MEM_EXT_EN = true) --

    fence_o     : out std_ulogic; -- indicates an executed FENCE operation

    fencei_o    : out std_ulogic; -- indicates an executed FENCEI operation

    -- GPIO (available if IO_GPIO_EN = true) --

    gpio_o      : out std_ulogic_vector(31 downto 0); -- parallel output

    gpio_i      : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input

    -- primary UART0 (available if IO_UART0_EN = true) --

    uart0_txd_o : out std_ulogic; -- UART0 send data

    uart0_rxd_i : in  std_ulogic := '0'; -- UART0 receive data

    uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional

    uart0_cts_i : in  std_ulogic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional

    -- secondary UART1 (available if IO_UART1_EN = true) --

    uart1_txd_o : out std_ulogic; -- UART1 send data

    uart1_rxd_i : in  std_ulogic := '0'; -- UART1 receive data

    uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional

    uart1_cts_i : in  std_ulogic := '0'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional

    -- SPI (available if IO_SPI_EN = true) --

    spi_sck_o   : out std_ulogic; -- SPI serial clock

    spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in

    spi_sdi_i   : in  std_ulogic := '0'; -- controller data in, peripheral data out

    spi_csn_o   : out std_ulogic_vector(07 downto 0); -- chip-select

    -- TWI (available if IO_TWI_EN = true) --

    twi_sda_io  : inout std_logic; -- twi serial data line

    twi_scl_io  : inout std_logic; -- twi serial clock line

    -- PWM (available if IO_PWM_EN = true) --

    pwm_o       : out std_ulogic_vector(03 downto 0); -- pwm channels

    -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --

    cfs_in_i    : in  std_ulogic_vector(IO_CFS_IN_SIZE-1  downto 0); -- custom CFS inputs conduit

    cfs_out_o   : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit

    -- NCO output (available if IO_NCO_EN = true) --

    nco_o       : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels

    -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --

    neoled_o    : out std_ulogic; -- async serial data line

    -- system time input from external MTIME (available if IO_MTIME_EN = false) --

    mtime_i     : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time

    -- Interrupts --

    soc_firq_i  : in  std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels

    mtime_irq_i : in  std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false

    msw_irq_i   : in  std_ulogic := '0'; -- machine software interrupt

    mext_irq_i  : in  std_ulogic := '0'  -- machine external interrupt

  );

end neorv32_top;

architecture neorv32_top_rtl of neorv32_top is

  -- CPU boot address --

  constant cpu_boot_addr_c : std_ulogic_vector(31 downto 0) := cond_sel_stdulogicvector_f(BOOTLOADER_EN, boot_rom_base_c, ispace_base_c);

  -- Bus timeout --

  constant bus_timeout_temp_c : natural := 2**index_size_f(bus_timeout_c); -- round to next power-of-two

  constant bus_timeout_proc_c : natural := cond_sel_natural_f(ICACHE_EN, ((ICACHE_BLOCK_SIZE/4)*bus_timeout_temp_c)-1, bus_timeout_c);

  -- alignment check for internal memories --

  constant imem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) := (others => '0');

  constant dmem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) := (others => '0');

  -- reset generator --

  signal rstn_i_sync0 : std_ulogic;

  signal rstn_i_sync1 : std_ulogic;

  signal rstn_i_sync2 : std_ulogic;

  signal rstn_gen     : std_ulogic_vector(3 downto 0);

  signal ext_rstn     : std_ulogic;

  signal sys_rstn     : std_ulogic;

  signal wdt_rstn     : std_ulogic;

  -- clock generator --

  signal clk_div    : std_ulogic_vector(11 downto 0);

  signal clk_div_ff : std_ulogic_vector(11 downto 0);

  signal clk_gen    : std_ulogic_vector(07 downto 0);

  signal clk_gen_en : std_ulogic_vector(08 downto 0);

  --

  signal wdt_cg_en    : std_ulogic;

  signal uart0_cg_en  : std_ulogic;

  signal uart1_cg_en  : std_ulogic;

  signal spi_cg_en    : std_ulogic;

  signal twi_cg_en    : std_ulogic;

  signal pwm_cg_en    : std_ulogic;

  signal cfs_cg_en    : std_ulogic;

  signal nco_cg_en    : std_ulogic;

  signal neoled_cg_en : std_ulogic;

  -- bus interface --

  type bus_interface_t is record

    addr   : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address

    rdata  : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data

    wdata  : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data

    ben    : std_ulogic_vector(03 downto 0); -- byte enable

    we     : std_ulogic; -- write enable

    re     : std_ulogic; -- read enable

    cancel : std_ulogic; -- cancel current transfer

    ack    : std_ulogic; -- bus transfer acknowledge

    err    : std_ulogic; -- bus transfer error

    fence  : std_ulogic; -- fence(i) instruction executed

    priv   : std_ulogic_vector(1 downto 0); -- current privilege level

    src    : std_ulogic; -- access source (1=instruction fetch, 0=data access)

    excl   : std_ulogic; -- exclusive access

  end record;

  signal cpu_i, i_cache, cpu_d, p_bus : bus_interface_t;

  signal cpu_d_exclr : std_ulogic; -- CPU D-bus, exclusive access response

  -- io space access --

  signal io_acc  : std_ulogic;

  signal io_rden : std_ulogic;

  signal io_wren : std_ulogic;

  -- read-back busses -

  signal imem_rdata     : std_ulogic_vector(data_width_c-1 downto 0);

  signal imem_ack       : std_ulogic;

  signal dmem_rdata     : std_ulogic_vector(data_width_c-1 downto 0);

  signal dmem_ack       : std_ulogic;

  signal bootrom_rdata  : std_ulogic_vector(data_width_c-1 downto 0);

  signal bootrom_ack    : std_ulogic;

  signal wishbone_rdata : std_ulogic_vector(data_width_c-1 downto 0);

  signal wishbone_ack   : std_ulogic;

  signal wishbone_err   : std_ulogic;

  signal wishbone_exclr : std_ulogic;

  signal gpio_rdata     : std_ulogic_vector(data_width_c-1 downto 0);

  signal gpio_ack       : std_ulogic;

  signal mtime_rdata    : std_ulogic_vector(data_width_c-1 downto 0);

  signal mtime_ack      : std_ulogic;

  signal uart0_rdata    : std_ulogic_vector(data_width_c-1 downto 0);

  signal uart0_ack      : std_ulogic;

  signal uart1_rdata    : std_ulogic_vector(data_width_c-1 downto 0);

  signal uart1_ack      : std_ulogic;

  signal spi_rdata      : std_ulogic_vector(data_width_c-1 downto 0);

  signal spi_ack        : std_ulogic;

  signal twi_rdata      : std_ulogic_vector(data_width_c-1 downto 0);

  signal twi_ack        : std_ulogic;

  signal pwm_rdata      : std_ulogic_vector(data_width_c-1 downto 0);

  signal pwm_ack        : std_ulogic;

  signal wdt_rdata      : std_ulogic_vector(data_width_c-1 downto 0);

  signal wdt_ack        : std_ulogic;

  signal trng_rdata     : std_ulogic_vector(data_width_c-1 downto 0);

  signal trng_ack       : std_ulogic;

  signal cfs_rdata      : std_ulogic_vector(data_width_c-1 downto 0);

  signal cfs_ack        : std_ulogic;

  signal nco_rdata      : std_ulogic_vector(data_width_c-1 downto 0);

  signal nco_ack        : std_ulogic;

  signal neoled_rdata   : std_ulogic_vector(data_width_c-1 downto 0);

  signal neoled_ack     : std_ulogic;

  signal sysinfo_rdata  : std_ulogic_vector(data_width_c-1 downto 0);

  signal sysinfo_ack    : std_ulogic;

  -- IRQs --

  signal mtime_irq    : std_ulogic;

  --

  signal fast_irq     : std_ulogic_vector(15 downto 0);

  signal fast_irq_ack : std_ulogic_vector(15 downto 0);

  --

  signal gpio_irq      : std_ulogic;

  signal wdt_irq       : std_ulogic;

  signal uart0_rxd_irq : std_ulogic;

  signal uart0_txd_irq : std_ulogic;

  signal uart1_rxd_irq : std_ulogic;

  signal uart1_txd_irq : std_ulogic;

  signal spi_irq       : std_ulogic;

  signal twi_irq       : std_ulogic;

  signal cfs_irq       : std_ulogic;

  signal cfs_irq_ack   : std_ulogic;

  signal neoled_irq    : std_ulogic;

  -- misc --

  signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME

  signal cpu_sleep  : std_ulogic; -- CPU is in sleep mode when set

begin

  -- Sanity Checks --------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- clock --

  assert not (CLOCK_FREQUENCY = 0) report "NEORV32 PROCESSOR CONFIG ERROR! Core clock frequency (CLOCK_FREQUENCY) not specified." severity error;

  -- internal bootloader ROM --

  assert not ((BOOTLOADER_EN = true) and (boot_rom_size_c > boot_rom_max_size_c)) report "NEORV32 PROCESSOR CONFIG ERROR! Boot ROM size out of range." severity error;

  assert not ((BOOTLOADER_EN = true) and (MEM_INT_IMEM_ROM = true)) report "NEORV32 PROCESSOR CONFIG WARNING! IMEM is configured as read-only. Bootloader will not be able to load new executables." severity warning;

  -- memory system - data/instruction fetch --

  assert not ((MEM_EXT_EN = false) and (MEM_INT_DMEM_EN = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch data without external memory interface and internal data memory." severity error;

  assert not ((MEM_EXT_EN = false) and (MEM_INT_IMEM_EN = false) and (BOOTLOADER_EN = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch instructions without external memory interface, internal data memory and bootloader." severity error;

  -- memory system - size --

  assert not ((MEM_INT_DMEM_EN = true) and (is_power_of_two_f(MEM_INT_IMEM_SIZE) = false)) report "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_IMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning;

  assert not ((MEM_INT_IMEM_EN = true) and (is_power_of_two_f(MEM_INT_DMEM_SIZE) = false)) report "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_DMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning;

  -- memory system - alignment --

  assert not (ispace_base_c(1 downto 0) /= "00") report "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address must be 4-byte-aligned." severity error;

  assert not (dspace_base_c(1 downto 0) /= "00") report "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address must be 4-byte-aligned." severity error;

  assert not ((ispace_base_c(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) /= imem_align_check_c) and (MEM_INT_IMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address has to be aligned to IMEM size." severity error;

  assert not ((dspace_base_c(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) /= dmem_align_check_c) and (MEM_INT_DMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address has to be aligned to DMEM size." severity error;

  -- memory system - layout warning --

  assert not (ispace_base_c /= x"00000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framework." severity warning;

  assert not (dspace_base_c /= x"80000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the software framework." severity warning;

  -- memory system - the i-cache is intended to accelerate instruction fetch via the external memory interface only --

  assert not ((ICACHE_EN = true) and (MEM_EXT_EN = false)) report "NEORV32 PROCESSOR CONFIG NOTE. Implementing i-cache without having the external memory interface implemented. The i-cache is intended to accelerate instruction fetch via the external memory interface." severity note;

  -- memory system - cached instruction fetch latency check --

  assert not (ICACHE_EN = true) report "NEORV32 PROCESSOR CONFIG WARNING! Implementing i-cache. Increasing bus access timeout from " & integer'image(bus_timeout_c) & " cycles to " & integer'image(bus_timeout_proc_c) & " cycles." severity warning;

  -- Reset Generator ------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  reset_generator_sync: process(clk_i)

  begin

    -- make sure the external reset is free of metastability and has a minimal duration of 1 clock cycle

    if rising_edge(clk_i) then

      rstn_i_sync0 <= rstn_i;

      rstn_i_sync1 <= rstn_i_sync0;

      rstn_i_sync2 <= rstn_i_sync1;

    end if;

  end process reset_generator_sync;

  -- keep internal reset active for at least 4 clock cycles

  reset_generator: process(rstn_i_sync1, rstn_i_sync2, clk_i)

  begin

    if ((rstn_i_sync1 and rstn_i_sync2) = '0') then -- signal stable?

      rstn_gen <= (others => '0');

    elsif rising_edge(clk_i) then

      rstn_gen <= rstn_gen(rstn_gen'left-1 downto 0) & '1';

    end if;

  end process reset_generator;

  ext_rstn <= rstn_gen(rstn_gen'left); -- the beautified external reset signal

  sys_rstn <= ext_rstn and wdt_rstn;   -- system reset - can also be triggered by watchdog

  -- Clock Generator ------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  clock_generator: process(sys_rstn, clk_i)

  begin

    if (sys_rstn = '0') then

      clk_div    <= (others => '0');

      clk_div_ff <= (others => '0');

      clk_gen_en <= (others => '0');

    elsif rising_edge(clk_i) then

      -- fresh clocks anyone? --

      clk_gen_en(0) <= wdt_cg_en;

      clk_gen_en(1) <= uart0_cg_en;

      clk_gen_en(2) <= uart1_cg_en;

      clk_gen_en(3) <= spi_cg_en;

      clk_gen_en(4) <= twi_cg_en;

      clk_gen_en(5) <= pwm_cg_en;

      clk_gen_en(6) <= cfs_cg_en;

      clk_gen_en(7) <= nco_cg_en;

      clk_gen_en(8) <= neoled_cg_en;

      if (or_all_f(clk_gen_en) = '1') then

        clk_div <= std_ulogic_vector(unsigned(clk_div) + 1);

      end if;

      clk_div_ff <= clk_div;

    end if;

  end process clock_generator;

  -- clock enables: rising edge detectors --

  clock_generator_edge: process(clk_i)

  begin

    if rising_edge(clk_i) then

      clk_gen(clk_div2_c)    <= clk_div(0)  and (not clk_div_ff(0));  -- CLK/2

      clk_gen(clk_div4_c)    <= clk_div(1)  and (not clk_div_ff(1));  -- CLK/4

      clk_gen(clk_div8_c)    <= clk_div(2)  and (not clk_div_ff(2));  -- CLK/8

      clk_gen(clk_div64_c)   <= clk_div(5)  and (not clk_div_ff(5));  -- CLK/64

      clk_gen(clk_div128_c)  <= clk_div(6)  and (not clk_div_ff(6));  -- CLK/128

      clk_gen(clk_div1024_c) <= clk_div(9)  and (not clk_div_ff(9));  -- CLK/1024

      clk_gen(clk_div2048_c) <= clk_div(10) and (not clk_div_ff(10)); -- CLK/2048

      clk_gen(clk_div4096_c) <= clk_div(11) and (not clk_div_ff(11)); -- CLK/4096

    end if;

  end process clock_generator_edge;

  -- CPU Core -------------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  neorv32_cpu_inst: neorv32_cpu

  generic map (

    -- General --

    HW_THREAD_ID                 => HW_THREAD_ID,        -- hardware thread id

    CPU_BOOT_ADDR                => cpu_boot_addr_c,     -- cpu boot address

    BUS_TIMEOUT                  => bus_timeout_proc_c,  -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception

    -- RISC-V CPU Extensions --

    CPU_EXTENSION_RISCV_A        => CPU_EXTENSION_RISCV_A,        -- implement atomic extension?

    CPU_EXTENSION_RISCV_B        => CPU_EXTENSION_RISCV_B,        -- implement bit manipulation extensions?

    CPU_EXTENSION_RISCV_C        => CPU_EXTENSION_RISCV_C,        -- implement compressed extension?

    CPU_EXTENSION_RISCV_E        => CPU_EXTENSION_RISCV_E,        -- implement embedded RF extension?

    CPU_EXTENSION_RISCV_M        => CPU_EXTENSION_RISCV_M,        -- implement muld/div extension?

    CPU_EXTENSION_RISCV_U        => CPU_EXTENSION_RISCV_U,        -- implement user mode extension?

    CPU_EXTENSION_RISCV_Zfinx    => CPU_EXTENSION_RISCV_Zfinx,    -- implement 32-bit floating-point extension (using INT reg!)

    CPU_EXTENSION_RISCV_Zicsr    => CPU_EXTENSION_RISCV_Zicsr,    -- implement CSR system?

    CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?

    -- Extension Options --

    FAST_MUL_EN                  => FAST_MUL_EN,         -- use DSPs for M extension's multiplier

    FAST_SHIFT_EN                => FAST_SHIFT_EN,       -- use barrel shifter for shift operations

    CPU_CNT_WIDTH                => CPU_CNT_WIDTH,       -- total width of CPU cycle and instret counters (0..64)

    -- Physical Memory Protection (PMP) --

    PMP_NUM_REGIONS              => PMP_NUM_REGIONS,     -- number of regions (0..64)

    PMP_MIN_GRANULARITY          => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes

    -- Hardware Performance Monitors (HPM) --

    HPM_NUM_CNTS                 => HPM_NUM_CNTS,        -- number of implemented HPM counters (0..29)

    HPM_CNT_WIDTH                => HPM_CNT_WIDTH        -- total size of HPM counters (1..64)

  )

  port map (

    -- global control --

    clk_i          => clk_i,        -- global clock, rising edge

    rstn_i         => sys_rstn,     -- global reset, low-active, async

    sleep_o        => cpu_sleep,    -- cpu is in sleep mode when set

    -- instruction bus interface --

    i_bus_addr_o   => cpu_i.addr,   -- bus access address

    i_bus_rdata_i  => cpu_i.rdata,  -- bus read data

    i_bus_wdata_o  => cpu_i.wdata,  -- bus write data

    i_bus_ben_o    => cpu_i.ben,    -- byte enable

    i_bus_we_o     => cpu_i.we,     -- write enable

    i_bus_re_o     => cpu_i.re,     -- read enable

    i_bus_cancel_o => cpu_i.cancel, -- cancel current bus transaction

    i_bus_ack_i    => cpu_i.ack,    -- bus transfer acknowledge

    i_bus_err_i    => cpu_i.err,    -- bus transfer error

    i_bus_fence_o  => cpu_i.fence,  -- executed FENCEI operation

    i_bus_priv_o   => cpu_i.priv,   -- privilege level

    -- data bus interface --

    d_bus_addr_o   => cpu_d.addr,   -- bus access address

    d_bus_rdata_i  => cpu_d.rdata,  -- bus read data

    d_bus_wdata_o  => cpu_d.wdata,  -- bus write data

    d_bus_ben_o    => cpu_d.ben,    -- byte enable

    d_bus_we_o     => cpu_d.we,     -- write enable

    d_bus_re_o     => cpu_d.re,     -- read enable

    d_bus_cancel_o => cpu_d.cancel, -- cancel current bus transaction

    d_bus_ack_i    => cpu_d.ack,    -- bus transfer acknowledge

    d_bus_err_i    => cpu_d.err,    -- bus transfer error

    d_bus_fence_o  => cpu_d.fence,  -- executed FENCE operation

    d_bus_priv_o   => cpu_d.priv,   -- privilege level

    d_bus_excl_o   => cpu_d.excl,   -- exclusive access

    d_bus_excl_i   => cpu_d_exclr,  -- state of exclusiv access (set if success)

    -- system time input from MTIME --

    time_i         => mtime_time,   -- current system time

    -- interrupts (risc-v compliant) --

    msw_irq_i      => msw_irq_i,    -- machine software interrupt

    mext_irq_i     => mext_irq_i,   -- machine external interrupt request

    mtime_irq_i    => mtime_irq,    -- machine timer interrupt

    -- fast interrupts (custom) --

    firq_i         => fast_irq,     -- fast interrupt trigger

    firq_ack_o     => fast_irq_ack  -- fast interrupt acknowledge mask

  );

  -- misc --

  cpu_i.excl <= '0'; -- i-fetch cannot do exclusive accesses

  cpu_i.src  <= '1'; -- initialized but unused

  cpu_d.src  <= '0'; -- initialized but unused

  -- advanced memory control --

  fence_o  <= cpu_d.fence; -- indicates an executed FENCE operation

  fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation

  -- fast interrupts - processor-internal --

  fast_irq(00) <= wdt_irq;       -- HIGHEST PRIORITY - watchdog timeout

  fast_irq(01) <= cfs_irq;       -- custom functions subsystem

  fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) data received

  fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) sending done

  fast_irq(04) <= uart1_rxd_irq; -- secondary UART (UART1) data received

  fast_irq(05) <= uart1_txd_irq; -- secondary UART (UART1) sending done

  fast_irq(06) <= spi_irq;       -- SPI transmission done

  fast_irq(07) <= twi_irq;       -- TWI transmission done

  fast_irq(08) <= gpio_irq;      -- GPIO pin-change

  fast_irq(09) <= neoled_irq;    -- NEOLED buffer free

  -- fast interrupts - platform level (for custom use) --

  fast_irq(10) <= soc_firq_i(0);

  fast_irq(11) <= soc_firq_i(1);

  fast_irq(12) <= soc_firq_i(2);

  fast_irq(13) <= soc_firq_i(3);

  fast_irq(14) <= soc_firq_i(4);

  fast_irq(15) <= soc_firq_i(5);

  -- CFS IRQ acknowledge --

  cfs_irq_ack <= fast_irq_ack(1);

  -- CPU Instruction Cache ------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  neorv32_icache_inst_true:

  if (ICACHE_EN = true) generate

    neorv32_icache_inst: neorv32_icache

    generic map (

      ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS,   -- number of blocks (min 2), has to be a power of 2

      ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE,   -- block size in bytes (min 4), has to be a power of 2

      ICACHE_NUM_SETS   => ICACHE_ASSOCIATIVITY -- associativity / number of sets (1=direct_mapped), has to be a power of 2

    )

    port map (

      -- global control --

      clk_i         => clk_i,          -- global clock, rising edge

      rstn_i        => sys_rstn,       -- global reset, low-active, async

      clear_i       => cpu_i.fence,    -- cache clear

      -- host controller interface --

      host_addr_i   => cpu_i.addr,     -- bus access address

      host_rdata_o  => cpu_i.rdata,    -- bus read data

      host_wdata_i  => cpu_i.wdata,    -- bus write data

      host_ben_i    => cpu_i.ben,      -- byte enable

      host_we_i     => cpu_i.we,       -- write enable

      host_re_i     => cpu_i.re,       -- read enable

      host_cancel_i => cpu_i.cancel,   -- cancel current bus transaction

      host_ack_o    => cpu_i.ack,      -- bus transfer acknowledge

      host_err_o    => cpu_i.err,      -- bus transfer error

      -- peripheral bus interface --

      bus_addr_o    => i_cache.addr,   -- bus access address

      bus_rdata_i   => i_cache.rdata,  -- bus read data

      bus_wdata_o   => i_cache.wdata,  -- bus write data

      bus_ben_o     => i_cache.ben,    -- byte enable

      bus_we_o      => i_cache.we,     -- write enable

      bus_re_o      => i_cache.re,     -- read enable

      bus_cancel_o  => i_cache.cancel, -- cancel current bus transaction

      bus_ack_i     => i_cache.ack,    -- bus transfer acknowledge

      bus_err_i     => i_cache.err     -- bus transfer error

    );

  end generate;

  neorv32_icache_inst_false:

  if (ICACHE_EN = false) generate

    i_cache.addr   <= cpu_i.addr;

    cpu_i.rdata    <= i_cache.rdata;

    i_cache.wdata  <= cpu_i.wdata;

    i_cache.ben    <= cpu_i.ben;

    i_cache.we     <= cpu_i.we;

    i_cache.re     <= cpu_i.re;

    i_cache.cancel <= cpu_i.cancel;

    cpu_i.ack      <= i_cache.ack;

    cpu_i.err      <= i_cache.err;

  end generate;

  -- no exclusive accesses for i-fetch --

  i_cache.excl <= '0';

  -- CPU Bus Switch -------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  neorv32_busswitch_inst: neorv32_busswitch

  generic map (

    PORT_CA_READ_ONLY => false, -- set if controller port A is read-only

    PORT_CB_READ_ONLY => true   -- set if controller port B is read-only

  )

  port map (

    -- global control --

    clk_i           => clk_i,          -- global clock, rising edge

    rstn_i          => sys_rstn,       -- global reset, low-active, async

    -- controller interface a --

    ca_bus_addr_i   => cpu_d.addr,     -- bus access address

    ca_bus_rdata_o  => cpu_d.rdata,    -- bus read data

    ca_bus_wdata_i  => cpu_d.wdata,    -- bus write data

    ca_bus_ben_i    => cpu_d.ben,      -- byte enable

    ca_bus_we_i     => cpu_d.we,       -- write enable

    ca_bus_re_i     => cpu_d.re,       -- read enable

    ca_bus_cancel_i => cpu_d.cancel,   -- cancel current bus transaction

    ca_bus_excl_i   => cpu_d.excl,     -- exclusive access