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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_top.vhd] - Blame information for rev 6

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1 2 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - Processor Top Entity >>                                                          #
3
-- # ********************************************************************************************* #
4
-- # This is the top entity of the NEORV32 Processor. Instantiate this unit in your own project    #
5
-- # and define all the configuration generics according to your needs. Alternatively, you can use #
6
-- # one of the alternative top entities provided in the "rtl\top_templates" folder.               #
7
-- # Check the processor's documentary for more information: doc\NEORV32.pdf                       #
8
-- # ********************************************************************************************* #
9
-- # BSD 3-Clause License                                                                          #
10
-- #                                                                                               #
11
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
12
-- #                                                                                               #
13
-- # Redistribution and use in source and binary forms, with or without modification, are          #
14
-- # permitted provided that the following conditions are met:                                     #
15
-- #                                                                                               #
16
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
17
-- #    conditions and the following disclaimer.                                                   #
18
-- #                                                                                               #
19
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
20
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
21
-- #    provided with the distribution.                                                            #
22
-- #                                                                                               #
23
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
24
-- #    endorse or promote products derived from this software without specific prior written      #
25
-- #    permission.                                                                                #
26
-- #                                                                                               #
27
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
28
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
29
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
30
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
31
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
32
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
33
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
34
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
35
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
36
-- # ********************************************************************************************* #
37
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
38
-- #################################################################################################
39
 
40
library ieee;
41
use ieee.std_logic_1164.all;
42
use ieee.numeric_std.all;
43
 
44
library neorv32;
45
use neorv32.neorv32_package.all;
46
 
47
entity neorv32_top is
48
  generic (
49
    -- General --
50
    CLOCK_FREQUENCY           : natural := 0; -- clock frequency of clk_i in Hz
51
    HART_ID                   : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
52
    BOOTLOADER_USE            : boolean := true;   -- implement processor-internal bootloader?
53 6 zero_gravi
    CSR_COUNTERS_USE          : boolean := true;   -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
54 2 zero_gravi
    -- RISC-V CPU Extensions --
55
    CPU_EXTENSION_RISCV_C     : boolean := false;  -- implement compressed extension?
56
    CPU_EXTENSION_RISCV_E     : boolean := false;  -- implement embedded RF extension?
57
    CPU_EXTENSION_RISCV_M     : boolean := false;  -- implement muld/div extension?
58
    CPU_EXTENSION_RISCV_Zicsr : boolean := true;   -- implement CSR system?
59
    -- Memory configuration: Instruction memory --
60
    MEM_ISPACE_BASE           : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
61
    MEM_ISPACE_SIZE           : natural := 16*1024; -- total size of instruction memory space in byte
62
    MEM_INT_IMEM_USE          : boolean := true;   -- implement processor-internal instruction memory
63
    MEM_INT_IMEM_SIZE         : natural := 16*1024; -- size of processor-internal instruction memory in bytes
64
    MEM_INT_IMEM_ROM          : boolean := false;  -- implement processor-internal instruction memory as ROM
65
    -- Memory configuration: Data memory --
66
    MEM_DSPACE_BASE           : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
67
    MEM_DSPACE_SIZE           : natural := 8*1024; -- total size of data memory space in byte
68
    MEM_INT_DMEM_USE          : boolean := true;   -- implement processor-internal data memory
69
    MEM_INT_DMEM_SIZE         : natural := 8*1024; -- size of processor-internal data memory in bytes
70
    -- Memory configuration: External memory interface --
71
    MEM_EXT_USE               : boolean := false;  -- implement external memory bus interface?
72
    MEM_EXT_REG_STAGES        : natural := 2;      -- number of interface register stages (0,1,2)
73
    MEM_EXT_TIMEOUT           : natural := 15;     -- cycles after which a valid bus access will timeout
74
    -- Processor peripherals --
75
    IO_GPIO_USE               : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
76
    IO_MTIME_USE              : boolean := true;   -- implement machine system timer (MTIME)?
77
    IO_UART_USE               : boolean := true;   -- implement universal asynchronous receiver/transmitter (UART)?
78
    IO_SPI_USE                : boolean := true;   -- implement serial peripheral interface (SPI)?
79
    IO_TWI_USE                : boolean := true;   -- implement two-wire interface (TWI)?
80
    IO_PWM_USE                : boolean := true;   -- implement pulse-width modulation unit (PWM)?
81
    IO_WDT_USE                : boolean := true;   -- implement watch dog timer (WDT)?
82
    IO_CLIC_USE               : boolean := true;   -- implement core local interrupt controller (CLIC)?
83 3 zero_gravi
    IO_TRNG_USE               : boolean := false;  -- implement true random number generator (TRNG)?
84
    IO_DEVNULL_USE            : boolean := true    -- implement dummy device (DEVNULL)?
85 2 zero_gravi
  );
86
  port (
87
    -- Global control --
88
    clk_i      : in  std_ulogic := '0'; -- global clock, rising edge
89
    rstn_i     : in  std_ulogic := '0'; -- global reset, low-active, async
90
    -- Wishbone bus interface (available if MEM_EXT_USE = true) --
91
    wb_adr_o   : out std_ulogic_vector(31 downto 0); -- address
92
    wb_dat_i   : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
93
    wb_dat_o   : out std_ulogic_vector(31 downto 0); -- write data
94
    wb_we_o    : out std_ulogic; -- read/write
95
    wb_sel_o   : out std_ulogic_vector(03 downto 0); -- byte enable
96
    wb_stb_o   : out std_ulogic; -- strobe
97
    wb_cyc_o   : out std_ulogic; -- valid cycle
98
    wb_ack_i   : in  std_ulogic := '0'; -- transfer acknowledge
99
    wb_err_i   : in  std_ulogic := '0'; -- transfer error
100
    -- GPIO (available if IO_GPIO_USE = true) --
101
    gpio_o     : out std_ulogic_vector(15 downto 0); -- parallel output
102
    gpio_i     : in  std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
103
    -- UART (available if IO_UART_USE = true) --
104
    uart_txd_o : out std_ulogic; -- UART send data
105
    uart_rxd_i : in  std_ulogic := '0'; -- UART receive data
106
    -- SPI (available if IO_SPI_USE = true) --
107 6 zero_gravi
    spi_sck_o  : out std_ulogic; -- SPI serial clock
108
    spi_sdo_o  : out std_ulogic; -- controller data out, peripheral data in
109
    spi_sdi_i  : in  std_ulogic; -- controller data in, peripheral data out
110 2 zero_gravi
    spi_csn_o  : out std_ulogic_vector(07 downto 0); -- SPI CS
111
    -- TWI (available if IO_TWI_USE = true) --
112
    twi_sda_io : inout std_logic := 'H'; -- twi serial data line
113
    twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
114
    -- PWM (available if IO_PWM_USE = true) --
115
    pwm_o      : out std_ulogic_vector(03 downto 0);  -- pwm channels
116
    -- Interrupts (available if IO_CLIC_USE = true) --
117
    ext_irq_i  : in  std_ulogic_vector(01 downto 0) := (others => '0'); -- external interrupt request
118
    ext_ack_o  : out std_ulogic_vector(01 downto 0)  -- external interrupt request acknowledge
119
  );
120
end neorv32_top;
121
 
122
architecture neorv32_top_rtl of neorv32_top is
123
 
124
  -- reset generator --
125
  signal rstn_i_sync0 : std_ulogic;
126
  signal rstn_i_sync1 : std_ulogic;
127
  signal rstn_i_sync2 : std_ulogic;
128
  signal rstn_gen     : std_ulogic_vector(3 downto 0);
129
  signal ext_rstn     : std_ulogic;
130
  signal sys_rstn     : std_ulogic;
131
  signal wdt_rstn     : std_ulogic;
132
 
133
  -- clock generator --
134
  signal clk_div    : std_ulogic_vector(11 downto 0);
135
  signal clk_div_ff : std_ulogic_vector(11 downto 0);
136
  signal clk_gen    : std_ulogic_vector(07 downto 0);
137
  signal wdt_cg_en  : std_ulogic;
138
  signal uart_cg_en : std_ulogic;
139
  signal spi_cg_en  : std_ulogic;
140
  signal twi_cg_en  : std_ulogic;
141
  signal pwm_cg_en  : std_ulogic;
142
 
143
  -- cpu bus --
144
  signal cpu_addr  : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
145
  signal cpu_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
146
  signal cpu_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
147
  signal cpu_ben   : std_ulogic_vector(03 downto 0); -- byte enable
148
  signal cpu_we    : std_ulogic; -- write enable
149
  signal cpu_re    : std_ulogic; -- read enable
150
  signal cpu_ack   : std_ulogic; -- bus transfer acknowledge
151
  signal cpu_err   : std_ulogic; -- bus transfer error
152
 
153
  -- io space access --
154
  signal io_acc  : std_ulogic;
155
  signal io_rden : std_ulogic;
156
  signal io_wren : std_ulogic;
157
 
158
  -- read-back busses -
159
  signal imem_rdata     : std_ulogic_vector(data_width_c-1 downto 0);
160
  signal imem_ack       : std_ulogic;
161
  signal dmem_rdata     : std_ulogic_vector(data_width_c-1 downto 0);
162
  signal dmem_ack       : std_ulogic;
163
  signal bootrom_rdata  : std_ulogic_vector(data_width_c-1 downto 0);
164
  signal bootrom_ack    : std_ulogic;
165
  signal wishbone_rdata : std_ulogic_vector(data_width_c-1 downto 0);
166
  signal wishbone_ack   : std_ulogic;
167
  signal wishbone_err   : std_ulogic;
168
  signal gpio_rdata     : std_ulogic_vector(data_width_c-1 downto 0);
169
  signal gpio_ack       : std_ulogic;
170
  signal mtime_rdata    : std_ulogic_vector(data_width_c-1 downto 0);
171
  signal mtime_ack      : std_ulogic;
172
  signal uart_rdata     : std_ulogic_vector(data_width_c-1 downto 0);
173
  signal uart_ack       : std_ulogic;
174
  signal spi_rdata      : std_ulogic_vector(data_width_c-1 downto 0);
175
  signal spi_ack        : std_ulogic;
176
  signal twi_rdata      : std_ulogic_vector(data_width_c-1 downto 0);
177
  signal twi_ack        : std_ulogic;
178
  signal pwm_rdata      : std_ulogic_vector(data_width_c-1 downto 0);
179
  signal pwm_ack        : std_ulogic;
180
  signal wdt_rdata      : std_ulogic_vector(data_width_c-1 downto 0);
181
  signal wdt_ack        : std_ulogic;
182
  signal clic_rdata     : std_ulogic_vector(data_width_c-1 downto 0);
183
  signal clic_ack       : std_ulogic;
184
  signal trng_rdata     : std_ulogic_vector(data_width_c-1 downto 0);
185
  signal trng_ack       : std_ulogic;
186 3 zero_gravi
  signal devnull_rdata  : std_ulogic_vector(data_width_c-1 downto 0);
187
  signal devnull_ack    : std_ulogic;
188 2 zero_gravi
 
189
  -- IRQs --
190
  signal mtime_irq : std_ulogic;
191
  signal clic_irq  : std_ulogic;
192
  signal clic_xirq : std_ulogic_vector(7 downto 0);
193
  signal clic_xack : std_ulogic_vector(7 downto 0);
194
  signal gpio_irq  : std_ulogic;
195
  signal wdt_irq   : std_ulogic;
196
  signal uart_irq  : std_ulogic;
197
  signal spi_irq   : std_ulogic;
198
  signal twi_irq   : std_ulogic;
199
 
200
begin
201
 
202
  -- Sanity Checks --------------------------------------------------------------------------
203
  -- -------------------------------------------------------------------------------------------
204
  sanity_check: process(clk_i)
205
  begin
206
    if rising_edge(clk_i) then
207
      -- internal bootloader memory --
208
      if (BOOTLOADER_USE = true) and (boot_size_c > boot_max_size_c) then
209
        assert false report "NEORV32 CONFIG ERROR! Boot ROM size out of range." severity error;
210
      end if;
211
 
212
      -- memory system - data/instruction fetch --
213
      if (MEM_EXT_USE = false) then
214
        if (MEM_INT_DMEM_USE = false) then
215
          assert false report "NEORV32 CONFIG ERROR! Core cannot fetch data without external memory interface and internal data memory." severity error;
216
        end if;
217
        if (MEM_INT_IMEM_USE = false) and (BOOTLOADER_USE = false) then
218
          assert false report "NEORV32 CONFIG ERROR! Core cannot fetch instructions without external memory interface, internal data memory and bootloader." severity error;
219
        end if;
220
      end if;
221
 
222
      -- memory system - address space --
223
      if (MEM_INT_IMEM_USE = true) and (MEM_INT_IMEM_SIZE > MEM_ISPACE_SIZE) then
224
        assert false report "NEORV32 CONFIG ERROR! Internal instruction memory (IMEM) cannot be greater than total instruction address space." severity error;
225
      end if;
226
      if (MEM_INT_DMEM_USE = true) and (MEM_INT_DMEM_SIZE > MEM_DSPACE_SIZE) then
227
        assert false report "NEORV32 CONFIG ERROR! Internal data memory (DMEM) cannot be greater than total data address space." severity error;
228
      end if;
229
      if (MEM_EXT_TIMEOUT <= 1) then
230
        assert false report "NEORV32 CONFIG ERROR! Invalid bus timeout. Internal components require 1 cycle delay." severity error;
231
      end if;
232
 
233
      -- clock --
234
      if (CLOCK_FREQUENCY = 0) then
235
        assert false report "NEORV32 CONFIG ERROR! Core clock frequency (CLOCK_FREQUENCY) not specified." severity error;
236
      end if;
237
 
238
      -- CSR system not implemented --
239
      if (CPU_EXTENSION_RISCV_Zicsr = false) then
240
        assert false report "NEORV32 CONFIG WARNING! No exception/interrupt/machine status features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning;
241
      end if;
242
      -- core local interrupt controller --
243
      if (CPU_EXTENSION_RISCV_Zicsr = false) and (IO_CLIC_USE = true) then
244
        assert false report "NEORV32 CONFIG ERROR! Core local interrupt controller (CLIC) cannot be used without >Zicsr< CPU extension." severity error;
245
      end if;
246
 
247
      -- memory layout notifier --
248
      if (MEM_ISPACE_BASE /= x"00000000") then
249
        assert false report "NEORV32 CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the linker script." severity warning;
250
      end if;
251
      if (MEM_DSPACE_BASE /= x"80000000") then
252
        assert false report "NEORV32 CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the linker script." severity warning;
253
      end if;
254
    end if;
255
  end process sanity_check;
256
 
257
 
258
  -- Reset Generator ------------------------------------------------------------------------
259
  -- -------------------------------------------------------------------------------------------
260
  reset_generator_sync: process(clk_i)
261
  begin
262
    -- make sure the external reset is free of metastability and has a minimal duration of 1 clock cycle
263
    if rising_edge(clk_i) then
264
      rstn_i_sync0 <= rstn_i;
265
      rstn_i_sync1 <= rstn_i_sync0;
266
      rstn_i_sync2 <= rstn_i_sync1;
267
    end if;
268
  end process reset_generator_sync;
269
 
270
  -- keep internal reset active for at least 4 clock cycles
271
  reset_generator: process(rstn_i_sync1, rstn_i_sync2, clk_i)
272
  begin
273
    if ((rstn_i_sync1 or rstn_i_sync2) = '0') then -- signal stable somehow?
274
      rstn_gen <= (others => '0');
275
    elsif rising_edge(clk_i) then
276
      rstn_gen <= rstn_gen(rstn_gen'left-1 downto 0) & '1';
277
    end if;
278
  end process reset_generator;
279
 
280
  ext_rstn <= rstn_gen(rstn_gen'left); -- the beautified external reset signal
281
  sys_rstn <= ext_rstn and wdt_rstn; -- system reset - can also be triggered by watchdog
282
 
283
 
284
  -- Clock Generator ------------------------------------------------------------------------
285
  -- -------------------------------------------------------------------------------------------
286
  clock_generator: process(sys_rstn, clk_i)
287
  begin
288
    if (sys_rstn = '0') then
289
      clk_div    <= (others => '0');
290
      clk_div_ff <= (others => '0');
291
    elsif rising_edge(clk_i) then
292
      -- anybody wanting some fresh clocks? --
293
      if ((wdt_cg_en or uart_cg_en or spi_cg_en or twi_cg_en or pwm_cg_en) = '1') then
294
        clk_div    <= std_ulogic_vector(unsigned(clk_div) + 1);
295
        clk_div_ff <= clk_div;
296
      end if;
297
    end if;
298
  end process clock_generator;
299
 
300
  -- clock enable select: rising edge detectors --
301
  clk_gen(clk_div2_c)    <= clk_div(0)  and (not clk_div_ff(0));  -- CLK/2
302
  clk_gen(clk_div4_c)    <= clk_div(1)  and (not clk_div_ff(1));  -- CLK/4
303
  clk_gen(clk_div8_c)    <= clk_div(2)  and (not clk_div_ff(2));  -- CLK/8
304
  clk_gen(clk_div64_c)   <= clk_div(5)  and (not clk_div_ff(5));  -- CLK/64
305
  clk_gen(clk_div128_c)  <= clk_div(6)  and (not clk_div_ff(6));  -- CLK/128
306
  clk_gen(clk_div1024_c) <= clk_div(9)  and (not clk_div_ff(9));  -- CLK/1024
307
  clk_gen(clk_div2048_c) <= clk_div(10) and (not clk_div_ff(10)); -- CLK/2048
308
  clk_gen(clk_div4096_c) <= clk_div(11) and (not clk_div_ff(11)); -- CLK/4096
309
 
310
 
311
  -- CPU ------------------------------------------------------------------------------------
312
  -- -------------------------------------------------------------------------------------------
313
  neorv32_cpu_inst: neorv32_cpu
314
  generic map (
315
    -- General --
316
    CLOCK_FREQUENCY           => CLOCK_FREQUENCY,   -- clock frequency of clk_i in Hz
317
    HART_ID                   => HART_ID,           -- custom hardware thread ID
318
    BOOTLOADER_USE            => BOOTLOADER_USE,    -- implement processor-internal bootloader?
319 6 zero_gravi
    CSR_COUNTERS_USE          => CSR_COUNTERS_USE,  -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
320 2 zero_gravi
    -- RISC-V CPU Extensions --
321
    CPU_EXTENSION_RISCV_C     => CPU_EXTENSION_RISCV_C,     -- implement compressed extension?
322
    CPU_EXTENSION_RISCV_E     => CPU_EXTENSION_RISCV_E,     -- implement embedded RF extension?
323
    CPU_EXTENSION_RISCV_M     => CPU_EXTENSION_RISCV_M,     -- implement muld/div extension?
324
    CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
325
    -- Memory configuration: Instruction memory --
326
    MEM_ISPACE_BASE           => MEM_ISPACE_BASE,   -- base address of instruction memory space
327
    MEM_ISPACE_SIZE           => MEM_ISPACE_SIZE,   -- total size of instruction memory space in byte
328
    MEM_INT_IMEM_USE          => MEM_INT_IMEM_USE,  -- implement processor-internal instruction memory
329
    MEM_INT_IMEM_SIZE         => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
330
    MEM_INT_IMEM_ROM          => MEM_INT_IMEM_ROM,  -- implement processor-internal instruction memory as ROM
331
    -- Memory configuration: Data memory --
332
    MEM_DSPACE_BASE           => MEM_DSPACE_BASE,   -- base address of data memory space
333
    MEM_DSPACE_SIZE           => MEM_DSPACE_SIZE,   -- total size of data memory space in byte
334
    MEM_INT_DMEM_USE          => MEM_INT_DMEM_USE,  -- implement processor-internal data memory
335
    MEM_INT_DMEM_SIZE         => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
336
    -- Memory configuration: External memory interface --
337
    MEM_EXT_USE               => MEM_EXT_USE,       -- implement external memory bus interface?
338
    MEM_EXT_TIMEOUT           => MEM_EXT_TIMEOUT,   -- cycles after which a valid bus access will timeout
339
    -- Processor peripherals --
340
    IO_GPIO_USE               => IO_GPIO_USE,       -- implement general purpose input/output port unit (GPIO)?
341
    IO_MTIME_USE              => IO_MTIME_USE,      -- implement machine system timer (MTIME)?
342
    IO_UART_USE               => IO_UART_USE,       -- implement universal asynchronous receiver/transmitter (UART)?
343
    IO_SPI_USE                => IO_SPI_USE,        -- implement serial peripheral interface (SPI)?
344
    IO_TWI_USE                => IO_TWI_USE,        -- implement two-wire interface (TWI)?
345
    IO_PWM_USE                => IO_PWM_USE,        -- implement pulse-width modulation unit (PWM)?
346
    IO_WDT_USE                => IO_WDT_USE,        -- implement watch dog timer (WDT)?
347
    IO_CLIC_USE               => IO_CLIC_USE,       -- implement core local interrupt controller (CLIC)?
348 3 zero_gravi
    IO_TRNG_USE               => IO_TRNG_USE,       -- implement true random number generator (TRNG)?
349
    IO_DEVNULL_USE            => IO_DEVNULL_USE     -- implement dummy device (DEVNULL)?
350 2 zero_gravi
  )
351
  port map (
352
    -- global control --
353
    clk_i       => clk_i,        -- global clock, rising edge
354
    rstn_i      => sys_rstn,     -- global reset, low-active, async
355
    -- bus interface --
356
    bus_addr_o  => cpu_addr,     -- bus access address
357
    bus_rdata_i => cpu_rdata,    -- bus read data
358
    bus_wdata_o => cpu_wdata,    -- bus write data
359
    bus_ben_o   => cpu_ben,      -- byte enable
360
    bus_we_o    => cpu_we,       -- write enable
361
    bus_re_o    => cpu_re,       -- read enable
362
    bus_ack_i   => cpu_ack,      -- bus transfer acknowledge
363
    bus_err_i   => cpu_err,      -- bus transfer error
364
    -- external interrupts --
365
    clic_irq_i  => clic_irq,     -- CLIC interrupt request
366
    mtime_irq_i => mtime_irq     -- machine timer interrupt
367
  );
368
 
369
  -- CPU data input --
370
  cpu_rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or
371 3 zero_gravi
               uart_rdata or spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or clic_rdata or trng_rdata or devnull_rdata);
372 2 zero_gravi
 
373
  -- CPU ACK input --
374
  cpu_ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or
375 3 zero_gravi
              uart_ack or spi_ack or twi_ack or pwm_ack or wdt_ack or clic_ack or trng_ack or devnull_ack);
376 2 zero_gravi
 
377
  -- CPU bus error input --
378
  cpu_err <= wishbone_err;
379
 
380
 
381
  -- Processor-Internal Instruction Memory (IMEM) -------------------------------------------
382
  -- -------------------------------------------------------------------------------------------
383
  neorv32_int_imem_inst_true:
384
  if (MEM_INT_IMEM_USE = true) generate
385
    neorv32_int_imem_inst: neorv32_imem
386
    generic map (
387
      IMEM_BASE      => MEM_ISPACE_BASE,   -- memory base address
388
      IMEM_SIZE      => MEM_INT_IMEM_SIZE, -- processor-internal instruction memory size in bytes
389
      IMEM_AS_ROM    => MEM_INT_IMEM_ROM,  -- implement IMEM as read-only memory?
390
      BOOTLOADER_USE => BOOTLOADER_USE     -- implement and use bootloader?
391
    )
392
    port map (
393
      clk_i  => clk_i,      -- global clock line
394
      rden_i => cpu_re,     -- read enable
395
      wren_i => cpu_we,     -- write enable
396
      ben_i  => cpu_ben,    -- byte write enable
397
      upen_i => '1',        -- update enable
398
      addr_i => cpu_addr,   -- address
399
      data_i => cpu_wdata,  -- data in
400
      data_o => imem_rdata, -- data out
401
      ack_o  => imem_ack    -- transfer acknowledge
402
    );
403
  end generate;
404
 
405
  neorv32_int_imem_inst_false:
406
  if (MEM_INT_IMEM_USE = false) generate
407
    imem_rdata <= (others => '0');
408
    imem_ack   <= '0';
409
  end generate;
410
 
411
 
412
  -- Processor-Internal Data Memory (DMEM) --------------------------------------------------
413
  -- -------------------------------------------------------------------------------------------
414
  neorv32_int_dmem_inst_true:
415
  if (MEM_INT_DMEM_USE = true) generate
416
    neorv32_int_dmem_inst: neorv32_dmem
417
    generic map (
418
      DMEM_BASE => MEM_DSPACE_BASE,  -- memory base address
419
      DMEM_SIZE => MEM_INT_DMEM_SIZE -- processor-internal data memory size in bytes
420
    )
421
    port map (
422
      clk_i  => clk_i,      -- global clock line
423
      rden_i => cpu_re,     -- read enable
424
      wren_i => cpu_we,     -- write enable
425
      ben_i  => cpu_ben,    -- byte write enable
426
      addr_i => cpu_addr,   -- address
427
      data_i => cpu_wdata,  -- data in
428
      data_o => dmem_rdata, -- data out
429
      ack_o  => dmem_ack    -- transfer acknowledge
430
    );
431
  end generate;
432
 
433
  neorv32_int_dmem_inst_false:
434
  if (MEM_INT_DMEM_USE = false) generate
435
    dmem_rdata <= (others => '0');
436
    dmem_ack   <= '0';
437
  end generate;
438
 
439
 
440
  -- Processor-Internal Bootloader ROM (BOOTROM) --------------------------------------------
441
  -- -------------------------------------------------------------------------------------------
442
  neorv32_boot_rom_inst_true:
443
  if (BOOTLOADER_USE = true) generate
444
    neorv32_boot_rom_inst: neorv32_boot_rom
445
    port map (
446
      clk_i  => clk_i,         -- global clock line
447
      rden_i => cpu_re,        -- read enable
448
      addr_i => cpu_addr,      -- address
449
      data_o => bootrom_rdata, -- data out
450
      ack_o  => bootrom_ack    -- transfer acknowledge
451
    );
452
  end generate;
453
 
454
  neorv32_boot_rom_inst_false:
455
  if (BOOTLOADER_USE = false) generate
456
    bootrom_rdata <= (others => '0');
457
    bootrom_ack   <= '0';
458
  end generate;
459
 
460
 
461
  -- External Wishbone Gateway (WISHBONE) ---------------------------------------------------
462
  -- -------------------------------------------------------------------------------------------
463
  neorv32_wishbone_inst_true:
464
  if (MEM_EXT_USE = true) generate
465
    neorv32_wishbone_inst: neorv32_wishbone
466
    generic map (
467
      INTERFACE_REG_STAGES => MEM_EXT_REG_STAGES, -- number of interface register stages (0,1,2)
468
      -- Memory configuration: Instruction memory --
469
      MEM_ISPACE_BASE      => MEM_ISPACE_BASE,   -- base address of instruction memory space
470
      MEM_ISPACE_SIZE      => MEM_ISPACE_SIZE,   -- total size of instruction memory space in byte
471
      MEM_INT_IMEM_USE     => MEM_INT_IMEM_USE,  -- implement processor-internal instruction memory
472
      MEM_INT_IMEM_SIZE    => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
473
      -- Memory configuration: Data memory --
474
      MEM_DSPACE_BASE      => MEM_DSPACE_BASE,   -- base address of data memory space
475
      MEM_DSPACE_SIZE      => MEM_DSPACE_SIZE,   -- total size of data memory space in byte
476
      MEM_INT_DMEM_USE     => MEM_INT_DMEM_USE,  -- implement processor-internal data memory
477
      MEM_INT_DMEM_SIZE    => MEM_INT_DMEM_SIZE  -- size of processor-internal data memory in bytes
478
    )
479
    port map (
480
      -- global control --
481
      clk_i    => clk_i,          -- global clock line
482
      rstn_i   => sys_rstn,       -- global reset line, low-active
483
      -- host access --
484
      addr_i   => cpu_addr,       -- address
485
      rden_i   => cpu_re,         -- read enable
486
      wren_i   => cpu_we,         -- write enable
487
      ben_i    => cpu_ben,        -- byte write enable
488
      data_i   => cpu_wdata,      -- data in
489
      data_o   => wishbone_rdata, -- data out
490
      ack_o    => wishbone_ack,   -- transfer acknowledge
491
      err_o    => wishbone_err,   -- transfer error
492
      -- wishbone interface --
493
      wb_adr_o => wb_adr_o,       -- address
494
      wb_dat_i => wb_dat_i,       -- read data
495
      wb_dat_o => wb_dat_o,       -- write data
496
      wb_we_o  => wb_we_o,        -- read/write
497
      wb_sel_o => wb_sel_o,       -- byte enable
498
      wb_stb_o => wb_stb_o,       -- strobe
499
      wb_cyc_o => wb_cyc_o,       -- valid cycle
500
      wb_ack_i => wb_ack_i,       -- transfer acknowledge
501
      wb_err_i => wb_err_i        -- transfer error
502
    );
503
  end generate;
504
 
505
  neorv32_wishbone_inst_false:
506
  if (MEM_EXT_USE = false) generate
507
    wishbone_rdata <= (others => '0');
508
    wishbone_ack   <= '0';
509
    wishbone_err   <= '0';
510
    --
511
    wb_adr_o <= (others => '0');
512
    wb_dat_o <= (others => '0');
513
    wb_we_o  <= '0';
514
    wb_sel_o <= (others => '0');
515
    wb_stb_o <= '0';
516
    wb_cyc_o <= '0';
517
  end generate;
518
 
519
 
520
  -- IO Access? -----------------------------------------------------------------------------
521
  -- -------------------------------------------------------------------------------------------
522
  io_acc  <= '1' when (cpu_addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0';
523
  io_rden <= io_acc and cpu_re;
524
  io_wren <= io_acc and cpu_we;
525
 
526
 
527
  -- General Purpose Input/Output Port (GPIO) -----------------------------------------------
528
  -- -------------------------------------------------------------------------------------------
529
  neorv32_gpio_inst_true:
530
  if (IO_GPIO_USE = true) generate
531
    neorv32_gpio_inst: neorv32_gpio
532
    port map (
533
      -- host access --
534
      clk_i  => clk_i,      -- global clock line
535
      addr_i => cpu_addr,   -- address
536
      rden_i => io_rden,    -- read enable
537
      wren_i => io_wren,    -- write enable
538
      ben_i  => cpu_ben,    -- byte write enable
539
      data_i => cpu_wdata,  -- data in
540
      data_o => gpio_rdata, -- data out
541
      ack_o  => gpio_ack,   -- transfer acknowledge
542
      -- parallel io --
543
      gpio_o => gpio_o,
544
      gpio_i => gpio_i,
545
      -- interrupt --
546
      irq_o  => gpio_irq    -- pin-change interrupt
547
    );
548
  end generate;
549
 
550
  neorv32_gpio_inst_false:
551
  if (IO_GPIO_USE = false) generate
552
    gpio_rdata <= (others => '0');
553
    gpio_ack   <= '0';
554
    gpio_o     <= (others => '0');
555
    gpio_irq   <= '0';
556
  end generate;
557
 
558
 
559
  -- Core-Local Interrupt Controller (CLIC) -------------------------------------------------
560
  -- -------------------------------------------------------------------------------------------
561
  neorv32_clic_inst_true:
562
  if (IO_CLIC_USE = true) generate
563
    neorv32_clic_inst: neorv32_clic
564
    port map (
565
      -- host access --
566
      clk_i     => clk_i,      -- global clock line
567
      rden_i    => io_rden,    -- read enable
568
      wren_i    => io_wren,    -- write enable
569
      ben_i     => cpu_ben,    -- byte write enable
570
      addr_i    => cpu_addr,   -- address
571
      data_i    => cpu_wdata,  -- data in
572
      data_o    => clic_rdata, -- data out
573
      ack_o     => clic_ack,   -- transfer acknowledge
574
      -- cpu interrupt --
575
      cpu_irq_o => clic_irq,   -- trigger CPU's external IRQ
576
      -- external interrupt lines --
577
      ext_irq_i => clic_xirq,  -- IRQ, triggering on HIGH level
578
      ext_ack_o => clic_xack   -- acknowledge
579
    );
580
  end generate;
581
 
582
  -- CLIC interrupt channels and priority --
583
  clic_xirq(0) <= wdt_irq; -- highest priority
584
  clic_xirq(1) <= '0'; -- reserved
585
  clic_xirq(2) <= gpio_irq;
586
  clic_xirq(3) <= uart_irq;
587
  clic_xirq(4) <= spi_irq;
588
  clic_xirq(5) <= twi_irq;
589
  clic_xirq(6) <= ext_irq_i(0);
590
  clic_xirq(7) <= ext_irq_i(1); -- lowest priority
591
 
592 4 zero_gravi
  -- external interrupt request acknowledge --
593
  ext_ack_o(0) <= clic_xack(6);
594
  ext_ack_o(1) <= clic_xack(7);
595 2 zero_gravi
 
596
  neorv32_clic_inst_false:
597
  if (IO_CLIC_USE = false) generate
598
    clic_rdata <= (others => '0');
599
    clic_ack   <= '0';
600
    clic_irq   <= '0';
601
    clic_xack  <= (others => '0');
602
  end generate;
603
 
604
 
605
  -- Watch Dog Timer (WDT) ------------------------------------------------------------------
606
  -- -------------------------------------------------------------------------------------------
607
  neorv32_wdt_inst_true:
608
  if (IO_WDT_USE = true) generate
609
    neorv32_wdt_inst: neorv32_wdt
610
    port map (
611
      -- host access --
612
      clk_i       => clk_i,      -- global clock line
613
      rstn_i      => ext_rstn,   -- global reset line, low-active
614
      rden_i      => io_rden,    -- read enable
615
      wren_i      => io_wren,    -- write enable
616
      ben_i       => cpu_ben,    -- byte write enable
617
      addr_i      => cpu_addr,   -- address
618
      data_i      => cpu_wdata,  -- data in
619
      data_o      => wdt_rdata,  -- data out
620
      ack_o       => wdt_ack,    -- transfer acknowledge
621
      -- clock generator --
622
      clkgen_en_o => wdt_cg_en,  -- enable clock generator
623
      clkgen_i    => clk_gen,
624
      -- timeout event --
625
      irq_o       => wdt_irq,    -- timeout IRQ
626
      rstn_o      => wdt_rstn    -- timeout reset, low_active, use it as async!
627
    );
628
  end generate;
629
 
630
  neorv32_wdt_inst_false:
631
  if (IO_WDT_USE = false) generate
632
    wdt_rdata <= (others => '0');
633
    wdt_ack   <= '0';
634
    wdt_irq   <= '0';
635
    wdt_rstn  <= '1';
636
    wdt_cg_en <= '0';
637
  end generate;
638
 
639
 
640
  -- Machine System Timer (MTIME) -----------------------------------------------------------
641
  -- -------------------------------------------------------------------------------------------
642
  neorv32_mtime_inst_true:
643
  if (IO_MTIME_USE = true) generate
644
    neorv32_mtime_inst: neorv32_mtime
645
    port map (
646
      -- host access --
647
      clk_i     => clk_i,        -- global clock line
648 4 zero_gravi
      rstn_i    => sys_rstn,     -- global reset, low-active, async
649 2 zero_gravi
      addr_i    => cpu_addr,     -- address
650
      rden_i    => io_rden,      -- read enable
651
      wren_i    => io_wren,      -- write enable
652
      ben_i     => cpu_ben,      -- byte write enable
653
      data_i    => cpu_wdata,    -- data in
654
      data_o    => mtime_rdata,  -- data out
655
      ack_o     => mtime_ack,    -- transfer acknowledge
656
      -- interrupt --
657
      irq_o     => mtime_irq     -- interrupt request
658
    );
659
  end generate;
660
 
661
  neorv32_mtime_inst_false:
662
  if (IO_MTIME_USE = false) generate
663
    mtime_rdata <= (others => '0');
664
    mtime_ack   <= '0';
665
    mtime_irq   <= '0';
666
  end generate;
667
 
668
 
669
  -- Universal Asynchronous Receiver/Transmitter (UART) -------------------------------------
670
  -- -------------------------------------------------------------------------------------------
671
  neorv32_uart_inst_true:
672
  if (IO_UART_USE = true) generate
673
    neorv32_uart_inst: neorv32_uart
674
    port map (
675
      -- host access --
676
      clk_i       => clk_i,      -- global clock line
677
      addr_i      => cpu_addr,   -- address
678
      rden_i      => io_rden,    -- read enable
679
      wren_i      => io_wren,    -- write enable
680
      ben_i       => cpu_ben,    -- byte write enable
681
      data_i      => cpu_wdata,  -- data in
682
      data_o      => uart_rdata, -- data out
683
      ack_o       => uart_ack,   -- transfer acknowledge
684
      -- clock generator --
685
      clkgen_en_o => uart_cg_en, -- enable clock generator
686
      clkgen_i    => clk_gen,
687
      -- com lines --
688
      uart_txd_o  => uart_txd_o,
689
      uart_rxd_i  => uart_rxd_i,
690
      -- interrupts --
691
      uart_irq_o  => uart_irq    -- uart rx/tx interrupt
692
    );
693
  end generate;
694
 
695
  neorv32_uart_inst_false:
696
  if (IO_UART_USE = false) generate
697
    uart_rdata <= (others => '0');
698
    uart_ack   <= '0';
699
    uart_txd_o <= '0';
700
    uart_cg_en <= '0';
701
    uart_irq   <= '0';
702
  end generate;
703
 
704
 
705
  -- Serial Peripheral Interface (SPI) ------------------------------------------------------
706
  -- -------------------------------------------------------------------------------------------
707
  neorv32_spi_inst_true:
708
  if (IO_SPI_USE = true) generate
709
    neorv32_spi_inst: neorv32_spi
710
    port map (
711
      -- host access --
712
      clk_i       => clk_i,      -- global clock line
713
      addr_i      => cpu_addr,   -- address
714
      rden_i      => io_rden,    -- read enable
715
      wren_i      => io_wren,    -- write enable
716
      ben_i       => cpu_ben,    -- byte write enable
717
      data_i      => cpu_wdata,  -- data in
718
      data_o      => spi_rdata,  -- data out
719
      ack_o       => spi_ack,    -- transfer acknowledge
720
      -- clock generator --
721
      clkgen_en_o => spi_cg_en,  -- enable clock generator
722
      clkgen_i    => clk_gen,
723
      -- com lines --
724 6 zero_gravi
      spi_sck_o   => spi_sck_o,  -- SPI serial clock
725
      spi_sdo_o   => spi_sdo_o,  -- controller data out, peripheral data in
726
      spi_sdi_i   => spi_sdi_i,  -- controller data in, peripheral data out
727 2 zero_gravi
      spi_csn_o   => spi_csn_o,  -- SPI CS
728
      -- interrupt --
729
      spi_irq_o   => spi_irq     -- transmission done interrupt
730
    );
731
  end generate;
732
 
733
  neorv32_spi_inst_false:
734
  if (IO_SPI_USE = false) generate
735
    spi_rdata  <= (others => '0');
736
    spi_ack    <= '0';
737 6 zero_gravi
    spi_sck_o  <= '0';
738
    spi_sdo_o  <= '0';
739 2 zero_gravi
    spi_csn_o  <= (others => '1'); -- CSn lines are low-active
740
    spi_cg_en  <= '0';
741
    spi_irq    <= '0';
742
  end generate;
743
 
744
 
745
  -- Two-Wire Interface (TWI) ---------------------------------------------------------------
746
  -- -------------------------------------------------------------------------------------------
747
  neorv32_twi_inst_true:
748
  if (IO_TWI_USE = true) generate
749
    neorv32_twi_inst: neorv32_twi
750
    port map (
751
      -- host access --
752
      clk_i       => clk_i,      -- global clock line
753
      addr_i      => cpu_addr,   -- address
754
      rden_i      => io_rden,    -- read enable
755
      wren_i      => io_wren,    -- write enable
756
      ben_i       => cpu_ben,    -- byte write enable
757
      data_i      => cpu_wdata,  -- data in
758
      data_o      => twi_rdata,  -- data out
759
      ack_o       => twi_ack,    -- transfer acknowledge
760
      -- clock generator --
761
      clkgen_en_o => twi_cg_en,  -- enable clock generator
762
      clkgen_i    => clk_gen,
763
      -- com lines --
764
      twi_sda_io  => twi_sda_io, -- serial data line
765
      twi_scl_io  => twi_scl_io, -- serial clock line
766
      -- interrupt --
767
      twi_irq_o   => twi_irq     -- transfer done IRQ
768
    );
769
  end generate;
770
 
771
  neorv32_twi_inst_false:
772
  if (IO_TWI_USE = false) generate
773
    twi_rdata  <= (others => '0');
774
    twi_ack    <= '0';
775
--  twi_sda_io <= 'H';
776
--  twi_scl_io <= 'H';
777
    twi_cg_en  <= '0';
778
    twi_irq    <= '0';
779
  end generate;
780
 
781
 
782
  -- Pulse-Width Modulation Controller (PWM) ------------------------------------------------
783
  -- -------------------------------------------------------------------------------------------
784
  neorv32_pwm_inst_true:
785
  if (IO_PWM_USE = true) generate
786
    neorv32_pwm_inst: neorv32_pwm
787
    port map (
788
      -- host access --
789
      clk_i       => clk_i,      -- global clock line
790
      addr_i      => cpu_addr,   -- address
791
      rden_i      => io_rden,    -- read enable
792
      wren_i      => io_wren,    -- write enable
793
      ben_i       => cpu_ben,    -- byte write enable
794
      data_i      => cpu_wdata,  -- data in
795
      data_o      => pwm_rdata,  -- data out
796
      ack_o       => pwm_ack,    -- transfer acknowledge
797
      -- clock generator --
798
      clkgen_en_o => pwm_cg_en,  -- enable clock generator
799
      clkgen_i    => clk_gen,
800
      -- pwm output channels --
801
      pwm_o       => pwm_o
802
    );
803
  end generate;
804
 
805
  neorv32_pwm_inst_false:
806
  if (IO_PWM_USE = false) generate
807
    pwm_rdata <= (others => '0');
808
    pwm_ack   <= '0';
809
    pwm_cg_en <= '0';
810
    pwm_o     <= (others => '0');
811
  end generate;
812
 
813
 
814
  -- True Random Number Generator (TRNG) ----------------------------------------------------
815
  -- -------------------------------------------------------------------------------------------
816
  neorv32_trng_inst_true:
817
  if (IO_TRNG_USE = true) generate
818
    neorv32_trng_inst: neorv32_trng
819
    port map (
820
      -- host access --
821
      clk_i  => clk_i,      -- global clock line
822
      addr_i => cpu_addr,   -- address
823
      rden_i => io_rden,    -- read enable
824
      wren_i => io_wren,    -- write enable
825
      ben_i  => cpu_ben,    -- byte write enable
826
      data_i => cpu_wdata,  -- data in
827
      data_o => trng_rdata, -- data out
828
      ack_o  => trng_ack    -- transfer acknowledge
829
    );
830
  end generate;
831
 
832
  neorv32_trng_inst_false:
833
  if (IO_TRNG_USE = false) generate
834
    trng_rdata <= (others => '0');
835
    trng_ack   <= '0';
836
  end generate;
837
 
838
 
839 3 zero_gravi
  -- Dummy Device (DEVNULL) -----------------------------------------------------------------
840
  -- -------------------------------------------------------------------------------------------
841
  neorv32_devnull_inst_true:
842
  if (IO_DEVNULL_USE = true) generate
843
    neorv32_devnull_inst: neorv32_devnull
844
    port map (
845
      -- host access --
846
      clk_i  => clk_i,         -- global clock line
847
      addr_i => cpu_addr,      -- address
848
      rden_i => io_rden,       -- read enable
849
      wren_i => io_wren,       -- write enable
850
      ben_i  => cpu_ben,       -- byte write enable
851
      data_i => cpu_wdata,     -- data in
852
      data_o => devnull_rdata, -- data out
853
      ack_o  => devnull_ack    -- transfer acknowledge
854
    );
855
  end generate;
856 4 zero_gravi
 
857 3 zero_gravi
  neorv32_devnull_inst_false:
858
  if (IO_DEVNULL_USE = false) generate
859
    devnull_rdata <= (others => '0');
860
    devnull_ack   <= '0';
861
  end generate;
862
 
863
 
864 2 zero_gravi
end neorv32_top_rtl;

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