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1 2 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - Processor Top Entity >>                                                          #
3
-- # ********************************************************************************************* #
4 18 zero_gravi
-- # This is the top entity of the NEORV32 PROCESSOR. Instantiate this unit in your own project    #
5 63 zero_gravi
-- # and define all the configuration generics according to your needs or use one of the           #
6
-- # pre-defined template wrappers.                                                                #
7 18 zero_gravi
-- #                                                                                               #
8 63 zero_gravi
-- # Check out the processor's online documentation for more information:                          #
9
-- #  HQ:         https://github.com/stnolting/neorv32                                             #
10
-- #  Data Sheet: https://stnolting.github.io/neorv32                                              #
11
-- #  User Guide: https://stnolting.github.io/neorv32/ug                                           #
12 2 zero_gravi
-- # ********************************************************************************************* #
13
-- # BSD 3-Clause License                                                                          #
14
-- #                                                                                               #
15 42 zero_gravi
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
16 2 zero_gravi
-- #                                                                                               #
17
-- # Redistribution and use in source and binary forms, with or without modification, are          #
18
-- # permitted provided that the following conditions are met:                                     #
19
-- #                                                                                               #
20
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
21
-- #    conditions and the following disclaimer.                                                   #
22
-- #                                                                                               #
23
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
24
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
25
-- #    provided with the distribution.                                                            #
26
-- #                                                                                               #
27
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
28
-- #    endorse or promote products derived from this software without specific prior written      #
29
-- #    permission.                                                                                #
30
-- #                                                                                               #
31
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
32
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
33
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
34
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
35
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
36
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
37
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
38
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
39
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
40
-- # ********************************************************************************************* #
41
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
42
-- #################################################################################################
43
 
44
library ieee;
45
use ieee.std_logic_1164.all;
46
use ieee.numeric_std.all;
47
 
48
library neorv32;
49
use neorv32.neorv32_package.all;
50
 
51
entity neorv32_top is
52
  generic (
53
    -- General --
54 62 zero_gravi
    CLOCK_FREQUENCY              : natural;           -- clock frequency of clk_i in Hz
55 49 zero_gravi
    HW_THREAD_ID                 : natural := 0;      -- hardware thread id (32-bit)
56 62 zero_gravi
    INT_BOOTLOADER_EN            : boolean := false;  -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
57 50 zero_gravi
 
58 59 zero_gravi
    -- On-Chip Debugger (OCD) --
59
    ON_CHIP_DEBUGGER_EN          : boolean := false;  -- implement on-chip debugger
60
 
61 2 zero_gravi
    -- RISC-V CPU Extensions --
62 39 zero_gravi
    CPU_EXTENSION_RISCV_A        : boolean := false;  -- implement atomic extension?
63 11 zero_gravi
    CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?
64 8 zero_gravi
    CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
65 61 zero_gravi
    CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement mul/div extension?
66 15 zero_gravi
    CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?
67 63 zero_gravi
    CPU_EXTENSION_RISCV_Zbb      : boolean := false;  -- implement basic bit-manipulation sub-extension?
68 57 zero_gravi
    CPU_EXTENSION_RISCV_Zfinx    : boolean := false;  -- implement 32-bit floating-point extension (using INT regs!)
69 8 zero_gravi
    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?
70 39 zero_gravi
    CPU_EXTENSION_RISCV_Zifencei : boolean := false;  -- implement instruction stream sync.?
71 61 zero_gravi
    CPU_EXTENSION_RISCV_Zmmul    : boolean := false;  -- implement multiply-only M sub-extension?
72 50 zero_gravi
 
73 19 zero_gravi
    -- Extension Options --
74 23 zero_gravi
    FAST_MUL_EN                  : boolean := false;  -- use DSPs for M extension's multiplier
75 39 zero_gravi
    FAST_SHIFT_EN                : boolean := false;  -- use barrel shifter for shift operations
76 56 zero_gravi
    CPU_CNT_WIDTH                : natural := 64;     -- total width of CPU cycle and instret counters (0..64)
77 62 zero_gravi
    CPU_IPB_ENTRIES              : natural := 2;      -- entries is instruction prefetch buffer, has to be a power of 2
78 50 zero_gravi
 
79 15 zero_gravi
    -- Physical Memory Protection (PMP) --
80 42 zero_gravi
    PMP_NUM_REGIONS              : natural := 0;      -- number of regions (0..64)
81
    PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
82 50 zero_gravi
 
83 42 zero_gravi
    -- Hardware Performance Monitors (HPM) --
84 47 zero_gravi
    HPM_NUM_CNTS                 : natural := 0;      -- number of implemented HPM counters (0..29)
85 60 zero_gravi
    HPM_CNT_WIDTH                : natural := 40;     -- total size of HPM counters (0..64)
86 50 zero_gravi
 
87 61 zero_gravi
    -- Internal Instruction memory (IMEM) --
88 62 zero_gravi
    MEM_INT_IMEM_EN              : boolean := false;  -- implement processor-internal instruction memory
89 8 zero_gravi
    MEM_INT_IMEM_SIZE            : natural := 16*1024; -- size of processor-internal instruction memory in bytes
90 50 zero_gravi
 
91 61 zero_gravi
    -- Internal Data memory (DMEM) --
92 62 zero_gravi
    MEM_INT_DMEM_EN              : boolean := false;  -- implement processor-internal data memory
93 8 zero_gravi
    MEM_INT_DMEM_SIZE            : natural := 8*1024; -- size of processor-internal data memory in bytes
94 50 zero_gravi
 
95 61 zero_gravi
    -- Internal Cache memory (iCACHE) --
96 44 zero_gravi
    ICACHE_EN                    : boolean := false;  -- implement instruction cache
97 41 zero_gravi
    ICACHE_NUM_BLOCKS            : natural := 4;      -- i-cache: number of blocks (min 1), has to be a power of 2
98
    ICACHE_BLOCK_SIZE            : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
99 45 zero_gravi
    ICACHE_ASSOCIATIVITY         : natural := 1;      -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
100 50 zero_gravi
 
101 61 zero_gravi
    -- External memory interface (WISHBONE) --
102 44 zero_gravi
    MEM_EXT_EN                   : boolean := false;  -- implement external memory bus interface?
103 57 zero_gravi
    MEM_EXT_TIMEOUT              : natural := 255;    -- cycles after a pending bus access auto-terminates (0 = disabled)
104 62 zero_gravi
    MEM_EXT_PIPE_MODE            : boolean := false;  -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
105
    MEM_EXT_BIG_ENDIAN           : boolean := false;  -- byte order: true=big-endian, false=little-endian
106
    MEM_EXT_ASYNC_RX             : boolean := false;  -- use register buffer for RX data when false
107 50 zero_gravi
 
108 61 zero_gravi
    -- Stream link interface (SLINK) --
109
    SLINK_NUM_TX                 : natural := 0;      -- number of TX links (0..8)
110
    SLINK_NUM_RX                 : natural := 0;      -- number of TX links (0..8)
111
    SLINK_TX_FIFO                : natural := 1;      -- TX fifo depth, has to be a power of two
112
    SLINK_RX_FIFO                : natural := 1;      -- RX fifo depth, has to be a power of two
113
 
114
    -- External Interrupts Controller (XIRQ) --
115
    XIRQ_NUM_CH                  : natural := 0;      -- number of external IRQ channels (0..32)
116 63 zero_gravi
    XIRQ_TRIGGER_TYPE            : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger type: 0=level, 1=edge
117
    XIRQ_TRIGGER_POLARITY        : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
118 61 zero_gravi
 
119 2 zero_gravi
    -- Processor peripherals --
120 62 zero_gravi
    IO_GPIO_EN                   : boolean := false;  -- implement general purpose input/output port unit (GPIO)?
121
    IO_MTIME_EN                  : boolean := false;  -- implement machine system timer (MTIME)?
122
    IO_UART0_EN                  : boolean := false;  -- implement primary universal asynchronous receiver/transmitter (UART0)?
123
    IO_UART1_EN                  : boolean := false;  -- implement secondary universal asynchronous receiver/transmitter (UART1)?
124
    IO_SPI_EN                    : boolean := false;  -- implement serial peripheral interface (SPI)?
125
    IO_TWI_EN                    : boolean := false;  -- implement two-wire interface (TWI)?
126
    IO_PWM_NUM_CH                : natural := 0;      -- number of PWM channels to implement (0..60); 0 = disabled
127
    IO_WDT_EN                    : boolean := false;  -- implement watch dog timer (WDT)?
128 44 zero_gravi
    IO_TRNG_EN                   : boolean := false;  -- implement true random number generator (TRNG)?
129 47 zero_gravi
    IO_CFS_EN                    : boolean := false;  -- implement custom functions subsystem (CFS)?
130 56 zero_gravi
    IO_CFS_CONFIG                : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
131 52 zero_gravi
    IO_CFS_IN_SIZE               : positive := 32;    -- size of CFS input conduit in bits
132
    IO_CFS_OUT_SIZE              : positive := 32;    -- size of CFS output conduit in bits
133 62 zero_gravi
    IO_NEOLED_EN                 : boolean := false;  -- implement NeoPixel-compatible smart LED interface (NEOLED)?
134
    IO_NEOLED_TX_FIFO            : natural := 1       -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
135 2 zero_gravi
  );
136
  port (
137
    -- Global control --
138 62 zero_gravi
    clk_i          : in  std_ulogic; -- global clock, rising edge
139
    rstn_i         : in  std_ulogic; -- global reset, low-active, async
140 50 zero_gravi
 
141 59 zero_gravi
    -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
142 62 zero_gravi
    jtag_trst_i    : in  std_ulogic := 'U'; -- low-active TAP reset (optional)
143
    jtag_tck_i     : in  std_ulogic := 'U'; -- serial clock
144
    jtag_tdi_i     : in  std_ulogic := 'U'; -- serial data input
145 61 zero_gravi
    jtag_tdo_o     : out std_ulogic;        -- serial data output
146 62 zero_gravi
    jtag_tms_i     : in  std_ulogic := 'U'; -- mode select
147 59 zero_gravi
 
148 44 zero_gravi
    -- Wishbone bus interface (available if MEM_EXT_EN = true) --
149 61 zero_gravi
    wb_tag_o       : out std_ulogic_vector(02 downto 0); -- request tag
150
    wb_adr_o       : out std_ulogic_vector(31 downto 0); -- address
151 62 zero_gravi
    wb_dat_i       : in  std_ulogic_vector(31 downto 0) := (others => 'U'); -- read data
152 61 zero_gravi
    wb_dat_o       : out std_ulogic_vector(31 downto 0); -- write data
153
    wb_we_o        : out std_ulogic; -- read/write
154
    wb_sel_o       : out std_ulogic_vector(03 downto 0); -- byte enable
155
    wb_stb_o       : out std_ulogic; -- strobe
156
    wb_cyc_o       : out std_ulogic; -- valid cycle
157
    wb_lock_o      : out std_ulogic; -- exclusive access request
158 62 zero_gravi
    wb_ack_i       : in  std_ulogic := 'L'; -- transfer acknowledge
159
    wb_err_i       : in  std_ulogic := 'L'; -- transfer error
160 50 zero_gravi
 
161 44 zero_gravi
    -- Advanced memory control signals (available if MEM_EXT_EN = true) --
162 61 zero_gravi
    fence_o        : out std_ulogic; -- indicates an executed FENCE operation
163
    fencei_o       : out std_ulogic; -- indicates an executed FENCEI operation
164 50 zero_gravi
 
165 61 zero_gravi
    -- TX stream interfaces (available if SLINK_NUM_TX > 0) --
166
    slink_tx_dat_o : out sdata_8x32_t; -- output data
167
    slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output
168 62 zero_gravi
    slink_tx_rdy_i : in  std_ulogic_vector(7 downto 0) := (others => 'L'); -- ready to send
169 61 zero_gravi
 
170
    -- RX stream interfaces (available if SLINK_NUM_RX > 0) --
171 62 zero_gravi
    slink_rx_dat_i : in  sdata_8x32_t := (others => (others => 'U')); -- input data
172
    slink_rx_val_i : in  std_ulogic_vector(7 downto 0) := (others => 'L'); -- valid input
173 61 zero_gravi
    slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive
174
 
175 44 zero_gravi
    -- GPIO (available if IO_GPIO_EN = true) --
176 61 zero_gravi
    gpio_o         : out std_ulogic_vector(63 downto 0); -- parallel output
177 62 zero_gravi
    gpio_i         : in  std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input
178 50 zero_gravi
 
179
    -- primary UART0 (available if IO_UART0_EN = true) --
180 61 zero_gravi
    uart0_txd_o    : out std_ulogic; -- UART0 send data
181 62 zero_gravi
    uart0_rxd_i    : in  std_ulogic := 'U'; -- UART0 receive data
182 61 zero_gravi
    uart0_rts_o    : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
183 62 zero_gravi
    uart0_cts_i    : in  std_ulogic := 'L'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
184 50 zero_gravi
 
185
    -- secondary UART1 (available if IO_UART1_EN = true) --
186 61 zero_gravi
    uart1_txd_o    : out std_ulogic; -- UART1 send data
187 62 zero_gravi
    uart1_rxd_i    : in  std_ulogic := 'U'; -- UART1 receive data
188 61 zero_gravi
    uart1_rts_o    : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
189 62 zero_gravi
    uart1_cts_i    : in  std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
190 50 zero_gravi
 
191 44 zero_gravi
    -- SPI (available if IO_SPI_EN = true) --
192 61 zero_gravi
    spi_sck_o      : out std_ulogic; -- SPI serial clock
193
    spi_sdo_o      : out std_ulogic; -- controller data out, peripheral data in
194 62 zero_gravi
    spi_sdi_i      : in  std_ulogic := 'U'; -- controller data in, peripheral data out
195 61 zero_gravi
    spi_csn_o      : out std_ulogic_vector(07 downto 0); -- chip-select
196 50 zero_gravi
 
197 44 zero_gravi
    -- TWI (available if IO_TWI_EN = true) --
198 62 zero_gravi
    twi_sda_io     : inout std_logic := 'U'; -- twi serial data line
199
    twi_scl_io     : inout std_logic := 'U'; -- twi serial clock line
200 50 zero_gravi
 
201 60 zero_gravi
    -- PWM (available if IO_PWM_NUM_CH > 0) --
202 61 zero_gravi
    pwm_o          : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels
203 50 zero_gravi
 
204 47 zero_gravi
    -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
205 62 zero_gravi
    cfs_in_i       : in  std_ulogic_vector(IO_CFS_IN_SIZE-1  downto 0) := (others => 'U'); -- custom CFS inputs conduit
206 61 zero_gravi
    cfs_out_o      : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
207 50 zero_gravi
 
208 52 zero_gravi
    -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
209 61 zero_gravi
    neoled_o       : out std_ulogic; -- async serial data line
210 52 zero_gravi
 
211 59 zero_gravi
    -- System time --
212 62 zero_gravi
    mtime_i        : in  std_ulogic_vector(63 downto 0) := (others => 'U'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
213 61 zero_gravi
    mtime_o        : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
214 50 zero_gravi
 
215 61 zero_gravi
    -- External platform interrupts (available if XIRQ_NUM_CH > 0) --
216 62 zero_gravi
    xirq_i         : in  std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => 'L'); -- IRQ channels
217 61 zero_gravi
 
218
    -- CPU interrupts --
219 62 zero_gravi
    nm_irq_i       : in  std_ulogic := 'L'; -- non-maskable interrupt
220
    mtime_irq_i    : in  std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false
221
    msw_irq_i      : in  std_ulogic := 'L'; -- machine software interrupt
222
    mext_irq_i     : in  std_ulogic := 'L'  -- machine external interrupt
223 2 zero_gravi
  );
224
end neorv32_top;
225
 
226
architecture neorv32_top_rtl of neorv32_top is
227
 
228 61 zero_gravi
  -- CPU boot configuration --
229
  constant cpu_boot_addr_c : std_ulogic_vector(31 downto 0) := cond_sel_stdulogicvector_f(INT_BOOTLOADER_EN, boot_rom_base_c, ispace_base_c);
230 12 zero_gravi
 
231 29 zero_gravi
  -- alignment check for internal memories --
232
  constant imem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) := (others => '0');
233
  constant dmem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) := (others => '0');
234
 
235 61 zero_gravi
  -- helpers --
236
  constant io_slink_en_c : boolean := boolean(SLINK_NUM_RX > 0) or boolean(SLINK_NUM_TX > 0); -- implement slink at all?
237
 
238 2 zero_gravi
  -- reset generator --
239 63 zero_gravi
  signal rstn_gen : std_ulogic_vector(7 downto 0) := (others => '0'); -- initialize (=reset) via  (for FPGAs only)
240 60 zero_gravi
  signal ext_rstn : std_ulogic;
241
  signal sys_rstn : std_ulogic;
242
  signal wdt_rstn : std_ulogic;
243 2 zero_gravi
 
244
  -- clock generator --
245
  signal clk_div    : std_ulogic_vector(11 downto 0);
246
  signal clk_div_ff : std_ulogic_vector(11 downto 0);
247
  signal clk_gen    : std_ulogic_vector(07 downto 0);
248 61 zero_gravi
  signal clk_gen_en : std_ulogic_vector(07 downto 0);
249 47 zero_gravi
  --
250 52 zero_gravi
  signal wdt_cg_en    : std_ulogic;
251
  signal uart0_cg_en  : std_ulogic;
252
  signal uart1_cg_en  : std_ulogic;
253
  signal spi_cg_en    : std_ulogic;
254
  signal twi_cg_en    : std_ulogic;
255
  signal pwm_cg_en    : std_ulogic;
256
  signal cfs_cg_en    : std_ulogic;
257
  signal neoled_cg_en : std_ulogic;
258 2 zero_gravi
 
259 12 zero_gravi
  -- bus interface --
260
  type bus_interface_t is record
261 11 zero_gravi
    addr   : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
262
    rdata  : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
263
    wdata  : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
264
    ben    : std_ulogic_vector(03 downto 0); -- byte enable
265
    we     : std_ulogic; -- write enable
266
    re     : std_ulogic; -- read enable
267
    ack    : std_ulogic; -- bus transfer acknowledge
268
    err    : std_ulogic; -- bus transfer error
269 12 zero_gravi
    fence  : std_ulogic; -- fence(i) instruction executed
270 35 zero_gravi
    priv   : std_ulogic_vector(1 downto 0); -- current privilege level
271 40 zero_gravi
    src    : std_ulogic; -- access source (1=instruction fetch, 0=data access)
272 57 zero_gravi
    lock   : std_ulogic; -- exclusive access request
273 11 zero_gravi
  end record;
274 41 zero_gravi
  signal cpu_i, i_cache, cpu_d, p_bus : bus_interface_t;
275 2 zero_gravi
 
276 59 zero_gravi
  -- debug core interface (DCI) --
277
  signal dci_ndmrstn  : std_ulogic;
278
  signal dci_halt_req : std_ulogic;
279
 
280
  -- debug module interface (DMI) --
281
  type dmi_t is record
282
    rstn       : std_ulogic;
283
    req_valid  : std_ulogic;
284
    req_ready  : std_ulogic; -- DMI is allowed to make new requests when set
285
    req_addr   : std_ulogic_vector(06 downto 0);
286
    req_op     : std_ulogic; -- 0=read, 1=write
287
    req_data   : std_ulogic_vector(31 downto 0);
288
    resp_valid : std_ulogic; -- response valid when set
289
    resp_ready : std_ulogic; -- ready to receive respond
290
    resp_data  : std_ulogic_vector(31 downto 0);
291
    resp_err   : std_ulogic; -- 0=ok, 1=error
292
  end record;
293
  signal dmi : dmi_t;
294
 
295 2 zero_gravi
  -- io space access --
296
  signal io_acc  : std_ulogic;
297
  signal io_rden : std_ulogic;
298
  signal io_wren : std_ulogic;
299
 
300 60 zero_gravi
  -- module response bus - entry type --
301
  type resp_bus_entry_t is record
302
    rdata : std_ulogic_vector(data_width_c-1 downto 0);
303
    ack   : std_ulogic;
304
    err   : std_ulogic;
305
  end record;
306
  constant resp_bus_entry_terminate_c : resp_bus_entry_t := (rdata => (others => '0'), ack => '0', err => '0');
307 2 zero_gravi
 
308 60 zero_gravi
  -- module response bus - device ID --
309
  type resp_bus_id_t is (RESP_IMEM, RESP_DMEM, RESP_BOOTROM, RESP_WISHBONE, RESP_GPIO, RESP_MTIME, RESP_UART0, RESP_UART1, RESP_SPI,
310 61 zero_gravi
                         RESP_TWI, RESP_PWM, RESP_WDT, RESP_TRNG, RESP_CFS, RESP_NEOLED, RESP_SYSINFO, RESP_OCD, RESP_SLINK, RESP_XIRQ);
311 60 zero_gravi
 
312
  -- module response bus --
313
  type resp_bus_t is array (resp_bus_id_t) of resp_bus_entry_t;
314
  signal resp_bus : resp_bus_t := (others => resp_bus_entry_terminate_c);
315
 
316 2 zero_gravi
  -- IRQs --
317 59 zero_gravi
  signal fast_irq      : std_ulogic_vector(15 downto 0);
318 60 zero_gravi
  signal mtime_irq     : std_ulogic;
319 50 zero_gravi
  signal wdt_irq       : std_ulogic;
320
  signal uart0_rxd_irq : std_ulogic;
321
  signal uart0_txd_irq : std_ulogic;
322
  signal uart1_rxd_irq : std_ulogic;
323
  signal uart1_txd_irq : std_ulogic;
324
  signal spi_irq       : std_ulogic;
325
  signal twi_irq       : std_ulogic;
326
  signal cfs_irq       : std_ulogic;
327 52 zero_gravi
  signal neoled_irq    : std_ulogic;
328 61 zero_gravi
  signal slink_tx_irq  : std_ulogic;
329
  signal slink_rx_irq  : std_ulogic;
330
  signal xirq_irq      : std_ulogic;
331 2 zero_gravi
 
332 62 zero_gravi
  -- machine (CPU) interrupts --
333
  signal x_nm_irq,    nm_irq_ff    : std_ulogic;
334
  signal x_mtime_irq, mtime_irq_ff : std_ulogic;
335
  signal x_msw_irq,   msw_irq_ff   : std_ulogic;
336
  signal x_mext_irq,  mext_irq_ff  : std_ulogic;
337
 
338 11 zero_gravi
  -- misc --
339 60 zero_gravi
  signal mtime_time     : std_ulogic_vector(63 downto 0); -- current system time from MTIME
340
  signal cpu_sleep      : std_ulogic; -- CPU is in sleep mode when set
341
  signal bus_keeper_err : std_ulogic; -- bus keeper: bus access timeout
342 11 zero_gravi
 
343 2 zero_gravi
begin
344
 
345 61 zero_gravi
  -- Processor IO/Peripherals Configuration -------------------------------------------------
346
  -- -------------------------------------------------------------------------------------------
347
  assert false report
348
  "NEORV32 PROCESSOR IO Configuration: " &
349
  cond_sel_string_f(IO_GPIO_EN, "GPIO ", "") &
350
  cond_sel_string_f(IO_MTIME_EN, "MTIME ", "") &
351
  cond_sel_string_f(IO_UART0_EN, "UART0 ", "") &
352
  cond_sel_string_f(IO_UART1_EN, "UART1 ", "") &
353
  cond_sel_string_f(IO_SPI_EN, "SPI ", "") &
354
  cond_sel_string_f(IO_TWI_EN, "TWI ", "") &
355
  cond_sel_string_f(boolean(IO_PWM_NUM_CH > 0), "PWM ", "") &
356
  cond_sel_string_f(IO_WDT_EN, "WDT ", "") &
357
  cond_sel_string_f(IO_TRNG_EN, "TRNG ", "") &
358
  cond_sel_string_f(IO_CFS_EN, "CFS ", "") &
359
  cond_sel_string_f(io_slink_en_c, "SLINK ", "") &
360
  cond_sel_string_f(IO_NEOLED_EN, "NEOLED ", "") &
361
  cond_sel_string_f(boolean(XIRQ_NUM_CH > 0), "XIRQ ", "") &
362
  ""
363
  severity note;
364
 
365
 
366 2 zero_gravi
  -- Sanity Checks --------------------------------------------------------------------------
367
  -- -------------------------------------------------------------------------------------------
368 61 zero_gravi
  -- boot configuration --
369
  assert not (INT_BOOTLOADER_EN = true) report "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Indirect boot via bootloader (processor-internal BOOTROM)." severity note;
370
  assert not ((INT_BOOTLOADER_EN = false) and (MEM_INT_IMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Direct boot from memory (processor-internal IMEM)." severity note;
371
  assert not ((INT_BOOTLOADER_EN = false) and (MEM_INT_IMEM_EN = false)) report "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Direct boot from memory (processor-external (I)MEM)." severity note;
372
  --
373
  assert not ((MEM_EXT_EN = false) and (MEM_INT_DMEM_EN = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch data without external memory interface and internal IMEM." severity error;
374
  assert not ((MEM_EXT_EN = false) and (MEM_INT_IMEM_EN = false) and (INT_BOOTLOADER_EN = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch instructions without external memory interface, internal IMEM and bootloader." severity error;
375
 
376 36 zero_gravi
  -- memory system - size --
377 44 zero_gravi
  assert not ((MEM_INT_DMEM_EN = true) and (is_power_of_two_f(MEM_INT_IMEM_SIZE) = false)) report "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_IMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning;
378
  assert not ((MEM_INT_IMEM_EN = true) and (is_power_of_two_f(MEM_INT_DMEM_SIZE) = false)) report "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_DMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning;
379 61 zero_gravi
 
380 29 zero_gravi
  -- memory system - alignment --
381
  assert not (ispace_base_c(1 downto 0) /= "00") report "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address must be 4-byte-aligned." severity error;
382
  assert not (dspace_base_c(1 downto 0) /= "00") report "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address must be 4-byte-aligned." severity error;
383 44 zero_gravi
  assert not ((ispace_base_c(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) /= imem_align_check_c) and (MEM_INT_IMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address has to be aligned to IMEM size." severity error;
384
  assert not ((dspace_base_c(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) /= dmem_align_check_c) and (MEM_INT_DMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address has to be aligned to DMEM size." severity error;
385 61 zero_gravi
 
386 36 zero_gravi
  -- memory system - layout warning --
387 29 zero_gravi
  assert not (ispace_base_c /= x"00000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framework." severity warning;
388
  assert not (dspace_base_c /= x"80000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the software framework." severity warning;
389 61 zero_gravi
 
390 41 zero_gravi
  -- memory system - the i-cache is intended to accelerate instruction fetch via the external memory interface only --
391 44 zero_gravi
  assert not ((ICACHE_EN = true) and (MEM_EXT_EN = false)) report "NEORV32 PROCESSOR CONFIG NOTE. Implementing i-cache without having the external memory interface implemented. The i-cache is intended to accelerate instruction fetch via the external memory interface." severity note;
392 61 zero_gravi
 
393 59 zero_gravi
  -- on-chip debugger --
394 61 zero_gravi
  assert not (ON_CHIP_DEBUGGER_EN = true) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing on-chip debugger (OCD)." severity note;
395 2 zero_gravi
 
396 59 zero_gravi
 
397 2 zero_gravi
  -- Reset Generator ------------------------------------------------------------------------
398
  -- -------------------------------------------------------------------------------------------
399 60 zero_gravi
  reset_generator: process(rstn_i, clk_i)
400 2 zero_gravi
  begin
401 60 zero_gravi
    if (rstn_i = '0') then
402 2 zero_gravi
      rstn_gen <= (others => '0');
403 60 zero_gravi
      sys_rstn <= '0';
404 2 zero_gravi
    elsif rising_edge(clk_i) then
405 60 zero_gravi
      -- keep internal reset active for at least <rstn_gen'size> clock cycles --
406 2 zero_gravi
      rstn_gen <= rstn_gen(rstn_gen'left-1 downto 0) & '1';
407 60 zero_gravi
      -- system reset: can also be triggered by watchdog and debug module --
408
      sys_rstn <= ext_rstn and wdt_rstn and dci_ndmrstn;
409 2 zero_gravi
    end if;
410
  end process reset_generator;
411
 
412 60 zero_gravi
  -- beautified external reset signal --
413
  ext_rstn <= rstn_gen(rstn_gen'left);
414 2 zero_gravi
 
415
 
416
  -- Clock Generator ------------------------------------------------------------------------
417
  -- -------------------------------------------------------------------------------------------
418
  clock_generator: process(sys_rstn, clk_i)
419
  begin
420
    if (sys_rstn = '0') then
421 60 zero_gravi
      clk_gen_en <= (others => '-');
422 2 zero_gravi
      clk_div    <= (others => '0');
423 60 zero_gravi
      clk_div_ff <= (others => '-');
424
      clk_gen    <= (others => '-');
425 2 zero_gravi
    elsif rising_edge(clk_i) then
426 23 zero_gravi
      -- fresh clocks anyone? --
427 50 zero_gravi
      clk_gen_en(0) <= wdt_cg_en;
428
      clk_gen_en(1) <= uart0_cg_en;
429
      clk_gen_en(2) <= uart1_cg_en;
430
      clk_gen_en(3) <= spi_cg_en;
431
      clk_gen_en(4) <= twi_cg_en;
432
      clk_gen_en(5) <= pwm_cg_en;
433
      clk_gen_en(6) <= cfs_cg_en;
434 61 zero_gravi
      clk_gen_en(7) <= neoled_cg_en;
435 60 zero_gravi
      -- actual clock generator --
436
      if (or_reduce_f(clk_gen_en) = '1') then
437 23 zero_gravi
        clk_div <= std_ulogic_vector(unsigned(clk_div) + 1);
438 2 zero_gravi
      end if;
439 60 zero_gravi
      -- clock enables: rising edge detectors --
440 23 zero_gravi
      clk_div_ff <= clk_div;
441
      clk_gen(clk_div2_c)    <= clk_div(0)  and (not clk_div_ff(0));  -- CLK/2
442
      clk_gen(clk_div4_c)    <= clk_div(1)  and (not clk_div_ff(1));  -- CLK/4
443
      clk_gen(clk_div8_c)    <= clk_div(2)  and (not clk_div_ff(2));  -- CLK/8
444
      clk_gen(clk_div64_c)   <= clk_div(5)  and (not clk_div_ff(5));  -- CLK/64
445
      clk_gen(clk_div128_c)  <= clk_div(6)  and (not clk_div_ff(6));  -- CLK/128
446
      clk_gen(clk_div1024_c) <= clk_div(9)  and (not clk_div_ff(9));  -- CLK/1024
447
      clk_gen(clk_div2048_c) <= clk_div(10) and (not clk_div_ff(10)); -- CLK/2048
448
      clk_gen(clk_div4096_c) <= clk_div(11) and (not clk_div_ff(11)); -- CLK/4096
449
    end if;
450 60 zero_gravi
  end process clock_generator;
451 2 zero_gravi
 
452
 
453 45 zero_gravi
  -- CPU Core -------------------------------------------------------------------------------
454 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
455
  neorv32_cpu_inst: neorv32_cpu
456
  generic map (
457
    -- General --
458 41 zero_gravi
    HW_THREAD_ID                 => HW_THREAD_ID,        -- hardware thread id
459
    CPU_BOOT_ADDR                => cpu_boot_addr_c,     -- cpu boot address
460 59 zero_gravi
    CPU_DEBUG_ADDR               => dm_base_c,           -- cpu debug mode start address
461 2 zero_gravi
    -- RISC-V CPU Extensions --
462 39 zero_gravi
    CPU_EXTENSION_RISCV_A        => CPU_EXTENSION_RISCV_A,        -- implement atomic extension?
463 8 zero_gravi
    CPU_EXTENSION_RISCV_C        => CPU_EXTENSION_RISCV_C,        -- implement compressed extension?
464
    CPU_EXTENSION_RISCV_E        => CPU_EXTENSION_RISCV_E,        -- implement embedded RF extension?
465
    CPU_EXTENSION_RISCV_M        => CPU_EXTENSION_RISCV_M,        -- implement muld/div extension?
466 15 zero_gravi
    CPU_EXTENSION_RISCV_U        => CPU_EXTENSION_RISCV_U,        -- implement user mode extension?
467 63 zero_gravi
    CPU_EXTENSION_RISCV_Zbb      => CPU_EXTENSION_RISCV_Zbb,      -- implement basic bit-manipulation sub-extension?
468 55 zero_gravi
    CPU_EXTENSION_RISCV_Zfinx    => CPU_EXTENSION_RISCV_Zfinx,    -- implement 32-bit floating-point extension (using INT reg!)
469 8 zero_gravi
    CPU_EXTENSION_RISCV_Zicsr    => CPU_EXTENSION_RISCV_Zicsr,    -- implement CSR system?
470
    CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
471 61 zero_gravi
    CPU_EXTENSION_RISCV_Zmmul    => CPU_EXTENSION_RISCV_Zmmul,    -- implement multiply-only M sub-extension?
472 59 zero_gravi
    CPU_EXTENSION_RISCV_DEBUG    => ON_CHIP_DEBUGGER_EN,          -- implement CPU debug mode?
473 19 zero_gravi
    -- Extension Options --
474 41 zero_gravi
    FAST_MUL_EN                  => FAST_MUL_EN,         -- use DSPs for M extension's multiplier
475
    FAST_SHIFT_EN                => FAST_SHIFT_EN,       -- use barrel shifter for shift operations
476 56 zero_gravi
    CPU_CNT_WIDTH                => CPU_CNT_WIDTH,       -- total width of CPU cycle and instret counters (0..64)
477 62 zero_gravi
    CPU_IPB_ENTRIES              => CPU_IPB_ENTRIES,     -- entries is instruction prefetch buffer, has to be a power of 2
478 15 zero_gravi
    -- Physical Memory Protection (PMP) --
479 42 zero_gravi
    PMP_NUM_REGIONS              => PMP_NUM_REGIONS,     -- number of regions (0..64)
480
    PMP_MIN_GRANULARITY          => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
481
    -- Hardware Performance Monitors (HPM) --
482 56 zero_gravi
    HPM_NUM_CNTS                 => HPM_NUM_CNTS,        -- number of implemented HPM counters (0..29)
483 60 zero_gravi
    HPM_CNT_WIDTH                => HPM_CNT_WIDTH        -- total size of HPM counters (0..64)
484 2 zero_gravi
  )
485
  port map (
486
    -- global control --
487 12 zero_gravi
    clk_i          => clk_i,        -- global clock, rising edge
488
    rstn_i         => sys_rstn,     -- global reset, low-active, async
489 47 zero_gravi
    sleep_o        => cpu_sleep,    -- cpu is in sleep mode when set
490 12 zero_gravi
    -- instruction bus interface --
491
    i_bus_addr_o   => cpu_i.addr,   -- bus access address
492
    i_bus_rdata_i  => cpu_i.rdata,  -- bus read data
493
    i_bus_wdata_o  => cpu_i.wdata,  -- bus write data
494
    i_bus_ben_o    => cpu_i.ben,    -- byte enable
495
    i_bus_we_o     => cpu_i.we,     -- write enable
496
    i_bus_re_o     => cpu_i.re,     -- read enable
497 57 zero_gravi
    i_bus_lock_o   => cpu_i.lock,   -- exclusive access request
498 12 zero_gravi
    i_bus_ack_i    => cpu_i.ack,    -- bus transfer acknowledge
499
    i_bus_err_i    => cpu_i.err,    -- bus transfer error
500
    i_bus_fence_o  => cpu_i.fence,  -- executed FENCEI operation
501 35 zero_gravi
    i_bus_priv_o   => cpu_i.priv,   -- privilege level
502 12 zero_gravi
    -- data bus interface --
503
    d_bus_addr_o   => cpu_d.addr,   -- bus access address
504
    d_bus_rdata_i  => cpu_d.rdata,  -- bus read data
505
    d_bus_wdata_o  => cpu_d.wdata,  -- bus write data
506
    d_bus_ben_o    => cpu_d.ben,    -- byte enable
507
    d_bus_we_o     => cpu_d.we,     -- write enable
508
    d_bus_re_o     => cpu_d.re,     -- read enable
509 57 zero_gravi
    d_bus_lock_o   => cpu_d.lock,   -- exclusive access request
510 12 zero_gravi
    d_bus_ack_i    => cpu_d.ack,    -- bus transfer acknowledge
511
    d_bus_err_i    => cpu_d.err,    -- bus transfer error
512
    d_bus_fence_o  => cpu_d.fence,  -- executed FENCE operation
513 35 zero_gravi
    d_bus_priv_o   => cpu_d.priv,   -- privilege level
514 11 zero_gravi
    -- system time input from MTIME --
515 12 zero_gravi
    time_i         => mtime_time,   -- current system time
516 58 zero_gravi
    -- non-maskable interrupt --
517 62 zero_gravi
    nm_irq_i       => x_nm_irq,     -- NMI
518
    msw_irq_i      => x_msw_irq,    -- machine software interrupt
519
    mext_irq_i     => x_mext_irq,   -- machine external interrupt request
520 14 zero_gravi
    mtime_irq_i    => mtime_irq,    -- machine timer interrupt
521
    -- fast interrupts (custom) --
522 47 zero_gravi
    firq_i         => fast_irq,     -- fast interrupt trigger
523 59 zero_gravi
    -- debug mode (halt) request --
524
    db_halt_req_i  => dci_halt_req
525 2 zero_gravi
  );
526
 
527 36 zero_gravi
  -- misc --
528 57 zero_gravi
  cpu_i.src <= '1'; -- initialized but unused
529
  cpu_d.src <= '0'; -- initialized but unused
530 36 zero_gravi
 
531 14 zero_gravi
  -- advanced memory control --
532
  fence_o  <= cpu_d.fence; -- indicates an executed FENCE operation
533
  fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
534 2 zero_gravi
 
535 62 zero_gravi
  -- external machine-level (CPU) interrupts --
536
  nm_irq_ff    <= nm_irq_i    when rising_edge(clk_i);
537
  mtime_irq_ff <= mtime_irq_i when rising_edge(clk_i);
538
  msw_irq_ff   <= msw_irq_i   when rising_edge(clk_i);
539
  mext_irq_ff  <= mext_irq_i  when rising_edge(clk_i);
540
  -- rising-edge detector --
541 63 zero_gravi
  x_nm_irq     <= nm_irq_i    and (not nm_irq_ff);
542
  x_mtime_irq  <= mtime_irq_i and (not mtime_irq_ff);
543
  x_msw_irq    <= msw_irq_i   and (not msw_irq_ff);
544
  x_mext_irq   <= mext_irq_i  and (not mext_irq_ff);
545 62 zero_gravi
 
546 61 zero_gravi
  -- fast interrupts --
547 50 zero_gravi
  fast_irq(00) <= wdt_irq;       -- HIGHEST PRIORITY - watchdog timeout
548
  fast_irq(01) <= cfs_irq;       -- custom functions subsystem
549
  fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) data received
550
  fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) sending done
551
  fast_irq(04) <= uart1_rxd_irq; -- secondary UART (UART1) data received
552
  fast_irq(05) <= uart1_txd_irq; -- secondary UART (UART1) sending done
553
  fast_irq(06) <= spi_irq;       -- SPI transmission done
554
  fast_irq(07) <= twi_irq;       -- TWI transmission done
555 61 zero_gravi
  fast_irq(08) <= xirq_irq;      -- external interrupt controller
556 52 zero_gravi
  fast_irq(09) <= neoled_irq;    -- NEOLED buffer free
557 61 zero_gravi
  fast_irq(10) <= slink_rx_irq;  -- SLINK data received
558
  fast_irq(11) <= slink_tx_irq;  -- SLINK data send
559
  --
560 62 zero_gravi
  fast_irq(12) <= '0'; -- reserved
561
  fast_irq(13) <= '0'; -- reserved
562
  fast_irq(14) <= '0'; -- reserved
563
  fast_irq(15) <= '0'; -- reserved
564 14 zero_gravi
 
565
 
566 41 zero_gravi
  -- CPU Instruction Cache ------------------------------------------------------------------
567
  -- -------------------------------------------------------------------------------------------
568
  neorv32_icache_inst_true:
569 44 zero_gravi
  if (ICACHE_EN = true) generate
570 45 zero_gravi
    neorv32_icache_inst: neorv32_icache
571 41 zero_gravi
    generic map (
572 47 zero_gravi
      ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS,   -- number of blocks (min 2), has to be a power of 2
573
      ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE,   -- block size in bytes (min 4), has to be a power of 2
574
      ICACHE_NUM_SETS   => ICACHE_ASSOCIATIVITY -- associativity / number of sets (1=direct_mapped), has to be a power of 2
575 41 zero_gravi
    )
576
    port map (
577
      -- global control --
578
      clk_i         => clk_i,          -- global clock, rising edge
579
      rstn_i        => sys_rstn,       -- global reset, low-active, async
580
      clear_i       => cpu_i.fence,    -- cache clear
581
      -- host controller interface --
582
      host_addr_i   => cpu_i.addr,     -- bus access address
583
      host_rdata_o  => cpu_i.rdata,    -- bus read data
584
      host_wdata_i  => cpu_i.wdata,    -- bus write data
585
      host_ben_i    => cpu_i.ben,      -- byte enable
586
      host_we_i     => cpu_i.we,       -- write enable
587
      host_re_i     => cpu_i.re,       -- read enable
588
      host_ack_o    => cpu_i.ack,      -- bus transfer acknowledge
589
      host_err_o    => cpu_i.err,      -- bus transfer error
590
      -- peripheral bus interface --
591
      bus_addr_o    => i_cache.addr,   -- bus access address
592
      bus_rdata_i   => i_cache.rdata,  -- bus read data
593
      bus_wdata_o   => i_cache.wdata,  -- bus write data
594
      bus_ben_o     => i_cache.ben,    -- byte enable
595
      bus_we_o      => i_cache.we,     -- write enable
596
      bus_re_o      => i_cache.re,     -- read enable
597
      bus_ack_i     => i_cache.ack,    -- bus transfer acknowledge
598
      bus_err_i     => i_cache.err     -- bus transfer error
599
    );
600
  end generate;
601
 
602 57 zero_gravi
  -- TODO: do not use LOCKED instruction fetch --
603
  i_cache.lock <= '0';
604
 
605 41 zero_gravi
  neorv32_icache_inst_false:
606 44 zero_gravi
  if (ICACHE_EN = false) generate
607 57 zero_gravi
    i_cache.addr  <= cpu_i.addr;
608
    cpu_i.rdata   <= i_cache.rdata;
609
    i_cache.wdata <= cpu_i.wdata;
610
    i_cache.ben   <= cpu_i.ben;
611
    i_cache.we    <= cpu_i.we;
612
    i_cache.re    <= cpu_i.re;
613
    cpu_i.ack     <= i_cache.ack;
614
    cpu_i.err     <= i_cache.err;
615 41 zero_gravi
  end generate;
616
 
617
 
618 45 zero_gravi
  -- CPU Bus Switch -------------------------------------------------------------------------
619 12 zero_gravi
  -- -------------------------------------------------------------------------------------------
620
  neorv32_busswitch_inst: neorv32_busswitch
621
  generic map (
622
    PORT_CA_READ_ONLY => false, -- set if controller port A is read-only
623
    PORT_CB_READ_ONLY => true   -- set if controller port B is read-only
624
  )
625
  port map (
626
    -- global control --
627 41 zero_gravi
    clk_i           => clk_i,          -- global clock, rising edge
628
    rstn_i          => sys_rstn,       -- global reset, low-active, async
629 12 zero_gravi
    -- controller interface a --
630 41 zero_gravi
    ca_bus_addr_i   => cpu_d.addr,     -- bus access address
631
    ca_bus_rdata_o  => cpu_d.rdata,    -- bus read data
632
    ca_bus_wdata_i  => cpu_d.wdata,    -- bus write data
633
    ca_bus_ben_i    => cpu_d.ben,      -- byte enable
634
    ca_bus_we_i     => cpu_d.we,       -- write enable
635
    ca_bus_re_i     => cpu_d.re,       -- read enable
636 57 zero_gravi
    ca_bus_lock_i   => cpu_d.lock,     -- exclusive access request
637 41 zero_gravi
    ca_bus_ack_o    => cpu_d.ack,      -- bus transfer acknowledge
638
    ca_bus_err_o    => cpu_d.err,      -- bus transfer error
639 12 zero_gravi
    -- controller interface b --
640 41 zero_gravi
    cb_bus_addr_i   => i_cache.addr,   -- bus access address
641
    cb_bus_rdata_o  => i_cache.rdata,  -- bus read data
642
    cb_bus_wdata_i  => i_cache.wdata,  -- bus write data
643
    cb_bus_ben_i    => i_cache.ben,    -- byte enable
644
    cb_bus_we_i     => i_cache.we,     -- write enable
645
    cb_bus_re_i     => i_cache.re,     -- read enable
646 57 zero_gravi
    cb_bus_lock_i   => i_cache.lock,   -- exclusive access request
647 41 zero_gravi
    cb_bus_ack_o    => i_cache.ack,    -- bus transfer acknowledge
648
    cb_bus_err_o    => i_cache.err,    -- bus transfer error
649 12 zero_gravi
    -- peripheral bus --
650 41 zero_gravi
    p_bus_src_o     => p_bus.src,      -- access source: 0 = A (data), 1 = B (instructions)
651
    p_bus_addr_o    => p_bus.addr,     -- bus access address
652
    p_bus_rdata_i   => p_bus.rdata,    -- bus read data
653
    p_bus_wdata_o   => p_bus.wdata,    -- bus write data
654
    p_bus_ben_o     => p_bus.ben,      -- byte enable
655
    p_bus_we_o      => p_bus.we,       -- write enable
656
    p_bus_re_o      => p_bus.re,       -- read enable
657 57 zero_gravi
    p_bus_lock_o    => p_bus.lock,     -- exclusive access request
658 41 zero_gravi
    p_bus_ack_i     => p_bus.ack,      -- bus transfer acknowledge
659
    p_bus_err_i     => p_bus.err       -- bus transfer error
660 12 zero_gravi
  );
661 2 zero_gravi
 
662 60 zero_gravi
  -- current CPU privilege level --
663
  p_bus.priv <= cpu_i.priv; -- note: cpu_i.priv == cpu_d.priv
664 53 zero_gravi
 
665 60 zero_gravi
  -- fence operation (unused) --
666
  p_bus.fence <= cpu_d.fence or cpu_i.fence;
667 2 zero_gravi
 
668 60 zero_gravi
  -- bus response --
669
  bus_response: process(resp_bus, bus_keeper_err)
670
    variable rdata_v : std_ulogic_vector(data_width_c-1 downto 0);
671
    variable ack_v   : std_ulogic;
672
    variable err_v   : std_ulogic;
673
  begin
674
    rdata_v := (others => '0');
675
    ack_v   := '0';
676
    err_v   := '0';
677
    for i in resp_bus'range loop
678
      rdata_v := rdata_v or resp_bus(i).rdata; -- read data
679
      ack_v   := ack_v   or resp_bus(i).ack;   -- acknowledge
680
      err_v   := err_v   or resp_bus(i).err;   -- error
681
    end loop; -- i
682
    p_bus.rdata <= rdata_v; -- processor bus: CPU transfer data input
683
    p_bus.ack   <= ack_v;   -- processor bus: CPU transfer ACK input
684
    p_bus.err   <= err_v or bus_keeper_err; -- processor bus: CPU transfer data bus error input
685
  end process;
686 12 zero_gravi
 
687
 
688 59 zero_gravi
  -- Processor-Internal Bus Keeper (BUS_KEEPER) ---------------------------------------------
689 57 zero_gravi
  -- -------------------------------------------------------------------------------------------
690
  neorv32_bus_keeper_inst: neorv32_bus_keeper
691
  generic map (
692 59 zero_gravi
    -- External memory interface --
693
    MEM_EXT_EN        => MEM_EXT_EN,        -- implement external memory bus interface?
694 57 zero_gravi
    -- Internal instruction memory --
695
    MEM_INT_IMEM_EN   => MEM_INT_IMEM_EN,   -- implement processor-internal instruction memory
696
    MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
697
    -- Internal data memory --
698
    MEM_INT_DMEM_EN   => MEM_INT_DMEM_EN,   -- implement processor-internal data memory
699
    MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE  -- size of processor-internal data memory in bytes
700
  )
701
  port map (
702
    -- host access --
703
    clk_i  => clk_i,         -- global clock line
704
    rstn_i => sys_rstn,      -- global reset line, low-active
705
    addr_i => p_bus.addr,    -- address
706
    rden_i => p_bus.re,      -- read enable
707
    wren_i => p_bus.we,      -- write enable
708
    ack_i  => p_bus.ack,     -- transfer acknowledge from bus system
709
    err_i  => p_bus.err,     -- transfer error from bus system
710
    err_o  => bus_keeper_err -- bus error
711
  );
712 36 zero_gravi
 
713 57 zero_gravi
 
714 2 zero_gravi
  -- Processor-Internal Instruction Memory (IMEM) -------------------------------------------
715
  -- -------------------------------------------------------------------------------------------
716
  neorv32_int_imem_inst_true:
717 44 zero_gravi
  if (MEM_INT_IMEM_EN = true) generate
718 2 zero_gravi
    neorv32_int_imem_inst: neorv32_imem
719
    generic map (
720 61 zero_gravi
      IMEM_BASE    => imem_base_c,          -- memory base address
721
      IMEM_SIZE    => MEM_INT_IMEM_SIZE,    -- processor-internal instruction memory size in bytes
722
      IMEM_AS_IROM => not INT_BOOTLOADER_EN -- implement IMEM as pre-initialized read-only memory?
723 2 zero_gravi
    )
724
    port map (
725 60 zero_gravi
      clk_i  => clk_i,                     -- global clock line
726
      rden_i => p_bus.re,                  -- read enable
727
      wren_i => p_bus.we,                  -- write enable
728
      ben_i  => p_bus.ben,                 -- byte write enable
729
      addr_i => p_bus.addr,                -- address
730
      data_i => p_bus.wdata,               -- data in
731
      data_o => resp_bus(RESP_IMEM).rdata, -- data out
732
      ack_o  => resp_bus(RESP_IMEM).ack    -- transfer acknowledge
733 2 zero_gravi
    );
734 60 zero_gravi
    resp_bus(RESP_IMEM).err <= '0'; -- no access error possible
735 2 zero_gravi
  end generate;
736
 
737
  neorv32_int_imem_inst_false:
738 44 zero_gravi
  if (MEM_INT_IMEM_EN = false) generate
739 60 zero_gravi
    resp_bus(RESP_IMEM) <= resp_bus_entry_terminate_c;
740 2 zero_gravi
  end generate;
741
 
742
 
743
  -- Processor-Internal Data Memory (DMEM) --------------------------------------------------
744
  -- -------------------------------------------------------------------------------------------
745
  neorv32_int_dmem_inst_true:
746 44 zero_gravi
  if (MEM_INT_DMEM_EN = true) generate
747 2 zero_gravi
    neorv32_int_dmem_inst: neorv32_dmem
748
    generic map (
749 23 zero_gravi
      DMEM_BASE => dmem_base_c,      -- memory base address
750 2 zero_gravi
      DMEM_SIZE => MEM_INT_DMEM_SIZE -- processor-internal data memory size in bytes
751
    )
752
    port map (
753 60 zero_gravi
      clk_i  => clk_i,                     -- global clock line
754
      rden_i => p_bus.re,                  -- read enable
755
      wren_i => p_bus.we,                  -- write enable
756
      ben_i  => p_bus.ben,                 -- byte write enable
757
      addr_i => p_bus.addr,                -- address
758
      data_i => p_bus.wdata,               -- data in
759
      data_o => resp_bus(RESP_DMEM).rdata, -- data out
760
      ack_o  => resp_bus(RESP_DMEM).ack    -- transfer acknowledge
761 2 zero_gravi
    );
762 60 zero_gravi
    resp_bus(RESP_DMEM).err <= '0'; -- no access error possible
763 2 zero_gravi
  end generate;
764
 
765
  neorv32_int_dmem_inst_false:
766 44 zero_gravi
  if (MEM_INT_DMEM_EN = false) generate
767 60 zero_gravi
    resp_bus(RESP_DMEM) <= resp_bus_entry_terminate_c;
768 2 zero_gravi
  end generate;
769
 
770
 
771
  -- Processor-Internal Bootloader ROM (BOOTROM) --------------------------------------------
772
  -- -------------------------------------------------------------------------------------------
773
  neorv32_boot_rom_inst_true:
774 61 zero_gravi
  if (INT_BOOTLOADER_EN = true) generate
775 2 zero_gravi
    neorv32_boot_rom_inst: neorv32_boot_rom
776 23 zero_gravi
    generic map (
777 61 zero_gravi
      BOOTROM_BASE => boot_rom_base_c -- boot ROM base address
778 23 zero_gravi
    )
779 2 zero_gravi
    port map (
780 60 zero_gravi
      clk_i  => clk_i,                        -- global clock line
781
      rden_i => p_bus.re,                     -- read enable
782
      addr_i => p_bus.addr,                   -- address
783
      data_o => resp_bus(RESP_BOOTROM).rdata, -- data out
784
      ack_o  => resp_bus(RESP_BOOTROM).ack    -- transfer acknowledge
785 2 zero_gravi
    );
786 60 zero_gravi
    resp_bus(RESP_BOOTROM).err <= '0'; -- no access error possible
787 2 zero_gravi
  end generate;
788
 
789
  neorv32_boot_rom_inst_false:
790 61 zero_gravi
  if (INT_BOOTLOADER_EN = false) generate
791 60 zero_gravi
    resp_bus(RESP_BOOTROM) <= resp_bus_entry_terminate_c;
792 2 zero_gravi
  end generate;
793
 
794
 
795
  -- External Wishbone Gateway (WISHBONE) ---------------------------------------------------
796
  -- -------------------------------------------------------------------------------------------
797
  neorv32_wishbone_inst_true:
798 44 zero_gravi
  if (MEM_EXT_EN = true) generate
799 2 zero_gravi
    neorv32_wishbone_inst: neorv32_wishbone
800
    generic map (
801 23 zero_gravi
      -- Internal instruction memory --
802 62 zero_gravi
      MEM_INT_IMEM_EN   => MEM_INT_IMEM_EN,    -- implement processor-internal instruction memory
803
      MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE,  -- size of processor-internal instruction memory in bytes
804 23 zero_gravi
      -- Internal data memory --
805 62 zero_gravi
      MEM_INT_DMEM_EN   => MEM_INT_DMEM_EN,    -- implement processor-internal data memory
806
      MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE,  -- size of processor-internal data memory in bytes
807
      -- Interface Configuration --
808
      BUS_TIMEOUT       => MEM_EXT_TIMEOUT,    -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
809
      PIPE_MODE         => MEM_EXT_PIPE_MODE,  -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
810
      BIG_ENDIAN        => MEM_EXT_BIG_ENDIAN, -- byte order: true=big-endian, false=little-endian
811
      ASYNC_RX          => MEM_EXT_ASYNC_RX    -- use register buffer for RX data when false
812 2 zero_gravi
    )
813
    port map (
814
      -- global control --
815 60 zero_gravi
      clk_i     => clk_i,                         -- global clock line
816
      rstn_i    => sys_rstn,                      -- global reset line, low-active
817 2 zero_gravi
      -- host access --
818 60 zero_gravi
      src_i     => p_bus.src,                     -- access type (0: data, 1:instruction)
819
      addr_i    => p_bus.addr,                    -- address
820
      rden_i    => p_bus.re,                      -- read enable
821
      wren_i    => p_bus.we,                      -- write enable
822
      ben_i     => p_bus.ben,                     -- byte write enable
823
      data_i    => p_bus.wdata,                   -- data in
824
      data_o    => resp_bus(RESP_WISHBONE).rdata, -- data out
825
      lock_i    => p_bus.lock,                    -- exclusive access request
826
      ack_o     => resp_bus(RESP_WISHBONE).ack,   -- transfer acknowledge
827
      err_o     => resp_bus(RESP_WISHBONE).err,   -- transfer error
828
      priv_i    => p_bus.priv,                    -- current CPU privilege level
829 2 zero_gravi
      -- wishbone interface --
830 60 zero_gravi
      wb_tag_o  => wb_tag_o,                      -- request tag
831
      wb_adr_o  => wb_adr_o,                      -- address
832
      wb_dat_i  => wb_dat_i,                      -- read data
833
      wb_dat_o  => wb_dat_o,                      -- write data
834
      wb_we_o   => wb_we_o,                       -- read/write
835
      wb_sel_o  => wb_sel_o,                      -- byte enable
836
      wb_stb_o  => wb_stb_o,                      -- strobe
837
      wb_cyc_o  => wb_cyc_o,                      -- valid cycle
838
      wb_lock_o => wb_lock_o,                     -- exclusive access request
839
      wb_ack_i  => wb_ack_i,                      -- transfer acknowledge
840
      wb_err_i  => wb_err_i                       -- transfer error
841 2 zero_gravi
    );
842
  end generate;
843
 
844
  neorv32_wishbone_inst_false:
845 44 zero_gravi
  if (MEM_EXT_EN = false) generate
846 60 zero_gravi
    resp_bus(RESP_WISHBONE) <= resp_bus_entry_terminate_c;
847 2 zero_gravi
    --
848 60 zero_gravi
    wb_adr_o  <= (others => '0');
849
    wb_dat_o  <= (others => '0');
850
    wb_we_o   <= '0';
851
    wb_sel_o  <= (others => '0');
852
    wb_stb_o  <= '0';
853
    wb_cyc_o  <= '0';
854
    wb_lock_o <= '0';
855
    wb_tag_o  <= (others => '0');
856 2 zero_gravi
  end generate;
857
 
858
 
859
  -- IO Access? -----------------------------------------------------------------------------
860
  -- -------------------------------------------------------------------------------------------
861 12 zero_gravi
  io_acc  <= '1' when (p_bus.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0';
862 40 zero_gravi
  io_rden <= io_acc and p_bus.re and (not p_bus.src); -- PMA: no_execute for IO region
863 47 zero_gravi
  -- the default NEORV32 peripheral/IO devices in the IO area can only be written in word mode (reduces HW complexity)
864 60 zero_gravi
  io_wren <= io_acc and p_bus.we and and_reduce_f(p_bus.ben) and (not p_bus.src); -- PMA: write32 only, no_execute for IO region
865 2 zero_gravi
 
866
 
867 47 zero_gravi
  -- Custom Functions Subsystem (CFS) -------------------------------------------------------
868
  -- -------------------------------------------------------------------------------------------
869
  neorv32_cfs_inst_true:
870
  if (IO_CFS_EN = true) generate
871
    neorv32_cfs_inst: neorv32_cfs
872
    generic map (
873 61 zero_gravi
      CFS_CONFIG   => IO_CFS_CONFIG,  -- custom CFS configuration generic
874 52 zero_gravi
      CFS_IN_SIZE  => IO_CFS_IN_SIZE, -- size of CFS input conduit in bits
875
      CFS_OUT_SIZE => IO_CFS_OUT_SIZE -- size of CFS output conduit in bits
876 47 zero_gravi
    )
877
    port map (
878
      -- host access --
879 60 zero_gravi
      clk_i       => clk_i,                    -- global clock line
880
      rstn_i      => sys_rstn,                 -- global reset line, low-active, use as async
881
      addr_i      => p_bus.addr,               -- address
882
      rden_i      => io_rden,                  -- read enable
883
      wren_i      => io_wren,                  -- byte write enable
884
      data_i      => p_bus.wdata,              -- data in
885
      data_o      => resp_bus(RESP_CFS).rdata, -- data out
886
      ack_o       => resp_bus(RESP_CFS).ack,   -- transfer acknowledge
887 47 zero_gravi
      -- clock generator --
888 60 zero_gravi
      clkgen_en_o => cfs_cg_en,                -- enable clock generator
889
      clkgen_i    => clk_gen,                  -- "clock" inputs
890 47 zero_gravi
      -- CPU state --
891 60 zero_gravi
      sleep_i     => cpu_sleep,                -- set if cpu is in sleep mode
892 47 zero_gravi
      -- interrupt --
893 60 zero_gravi
      irq_o       => cfs_irq,                  -- interrupt request
894 47 zero_gravi
      -- custom io (conduit) --
895 60 zero_gravi
      cfs_in_i    => cfs_in_i,                 -- custom inputs
896
      cfs_out_o   => cfs_out_o                 -- custom outputs
897 47 zero_gravi
    );
898 60 zero_gravi
    resp_bus(RESP_CFS).err <= '0'; -- no access error possible
899 47 zero_gravi
  end generate;
900
 
901
  neorv32_cfs_inst_false:
902
  if (IO_CFS_EN = false) generate
903 60 zero_gravi
    resp_bus(RESP_CFS) <= resp_bus_entry_terminate_c;
904 47 zero_gravi
    cfs_cg_en <= '0';
905
    cfs_irq   <= '0';
906
    cfs_out_o <= (others => '0');
907
  end generate;
908
 
909
 
910 2 zero_gravi
  -- General Purpose Input/Output Port (GPIO) -----------------------------------------------
911
  -- -------------------------------------------------------------------------------------------
912
  neorv32_gpio_inst_true:
913 44 zero_gravi
  if (IO_GPIO_EN = true) generate
914 2 zero_gravi
    neorv32_gpio_inst: neorv32_gpio
915
    port map (
916
      -- host access --
917 60 zero_gravi
      clk_i  => clk_i,                     -- global clock line
918
      addr_i => p_bus.addr,                -- address
919
      rden_i => io_rden,                   -- read enable
920
      wren_i => io_wren,                   -- write enable
921
      data_i => p_bus.wdata,               -- data in
922
      data_o => resp_bus(RESP_GPIO).rdata, -- data out
923
      ack_o  => resp_bus(RESP_GPIO).ack,   -- transfer acknowledge
924 2 zero_gravi
      -- parallel io --
925
      gpio_o => gpio_o,
926 61 zero_gravi
      gpio_i => gpio_i
927 2 zero_gravi
    );
928 60 zero_gravi
    resp_bus(RESP_GPIO).err <= '0'; -- no access error possible
929 2 zero_gravi
  end generate;
930
 
931
  neorv32_gpio_inst_false:
932 44 zero_gravi
  if (IO_GPIO_EN = false) generate
933 60 zero_gravi
    resp_bus(RESP_GPIO) <= resp_bus_entry_terminate_c;
934 61 zero_gravi
    gpio_o <= (others => '0');
935 2 zero_gravi
  end generate;
936
 
937
 
938
  -- Watch Dog Timer (WDT) ------------------------------------------------------------------
939
  -- -------------------------------------------------------------------------------------------
940
  neorv32_wdt_inst_true:
941 44 zero_gravi
  if (IO_WDT_EN = true) generate
942 2 zero_gravi
    neorv32_wdt_inst: neorv32_wdt
943
    port map (
944
      -- host access --
945 60 zero_gravi
      clk_i       => clk_i,                    -- global clock line
946
      rstn_i      => ext_rstn,                 -- global reset line, low-active
947
      rden_i      => io_rden,                  -- read enable
948
      wren_i      => io_wren,                  -- write enable
949
      addr_i      => p_bus.addr,               -- address
950
      data_i      => p_bus.wdata,              -- data in
951
      data_o      => resp_bus(RESP_WDT).rdata, -- data out
952
      ack_o       => resp_bus(RESP_WDT).ack,   -- transfer acknowledge
953 2 zero_gravi
      -- clock generator --
954 60 zero_gravi
      clkgen_en_o => wdt_cg_en,                -- enable clock generator
955 2 zero_gravi
      clkgen_i    => clk_gen,
956
      -- timeout event --
957 60 zero_gravi
      irq_o       => wdt_irq,                  -- timeout IRQ
958
      rstn_o      => wdt_rstn                  -- timeout reset, low_active, use it as async!
959 2 zero_gravi
    );
960 60 zero_gravi
    resp_bus(RESP_WDT).err <= '0'; -- no access error possible
961 2 zero_gravi
  end generate;
962
 
963
  neorv32_wdt_inst_false:
964 44 zero_gravi
  if (IO_WDT_EN = false) generate
965 60 zero_gravi
    resp_bus(RESP_WDT) <= resp_bus_entry_terminate_c;
966 2 zero_gravi
    wdt_irq   <= '0';
967
    wdt_rstn  <= '1';
968
    wdt_cg_en <= '0';
969
  end generate;
970
 
971
 
972
  -- Machine System Timer (MTIME) -----------------------------------------------------------
973
  -- -------------------------------------------------------------------------------------------
974
  neorv32_mtime_inst_true:
975 44 zero_gravi
  if (IO_MTIME_EN = true) generate
976 2 zero_gravi
    neorv32_mtime_inst: neorv32_mtime
977
    port map (
978
      -- host access --
979 60 zero_gravi
      clk_i  => clk_i,                      -- global clock line
980
      addr_i => p_bus.addr,                 -- address
981
      rden_i => io_rden,                    -- read enable
982
      wren_i => io_wren,                    -- write enable
983
      data_i => p_bus.wdata,                -- data in
984
      data_o => resp_bus(RESP_MTIME).rdata, -- data out
985
      ack_o  => resp_bus(RESP_MTIME).ack,   -- transfer acknowledge
986 11 zero_gravi
      -- time output for CPU --
987 60 zero_gravi
      time_o => mtime_time,                 -- current system time
988 2 zero_gravi
      -- interrupt --
989 60 zero_gravi
      irq_o  => mtime_irq                   -- interrupt request
990 2 zero_gravi
    );
991 60 zero_gravi
    resp_bus(RESP_MTIME).err <= '0'; -- no access error possible
992 2 zero_gravi
  end generate;
993
 
994
  neorv32_mtime_inst_false:
995 44 zero_gravi
  if (IO_MTIME_EN = false) generate
996 60 zero_gravi
    resp_bus(RESP_MTIME) <= resp_bus_entry_terminate_c;
997
    mtime_time <= mtime_i; -- use external machine timer time signal
998 62 zero_gravi
    mtime_irq  <= x_mtime_irq; -- use external machine timer interrupt
999 2 zero_gravi
  end generate;
1000
 
1001
 
1002 60 zero_gravi
  -- system time output LO --
1003
  mtime_sync: process(clk_i)
1004
  begin
1005
    if rising_edge(clk_i) then
1006
      -- buffer low word one clock cycle to compensate for MTIME's 1-cycle delay
1007
      -- when overflowing from low-word to high-word -> only relevant for processor-external devices
1008
      -- processor-internal devices (= the CPU) do not care about this delay offset as 64-bit MTIME.TIME
1009
      -- cannot be accessed within a single cycle
1010
      if (IO_MTIME_EN = true) then
1011
        mtime_o(31 downto 0) <= mtime_time(31 downto 0);
1012
      else
1013
        mtime_o(31 downto 0) <= (others => '0');
1014
      end if;
1015
    end if;
1016
  end process mtime_sync;
1017 59 zero_gravi
 
1018 60 zero_gravi
  -- system time output HI --
1019
  mtime_o(63 downto 32) <= mtime_time(63 downto 32) when (IO_MTIME_EN = true) else (others => '0');
1020
 
1021
 
1022 51 zero_gravi
  -- Primary Universal Asynchronous Receiver/Transmitter (UART0) ----------------------------
1023 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
1024 50 zero_gravi
  neorv32_uart0_inst_true:
1025
  if (IO_UART0_EN = true) generate
1026
    neorv32_uart0_inst: neorv32_uart
1027
    generic map (
1028
      UART_PRIMARY => true -- true = primary UART (UART0), false = secondary UART (UART1)
1029
    )
1030 2 zero_gravi
    port map (
1031
      -- host access --
1032 60 zero_gravi
      clk_i       => clk_i,                      -- global clock line
1033
      addr_i      => p_bus.addr,                 -- address
1034
      rden_i      => io_rden,                    -- read enable
1035
      wren_i      => io_wren,                    -- write enable
1036
      data_i      => p_bus.wdata,                -- data in
1037
      data_o      => resp_bus(RESP_UART0).rdata, -- data out
1038
      ack_o       => resp_bus(RESP_UART0).ack,   -- transfer acknowledge
1039 2 zero_gravi
      -- clock generator --
1040 60 zero_gravi
      clkgen_en_o => uart0_cg_en,                -- enable clock generator
1041 2 zero_gravi
      clkgen_i    => clk_gen,
1042
      -- com lines --
1043 50 zero_gravi
      uart_txd_o  => uart0_txd_o,
1044
      uart_rxd_i  => uart0_rxd_i,
1045 51 zero_gravi
      -- hardware flow control --
1046 60 zero_gravi
      uart_rts_o  => uart0_rts_o,                -- UART.RX ready to receive ("RTR"), low-active, optional
1047
      uart_cts_i  => uart0_cts_i,                -- UART.TX allowed to transmit, low-active, optional
1048 2 zero_gravi
      -- interrupts --
1049 60 zero_gravi
      irq_rxd_o   => uart0_rxd_irq,              -- uart data received interrupt
1050
      irq_txd_o   => uart0_txd_irq               -- uart transmission done interrupt
1051 2 zero_gravi
    );
1052 60 zero_gravi
    resp_bus(RESP_UART0).err <= '0'; -- no access error possible
1053 2 zero_gravi
  end generate;
1054
 
1055 50 zero_gravi
  neorv32_uart0_inst_false:
1056
  if (IO_UART0_EN = false) generate
1057 60 zero_gravi
    resp_bus(RESP_UART0) <= resp_bus_entry_terminate_c;
1058 50 zero_gravi
    uart0_txd_o   <= '0';
1059 51 zero_gravi
    uart0_rts_o   <= '0';
1060 50 zero_gravi
    uart0_cg_en   <= '0';
1061
    uart0_rxd_irq <= '0';
1062
    uart0_txd_irq <= '0';
1063 2 zero_gravi
  end generate;
1064
 
1065
 
1066 51 zero_gravi
  -- Secondary Universal Asynchronous Receiver/Transmitter (UART1) --------------------------
1067 50 zero_gravi
  -- -------------------------------------------------------------------------------------------
1068
  neorv32_uart1_inst_true:
1069
  if (IO_UART1_EN = true) generate
1070
    neorv32_uart1_inst: neorv32_uart
1071
    generic map (
1072
      UART_PRIMARY => false -- true = primary UART (UART0), false = secondary UART (UART1)
1073
    )
1074
    port map (
1075
      -- host access --
1076 60 zero_gravi
      clk_i       => clk_i,                      -- global clock line
1077
      addr_i      => p_bus.addr,                 -- address
1078
      rden_i      => io_rden,                    -- read enable
1079
      wren_i      => io_wren,                    -- write enable
1080
      data_i      => p_bus.wdata,                -- data in
1081
      data_o      => resp_bus(RESP_UART1).rdata, -- data out
1082
      ack_o       => resp_bus(RESP_UART1).ack,   -- transfer acknowledge
1083 50 zero_gravi
      -- clock generator --
1084 60 zero_gravi
      clkgen_en_o => uart1_cg_en,                -- enable clock generator
1085 50 zero_gravi
      clkgen_i    => clk_gen,
1086
      -- com lines --
1087
      uart_txd_o  => uart1_txd_o,
1088
      uart_rxd_i  => uart1_rxd_i,
1089 51 zero_gravi
      -- hardware flow control --
1090 60 zero_gravi
      uart_rts_o  => uart1_rts_o,                -- UART.RX ready to receive ("RTR"), low-active, optional
1091
      uart_cts_i  => uart1_cts_i,                -- UART.TX allowed to transmit, low-active, optional
1092 50 zero_gravi
      -- interrupts --
1093 60 zero_gravi
      irq_rxd_o   => uart1_rxd_irq,              -- uart data received interrupt
1094
      irq_txd_o   => uart1_txd_irq               -- uart transmission done interrupt
1095 50 zero_gravi
    );
1096 60 zero_gravi
    resp_bus(RESP_UART1).err <= '0'; -- no access error possible
1097 50 zero_gravi
  end generate;
1098
 
1099
  neorv32_uart1_inst_false:
1100
  if (IO_UART1_EN = false) generate
1101 60 zero_gravi
    resp_bus(RESP_UART1) <= resp_bus_entry_terminate_c;
1102 50 zero_gravi
    uart1_txd_o   <= '0';
1103 51 zero_gravi
    uart1_rts_o   <= '0';
1104 50 zero_gravi
    uart1_cg_en   <= '0';
1105
    uart1_rxd_irq <= '0';
1106
    uart1_txd_irq <= '0';
1107
  end generate;
1108
 
1109
 
1110 2 zero_gravi
  -- Serial Peripheral Interface (SPI) ------------------------------------------------------
1111
  -- -------------------------------------------------------------------------------------------
1112
  neorv32_spi_inst_true:
1113 44 zero_gravi
  if (IO_SPI_EN = true) generate
1114 2 zero_gravi
    neorv32_spi_inst: neorv32_spi
1115
    port map (
1116
      -- host access --
1117 60 zero_gravi
      clk_i       => clk_i,                    -- global clock line
1118
      addr_i      => p_bus.addr,               -- address
1119
      rden_i      => io_rden,                  -- read enable
1120
      wren_i      => io_wren,                  -- write enable
1121
      data_i      => p_bus.wdata,              -- data in
1122
      data_o      => resp_bus(RESP_SPI).rdata, -- data out
1123
      ack_o       => resp_bus(RESP_SPI).ack,   -- transfer acknowledge
1124 2 zero_gravi
      -- clock generator --
1125 60 zero_gravi
      clkgen_en_o => spi_cg_en,                -- enable clock generator
1126 2 zero_gravi
      clkgen_i    => clk_gen,
1127
      -- com lines --
1128 60 zero_gravi
      spi_sck_o   => spi_sck_o,                -- SPI serial clock
1129
      spi_sdo_o   => spi_sdo_o,                -- controller data out, peripheral data in
1130
      spi_sdi_i   => spi_sdi_i,                -- controller data in, peripheral data out
1131
      spi_csn_o   => spi_csn_o,                -- SPI CS
1132 2 zero_gravi
      -- interrupt --
1133 60 zero_gravi
      irq_o       => spi_irq                   -- transmission done interrupt
1134 2 zero_gravi
    );
1135 60 zero_gravi
    resp_bus(RESP_SPI).err <= '0'; -- no access error possible
1136 2 zero_gravi
  end generate;
1137
 
1138
  neorv32_spi_inst_false:
1139 44 zero_gravi
  if (IO_SPI_EN = false) generate
1140 60 zero_gravi
    resp_bus(RESP_SPI) <= resp_bus_entry_terminate_c;
1141
    spi_sck_o <= '0';
1142
    spi_sdo_o <= '0';
1143
    spi_csn_o <= (others => '1'); -- CSn lines are low-active
1144
    spi_cg_en <= '0';
1145
    spi_irq   <= '0';
1146 2 zero_gravi
  end generate;
1147
 
1148
 
1149
  -- Two-Wire Interface (TWI) ---------------------------------------------------------------
1150
  -- -------------------------------------------------------------------------------------------
1151
  neorv32_twi_inst_true:
1152 44 zero_gravi
  if (IO_TWI_EN = true) generate
1153 2 zero_gravi
    neorv32_twi_inst: neorv32_twi
1154
    port map (
1155
      -- host access --
1156 60 zero_gravi
      clk_i       => clk_i,                    -- global clock line
1157
      addr_i      => p_bus.addr,               -- address
1158
      rden_i      => io_rden,                  -- read enable
1159
      wren_i      => io_wren,                  -- write enable
1160
      data_i      => p_bus.wdata,              -- data in
1161
      data_o      => resp_bus(RESP_TWI).rdata, -- data out
1162
      ack_o       => resp_bus(RESP_TWI).ack,   -- transfer acknowledge
1163 2 zero_gravi
      -- clock generator --
1164 60 zero_gravi
      clkgen_en_o => twi_cg_en,                -- enable clock generator
1165 2 zero_gravi
      clkgen_i    => clk_gen,
1166
      -- com lines --
1167 60 zero_gravi
      twi_sda_io  => twi_sda_io,               -- serial data line
1168
      twi_scl_io  => twi_scl_io,               -- serial clock line
1169 2 zero_gravi
      -- interrupt --
1170 60 zero_gravi
      irq_o       => twi_irq                   -- transfer done IRQ
1171 2 zero_gravi
    );
1172 60 zero_gravi
    resp_bus(RESP_TWI).err <= '0'; -- no access error possible
1173 2 zero_gravi
  end generate;
1174
 
1175
  neorv32_twi_inst_false:
1176 44 zero_gravi
  if (IO_TWI_EN = false) generate
1177 60 zero_gravi
    resp_bus(RESP_TWI) <= resp_bus_entry_terminate_c;
1178 51 zero_gravi
--  twi_sda_io <= 'Z'; -- FIXME?
1179
--  twi_scl_io <= 'Z'; -- FIXME?
1180 2 zero_gravi
    twi_cg_en  <= '0';
1181
    twi_irq    <= '0';
1182
  end generate;
1183
 
1184
 
1185
  -- Pulse-Width Modulation Controller (PWM) ------------------------------------------------
1186
  -- -------------------------------------------------------------------------------------------
1187
  neorv32_pwm_inst_true:
1188 60 zero_gravi
  if (IO_PWM_NUM_CH > 0) generate
1189 2 zero_gravi
    neorv32_pwm_inst: neorv32_pwm
1190 60 zero_gravi
    generic map (
1191
      NUM_CHANNELS => IO_PWM_NUM_CH -- number of PWM channels (0..60)
1192
    )
1193 2 zero_gravi
    port map (
1194
      -- host access --
1195 60 zero_gravi
      clk_i       => clk_i,                    -- global clock line
1196
      addr_i      => p_bus.addr,               -- address
1197
      rden_i      => io_rden,                  -- read enable
1198
      wren_i      => io_wren,                  -- write enable
1199
      data_i      => p_bus.wdata,              -- data in
1200
      data_o      => resp_bus(RESP_PWM).rdata, -- data out
1201
      ack_o       => resp_bus(RESP_PWM).ack,   -- transfer acknowledge
1202 2 zero_gravi
      -- clock generator --
1203 60 zero_gravi
      clkgen_en_o => pwm_cg_en,                -- enable clock generator
1204 2 zero_gravi
      clkgen_i    => clk_gen,
1205
      -- pwm output channels --
1206
      pwm_o       => pwm_o
1207
    );
1208 60 zero_gravi
    resp_bus(RESP_PWM).err <= '0'; -- no access error possible
1209 2 zero_gravi
  end generate;
1210
 
1211
  neorv32_pwm_inst_false:
1212 60 zero_gravi
  if (IO_PWM_NUM_CH = 0) generate
1213
    resp_bus(RESP_PWM) <= resp_bus_entry_terminate_c;
1214 2 zero_gravi
    pwm_cg_en <= '0';
1215
    pwm_o     <= (others => '0');
1216
  end generate;
1217
 
1218
 
1219
  -- True Random Number Generator (TRNG) ----------------------------------------------------
1220
  -- -------------------------------------------------------------------------------------------
1221
  neorv32_trng_inst_true:
1222 44 zero_gravi
  if (IO_TRNG_EN = true) generate
1223 2 zero_gravi
    neorv32_trng_inst: neorv32_trng
1224
    port map (
1225
      -- host access --
1226 60 zero_gravi
      clk_i  => clk_i,                     -- global clock line
1227
      addr_i => p_bus.addr,                -- address
1228
      rden_i => io_rden,                   -- read enable
1229
      wren_i => io_wren,                   -- write enable
1230
      data_i => p_bus.wdata,               -- data in
1231
      data_o => resp_bus(RESP_TRNG).rdata, -- data out
1232
      ack_o  => resp_bus(RESP_TRNG).ack    -- transfer acknowledge
1233 2 zero_gravi
    );
1234 60 zero_gravi
    resp_bus(RESP_TRNG).err <= '0'; -- no access error possible
1235 2 zero_gravi
  end generate;
1236
 
1237
  neorv32_trng_inst_false:
1238 44 zero_gravi
  if (IO_TRNG_EN = false) generate
1239 60 zero_gravi
    resp_bus(RESP_TRNG) <= resp_bus_entry_terminate_c;
1240 2 zero_gravi
  end generate;
1241
 
1242
 
1243 52 zero_gravi
  -- Smart LED (WS2811/WS2812) Interface (NEOLED) -------------------------------------------
1244
  -- -------------------------------------------------------------------------------------------
1245
  neorv32_neoled_inst_true:
1246
  if (IO_NEOLED_EN = true) generate
1247
    neorv32_neoled_inst: neorv32_neoled
1248 62 zero_gravi
    generic map (
1249
      FIFO_DEPTH => IO_NEOLED_TX_FIFO -- TX FIFO depth (1..32k, power of two)
1250
    )
1251 52 zero_gravi
    port map (
1252
      -- host access --
1253 60 zero_gravi
      clk_i       => clk_i,                       -- global clock line
1254
      addr_i      => p_bus.addr,                  -- address
1255
      rden_i      => io_rden,                     -- read enable
1256
      wren_i      => io_wren,                     -- write enable
1257
      data_i      => p_bus.wdata,                 -- data in
1258
      data_o      => resp_bus(RESP_NEOLED).rdata, -- data out
1259
      ack_o       => resp_bus(RESP_NEOLED).ack,   -- transfer acknowledge
1260 52 zero_gravi
      -- clock generator --
1261 60 zero_gravi
      clkgen_en_o => neoled_cg_en,                -- enable clock generator
1262 52 zero_gravi
      clkgen_i    => clk_gen,
1263
      -- interrupt --
1264 60 zero_gravi
      irq_o       => neoled_irq,                  -- interrupt request
1265 52 zero_gravi
      -- NEOLED output --
1266 60 zero_gravi
      neoled_o    => neoled_o                     -- serial async data line
1267 52 zero_gravi
    );
1268 60 zero_gravi
    resp_bus(RESP_NEOLED).err <= '0'; -- no access error possible
1269 52 zero_gravi
  end generate;
1270
 
1271
  neorv32_neoled_inst_false:
1272
  if (IO_NEOLED_EN = false) generate
1273 60 zero_gravi
    resp_bus(RESP_NEOLED) <= resp_bus_entry_terminate_c;
1274 52 zero_gravi
    neoled_cg_en <= '0';
1275
    neoled_irq   <= '0';
1276
    neoled_o     <= '0';
1277
  end generate;
1278
 
1279
 
1280 61 zero_gravi
  -- Stream Link Interface (SLINK) ----------------------------------------------------------
1281
  -- -------------------------------------------------------------------------------------------
1282
  neorv32_slink_inst_true:
1283
  if (io_slink_en_c = true) generate
1284
    neorv32_slink_inst: neorv32_slink
1285
    generic map (
1286
      SLINK_NUM_TX  => SLINK_NUM_TX,  -- number of TX links (0..8)
1287
      SLINK_NUM_RX  => SLINK_NUM_RX,  -- number of TX links (0..8)
1288
      SLINK_TX_FIFO => SLINK_TX_FIFO, -- TX fifo depth, has to be a power of two
1289
      SLINK_RX_FIFO => SLINK_RX_FIFO  -- RX fifo depth, has to be a power of two
1290
    )
1291
    port map (
1292
      -- host access --
1293
      clk_i          => clk_i,                      -- global clock line
1294
      addr_i         => p_bus.addr,                 -- address
1295
      rden_i         => io_rden,                    -- read enable
1296
      wren_i         => io_wren,                    -- write enable
1297
      data_i         => p_bus.wdata,                -- data in
1298
      data_o         => resp_bus(RESP_SLINK).rdata, -- data out
1299
      ack_o          => resp_bus(RESP_SLINK).ack,   -- transfer acknowledge
1300
      -- interrupt --
1301
      irq_tx_o       => slink_tx_irq,               -- transmission done
1302
      irq_rx_o       => slink_rx_irq,               -- data received
1303
      -- TX stream interfaces --
1304
      slink_tx_dat_o => slink_tx_dat_o,             -- output data
1305
      slink_tx_val_o => slink_tx_val_o,             -- valid output
1306
      slink_tx_rdy_i => slink_tx_rdy_i,             -- ready to send
1307
      -- RX stream interfaces --
1308
      slink_rx_dat_i => slink_rx_dat_i,             -- input data
1309
      slink_rx_val_i => slink_rx_val_i,             -- valid input
1310
      slink_rx_rdy_o => slink_rx_rdy_o              -- ready to receive
1311
    );
1312
    resp_bus(RESP_SLINK).err <= '0'; -- no access error possible
1313
  end generate;
1314
 
1315
  neorv32_slink_inst_false:
1316
  if (io_slink_en_c = false) generate
1317
    resp_bus(RESP_SLINK) <= resp_bus_entry_terminate_c;
1318
    slink_tx_irq   <= '0';
1319
    slink_rx_irq   <= '0';
1320
    slink_tx_dat_o <= (others => (others => '0'));
1321
    slink_tx_val_o <= (others => '0');
1322
    slink_rx_rdy_o <= (others => '0');
1323
  end generate;
1324
 
1325
 
1326
  -- External Interrupt Controller (XIRQ) ---------------------------------------------------
1327
  -- -------------------------------------------------------------------------------------------
1328
  neorv32_xirq_inst_true:
1329
  if (XIRQ_NUM_CH > 0) generate
1330
    neorv32_slink_inst: neorv32_xirq
1331
    generic map (
1332
      XIRQ_NUM_CH           => XIRQ_NUM_CH,          -- number of external IRQ channels (0..32)
1333
      XIRQ_TRIGGER_TYPE     => XIRQ_TRIGGER_TYPE,    -- trigger type: 0=level, 1=edge
1334
      XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
1335
    )
1336
    port map (
1337
      -- host access --
1338
      clk_i     => clk_i,                     -- global clock line
1339
      addr_i    => p_bus.addr,                -- address
1340
      rden_i    => io_rden,                   -- read enable
1341
      wren_i    => io_wren,                   -- write enable
1342
      data_i    => p_bus.wdata,               -- data in
1343
      data_o    => resp_bus(RESP_XIRQ).rdata, -- data out
1344
      ack_o     => resp_bus(RESP_XIRQ).ack,   -- transfer acknowledge
1345
      -- external interrupt lines --
1346
      xirq_i    => xirq_i,
1347
      -- CPU interrupt --
1348
      cpu_irq_o => xirq_irq
1349
    );
1350
    resp_bus(RESP_XIRQ).err <= '0'; -- no access error possible
1351
  end generate;
1352
 
1353
  neorv32_xirq_inst_false:
1354
  if (XIRQ_NUM_CH = 0) generate
1355
    resp_bus(RESP_XIRQ) <= resp_bus_entry_terminate_c;
1356
    xirq_irq <= '0';
1357
  end generate;
1358
 
1359
 
1360 12 zero_gravi
  -- System Configuration Information Memory (SYSINFO) --------------------------------------
1361
  -- -------------------------------------------------------------------------------------------
1362
  neorv32_sysinfo_inst: neorv32_sysinfo
1363
  generic map (
1364
    -- General --
1365 63 zero_gravi
    CLOCK_FREQUENCY              => CLOCK_FREQUENCY,      -- clock frequency of clk_i in Hz
1366
    INT_BOOTLOADER_EN            => INT_BOOTLOADER_EN,    -- implement processor-internal bootloader?
1367
    -- RISC-V CPU Extensions --
1368
    CPU_EXTENSION_RISCV_Zbb      => CPU_EXTENSION_RISCV_Zbb,      -- implement basic bit-manipulation sub-extension?
1369
    CPU_EXTENSION_RISCV_Zfinx    => CPU_EXTENSION_RISCV_Zfinx,    -- implement 32-bit floating-point extension (using INT reg!)
1370
    CPU_EXTENSION_RISCV_Zicsr    => CPU_EXTENSION_RISCV_Zicsr,    -- implement CSR system?
1371
    CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
1372
    CPU_EXTENSION_RISCV_Zmmul    => CPU_EXTENSION_RISCV_Zmmul,    -- implement multiply-only M sub-extension?
1373
    CPU_EXTENSION_RISCV_DEBUG    => ON_CHIP_DEBUGGER_EN,          -- implement CPU debug mode?
1374
    -- Extension Options --
1375
    FAST_MUL_EN                  => FAST_MUL_EN,          -- use DSPs for M extension's multiplier
1376
    FAST_SHIFT_EN                => FAST_SHIFT_EN,        -- use barrel shifter for shift operations
1377
    CPU_CNT_WIDTH                => CPU_CNT_WIDTH,        -- total width of CPU cycle and instret counters (0..64)
1378
    -- Physical memory protection (PMP) --
1379
    PMP_NUM_REGIONS              => PMP_NUM_REGIONS,      -- number of regions (0..64)
1380
    -- Hardware Performance Monitors (HPM) --
1381
    HPM_NUM_CNTS                 => HPM_NUM_CNTS,         -- number of implemented HPM counters (0..29)
1382 23 zero_gravi
    -- internal Instruction memory --
1383 63 zero_gravi
    MEM_INT_IMEM_EN              => MEM_INT_IMEM_EN,      -- implement processor-internal instruction memory
1384
    MEM_INT_IMEM_SIZE            => MEM_INT_IMEM_SIZE,    -- size of processor-internal instruction memory in bytes
1385 23 zero_gravi
    -- Internal Data memory --
1386 63 zero_gravi
    MEM_INT_DMEM_EN              => MEM_INT_DMEM_EN,      -- implement processor-internal data memory
1387
    MEM_INT_DMEM_SIZE            => MEM_INT_DMEM_SIZE,    -- size of processor-internal data memory in bytes
1388 41 zero_gravi
    -- Internal Cache memory --
1389 63 zero_gravi
    ICACHE_EN                    => ICACHE_EN,            -- implement instruction cache
1390
    ICACHE_NUM_BLOCKS            => ICACHE_NUM_BLOCKS,    -- i-cache: number of blocks (min 2), has to be a power of 2
1391
    ICACHE_BLOCK_SIZE            => ICACHE_BLOCK_SIZE,    -- i-cache: block size in bytes (min 4), has to be a power of 2
1392
    ICACHE_ASSOCIATIVITY         => ICACHE_ASSOCIATIVITY, -- i-cache: associativity (min 1), has to be a power 2
1393 23 zero_gravi
    -- External memory interface --
1394 63 zero_gravi
    MEM_EXT_EN                   => MEM_EXT_EN,           -- implement external memory bus interface?
1395
    MEM_EXT_BIG_ENDIAN           => MEM_EXT_BIG_ENDIAN,   -- byte order: true=big-endian, false=little-endian
1396 59 zero_gravi
    -- On-Chip Debugger --
1397 63 zero_gravi
    ON_CHIP_DEBUGGER_EN          => ON_CHIP_DEBUGGER_EN,  -- implement OCD?
1398 12 zero_gravi
    -- Processor peripherals --
1399 63 zero_gravi
    IO_GPIO_EN                   => IO_GPIO_EN,           -- implement general purpose input/output port unit (GPIO)?
1400
    IO_MTIME_EN                  => IO_MTIME_EN,          -- implement machine system timer (MTIME)?
1401
    IO_UART0_EN                  => IO_UART0_EN,          -- implement primary universal asynchronous receiver/transmitter (UART0)?
1402
    IO_UART1_EN                  => IO_UART1_EN,          -- implement secondary universal asynchronous receiver/transmitter (UART1)?
1403
    IO_SPI_EN                    => IO_SPI_EN,            -- implement serial peripheral interface (SPI)?
1404
    IO_TWI_EN                    => IO_TWI_EN,            -- implement two-wire interface (TWI)?
1405
    IO_PWM_NUM_CH                => IO_PWM_NUM_CH,        -- number of PWM channels to implement
1406
    IO_WDT_EN                    => IO_WDT_EN,            -- implement watch dog timer (WDT)?
1407
    IO_TRNG_EN                   => IO_TRNG_EN,           -- implement true random number generator (TRNG)?
1408
    IO_CFS_EN                    => IO_CFS_EN,            -- implement custom functions subsystem (CFS)?
1409
    IO_SLINK_EN                  => io_slink_en_c,        -- implement stream link interface?
1410
    IO_NEOLED_EN                 => IO_NEOLED_EN,         -- implement NeoPixel-compatible smart LED interface (NEOLED)?
1411
    IO_XIRQ_NUM_CH               => XIRQ_NUM_CH           -- number of external interrupt (XIRQ) channels to implement
1412 12 zero_gravi
  )
1413
  port map (
1414
    -- host access --
1415 60 zero_gravi
    clk_i  => clk_i,                        -- global clock line
1416
    addr_i => p_bus.addr,                   -- address
1417
    rden_i => io_rden,                      -- read enable
1418
    data_o => resp_bus(RESP_SYSINFO).rdata, -- data out
1419
    ack_o  => resp_bus(RESP_SYSINFO).ack    -- transfer acknowledge
1420 12 zero_gravi
  );
1421
 
1422 60 zero_gravi
  resp_bus(RESP_SYSINFO).err <= '0'; -- no access error possible
1423 12 zero_gravi
 
1424 60 zero_gravi
 
1425 59 zero_gravi
  -- **************************************************************************************************************************
1426
  -- On-Chip Debugger Complex
1427
  -- **************************************************************************************************************************
1428
 
1429
 
1430
  -- On-Chip Debugger - Debug Module (DM) ---------------------------------------------------
1431
  -- -------------------------------------------------------------------------------------------
1432
  neorv32_neorv32_debug_dm_true:
1433
  if (ON_CHIP_DEBUGGER_EN = true) generate
1434
    neorv32_debug_dm_inst: neorv32_debug_dm
1435
    port map (
1436
      -- global control --
1437 60 zero_gravi
      clk_i            => clk_i,                    -- global clock line
1438
      rstn_i           => ext_rstn,                 -- external reset, low-active
1439 59 zero_gravi
      -- debug module interface (DMI) --
1440
      dmi_rstn_i       => dmi.rstn,
1441
      dmi_req_valid_i  => dmi.req_valid,
1442
      dmi_req_ready_o  => dmi.req_ready,
1443
      dmi_req_addr_i   => dmi.req_addr,
1444
      dmi_req_op_i     => dmi.req_op,
1445
      dmi_req_data_i   => dmi.req_data,
1446 60 zero_gravi
      dmi_resp_valid_o => dmi.resp_valid,           -- response valid when set
1447
      dmi_resp_ready_i => dmi.resp_ready,           -- ready to receive respond
1448 59 zero_gravi
      dmi_resp_data_o  => dmi.resp_data,
1449 60 zero_gravi
      dmi_resp_err_o   => dmi.resp_err,             -- 0=ok, 1=error
1450 59 zero_gravi
      -- CPU bus access --
1451 60 zero_gravi
      cpu_addr_i       => p_bus.addr,               -- address
1452
      cpu_rden_i       => p_bus.re,                 -- read enable
1453
      cpu_wren_i       => p_bus.we,                 -- write enable
1454
      cpu_data_i       => p_bus.wdata,              -- data in
1455
      cpu_data_o       => resp_bus(RESP_OCD).rdata, -- data out
1456
      cpu_ack_o        => resp_bus(RESP_OCD).ack,   -- transfer acknowledge
1457 59 zero_gravi
      -- CPU control --
1458 60 zero_gravi
      cpu_ndmrstn_o    => dci_ndmrstn,              -- soc reset
1459
      cpu_halt_req_o   => dci_halt_req              -- request hart to halt (enter debug mode)
1460 59 zero_gravi
    );
1461 60 zero_gravi
    resp_bus(RESP_OCD).err <= '0'; -- no access error possible
1462 59 zero_gravi
  end generate;
1463
 
1464
  neorv32_debug_dm_false:
1465
  if (ON_CHIP_DEBUGGER_EN = false) generate
1466
    dmi.req_ready  <= '0';
1467
    dmi.resp_valid <= '0';
1468
    dmi.resp_data  <= (others => '0');
1469
    dmi.resp_err   <= '0';
1470
    --
1471 60 zero_gravi
    resp_bus(RESP_OCD) <= resp_bus_entry_terminate_c;
1472
    dci_ndmrstn  <= '1';
1473
    dci_halt_req <= '0';
1474 59 zero_gravi
  end generate;
1475
 
1476
 
1477
  -- On-Chip Debugger - Debug Transport Module (DTM) ----------------------------------------
1478
  -- -------------------------------------------------------------------------------------------
1479
  neorv32_neorv32_debug_dtm_true:
1480
  if (ON_CHIP_DEBUGGER_EN = true) generate
1481
    neorv32_debug_dtm_inst: neorv32_debug_dtm
1482
    generic map (
1483
      IDCODE_VERSION => jtag_tap_idcode_version_c, -- version
1484
      IDCODE_PARTID  => jtag_tap_idcode_partid_c,  -- part number
1485
      IDCODE_MANID   => jtag_tap_idcode_manid_c    -- manufacturer id
1486
    )
1487
    port map (
1488
      -- global control --
1489
      clk_i            => clk_i,          -- global clock line
1490
      rstn_i           => ext_rstn,       -- external reset, low-active
1491
      -- jtag connection --
1492
      jtag_trst_i      => jtag_trst_i,
1493
      jtag_tck_i       => jtag_tck_i,
1494
      jtag_tdi_i       => jtag_tdi_i,
1495
      jtag_tdo_o       => jtag_tdo_o,
1496
      jtag_tms_i       => jtag_tms_i,
1497
      -- debug module interface (DMI) --
1498
      dmi_rstn_o       => dmi.rstn,
1499
      dmi_req_valid_o  => dmi.req_valid,
1500
      dmi_req_ready_i  => dmi.req_ready,  -- DMI is allowed to make new requests when set
1501
      dmi_req_addr_o   => dmi.req_addr,
1502
      dmi_req_op_o     => dmi.req_op,     -- 0=read, 1=write
1503
      dmi_req_data_o   => dmi.req_data,
1504
      dmi_resp_valid_i => dmi.resp_valid, -- response valid when set
1505
      dmi_resp_ready_o => dmi.resp_ready, -- ready to receive respond
1506
      dmi_resp_data_i  => dmi.resp_data,
1507
      dmi_resp_err_i   => dmi.resp_err    -- 0=ok, 1=error
1508
    );
1509
  end generate;
1510
 
1511
  neorv32_debug_dtm_false:
1512
  if (ON_CHIP_DEBUGGER_EN = false) generate
1513
    jtag_tdo_o <= jtag_tdi_i; -- feed-through
1514
    --
1515
    dmi.rstn       <= '0';
1516
    dmi.req_valid  <= '0';
1517
    dmi.req_addr   <= (others => '0');
1518
    dmi.req_op     <= '0';
1519
    dmi.req_data   <= (others => '0');
1520
    dmi.resp_ready <= '0';
1521
  end generate;
1522
 
1523
 
1524 2 zero_gravi
end neorv32_top_rtl;

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