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-- #################################################################################################
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-- # << The NEORV32 RISC-V Processor - Top Entity >> #
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-- # ********************************************************************************************* #
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-- # Check out the processor's online documentation for more information: #
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-- # HQ: https://github.com/stnolting/neorv32 #
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-- # Data Sheet: https://stnolting.github.io/neorv32 #
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-- # User Guide: https://stnolting.github.io/neorv32/ug #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_top is
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generic (
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-- General --
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CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
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HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
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INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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zero_gravi |
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-- On-Chip Debugger (OCD) --
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ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
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CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters?
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CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
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CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit?
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zero_gravi |
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-- Tuning Options --
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FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
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CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
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CPU_IPB_ENTRIES : natural := 2; -- entries is instruction prefetch buffer, has to be a power of 2
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zero_gravi |
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-- Physical Memory Protection (PMP) --
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PMP_NUM_REGIONS : natural := 0; -- number of regions (0..16)
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PMP_MIN_GRANULARITY : natural := 4; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
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zero_gravi |
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
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HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64)
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zero_gravi |
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-- Internal Instruction memory (IMEM) --
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MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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zero_gravi |
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-- Internal Data memory (DMEM) --
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MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
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zero_gravi |
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-- Internal Instruction Cache (iCACHE) --
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ICACHE_EN : boolean := false; -- implement instruction cache
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ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
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ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
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ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
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zero_gravi |
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-- External memory interface (WISHBONE) --
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MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
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MEM_EXT_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled)
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MEM_EXT_PIPE_MODE : boolean := false; -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
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MEM_EXT_BIG_ENDIAN : boolean := false; -- byte order: true=big-endian, false=little-endian
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MEM_EXT_ASYNC_RX : boolean := false; -- use register buffer for RX data when false
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zero_gravi |
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-- Stream link interface (SLINK) --
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SLINK_NUM_TX : natural := 0; -- number of TX links (0..8)
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SLINK_NUM_RX : natural := 0; -- number of TX links (0..8)
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SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two
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SLINK_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two
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-- External Interrupts Controller (XIRQ) --
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XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32)
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XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger type: 0=level, 1=edge
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XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
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zero_gravi |
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-- Processor peripherals --
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IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)?
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IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1
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IO_UART0_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1
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IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1
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IO_UART1_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1
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zero_gravi |
IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)?
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IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)?
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IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..60); 0 = disabled
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IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)?
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IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
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IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
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IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
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IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
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IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
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IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
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IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)?
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IO_XIP_EN : boolean := false -- implement execute in place module (XIP)?
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zero_gravi |
);
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port (
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-- Global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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zero_gravi |
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zero_gravi |
-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
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zero_gravi |
jtag_trst_i : in std_ulogic := 'U'; -- low-active TAP reset (optional)
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jtag_tck_i : in std_ulogic := 'U'; -- serial clock
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jtag_tdi_i : in std_ulogic := 'U'; -- serial data input
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zero_gravi |
jtag_tdo_o : out std_ulogic; -- serial data output
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zero_gravi |
jtag_tms_i : in std_ulogic := 'U'; -- mode select
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zero_gravi |
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zero_gravi |
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
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zero_gravi |
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
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wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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zero_gravi |
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => 'U'); -- read data
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zero_gravi |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
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wb_we_o : out std_ulogic; -- read/write
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wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
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wb_stb_o : out std_ulogic; -- strobe
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wb_cyc_o : out std_ulogic; -- valid cycle
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wb_lock_o : out std_ulogic; -- exclusive access request
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zero_gravi |
wb_ack_i : in std_ulogic := 'L'; -- transfer acknowledge
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wb_err_i : in std_ulogic := 'L'; -- transfer error
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zero_gravi |
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zero_gravi |
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
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zero_gravi |
fence_o : out std_ulogic; -- indicates an executed FENCE operation
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fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
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zero_gravi |
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170 |
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zero_gravi |
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
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171 |
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xip_csn_o : out std_ulogic; -- chip-select, low-active
|
172 |
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xip_clk_o : out std_ulogic; -- serial clock
|
173 |
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xip_sdi_i : in std_ulogic := 'L'; -- device data input
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xip_sdo_o : out std_ulogic; -- controller data output
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175 |
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176 |
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zero_gravi |
-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
|
177 |
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slink_tx_dat_o : out sdata_8x32_t; -- output data
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178 |
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slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output
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zero_gravi |
slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- ready to send
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180 |
61 |
zero_gravi |
|
181 |
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-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
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182 |
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zero_gravi |
slink_rx_dat_i : in sdata_8x32_t := (others => (others => 'U')); -- input data
|
183 |
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slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- valid input
|
184 |
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zero_gravi |
slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive
|
185 |
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186 |
44 |
zero_gravi |
-- GPIO (available if IO_GPIO_EN = true) --
|
187 |
61 |
zero_gravi |
gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output
|
188 |
62 |
zero_gravi |
gpio_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input
|
189 |
50 |
zero_gravi |
|
190 |
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-- primary UART0 (available if IO_UART0_EN = true) --
|
191 |
61 |
zero_gravi |
uart0_txd_o : out std_ulogic; -- UART0 send data
|
192 |
62 |
zero_gravi |
uart0_rxd_i : in std_ulogic := 'U'; -- UART0 receive data
|
193 |
61 |
zero_gravi |
uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
|
194 |
62 |
zero_gravi |
uart0_cts_i : in std_ulogic := 'L'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
|
195 |
50 |
zero_gravi |
|
196 |
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-- secondary UART1 (available if IO_UART1_EN = true) --
|
197 |
61 |
zero_gravi |
uart1_txd_o : out std_ulogic; -- UART1 send data
|
198 |
62 |
zero_gravi |
uart1_rxd_i : in std_ulogic := 'U'; -- UART1 receive data
|
199 |
61 |
zero_gravi |
uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
|
200 |
62 |
zero_gravi |
uart1_cts_i : in std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
|
201 |
50 |
zero_gravi |
|
202 |
44 |
zero_gravi |
-- SPI (available if IO_SPI_EN = true) --
|
203 |
61 |
zero_gravi |
spi_sck_o : out std_ulogic; -- SPI serial clock
|
204 |
|
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spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
205 |
62 |
zero_gravi |
spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out
|
206 |
61 |
zero_gravi |
spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select
|
207 |
50 |
zero_gravi |
|
208 |
44 |
zero_gravi |
-- TWI (available if IO_TWI_EN = true) --
|
209 |
72 |
zero_gravi |
twi_sda_io : inout std_logic; -- twi serial data line
|
210 |
|
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twi_scl_io : inout std_logic; -- twi serial clock line
|
211 |
50 |
zero_gravi |
|
212 |
60 |
zero_gravi |
-- PWM (available if IO_PWM_NUM_CH > 0) --
|
213 |
70 |
zero_gravi |
pwm_o : out std_ulogic_vector(59 downto 0); -- pwm channels
|
214 |
50 |
zero_gravi |
|
215 |
47 |
zero_gravi |
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
|
216 |
62 |
zero_gravi |
cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit
|
217 |
61 |
zero_gravi |
cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
|
218 |
50 |
zero_gravi |
|
219 |
52 |
zero_gravi |
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
|
220 |
61 |
zero_gravi |
neoled_o : out std_ulogic; -- async serial data line
|
221 |
52 |
zero_gravi |
|
222 |
59 |
zero_gravi |
-- System time --
|
223 |
62 |
zero_gravi |
mtime_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
|
224 |
61 |
zero_gravi |
mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
|
225 |
50 |
zero_gravi |
|
226 |
61 |
zero_gravi |
-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
|
227 |
70 |
zero_gravi |
xirq_i : in std_ulogic_vector(31 downto 0) := (others => 'L'); -- IRQ channels
|
228 |
61 |
zero_gravi |
|
229 |
|
|
-- CPU interrupts --
|
230 |
62 |
zero_gravi |
mtime_irq_i : in std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false
|
231 |
|
|
msw_irq_i : in std_ulogic := 'L'; -- machine software interrupt
|
232 |
|
|
mext_irq_i : in std_ulogic := 'L' -- machine external interrupt
|
233 |
2 |
zero_gravi |
);
|
234 |
|
|
end neorv32_top;
|
235 |
|
|
|
236 |
|
|
architecture neorv32_top_rtl of neorv32_top is
|
237 |
|
|
|
238 |
61 |
zero_gravi |
-- CPU boot configuration --
|
239 |
|
|
constant cpu_boot_addr_c : std_ulogic_vector(31 downto 0) := cond_sel_stdulogicvector_f(INT_BOOTLOADER_EN, boot_rom_base_c, ispace_base_c);
|
240 |
12 |
zero_gravi |
|
241 |
29 |
zero_gravi |
-- alignment check for internal memories --
|
242 |
|
|
constant imem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) := (others => '0');
|
243 |
|
|
constant dmem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) := (others => '0');
|
244 |
|
|
|
245 |
61 |
zero_gravi |
-- helpers --
|
246 |
|
|
constant io_slink_en_c : boolean := boolean(SLINK_NUM_RX > 0) or boolean(SLINK_NUM_TX > 0); -- implement slink at all?
|
247 |
|
|
|
248 |
2 |
zero_gravi |
-- reset generator --
|
249 |
70 |
zero_gravi |
signal rstn_gen : std_ulogic_vector(7 downto 0) := (others => '0'); -- initialize (=reset) via bitstream (for FPGAs only)
|
250 |
60 |
zero_gravi |
signal ext_rstn : std_ulogic;
|
251 |
|
|
signal sys_rstn : std_ulogic;
|
252 |
|
|
signal wdt_rstn : std_ulogic;
|
253 |
2 |
zero_gravi |
|
254 |
|
|
-- clock generator --
|
255 |
70 |
zero_gravi |
signal clk_div : std_ulogic_vector(11 downto 0);
|
256 |
|
|
signal clk_div_ff : std_ulogic_vector(11 downto 0);
|
257 |
|
|
signal clk_gen : std_ulogic_vector(07 downto 0);
|
258 |
|
|
signal clk_gen_en : std_ulogic_vector(09 downto 0);
|
259 |
|
|
signal clk_gen_en_ff : std_ulogic;
|
260 |
47 |
zero_gravi |
--
|
261 |
52 |
zero_gravi |
signal wdt_cg_en : std_ulogic;
|
262 |
|
|
signal uart0_cg_en : std_ulogic;
|
263 |
|
|
signal uart1_cg_en : std_ulogic;
|
264 |
|
|
signal spi_cg_en : std_ulogic;
|
265 |
|
|
signal twi_cg_en : std_ulogic;
|
266 |
|
|
signal pwm_cg_en : std_ulogic;
|
267 |
|
|
signal cfs_cg_en : std_ulogic;
|
268 |
|
|
signal neoled_cg_en : std_ulogic;
|
269 |
67 |
zero_gravi |
signal gptmr_cg_en : std_ulogic;
|
270 |
70 |
zero_gravi |
signal xip_cg_en : std_ulogic;
|
271 |
2 |
zero_gravi |
|
272 |
12 |
zero_gravi |
-- bus interface --
|
273 |
|
|
type bus_interface_t is record
|
274 |
70 |
zero_gravi |
addr : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
275 |
|
|
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
276 |
|
|
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
277 |
|
|
ben : std_ulogic_vector(03 downto 0); -- byte enable
|
278 |
|
|
we : std_ulogic; -- write enable
|
279 |
|
|
re : std_ulogic; -- read enable
|
280 |
|
|
ack : std_ulogic; -- bus transfer acknowledge
|
281 |
|
|
err : std_ulogic; -- bus transfer error
|
282 |
|
|
fence : std_ulogic; -- fence(i) instruction executed
|
283 |
73 |
zero_gravi |
priv : std_ulogic; -- current privilege level
|
284 |
70 |
zero_gravi |
src : std_ulogic; -- access source (1=instruction fetch, 0=data access)
|
285 |
|
|
lock : std_ulogic; -- exclusive access request
|
286 |
11 |
zero_gravi |
end record;
|
287 |
41 |
zero_gravi |
signal cpu_i, i_cache, cpu_d, p_bus : bus_interface_t;
|
288 |
2 |
zero_gravi |
|
289 |
68 |
zero_gravi |
-- bus access error (from BUSKEEPER) --
|
290 |
|
|
signal bus_error : std_ulogic;
|
291 |
|
|
|
292 |
59 |
zero_gravi |
-- debug core interface (DCI) --
|
293 |
|
|
signal dci_ndmrstn : std_ulogic;
|
294 |
|
|
signal dci_halt_req : std_ulogic;
|
295 |
|
|
|
296 |
|
|
-- debug module interface (DMI) --
|
297 |
|
|
type dmi_t is record
|
298 |
|
|
rstn : std_ulogic;
|
299 |
|
|
req_valid : std_ulogic;
|
300 |
|
|
req_ready : std_ulogic; -- DMI is allowed to make new requests when set
|
301 |
|
|
req_addr : std_ulogic_vector(06 downto 0);
|
302 |
|
|
req_op : std_ulogic; -- 0=read, 1=write
|
303 |
|
|
req_data : std_ulogic_vector(31 downto 0);
|
304 |
|
|
resp_valid : std_ulogic; -- response valid when set
|
305 |
|
|
resp_ready : std_ulogic; -- ready to receive respond
|
306 |
|
|
resp_data : std_ulogic_vector(31 downto 0);
|
307 |
|
|
resp_err : std_ulogic; -- 0=ok, 1=error
|
308 |
|
|
end record;
|
309 |
|
|
signal dmi : dmi_t;
|
310 |
|
|
|
311 |
2 |
zero_gravi |
-- io space access --
|
312 |
|
|
signal io_acc : std_ulogic;
|
313 |
|
|
signal io_rden : std_ulogic;
|
314 |
|
|
signal io_wren : std_ulogic;
|
315 |
|
|
|
316 |
60 |
zero_gravi |
-- module response bus - entry type --
|
317 |
|
|
type resp_bus_entry_t is record
|
318 |
|
|
rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
319 |
|
|
ack : std_ulogic;
|
320 |
|
|
err : std_ulogic;
|
321 |
|
|
end record;
|
322 |
|
|
constant resp_bus_entry_terminate_c : resp_bus_entry_t := (rdata => (others => '0'), ack => '0', err => '0');
|
323 |
2 |
zero_gravi |
|
324 |
60 |
zero_gravi |
-- module response bus - device ID --
|
325 |
70 |
zero_gravi |
type resp_bus_id_t is (RESP_BUSKEEPER, RESP_IMEM, RESP_DMEM, RESP_BOOTROM, RESP_WISHBONE, RESP_GPIO, RESP_MTIME,
|
326 |
|
|
RESP_UART0, RESP_UART1, RESP_SPI, RESP_TWI, RESP_PWM, RESP_WDT, RESP_TRNG, RESP_CFS,
|
327 |
|
|
RESP_NEOLED, RESP_SYSINFO, RESP_OCD, RESP_SLINK, RESP_XIRQ, RESP_GPTMR, RESP_XIP_CT, RESP_XIP_IF);
|
328 |
60 |
zero_gravi |
|
329 |
|
|
-- module response bus --
|
330 |
|
|
type resp_bus_t is array (resp_bus_id_t) of resp_bus_entry_t;
|
331 |
|
|
signal resp_bus : resp_bus_t := (others => resp_bus_entry_terminate_c);
|
332 |
|
|
|
333 |
2 |
zero_gravi |
-- IRQs --
|
334 |
59 |
zero_gravi |
signal fast_irq : std_ulogic_vector(15 downto 0);
|
335 |
60 |
zero_gravi |
signal mtime_irq : std_ulogic;
|
336 |
50 |
zero_gravi |
signal wdt_irq : std_ulogic;
|
337 |
|
|
signal uart0_rxd_irq : std_ulogic;
|
338 |
|
|
signal uart0_txd_irq : std_ulogic;
|
339 |
|
|
signal uart1_rxd_irq : std_ulogic;
|
340 |
|
|
signal uart1_txd_irq : std_ulogic;
|
341 |
|
|
signal spi_irq : std_ulogic;
|
342 |
|
|
signal twi_irq : std_ulogic;
|
343 |
|
|
signal cfs_irq : std_ulogic;
|
344 |
52 |
zero_gravi |
signal neoled_irq : std_ulogic;
|
345 |
61 |
zero_gravi |
signal slink_tx_irq : std_ulogic;
|
346 |
|
|
signal slink_rx_irq : std_ulogic;
|
347 |
|
|
signal xirq_irq : std_ulogic;
|
348 |
67 |
zero_gravi |
signal gptmr_irq : std_ulogic;
|
349 |
2 |
zero_gravi |
|
350 |
11 |
zero_gravi |
-- misc --
|
351 |
68 |
zero_gravi |
signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME
|
352 |
|
|
signal ext_timeout : std_ulogic;
|
353 |
|
|
signal ext_access : std_ulogic;
|
354 |
70 |
zero_gravi |
signal xip_access : std_ulogic;
|
355 |
|
|
signal xip_enable : std_ulogic;
|
356 |
|
|
signal xip_page : std_ulogic_vector(3 downto 0);
|
357 |
69 |
zero_gravi |
signal debug_mode : std_ulogic;
|
358 |
11 |
zero_gravi |
|
359 |
2 |
zero_gravi |
begin
|
360 |
|
|
|
361 |
61 |
zero_gravi |
-- Processor IO/Peripherals Configuration -------------------------------------------------
|
362 |
|
|
-- -------------------------------------------------------------------------------------------
|
363 |
|
|
assert false report
|
364 |
|
|
"NEORV32 PROCESSOR IO Configuration: " &
|
365 |
|
|
cond_sel_string_f(IO_GPIO_EN, "GPIO ", "") &
|
366 |
|
|
cond_sel_string_f(IO_MTIME_EN, "MTIME ", "") &
|
367 |
|
|
cond_sel_string_f(IO_UART0_EN, "UART0 ", "") &
|
368 |
|
|
cond_sel_string_f(IO_UART1_EN, "UART1 ", "") &
|
369 |
|
|
cond_sel_string_f(IO_SPI_EN, "SPI ", "") &
|
370 |
|
|
cond_sel_string_f(IO_TWI_EN, "TWI ", "") &
|
371 |
|
|
cond_sel_string_f(boolean(IO_PWM_NUM_CH > 0), "PWM ", "") &
|
372 |
|
|
cond_sel_string_f(IO_WDT_EN, "WDT ", "") &
|
373 |
|
|
cond_sel_string_f(IO_TRNG_EN, "TRNG ", "") &
|
374 |
|
|
cond_sel_string_f(IO_CFS_EN, "CFS ", "") &
|
375 |
|
|
cond_sel_string_f(io_slink_en_c, "SLINK ", "") &
|
376 |
|
|
cond_sel_string_f(IO_NEOLED_EN, "NEOLED ", "") &
|
377 |
|
|
cond_sel_string_f(boolean(XIRQ_NUM_CH > 0), "XIRQ ", "") &
|
378 |
67 |
zero_gravi |
cond_sel_string_f(IO_GPTMR_EN, "GPTMR ", "") &
|
379 |
70 |
zero_gravi |
cond_sel_string_f(IO_XIP_EN, "XIP ", "") &
|
380 |
|
|
""
|
381 |
61 |
zero_gravi |
severity note;
|
382 |
|
|
|
383 |
|
|
|
384 |
2 |
zero_gravi |
-- Sanity Checks --------------------------------------------------------------------------
|
385 |
|
|
-- -------------------------------------------------------------------------------------------
|
386 |
61 |
zero_gravi |
-- boot configuration --
|
387 |
|
|
assert not (INT_BOOTLOADER_EN = true) report "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Indirect boot via bootloader (processor-internal BOOTROM)." severity note;
|
388 |
|
|
assert not ((INT_BOOTLOADER_EN = false) and (MEM_INT_IMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Direct boot from memory (processor-internal IMEM)." severity note;
|
389 |
|
|
assert not ((INT_BOOTLOADER_EN = false) and (MEM_INT_IMEM_EN = false)) report "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Direct boot from memory (processor-external (I)MEM)." severity note;
|
390 |
|
|
--
|
391 |
|
|
assert not ((MEM_EXT_EN = false) and (MEM_INT_DMEM_EN = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch data without external memory interface and internal IMEM." severity error;
|
392 |
|
|
assert not ((MEM_EXT_EN = false) and (MEM_INT_IMEM_EN = false) and (INT_BOOTLOADER_EN = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch instructions without external memory interface, internal IMEM and bootloader." severity error;
|
393 |
|
|
|
394 |
36 |
zero_gravi |
-- memory system - size --
|
395 |
44 |
zero_gravi |
assert not ((MEM_INT_DMEM_EN = true) and (is_power_of_two_f(MEM_INT_IMEM_SIZE) = false)) report "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_IMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning;
|
396 |
|
|
assert not ((MEM_INT_IMEM_EN = true) and (is_power_of_two_f(MEM_INT_DMEM_SIZE) = false)) report "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_DMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning;
|
397 |
61 |
zero_gravi |
|
398 |
29 |
zero_gravi |
-- memory system - alignment --
|
399 |
|
|
assert not (ispace_base_c(1 downto 0) /= "00") report "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address must be 4-byte-aligned." severity error;
|
400 |
|
|
assert not (dspace_base_c(1 downto 0) /= "00") report "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address must be 4-byte-aligned." severity error;
|
401 |
44 |
zero_gravi |
assert not ((ispace_base_c(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) /= imem_align_check_c) and (MEM_INT_IMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address has to be aligned to IMEM size." severity error;
|
402 |
|
|
assert not ((dspace_base_c(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) /= dmem_align_check_c) and (MEM_INT_DMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address has to be aligned to DMEM size." severity error;
|
403 |
61 |
zero_gravi |
|
404 |
36 |
zero_gravi |
-- memory system - layout warning --
|
405 |
29 |
zero_gravi |
assert not (ispace_base_c /= x"00000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framework." severity warning;
|
406 |
|
|
assert not (dspace_base_c /= x"80000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the software framework." severity warning;
|
407 |
61 |
zero_gravi |
|
408 |
41 |
zero_gravi |
-- memory system - the i-cache is intended to accelerate instruction fetch via the external memory interface only --
|
409 |
44 |
zero_gravi |
assert not ((ICACHE_EN = true) and (MEM_EXT_EN = false)) report "NEORV32 PROCESSOR CONFIG NOTE. Implementing i-cache without having the external memory interface implemented. The i-cache is intended to accelerate instruction fetch via the external memory interface." severity note;
|
410 |
61 |
zero_gravi |
|
411 |
59 |
zero_gravi |
-- on-chip debugger --
|
412 |
61 |
zero_gravi |
assert not (ON_CHIP_DEBUGGER_EN = true) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing on-chip debugger (OCD)." severity note;
|
413 |
2 |
zero_gravi |
|
414 |
59 |
zero_gravi |
|
415 |
2 |
zero_gravi |
-- Reset Generator ------------------------------------------------------------------------
|
416 |
|
|
-- -------------------------------------------------------------------------------------------
|
417 |
60 |
zero_gravi |
reset_generator: process(rstn_i, clk_i)
|
418 |
2 |
zero_gravi |
begin
|
419 |
60 |
zero_gravi |
if (rstn_i = '0') then
|
420 |
2 |
zero_gravi |
rstn_gen <= (others => '0');
|
421 |
60 |
zero_gravi |
sys_rstn <= '0';
|
422 |
2 |
zero_gravi |
elsif rising_edge(clk_i) then
|
423 |
60 |
zero_gravi |
-- keep internal reset active for at least <rstn_gen'size> clock cycles --
|
424 |
2 |
zero_gravi |
rstn_gen <= rstn_gen(rstn_gen'left-1 downto 0) & '1';
|
425 |
60 |
zero_gravi |
-- system reset: can also be triggered by watchdog and debug module --
|
426 |
|
|
sys_rstn <= ext_rstn and wdt_rstn and dci_ndmrstn;
|
427 |
2 |
zero_gravi |
end if;
|
428 |
|
|
end process reset_generator;
|
429 |
|
|
|
430 |
60 |
zero_gravi |
-- beautified external reset signal --
|
431 |
|
|
ext_rstn <= rstn_gen(rstn_gen'left);
|
432 |
2 |
zero_gravi |
|
433 |
|
|
|
434 |
|
|
-- Clock Generator ------------------------------------------------------------------------
|
435 |
|
|
-- -------------------------------------------------------------------------------------------
|
436 |
|
|
clock_generator: process(sys_rstn, clk_i)
|
437 |
|
|
begin
|
438 |
|
|
if (sys_rstn = '0') then
|
439 |
70 |
zero_gravi |
clk_gen_en_ff <= '-';
|
440 |
73 |
zero_gravi |
clk_div_ff <= (others => '-');
|
441 |
70 |
zero_gravi |
clk_div <= (others => '0'); -- reset required
|
442 |
2 |
zero_gravi |
elsif rising_edge(clk_i) then
|
443 |
70 |
zero_gravi |
clk_gen_en_ff <= or_reduce_f(clk_gen_en);
|
444 |
73 |
zero_gravi |
clk_div_ff <= clk_div;
|
445 |
|
|
if (clk_gen_en_ff = '1') then -- actual clock generator
|
446 |
23 |
zero_gravi |
clk_div <= std_ulogic_vector(unsigned(clk_div) + 1);
|
447 |
2 |
zero_gravi |
end if;
|
448 |
23 |
zero_gravi |
end if;
|
449 |
60 |
zero_gravi |
end process clock_generator;
|
450 |
2 |
zero_gravi |
|
451 |
73 |
zero_gravi |
-- clock enables: rising edge detectors --
|
452 |
|
|
clk_gen(clk_div2_c) <= clk_div(0) and (not clk_div_ff(0)); -- CLK/2
|
453 |
|
|
clk_gen(clk_div4_c) <= clk_div(1) and (not clk_div_ff(1)); -- CLK/4
|
454 |
|
|
clk_gen(clk_div8_c) <= clk_div(2) and (not clk_div_ff(2)); -- CLK/8
|
455 |
|
|
clk_gen(clk_div64_c) <= clk_div(5) and (not clk_div_ff(5)); -- CLK/64
|
456 |
|
|
clk_gen(clk_div128_c) <= clk_div(6) and (not clk_div_ff(6)); -- CLK/128
|
457 |
|
|
clk_gen(clk_div1024_c) <= clk_div(9) and (not clk_div_ff(9)); -- CLK/1024
|
458 |
|
|
clk_gen(clk_div2048_c) <= clk_div(10) and (not clk_div_ff(10)); -- CLK/2048
|
459 |
|
|
clk_gen(clk_div4096_c) <= clk_div(11) and (not clk_div_ff(11)); -- CLK/4096
|
460 |
|
|
|
461 |
70 |
zero_gravi |
-- fresh clocks anyone? --
|
462 |
|
|
clk_gen_en(0) <= wdt_cg_en;
|
463 |
|
|
clk_gen_en(1) <= uart0_cg_en;
|
464 |
|
|
clk_gen_en(2) <= uart1_cg_en;
|
465 |
|
|
clk_gen_en(3) <= spi_cg_en;
|
466 |
|
|
clk_gen_en(4) <= twi_cg_en;
|
467 |
|
|
clk_gen_en(5) <= pwm_cg_en;
|
468 |
|
|
clk_gen_en(6) <= cfs_cg_en;
|
469 |
|
|
clk_gen_en(7) <= neoled_cg_en;
|
470 |
|
|
clk_gen_en(8) <= gptmr_cg_en;
|
471 |
|
|
clk_gen_en(9) <= xip_cg_en;
|
472 |
2 |
zero_gravi |
|
473 |
70 |
zero_gravi |
|
474 |
45 |
zero_gravi |
-- CPU Core -------------------------------------------------------------------------------
|
475 |
2 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
476 |
|
|
neorv32_cpu_inst: neorv32_cpu
|
477 |
|
|
generic map (
|
478 |
|
|
-- General --
|
479 |
70 |
zero_gravi |
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id
|
480 |
|
|
CPU_BOOT_ADDR => cpu_boot_addr_c, -- cpu boot address
|
481 |
|
|
CPU_DEBUG_ADDR => dm_base_c, -- cpu debug mode start address
|
482 |
2 |
zero_gravi |
-- RISC-V CPU Extensions --
|
483 |
39 |
zero_gravi |
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
|
484 |
66 |
zero_gravi |
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit-manipulation extension?
|
485 |
8 |
zero_gravi |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
486 |
|
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
|
487 |
70 |
zero_gravi |
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension?
|
488 |
15 |
zero_gravi |
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
|
489 |
55 |
zero_gravi |
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
|
490 |
8 |
zero_gravi |
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
491 |
66 |
zero_gravi |
CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters?
|
492 |
|
|
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors?
|
493 |
8 |
zero_gravi |
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
494 |
61 |
zero_gravi |
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
|
495 |
72 |
zero_gravi |
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit?
|
496 |
59 |
zero_gravi |
CPU_EXTENSION_RISCV_DEBUG => ON_CHIP_DEBUGGER_EN, -- implement CPU debug mode?
|
497 |
19 |
zero_gravi |
-- Extension Options --
|
498 |
70 |
zero_gravi |
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
|
499 |
|
|
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
|
500 |
|
|
CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
|
501 |
|
|
CPU_IPB_ENTRIES => CPU_IPB_ENTRIES, -- entries is instruction prefetch buffer, has to be a power of 2
|
502 |
15 |
zero_gravi |
-- Physical Memory Protection (PMP) --
|
503 |
73 |
zero_gravi |
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..16)
|
504 |
|
|
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
|
505 |
42 |
zero_gravi |
-- Hardware Performance Monitors (HPM) --
|
506 |
70 |
zero_gravi |
HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29)
|
507 |
|
|
HPM_CNT_WIDTH => HPM_CNT_WIDTH -- total size of HPM counters (0..64)
|
508 |
2 |
zero_gravi |
)
|
509 |
|
|
port map (
|
510 |
|
|
-- global control --
|
511 |
70 |
zero_gravi |
clk_i => clk_i, -- global clock, rising edge
|
512 |
|
|
rstn_i => sys_rstn, -- global reset, low-active, async
|
513 |
|
|
sleep_o => open, -- cpu is in sleep mode when set
|
514 |
|
|
debug_o => debug_mode, -- cpu is in debug mode when set
|
515 |
12 |
zero_gravi |
-- instruction bus interface --
|
516 |
70 |
zero_gravi |
i_bus_addr_o => cpu_i.addr, -- bus access address
|
517 |
|
|
i_bus_rdata_i => cpu_i.rdata, -- bus read data
|
518 |
|
|
i_bus_wdata_o => cpu_i.wdata, -- bus write data
|
519 |
|
|
i_bus_ben_o => cpu_i.ben, -- byte enable
|
520 |
|
|
i_bus_we_o => cpu_i.we, -- write enable
|
521 |
|
|
i_bus_re_o => cpu_i.re, -- read enable
|
522 |
|
|
i_bus_lock_o => cpu_i.lock, -- exclusive access request
|
523 |
|
|
i_bus_ack_i => cpu_i.ack, -- bus transfer acknowledge
|
524 |
|
|
i_bus_err_i => cpu_i.err, -- bus transfer error
|
525 |
|
|
i_bus_fence_o => cpu_i.fence, -- executed FENCEI operation
|
526 |
|
|
i_bus_priv_o => cpu_i.priv, -- privilege level
|
527 |
12 |
zero_gravi |
-- data bus interface --
|
528 |
70 |
zero_gravi |
d_bus_addr_o => cpu_d.addr, -- bus access address
|
529 |
|
|
d_bus_rdata_i => cpu_d.rdata, -- bus read data
|
530 |
|
|
d_bus_wdata_o => cpu_d.wdata, -- bus write data
|
531 |
|
|
d_bus_ben_o => cpu_d.ben, -- byte enable
|
532 |
|
|
d_bus_we_o => cpu_d.we, -- write enable
|
533 |
|
|
d_bus_re_o => cpu_d.re, -- read enable
|
534 |
|
|
d_bus_lock_o => cpu_d.lock, -- exclusive access request
|
535 |
|
|
d_bus_ack_i => cpu_d.ack, -- bus transfer acknowledge
|
536 |
|
|
d_bus_err_i => cpu_d.err, -- bus transfer error
|
537 |
|
|
d_bus_fence_o => cpu_d.fence, -- executed FENCE operation
|
538 |
|
|
d_bus_priv_o => cpu_d.priv, -- privilege level
|
539 |
11 |
zero_gravi |
-- system time input from MTIME --
|
540 |
70 |
zero_gravi |
time_i => mtime_time, -- current system time
|
541 |
58 |
zero_gravi |
-- non-maskable interrupt --
|
542 |
70 |
zero_gravi |
msw_irq_i => msw_irq_i, -- machine software interrupt
|
543 |
|
|
mext_irq_i => mext_irq_i, -- machine external interrupt request
|
544 |
|
|
mtime_irq_i => mtime_irq, -- machine timer interrupt
|
545 |
14 |
zero_gravi |
-- fast interrupts (custom) --
|
546 |
70 |
zero_gravi |
firq_i => fast_irq, -- fast interrupt trigger
|
547 |
59 |
zero_gravi |
-- debug mode (halt) request --
|
548 |
70 |
zero_gravi |
db_halt_req_i => dci_halt_req
|
549 |
2 |
zero_gravi |
);
|
550 |
|
|
|
551 |
36 |
zero_gravi |
-- misc --
|
552 |
57 |
zero_gravi |
cpu_i.src <= '1'; -- initialized but unused
|
553 |
|
|
cpu_d.src <= '0'; -- initialized but unused
|
554 |
36 |
zero_gravi |
|
555 |
14 |
zero_gravi |
-- advanced memory control --
|
556 |
|
|
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
|
557 |
|
|
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
|
558 |
2 |
zero_gravi |
|
559 |
70 |
zero_gravi |
-- fast interrupt requests (FIRQs) - triggers are SINGLE-SHOT --
|
560 |
68 |
zero_gravi |
fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog
|
561 |
50 |
zero_gravi |
fast_irq(01) <= cfs_irq; -- custom functions subsystem
|
562 |
68 |
zero_gravi |
fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) RX
|
563 |
|
|
fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) TX
|
564 |
|
|
fast_irq(04) <= uart1_rxd_irq; -- secondary UART (UART1) RX
|
565 |
|
|
fast_irq(05) <= uart1_txd_irq; -- secondary UART (UART1) TX
|
566 |
70 |
zero_gravi |
fast_irq(06) <= spi_irq; -- SPI transfer done
|
567 |
|
|
fast_irq(07) <= twi_irq; -- TWI transfer done
|
568 |
61 |
zero_gravi |
fast_irq(08) <= xirq_irq; -- external interrupt controller
|
569 |
70 |
zero_gravi |
fast_irq(09) <= neoled_irq; -- NEOLED buffer IRQ
|
570 |
68 |
zero_gravi |
fast_irq(10) <= slink_rx_irq; -- SLINK RX
|
571 |
|
|
fast_irq(11) <= slink_tx_irq; -- SLINK TX
|
572 |
67 |
zero_gravi |
fast_irq(12) <= gptmr_irq; -- general purpose timer
|
573 |
61 |
zero_gravi |
--
|
574 |
70 |
zero_gravi |
fast_irq(13) <= '0'; -- reserved
|
575 |
|
|
fast_irq(14) <= '0'; -- reserved
|
576 |
|
|
fast_irq(15) <= '0'; -- LOWEST PRIORITY - reserved
|
577 |
14 |
zero_gravi |
|
578 |
|
|
|
579 |
41 |
zero_gravi |
-- CPU Instruction Cache ------------------------------------------------------------------
|
580 |
|
|
-- -------------------------------------------------------------------------------------------
|
581 |
|
|
neorv32_icache_inst_true:
|
582 |
44 |
zero_gravi |
if (ICACHE_EN = true) generate
|
583 |
45 |
zero_gravi |
neorv32_icache_inst: neorv32_icache
|
584 |
41 |
zero_gravi |
generic map (
|
585 |
47 |
zero_gravi |
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- number of blocks (min 2), has to be a power of 2
|
586 |
|
|
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- block size in bytes (min 4), has to be a power of 2
|
587 |
|
|
ICACHE_NUM_SETS => ICACHE_ASSOCIATIVITY -- associativity / number of sets (1=direct_mapped), has to be a power of 2
|
588 |
41 |
zero_gravi |
)
|
589 |
|
|
port map (
|
590 |
|
|
-- global control --
|
591 |
70 |
zero_gravi |
clk_i => clk_i, -- global clock, rising edge
|
592 |
|
|
rstn_i => sys_rstn, -- global reset, low-active, async
|
593 |
|
|
clear_i => cpu_i.fence, -- cache clear
|
594 |
73 |
zero_gravi |
miss_o => open, -- cache miss
|
595 |
41 |
zero_gravi |
-- host controller interface --
|
596 |
70 |
zero_gravi |
host_addr_i => cpu_i.addr, -- bus access address
|
597 |
|
|
host_rdata_o => cpu_i.rdata, -- bus read data
|
598 |
|
|
host_wdata_i => cpu_i.wdata, -- bus write data
|
599 |
|
|
host_ben_i => cpu_i.ben, -- byte enable
|
600 |
|
|
host_we_i => cpu_i.we, -- write enable
|
601 |
|
|
host_re_i => cpu_i.re, -- read enable
|
602 |
|
|
host_ack_o => cpu_i.ack, -- bus transfer acknowledge
|
603 |
|
|
host_err_o => cpu_i.err, -- bus transfer error
|
604 |
41 |
zero_gravi |
-- peripheral bus interface --
|
605 |
70 |
zero_gravi |
bus_addr_o => i_cache.addr, -- bus access address
|
606 |
|
|
bus_rdata_i => i_cache.rdata, -- bus read data
|
607 |
|
|
bus_wdata_o => i_cache.wdata, -- bus write data
|
608 |
|
|
bus_ben_o => i_cache.ben, -- byte enable
|
609 |
|
|
bus_we_o => i_cache.we, -- write enable
|
610 |
|
|
bus_re_o => i_cache.re, -- read enable
|
611 |
|
|
bus_ack_i => i_cache.ack, -- bus transfer acknowledge
|
612 |
|
|
bus_err_i => i_cache.err -- bus transfer error
|
613 |
41 |
zero_gravi |
);
|
614 |
|
|
end generate;
|
615 |
|
|
|
616 |
57 |
zero_gravi |
-- TODO: do not use LOCKED instruction fetch --
|
617 |
|
|
i_cache.lock <= '0';
|
618 |
|
|
|
619 |
41 |
zero_gravi |
neorv32_icache_inst_false:
|
620 |
44 |
zero_gravi |
if (ICACHE_EN = false) generate
|
621 |
57 |
zero_gravi |
i_cache.addr <= cpu_i.addr;
|
622 |
|
|
cpu_i.rdata <= i_cache.rdata;
|
623 |
|
|
i_cache.wdata <= cpu_i.wdata;
|
624 |
|
|
i_cache.ben <= cpu_i.ben;
|
625 |
|
|
i_cache.we <= cpu_i.we;
|
626 |
|
|
i_cache.re <= cpu_i.re;
|
627 |
|
|
cpu_i.ack <= i_cache.ack;
|
628 |
|
|
cpu_i.err <= i_cache.err;
|
629 |
41 |
zero_gravi |
end generate;
|
630 |
|
|
|
631 |
|
|
|
632 |
45 |
zero_gravi |
-- CPU Bus Switch -------------------------------------------------------------------------
|
633 |
12 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
634 |
|
|
neorv32_busswitch_inst: neorv32_busswitch
|
635 |
|
|
generic map (
|
636 |
|
|
PORT_CA_READ_ONLY => false, -- set if controller port A is read-only
|
637 |
|
|
PORT_CB_READ_ONLY => true -- set if controller port B is read-only
|
638 |
|
|
)
|
639 |
|
|
port map (
|
640 |
|
|
-- global control --
|
641 |
70 |
zero_gravi |
clk_i => clk_i, -- global clock, rising edge
|
642 |
|
|
rstn_i => sys_rstn, -- global reset, low-active, async
|
643 |
12 |
zero_gravi |
-- controller interface a --
|
644 |
70 |
zero_gravi |
ca_bus_addr_i => cpu_d.addr, -- bus access address
|
645 |
|
|
ca_bus_rdata_o => cpu_d.rdata, -- bus read data
|
646 |
|
|
ca_bus_wdata_i => cpu_d.wdata, -- bus write data
|
647 |
|
|
ca_bus_ben_i => cpu_d.ben, -- byte enable
|
648 |
|
|
ca_bus_we_i => cpu_d.we, -- write enable
|
649 |
|
|
ca_bus_re_i => cpu_d.re, -- read enable
|
650 |
|
|
ca_bus_lock_i => cpu_d.lock, -- exclusive access request
|
651 |
|
|
ca_bus_ack_o => cpu_d.ack, -- bus transfer acknowledge
|
652 |
|
|
ca_bus_err_o => cpu_d.err, -- bus transfer error
|
653 |
12 |
zero_gravi |
-- controller interface b --
|
654 |
70 |
zero_gravi |
cb_bus_addr_i => i_cache.addr, -- bus access address
|
655 |
|
|
cb_bus_rdata_o => i_cache.rdata, -- bus read data
|
656 |
|
|
cb_bus_wdata_i => i_cache.wdata, -- bus write data
|
657 |
|
|
cb_bus_ben_i => i_cache.ben, -- byte enable
|
658 |
|
|
cb_bus_we_i => i_cache.we, -- write enable
|
659 |
|
|
cb_bus_re_i => i_cache.re, -- read enable
|
660 |
|
|
cb_bus_lock_i => i_cache.lock, -- exclusive access request
|
661 |
|
|
cb_bus_ack_o => i_cache.ack, -- bus transfer acknowledge
|
662 |
|
|
cb_bus_err_o => i_cache.err, -- bus transfer error
|
663 |
12 |
zero_gravi |
-- peripheral bus --
|
664 |
70 |
zero_gravi |
p_bus_src_o => p_bus.src, -- access source: 0 = A (data), 1 = B (instructions)
|
665 |
|
|
p_bus_addr_o => p_bus.addr, -- bus access address
|
666 |
|
|
p_bus_rdata_i => p_bus.rdata, -- bus read data
|
667 |
|
|
p_bus_wdata_o => p_bus.wdata, -- bus write data
|
668 |
|
|
p_bus_ben_o => p_bus.ben, -- byte enable
|
669 |
|
|
p_bus_we_o => p_bus.we, -- write enable
|
670 |
|
|
p_bus_re_o => p_bus.re, -- read enable
|
671 |
|
|
p_bus_lock_o => p_bus.lock, -- exclusive access request
|
672 |
|
|
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge
|
673 |
|
|
p_bus_err_i => bus_error -- bus transfer error
|
674 |
12 |
zero_gravi |
);
|
675 |
2 |
zero_gravi |
|
676 |
60 |
zero_gravi |
-- current CPU privilege level --
|
677 |
|
|
p_bus.priv <= cpu_i.priv; -- note: cpu_i.priv == cpu_d.priv
|
678 |
53 |
zero_gravi |
|
679 |
60 |
zero_gravi |
-- fence operation (unused) --
|
680 |
|
|
p_bus.fence <= cpu_d.fence or cpu_i.fence;
|
681 |
2 |
zero_gravi |
|
682 |
60 |
zero_gravi |
-- bus response --
|
683 |
66 |
zero_gravi |
bus_response: process(resp_bus)
|
684 |
60 |
zero_gravi |
variable rdata_v : std_ulogic_vector(data_width_c-1 downto 0);
|
685 |
|
|
variable ack_v : std_ulogic;
|
686 |
|
|
variable err_v : std_ulogic;
|
687 |
|
|
begin
|
688 |
|
|
rdata_v := (others => '0');
|
689 |
|
|
ack_v := '0';
|
690 |
|
|
err_v := '0';
|
691 |
71 |
zero_gravi |
-- OR all module's response signals: only the module that is actually
|
692 |
|
|
-- been accessed is allowed to set it's bus output signals
|
693 |
60 |
zero_gravi |
for i in resp_bus'range loop
|
694 |
|
|
rdata_v := rdata_v or resp_bus(i).rdata; -- read data
|
695 |
|
|
ack_v := ack_v or resp_bus(i).ack; -- acknowledge
|
696 |
|
|
err_v := err_v or resp_bus(i).err; -- error
|
697 |
|
|
end loop; -- i
|
698 |
|
|
p_bus.rdata <= rdata_v; -- processor bus: CPU transfer data input
|
699 |
|
|
p_bus.ack <= ack_v; -- processor bus: CPU transfer ACK input
|
700 |
66 |
zero_gravi |
p_bus.err <= err_v; -- processor bus: CPU transfer data bus error input
|
701 |
60 |
zero_gravi |
end process;
|
702 |
12 |
zero_gravi |
|
703 |
|
|
|
704 |
66 |
zero_gravi |
-- Bus Keeper (BUSKEEPER) -----------------------------------------------------------------
|
705 |
57 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
706 |
|
|
neorv32_bus_keeper_inst: neorv32_bus_keeper
|
707 |
|
|
port map (
|
708 |
|
|
-- host access --
|
709 |
66 |
zero_gravi |
clk_i => clk_i, -- global clock line
|
710 |
|
|
rstn_i => sys_rstn, -- global reset line, low-active, use as async
|
711 |
|
|
addr_i => p_bus.addr, -- address
|
712 |
|
|
rden_i => io_rden, -- read enable
|
713 |
|
|
wren_i => io_wren, -- byte write enable
|
714 |
70 |
zero_gravi |
data_i => p_bus.wdata, -- data in
|
715 |
66 |
zero_gravi |
data_o => resp_bus(RESP_BUSKEEPER).rdata, -- data out
|
716 |
|
|
ack_o => resp_bus(RESP_BUSKEEPER).ack, -- transfer acknowledge
|
717 |
68 |
zero_gravi |
err_o => bus_error, -- transfer error
|
718 |
66 |
zero_gravi |
-- bus monitoring --
|
719 |
|
|
bus_addr_i => p_bus.addr, -- address
|
720 |
|
|
bus_rden_i => p_bus.re, -- read enable
|
721 |
|
|
bus_wren_i => p_bus.we, -- write enable
|
722 |
|
|
bus_ack_i => p_bus.ack, -- transfer acknowledge from bus system
|
723 |
68 |
zero_gravi |
bus_err_i => p_bus.err, -- transfer error from bus system
|
724 |
|
|
bus_tmo_i => ext_timeout, -- transfer timeout (external interface)
|
725 |
70 |
zero_gravi |
bus_ext_i => ext_access, -- external bus access
|
726 |
|
|
bus_xip_i => xip_access -- pending XIP access
|
727 |
57 |
zero_gravi |
);
|
728 |
36 |
zero_gravi |
|
729 |
68 |
zero_gravi |
-- unused, BUSKEEPER **directly** issues error to the CPU --
|
730 |
|
|
resp_bus(RESP_BUSKEEPER).err <= '0';
|
731 |
57 |
zero_gravi |
|
732 |
68 |
zero_gravi |
|
733 |
2 |
zero_gravi |
-- Processor-Internal Instruction Memory (IMEM) -------------------------------------------
|
734 |
|
|
-- -------------------------------------------------------------------------------------------
|
735 |
|
|
neorv32_int_imem_inst_true:
|
736 |
68 |
zero_gravi |
if (MEM_INT_IMEM_EN = true) and (MEM_INT_IMEM_SIZE > 0) generate
|
737 |
2 |
zero_gravi |
neorv32_int_imem_inst: neorv32_imem
|
738 |
|
|
generic map (
|
739 |
61 |
zero_gravi |
IMEM_BASE => imem_base_c, -- memory base address
|
740 |
|
|
IMEM_SIZE => MEM_INT_IMEM_SIZE, -- processor-internal instruction memory size in bytes
|
741 |
|
|
IMEM_AS_IROM => not INT_BOOTLOADER_EN -- implement IMEM as pre-initialized read-only memory?
|
742 |
2 |
zero_gravi |
)
|
743 |
|
|
port map (
|
744 |
60 |
zero_gravi |
clk_i => clk_i, -- global clock line
|
745 |
|
|
rden_i => p_bus.re, -- read enable
|
746 |
|
|
wren_i => p_bus.we, -- write enable
|
747 |
|
|
ben_i => p_bus.ben, -- byte write enable
|
748 |
|
|
addr_i => p_bus.addr, -- address
|
749 |
|
|
data_i => p_bus.wdata, -- data in
|
750 |
|
|
data_o => resp_bus(RESP_IMEM).rdata, -- data out
|
751 |
72 |
zero_gravi |
ack_o => resp_bus(RESP_IMEM).ack, -- transfer acknowledge
|
752 |
|
|
err_o => resp_bus(RESP_IMEM).err -- transfer error
|
753 |
2 |
zero_gravi |
);
|
754 |
|
|
end generate;
|
755 |
|
|
|
756 |
|
|
neorv32_int_imem_inst_false:
|
757 |
68 |
zero_gravi |
if (MEM_INT_IMEM_EN = false) or (MEM_INT_IMEM_SIZE = 0) generate
|
758 |
60 |
zero_gravi |
resp_bus(RESP_IMEM) <= resp_bus_entry_terminate_c;
|
759 |
2 |
zero_gravi |
end generate;
|
760 |
|
|
|
761 |
|
|
|
762 |
|
|
-- Processor-Internal Data Memory (DMEM) --------------------------------------------------
|
763 |
|
|
-- -------------------------------------------------------------------------------------------
|
764 |
|
|
neorv32_int_dmem_inst_true:
|
765 |
68 |
zero_gravi |
if (MEM_INT_DMEM_EN = true) and (MEM_INT_DMEM_SIZE > 0) generate
|
766 |
2 |
zero_gravi |
neorv32_int_dmem_inst: neorv32_dmem
|
767 |
|
|
generic map (
|
768 |
23 |
zero_gravi |
DMEM_BASE => dmem_base_c, -- memory base address
|
769 |
2 |
zero_gravi |
DMEM_SIZE => MEM_INT_DMEM_SIZE -- processor-internal data memory size in bytes
|
770 |
|
|
)
|
771 |
|
|
port map (
|
772 |
60 |
zero_gravi |
clk_i => clk_i, -- global clock line
|
773 |
|
|
rden_i => p_bus.re, -- read enable
|
774 |
|
|
wren_i => p_bus.we, -- write enable
|
775 |
|
|
ben_i => p_bus.ben, -- byte write enable
|
776 |
|
|
addr_i => p_bus.addr, -- address
|
777 |
|
|
data_i => p_bus.wdata, -- data in
|
778 |
|
|
data_o => resp_bus(RESP_DMEM).rdata, -- data out
|
779 |
|
|
ack_o => resp_bus(RESP_DMEM).ack -- transfer acknowledge
|
780 |
2 |
zero_gravi |
);
|
781 |
60 |
zero_gravi |
resp_bus(RESP_DMEM).err <= '0'; -- no access error possible
|
782 |
2 |
zero_gravi |
end generate;
|
783 |
|
|
|
784 |
|
|
neorv32_int_dmem_inst_false:
|
785 |
68 |
zero_gravi |
if (MEM_INT_DMEM_EN = false) or (MEM_INT_DMEM_SIZE = 0) generate
|
786 |
60 |
zero_gravi |
resp_bus(RESP_DMEM) <= resp_bus_entry_terminate_c;
|
787 |
2 |
zero_gravi |
end generate;
|
788 |
|
|
|
789 |
|
|
|
790 |
|
|
-- Processor-Internal Bootloader ROM (BOOTROM) --------------------------------------------
|
791 |
|
|
-- -------------------------------------------------------------------------------------------
|
792 |
|
|
neorv32_boot_rom_inst_true:
|
793 |
61 |
zero_gravi |
if (INT_BOOTLOADER_EN = true) generate
|
794 |
2 |
zero_gravi |
neorv32_boot_rom_inst: neorv32_boot_rom
|
795 |
23 |
zero_gravi |
generic map (
|
796 |
61 |
zero_gravi |
BOOTROM_BASE => boot_rom_base_c -- boot ROM base address
|
797 |
23 |
zero_gravi |
)
|
798 |
2 |
zero_gravi |
port map (
|
799 |
60 |
zero_gravi |
clk_i => clk_i, -- global clock line
|
800 |
|
|
rden_i => p_bus.re, -- read enable
|
801 |
72 |
zero_gravi |
wren_i => p_bus.we, -- write enable
|
802 |
60 |
zero_gravi |
addr_i => p_bus.addr, -- address
|
803 |
|
|
data_o => resp_bus(RESP_BOOTROM).rdata, -- data out
|
804 |
72 |
zero_gravi |
ack_o => resp_bus(RESP_BOOTROM).ack, -- transfer acknowledge
|
805 |
|
|
err_o => resp_bus(RESP_BOOTROM).err -- transfer error
|
806 |
2 |
zero_gravi |
);
|
807 |
|
|
end generate;
|
808 |
|
|
|
809 |
|
|
neorv32_boot_rom_inst_false:
|
810 |
61 |
zero_gravi |
if (INT_BOOTLOADER_EN = false) generate
|
811 |
60 |
zero_gravi |
resp_bus(RESP_BOOTROM) <= resp_bus_entry_terminate_c;
|
812 |
2 |
zero_gravi |
end generate;
|
813 |
|
|
|
814 |
|
|
|
815 |
|
|
-- External Wishbone Gateway (WISHBONE) ---------------------------------------------------
|
816 |
|
|
-- -------------------------------------------------------------------------------------------
|
817 |
|
|
neorv32_wishbone_inst_true:
|
818 |
44 |
zero_gravi |
if (MEM_EXT_EN = true) generate
|
819 |
2 |
zero_gravi |
neorv32_wishbone_inst: neorv32_wishbone
|
820 |
|
|
generic map (
|
821 |
23 |
zero_gravi |
-- Internal instruction memory --
|
822 |
62 |
zero_gravi |
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
|
823 |
|
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
824 |
23 |
zero_gravi |
-- Internal data memory --
|
825 |
62 |
zero_gravi |
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
|
826 |
|
|
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
|
827 |
|
|
-- Interface Configuration --
|
828 |
|
|
BUS_TIMEOUT => MEM_EXT_TIMEOUT, -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
|
829 |
|
|
PIPE_MODE => MEM_EXT_PIPE_MODE, -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
|
830 |
|
|
BIG_ENDIAN => MEM_EXT_BIG_ENDIAN, -- byte order: true=big-endian, false=little-endian
|
831 |
|
|
ASYNC_RX => MEM_EXT_ASYNC_RX -- use register buffer for RX data when false
|
832 |
2 |
zero_gravi |
)
|
833 |
|
|
port map (
|
834 |
|
|
-- global control --
|
835 |
70 |
zero_gravi |
clk_i => clk_i, -- global clock line
|
836 |
|
|
rstn_i => sys_rstn, -- global reset line, low-active
|
837 |
2 |
zero_gravi |
-- host access --
|
838 |
70 |
zero_gravi |
src_i => p_bus.src, -- access type (0: data, 1:instruction)
|
839 |
|
|
addr_i => p_bus.addr, -- address
|
840 |
|
|
rden_i => p_bus.re, -- read enable
|
841 |
|
|
wren_i => p_bus.we, -- write enable
|
842 |
|
|
ben_i => p_bus.ben, -- byte write enable
|
843 |
|
|
data_i => p_bus.wdata, -- data in
|
844 |
|
|
data_o => resp_bus(RESP_WISHBONE).rdata, -- data out
|
845 |
|
|
lock_i => p_bus.lock, -- exclusive access request
|
846 |
|
|
ack_o => resp_bus(RESP_WISHBONE).ack, -- transfer acknowledge
|
847 |
|
|
err_o => resp_bus(RESP_WISHBONE).err, -- transfer error
|
848 |
|
|
tmo_o => ext_timeout, -- transfer timeout
|
849 |
|
|
priv_i => p_bus.priv, -- current CPU privilege level
|
850 |
|
|
ext_o => ext_access, -- active external access
|
851 |
|
|
-- xip configuration --
|
852 |
|
|
xip_en_i => xip_enable, -- XIP module enabled
|
853 |
|
|
xip_page_i => xip_page, -- XIP memory page
|
854 |
2 |
zero_gravi |
-- wishbone interface --
|
855 |
70 |
zero_gravi |
wb_tag_o => wb_tag_o, -- request tag
|
856 |
|
|
wb_adr_o => wb_adr_o, -- address
|
857 |
|
|
wb_dat_i => wb_dat_i, -- read data
|
858 |
|
|
wb_dat_o => wb_dat_o, -- write data
|
859 |
|
|
wb_we_o => wb_we_o, -- read/write
|
860 |
|
|
wb_sel_o => wb_sel_o, -- byte enable
|
861 |
|
|
wb_stb_o => wb_stb_o, -- strobe
|
862 |
|
|
wb_cyc_o => wb_cyc_o, -- valid cycle
|
863 |
|
|
wb_lock_o => wb_lock_o, -- exclusive access request
|
864 |
|
|
wb_ack_i => wb_ack_i, -- transfer acknowledge
|
865 |
|
|
wb_err_i => wb_err_i -- transfer error
|
866 |
2 |
zero_gravi |
);
|
867 |
|
|
end generate;
|
868 |
|
|
|
869 |
|
|
neorv32_wishbone_inst_false:
|
870 |
44 |
zero_gravi |
if (MEM_EXT_EN = false) generate
|
871 |
60 |
zero_gravi |
resp_bus(RESP_WISHBONE) <= resp_bus_entry_terminate_c;
|
872 |
68 |
zero_gravi |
ext_timeout <= '0';
|
873 |
|
|
ext_access <= '0';
|
874 |
2 |
zero_gravi |
--
|
875 |
60 |
zero_gravi |
wb_adr_o <= (others => '0');
|
876 |
|
|
wb_dat_o <= (others => '0');
|
877 |
|
|
wb_we_o <= '0';
|
878 |
|
|
wb_sel_o <= (others => '0');
|
879 |
|
|
wb_stb_o <= '0';
|
880 |
|
|
wb_cyc_o <= '0';
|
881 |
|
|
wb_lock_o <= '0';
|
882 |
|
|
wb_tag_o <= (others => '0');
|
883 |
2 |
zero_gravi |
end generate;
|
884 |
|
|
|
885 |
|
|
|
886 |
70 |
zero_gravi |
-- Execute In Place Module (XIP) ----------------------------------------------------------
|
887 |
|
|
-- -------------------------------------------------------------------------------------------
|
888 |
|
|
neorv32_xip_inst_true:
|
889 |
|
|
if (IO_XIP_EN = true) generate
|
890 |
|
|
neorv32_xip_inst: neorv32_xip
|
891 |
|
|
port map (
|
892 |
|
|
-- global control --
|
893 |
|
|
clk_i => clk_i, -- global clock line
|
894 |
|
|
rstn_i => sys_rstn, -- global reset line, low-active
|
895 |
|
|
-- host access: control register access port --
|
896 |
|
|
ct_addr_i => p_bus.addr, -- address
|
897 |
|
|
ct_rden_i => io_rden, -- read enable
|
898 |
|
|
ct_wren_i => io_wren, -- write enable
|
899 |
|
|
ct_data_i => p_bus.wdata, -- data in
|
900 |
|
|
ct_data_o => resp_bus(RESP_XIP_CT).rdata, -- data out
|
901 |
|
|
ct_ack_o => resp_bus(RESP_XIP_CT).ack, -- transfer acknowledge
|
902 |
|
|
-- host access: instruction fetch access port (read-only) --
|
903 |
|
|
if_addr_i => p_bus.addr, -- address
|
904 |
|
|
if_rden_i => p_bus.re, -- read enable
|
905 |
|
|
if_data_o => resp_bus(RESP_XIP_IF).rdata, -- data out
|
906 |
|
|
if_ack_o => resp_bus(RESP_XIP_IF).ack, -- transfer acknowledge
|
907 |
|
|
-- status --
|
908 |
|
|
xip_en_o => xip_enable, -- XIP enable
|
909 |
|
|
xip_acc_o => xip_access, -- pending XIP access
|
910 |
|
|
xip_page_o => xip_page, -- XIP page
|
911 |
|
|
-- clock generator --
|
912 |
|
|
clkgen_en_o => xip_cg_en, -- enable clock generator
|
913 |
|
|
clkgen_i => clk_gen,
|
914 |
|
|
-- SPI device interface --
|
915 |
|
|
spi_csn_o => xip_csn_o, -- chip-select, low-active
|
916 |
|
|
spi_clk_o => xip_clk_o, -- serial clock
|
917 |
|
|
spi_data_i => xip_sdi_i, -- device data output
|
918 |
|
|
spi_data_o => xip_sdo_o -- controller data output
|
919 |
|
|
);
|
920 |
|
|
resp_bus(RESP_XIP_CT).err <= '0'; -- no access error possible
|
921 |
|
|
resp_bus(RESP_XIP_IF).err <= '0'; -- no access error possible
|
922 |
|
|
end generate;
|
923 |
|
|
|
924 |
|
|
neorv32_xip_inst_false:
|
925 |
|
|
if (IO_XIP_EN = false) generate
|
926 |
|
|
resp_bus(RESP_XIP_CT) <= resp_bus_entry_terminate_c;
|
927 |
|
|
resp_bus(RESP_XIP_IF) <= resp_bus_entry_terminate_c;
|
928 |
|
|
--
|
929 |
|
|
xip_enable <= '0';
|
930 |
|
|
xip_access <= '0';
|
931 |
|
|
xip_page <= (others => '0');
|
932 |
|
|
xip_cg_en <= '0';
|
933 |
|
|
xip_csn_o <= '1';
|
934 |
|
|
xip_clk_o <= '0';
|
935 |
|
|
xip_sdo_o <= '0';
|
936 |
|
|
end generate;
|
937 |
|
|
|
938 |
|
|
|
939 |
|
|
-- ****************************************************************************************************************************
|
940 |
|
|
-- IO/Peripheral Modules
|
941 |
|
|
-- ****************************************************************************************************************************
|
942 |
|
|
|
943 |
|
|
|
944 |
2 |
zero_gravi |
-- IO Access? -----------------------------------------------------------------------------
|
945 |
|
|
-- -------------------------------------------------------------------------------------------
|
946 |
12 |
zero_gravi |
io_acc <= '1' when (p_bus.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0';
|
947 |
73 |
zero_gravi |
io_rden <= io_acc and p_bus.re;
|
948 |
71 |
zero_gravi |
io_wren <= io_acc and p_bus.we and and_reduce_f(p_bus.ben); -- only full-word write accesses are allowed (reduces HW complexity)
|
949 |
2 |
zero_gravi |
|
950 |
|
|
|
951 |
47 |
zero_gravi |
-- Custom Functions Subsystem (CFS) -------------------------------------------------------
|
952 |
|
|
-- -------------------------------------------------------------------------------------------
|
953 |
|
|
neorv32_cfs_inst_true:
|
954 |
|
|
if (IO_CFS_EN = true) generate
|
955 |
|
|
neorv32_cfs_inst: neorv32_cfs
|
956 |
|
|
generic map (
|
957 |
61 |
zero_gravi |
CFS_CONFIG => IO_CFS_CONFIG, -- custom CFS configuration generic
|
958 |
52 |
zero_gravi |
CFS_IN_SIZE => IO_CFS_IN_SIZE, -- size of CFS input conduit in bits
|
959 |
|
|
CFS_OUT_SIZE => IO_CFS_OUT_SIZE -- size of CFS output conduit in bits
|
960 |
47 |
zero_gravi |
)
|
961 |
|
|
port map (
|
962 |
|
|
-- host access --
|
963 |
60 |
zero_gravi |
clk_i => clk_i, -- global clock line
|
964 |
|
|
rstn_i => sys_rstn, -- global reset line, low-active, use as async
|
965 |
|
|
addr_i => p_bus.addr, -- address
|
966 |
|
|
rden_i => io_rden, -- read enable
|
967 |
73 |
zero_gravi |
wren_i => io_wren, -- word write enable
|
968 |
60 |
zero_gravi |
data_i => p_bus.wdata, -- data in
|
969 |
|
|
data_o => resp_bus(RESP_CFS).rdata, -- data out
|
970 |
|
|
ack_o => resp_bus(RESP_CFS).ack, -- transfer acknowledge
|
971 |
68 |
zero_gravi |
err_o => resp_bus(RESP_CFS).err, -- access error
|
972 |
47 |
zero_gravi |
-- clock generator --
|
973 |
60 |
zero_gravi |
clkgen_en_o => cfs_cg_en, -- enable clock generator
|
974 |
|
|
clkgen_i => clk_gen, -- "clock" inputs
|
975 |
47 |
zero_gravi |
-- interrupt --
|
976 |
60 |
zero_gravi |
irq_o => cfs_irq, -- interrupt request
|
977 |
47 |
zero_gravi |
-- custom io (conduit) --
|
978 |
60 |
zero_gravi |
cfs_in_i => cfs_in_i, -- custom inputs
|
979 |
|
|
cfs_out_o => cfs_out_o -- custom outputs
|
980 |
47 |
zero_gravi |
);
|
981 |
|
|
end generate;
|
982 |
|
|
|
983 |
|
|
neorv32_cfs_inst_false:
|
984 |
|
|
if (IO_CFS_EN = false) generate
|
985 |
60 |
zero_gravi |
resp_bus(RESP_CFS) <= resp_bus_entry_terminate_c;
|
986 |
70 |
zero_gravi |
--
|
987 |
47 |
zero_gravi |
cfs_cg_en <= '0';
|
988 |
|
|
cfs_irq <= '0';
|
989 |
|
|
cfs_out_o <= (others => '0');
|
990 |
|
|
end generate;
|
991 |
|
|
|
992 |
|
|
|
993 |
2 |
zero_gravi |
-- General Purpose Input/Output Port (GPIO) -----------------------------------------------
|
994 |
|
|
-- -------------------------------------------------------------------------------------------
|
995 |
|
|
neorv32_gpio_inst_true:
|
996 |
44 |
zero_gravi |
if (IO_GPIO_EN = true) generate
|
997 |
2 |
zero_gravi |
neorv32_gpio_inst: neorv32_gpio
|
998 |
|
|
port map (
|
999 |
|
|
-- host access --
|
1000 |
60 |
zero_gravi |
clk_i => clk_i, -- global clock line
|
1001 |
|
|
addr_i => p_bus.addr, -- address
|
1002 |
|
|
rden_i => io_rden, -- read enable
|
1003 |
|
|
wren_i => io_wren, -- write enable
|
1004 |
|
|
data_i => p_bus.wdata, -- data in
|
1005 |
|
|
data_o => resp_bus(RESP_GPIO).rdata, -- data out
|
1006 |
|
|
ack_o => resp_bus(RESP_GPIO).ack, -- transfer acknowledge
|
1007 |
70 |
zero_gravi |
err_o => resp_bus(RESP_GPIO).err, -- transfer error
|
1008 |
2 |
zero_gravi |
-- parallel io --
|
1009 |
|
|
gpio_o => gpio_o,
|
1010 |
61 |
zero_gravi |
gpio_i => gpio_i
|
1011 |
2 |
zero_gravi |
);
|
1012 |
|
|
end generate;
|
1013 |
|
|
|
1014 |
|
|
neorv32_gpio_inst_false:
|
1015 |
44 |
zero_gravi |
if (IO_GPIO_EN = false) generate
|
1016 |
60 |
zero_gravi |
resp_bus(RESP_GPIO) <= resp_bus_entry_terminate_c;
|
1017 |
70 |
zero_gravi |
--
|
1018 |
61 |
zero_gravi |
gpio_o <= (others => '0');
|
1019 |
2 |
zero_gravi |
end generate;
|
1020 |
|
|
|
1021 |
|
|
|
1022 |
|
|
-- Watch Dog Timer (WDT) ------------------------------------------------------------------
|
1023 |
|
|
-- -------------------------------------------------------------------------------------------
|
1024 |
|
|
neorv32_wdt_inst_true:
|
1025 |
44 |
zero_gravi |
if (IO_WDT_EN = true) generate
|
1026 |
2 |
zero_gravi |
neorv32_wdt_inst: neorv32_wdt
|
1027 |
69 |
zero_gravi |
generic map(
|
1028 |
|
|
DEBUG_EN => ON_CHIP_DEBUGGER_EN -- CPU debug mode implemented?
|
1029 |
|
|
)
|
1030 |
2 |
zero_gravi |
port map (
|
1031 |
|
|
-- host access --
|
1032 |
60 |
zero_gravi |
clk_i => clk_i, -- global clock line
|
1033 |
|
|
rstn_i => ext_rstn, -- global reset line, low-active
|
1034 |
|
|
rden_i => io_rden, -- read enable
|
1035 |
|
|
wren_i => io_wren, -- write enable
|
1036 |
|
|
addr_i => p_bus.addr, -- address
|
1037 |
|
|
data_i => p_bus.wdata, -- data in
|
1038 |
|
|
data_o => resp_bus(RESP_WDT).rdata, -- data out
|
1039 |
|
|
ack_o => resp_bus(RESP_WDT).ack, -- transfer acknowledge
|
1040 |
69 |
zero_gravi |
-- CPU in debug mode? --
|
1041 |
|
|
cpu_debug_i => debug_mode,
|
1042 |
2 |
zero_gravi |
-- clock generator --
|
1043 |
60 |
zero_gravi |
clkgen_en_o => wdt_cg_en, -- enable clock generator
|
1044 |
2 |
zero_gravi |
clkgen_i => clk_gen,
|
1045 |
|
|
-- timeout event --
|
1046 |
60 |
zero_gravi |
irq_o => wdt_irq, -- timeout IRQ
|
1047 |
|
|
rstn_o => wdt_rstn -- timeout reset, low_active, use it as async!
|
1048 |
2 |
zero_gravi |
);
|
1049 |
60 |
zero_gravi |
resp_bus(RESP_WDT).err <= '0'; -- no access error possible
|
1050 |
2 |
zero_gravi |
end generate;
|
1051 |
|
|
|
1052 |
|
|
neorv32_wdt_inst_false:
|
1053 |
44 |
zero_gravi |
if (IO_WDT_EN = false) generate
|
1054 |
60 |
zero_gravi |
resp_bus(RESP_WDT) <= resp_bus_entry_terminate_c;
|
1055 |
70 |
zero_gravi |
--
|
1056 |
2 |
zero_gravi |
wdt_irq <= '0';
|
1057 |
|
|
wdt_rstn <= '1';
|
1058 |
|
|
wdt_cg_en <= '0';
|
1059 |
|
|
end generate;
|
1060 |
|
|
|
1061 |
|
|
|
1062 |
|
|
-- Machine System Timer (MTIME) -----------------------------------------------------------
|
1063 |
|
|
-- -------------------------------------------------------------------------------------------
|
1064 |
|
|
neorv32_mtime_inst_true:
|
1065 |
44 |
zero_gravi |
if (IO_MTIME_EN = true) generate
|
1066 |
2 |
zero_gravi |
neorv32_mtime_inst: neorv32_mtime
|
1067 |
|
|
port map (
|
1068 |
|
|
-- host access --
|
1069 |
60 |
zero_gravi |
clk_i => clk_i, -- global clock line
|
1070 |
|
|
addr_i => p_bus.addr, -- address
|
1071 |
|
|
rden_i => io_rden, -- read enable
|
1072 |
|
|
wren_i => io_wren, -- write enable
|
1073 |
|
|
data_i => p_bus.wdata, -- data in
|
1074 |
|
|
data_o => resp_bus(RESP_MTIME).rdata, -- data out
|
1075 |
|
|
ack_o => resp_bus(RESP_MTIME).ack, -- transfer acknowledge
|
1076 |
11 |
zero_gravi |
-- time output for CPU --
|
1077 |
60 |
zero_gravi |
time_o => mtime_time, -- current system time
|
1078 |
2 |
zero_gravi |
-- interrupt --
|
1079 |
60 |
zero_gravi |
irq_o => mtime_irq -- interrupt request
|
1080 |
2 |
zero_gravi |
);
|
1081 |
60 |
zero_gravi |
resp_bus(RESP_MTIME).err <= '0'; -- no access error possible
|
1082 |
2 |
zero_gravi |
end generate;
|
1083 |
|
|
|
1084 |
|
|
neorv32_mtime_inst_false:
|
1085 |
44 |
zero_gravi |
if (IO_MTIME_EN = false) generate
|
1086 |
60 |
zero_gravi |
resp_bus(RESP_MTIME) <= resp_bus_entry_terminate_c;
|
1087 |
70 |
zero_gravi |
--
|
1088 |
60 |
zero_gravi |
mtime_time <= mtime_i; -- use external machine timer time signal
|
1089 |
64 |
zero_gravi |
mtime_irq <= mtime_irq_i; -- use external machine timer interrupt
|
1090 |
2 |
zero_gravi |
end generate;
|
1091 |
|
|
|
1092 |
|
|
|
1093 |
60 |
zero_gravi |
-- system time output LO --
|
1094 |
|
|
mtime_sync: process(clk_i)
|
1095 |
|
|
begin
|
1096 |
|
|
if rising_edge(clk_i) then
|
1097 |
|
|
-- buffer low word one clock cycle to compensate for MTIME's 1-cycle delay
|
1098 |
|
|
-- when overflowing from low-word to high-word -> only relevant for processor-external devices
|
1099 |
|
|
-- processor-internal devices (= the CPU) do not care about this delay offset as 64-bit MTIME.TIME
|
1100 |
|
|
-- cannot be accessed within a single cycle
|
1101 |
|
|
if (IO_MTIME_EN = true) then
|
1102 |
|
|
mtime_o(31 downto 0) <= mtime_time(31 downto 0);
|
1103 |
|
|
else
|
1104 |
|
|
mtime_o(31 downto 0) <= (others => '0');
|
1105 |
|
|
end if;
|
1106 |
|
|
end if;
|
1107 |
|
|
end process mtime_sync;
|
1108 |
59 |
zero_gravi |
|
1109 |
60 |
zero_gravi |
-- system time output HI --
|
1110 |
|
|
mtime_o(63 downto 32) <= mtime_time(63 downto 32) when (IO_MTIME_EN = true) else (others => '0');
|
1111 |
|
|
|
1112 |
|
|
|
1113 |
51 |
zero_gravi |
-- Primary Universal Asynchronous Receiver/Transmitter (UART0) ----------------------------
|
1114 |
2 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
1115 |
50 |
zero_gravi |
neorv32_uart0_inst_true:
|
1116 |
|
|
if (IO_UART0_EN = true) generate
|
1117 |
|
|
neorv32_uart0_inst: neorv32_uart
|
1118 |
|
|
generic map (
|
1119 |
65 |
zero_gravi |
UART_PRIMARY => true, -- true = primary UART (UART0), false = secondary UART (UART1)
|
1120 |
|
|
UART_RX_FIFO => IO_UART0_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1
|
1121 |
|
|
UART_TX_FIFO => IO_UART0_TX_FIFO -- TX fifo depth, has to be a power of two, min 1
|
1122 |
50 |
zero_gravi |
)
|
1123 |
2 |
zero_gravi |
port map (
|
1124 |
|
|
-- host access --
|
1125 |
60 |
zero_gravi |
clk_i => clk_i, -- global clock line
|
1126 |
|
|
addr_i => p_bus.addr, -- address
|
1127 |
|
|
rden_i => io_rden, -- read enable
|
1128 |
|
|
wren_i => io_wren, -- write enable
|
1129 |
|
|
data_i => p_bus.wdata, -- data in
|
1130 |
|
|
data_o => resp_bus(RESP_UART0).rdata, -- data out
|
1131 |
|
|
ack_o => resp_bus(RESP_UART0).ack, -- transfer acknowledge
|
1132 |
2 |
zero_gravi |
-- clock generator --
|
1133 |
60 |
zero_gravi |
clkgen_en_o => uart0_cg_en, -- enable clock generator
|
1134 |
2 |
zero_gravi |
clkgen_i => clk_gen,
|
1135 |
|
|
-- com lines --
|
1136 |
50 |
zero_gravi |
uart_txd_o => uart0_txd_o,
|
1137 |
|
|
uart_rxd_i => uart0_rxd_i,
|
1138 |
51 |
zero_gravi |
-- hardware flow control --
|
1139 |
60 |
zero_gravi |
uart_rts_o => uart0_rts_o, -- UART.RX ready to receive ("RTR"), low-active, optional
|
1140 |
|
|
uart_cts_i => uart0_cts_i, -- UART.TX allowed to transmit, low-active, optional
|
1141 |
2 |
zero_gravi |
-- interrupts --
|
1142 |
60 |
zero_gravi |
irq_rxd_o => uart0_rxd_irq, -- uart data received interrupt
|
1143 |
|
|
irq_txd_o => uart0_txd_irq -- uart transmission done interrupt
|
1144 |
2 |
zero_gravi |
);
|
1145 |
60 |
zero_gravi |
resp_bus(RESP_UART0).err <= '0'; -- no access error possible
|
1146 |
2 |
zero_gravi |
end generate;
|
1147 |
|
|
|
1148 |
50 |
zero_gravi |
neorv32_uart0_inst_false:
|
1149 |
|
|
if (IO_UART0_EN = false) generate
|
1150 |
60 |
zero_gravi |
resp_bus(RESP_UART0) <= resp_bus_entry_terminate_c;
|
1151 |
70 |
zero_gravi |
--
|
1152 |
50 |
zero_gravi |
uart0_txd_o <= '0';
|
1153 |
51 |
zero_gravi |
uart0_rts_o <= '0';
|
1154 |
50 |
zero_gravi |
uart0_cg_en <= '0';
|
1155 |
|
|
uart0_rxd_irq <= '0';
|
1156 |
|
|
uart0_txd_irq <= '0';
|
1157 |
2 |
zero_gravi |
end generate;
|
1158 |
|
|
|
1159 |
|
|
|
1160 |
51 |
zero_gravi |
-- Secondary Universal Asynchronous Receiver/Transmitter (UART1) --------------------------
|
1161 |
50 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
1162 |
|
|
neorv32_uart1_inst_true:
|
1163 |
|
|
if (IO_UART1_EN = true) generate
|
1164 |
|
|
neorv32_uart1_inst: neorv32_uart
|
1165 |
|
|
generic map (
|
1166 |
65 |
zero_gravi |
UART_PRIMARY => false, -- true = primary UART (UART0), false = secondary UART (UART1)
|
1167 |
|
|
UART_RX_FIFO => IO_UART1_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1
|
1168 |
|
|
UART_TX_FIFO => IO_UART1_TX_FIFO -- TX fifo depth, has to be a power of two, min 1
|
1169 |
50 |
zero_gravi |
)
|
1170 |
|
|
port map (
|
1171 |
|
|
-- host access --
|
1172 |
60 |
zero_gravi |
clk_i => clk_i, -- global clock line
|
1173 |
|
|
addr_i => p_bus.addr, -- address
|
1174 |
|
|
rden_i => io_rden, -- read enable
|
1175 |
|
|
wren_i => io_wren, -- write enable
|
1176 |
|
|
data_i => p_bus.wdata, -- data in
|
1177 |
|
|
data_o => resp_bus(RESP_UART1).rdata, -- data out
|
1178 |
|
|
ack_o => resp_bus(RESP_UART1).ack, -- transfer acknowledge
|
1179 |
50 |
zero_gravi |
-- clock generator --
|
1180 |
60 |
zero_gravi |
clkgen_en_o => uart1_cg_en, -- enable clock generator
|
1181 |
50 |
zero_gravi |
clkgen_i => clk_gen,
|
1182 |
|
|
-- com lines --
|
1183 |
|
|
uart_txd_o => uart1_txd_o,
|
1184 |
|
|
uart_rxd_i => uart1_rxd_i,
|
1185 |
51 |
zero_gravi |
-- hardware flow control --
|
1186 |
60 |
zero_gravi |
uart_rts_o => uart1_rts_o, -- UART.RX ready to receive ("RTR"), low-active, optional
|
1187 |
|
|
uart_cts_i => uart1_cts_i, -- UART.TX allowed to transmit, low-active, optional
|
1188 |
50 |
zero_gravi |
-- interrupts --
|
1189 |
60 |
zero_gravi |
irq_rxd_o => uart1_rxd_irq, -- uart data received interrupt
|
1190 |
|
|
irq_txd_o => uart1_txd_irq -- uart transmission done interrupt
|
1191 |
50 |
zero_gravi |
);
|
1192 |
60 |
zero_gravi |
resp_bus(RESP_UART1).err <= '0'; -- no access error possible
|
1193 |
50 |
zero_gravi |
end generate;
|
1194 |
|
|
|
1195 |
|
|
neorv32_uart1_inst_false:
|
1196 |
|
|
if (IO_UART1_EN = false) generate
|
1197 |
60 |
zero_gravi |
resp_bus(RESP_UART1) <= resp_bus_entry_terminate_c;
|
1198 |
70 |
zero_gravi |
--
|
1199 |
50 |
zero_gravi |
uart1_txd_o <= '0';
|
1200 |
51 |
zero_gravi |
uart1_rts_o <= '0';
|
1201 |
50 |
zero_gravi |
uart1_cg_en <= '0';
|
1202 |
|
|
uart1_rxd_irq <= '0';
|
1203 |
|
|
uart1_txd_irq <= '0';
|
1204 |
|
|
end generate;
|
1205 |
|
|
|
1206 |
|
|
|
1207 |
2 |
zero_gravi |
-- Serial Peripheral Interface (SPI) ------------------------------------------------------
|
1208 |
|
|
-- -------------------------------------------------------------------------------------------
|
1209 |
|
|
neorv32_spi_inst_true:
|
1210 |
44 |
zero_gravi |
if (IO_SPI_EN = true) generate
|
1211 |
2 |
zero_gravi |
neorv32_spi_inst: neorv32_spi
|
1212 |
|
|
port map (
|
1213 |
|
|
-- host access --
|
1214 |
60 |
zero_gravi |
clk_i => clk_i, -- global clock line
|
1215 |
|
|
addr_i => p_bus.addr, -- address
|
1216 |
|
|
rden_i => io_rden, -- read enable
|
1217 |
|
|
wren_i => io_wren, -- write enable
|
1218 |
|
|
data_i => p_bus.wdata, -- data in
|
1219 |
|
|
data_o => resp_bus(RESP_SPI).rdata, -- data out
|
1220 |
|
|
ack_o => resp_bus(RESP_SPI).ack, -- transfer acknowledge
|
1221 |
2 |
zero_gravi |
-- clock generator --
|
1222 |
60 |
zero_gravi |
clkgen_en_o => spi_cg_en, -- enable clock generator
|
1223 |
2 |
zero_gravi |
clkgen_i => clk_gen,
|
1224 |
|
|
-- com lines --
|
1225 |
60 |
zero_gravi |
spi_sck_o => spi_sck_o, -- SPI serial clock
|
1226 |
|
|
spi_sdo_o => spi_sdo_o, -- controller data out, peripheral data in
|
1227 |
|
|
spi_sdi_i => spi_sdi_i, -- controller data in, peripheral data out
|
1228 |
|
|
spi_csn_o => spi_csn_o, -- SPI CS
|
1229 |
2 |
zero_gravi |
-- interrupt --
|
1230 |
60 |
zero_gravi |
irq_o => spi_irq -- transmission done interrupt
|
1231 |
2 |
zero_gravi |
);
|
1232 |
60 |
zero_gravi |
resp_bus(RESP_SPI).err <= '0'; -- no access error possible
|
1233 |
2 |
zero_gravi |
end generate;
|
1234 |
|
|
|
1235 |
|
|
neorv32_spi_inst_false:
|
1236 |
44 |
zero_gravi |
if (IO_SPI_EN = false) generate
|
1237 |
60 |
zero_gravi |
resp_bus(RESP_SPI) <= resp_bus_entry_terminate_c;
|
1238 |
70 |
zero_gravi |
--
|
1239 |
60 |
zero_gravi |
spi_sck_o <= '0';
|
1240 |
|
|
spi_sdo_o <= '0';
|
1241 |
|
|
spi_csn_o <= (others => '1'); -- CSn lines are low-active
|
1242 |
|
|
spi_cg_en <= '0';
|
1243 |
|
|
spi_irq <= '0';
|
1244 |
2 |
zero_gravi |
end generate;
|
1245 |
|
|
|
1246 |
|
|
|
1247 |
|
|
-- Two-Wire Interface (TWI) ---------------------------------------------------------------
|
1248 |
|
|
-- -------------------------------------------------------------------------------------------
|
1249 |
|
|
neorv32_twi_inst_true:
|
1250 |
44 |
zero_gravi |
if (IO_TWI_EN = true) generate
|
1251 |
2 |
zero_gravi |
neorv32_twi_inst: neorv32_twi
|
1252 |
|
|
port map (
|
1253 |
|
|
-- host access --
|
1254 |
60 |
zero_gravi |
clk_i => clk_i, -- global clock line
|
1255 |
|
|
addr_i => p_bus.addr, -- address
|
1256 |
|
|
rden_i => io_rden, -- read enable
|
1257 |
|
|
wren_i => io_wren, -- write enable
|
1258 |
|
|
data_i => p_bus.wdata, -- data in
|
1259 |
|
|
data_o => resp_bus(RESP_TWI).rdata, -- data out
|
1260 |
|
|
ack_o => resp_bus(RESP_TWI).ack, -- transfer acknowledge
|
1261 |
2 |
zero_gravi |
-- clock generator --
|
1262 |
60 |
zero_gravi |
clkgen_en_o => twi_cg_en, -- enable clock generator
|
1263 |
2 |
zero_gravi |
clkgen_i => clk_gen,
|
1264 |
|
|
-- com lines --
|
1265 |
60 |
zero_gravi |
twi_sda_io => twi_sda_io, -- serial data line
|
1266 |
|
|
twi_scl_io => twi_scl_io, -- serial clock line
|
1267 |
2 |
zero_gravi |
-- interrupt --
|
1268 |
60 |
zero_gravi |
irq_o => twi_irq -- transfer done IRQ
|
1269 |
2 |
zero_gravi |
);
|
1270 |
60 |
zero_gravi |
resp_bus(RESP_TWI).err <= '0'; -- no access error possible
|
1271 |
2 |
zero_gravi |
end generate;
|
1272 |
|
|
|
1273 |
|
|
neorv32_twi_inst_false:
|
1274 |
44 |
zero_gravi |
if (IO_TWI_EN = false) generate
|
1275 |
60 |
zero_gravi |
resp_bus(RESP_TWI) <= resp_bus_entry_terminate_c;
|
1276 |
70 |
zero_gravi |
--
|
1277 |
65 |
zero_gravi |
twi_sda_io <= 'Z';
|
1278 |
|
|
twi_scl_io <= 'Z';
|
1279 |
2 |
zero_gravi |
twi_cg_en <= '0';
|
1280 |
|
|
twi_irq <= '0';
|
1281 |
|
|
end generate;
|
1282 |
|
|
|
1283 |
|
|
|
1284 |
|
|
-- Pulse-Width Modulation Controller (PWM) ------------------------------------------------
|
1285 |
|
|
-- -------------------------------------------------------------------------------------------
|
1286 |
|
|
neorv32_pwm_inst_true:
|
1287 |
60 |
zero_gravi |
if (IO_PWM_NUM_CH > 0) generate
|
1288 |
2 |
zero_gravi |
neorv32_pwm_inst: neorv32_pwm
|
1289 |
60 |
zero_gravi |
generic map (
|
1290 |
|
|
NUM_CHANNELS => IO_PWM_NUM_CH -- number of PWM channels (0..60)
|
1291 |
|
|
)
|
1292 |
2 |
zero_gravi |
port map (
|
1293 |
|
|
-- host access --
|
1294 |
60 |
zero_gravi |
clk_i => clk_i, -- global clock line
|
1295 |
|
|
addr_i => p_bus.addr, -- address
|
1296 |
|
|
rden_i => io_rden, -- read enable
|
1297 |
|
|
wren_i => io_wren, -- write enable
|
1298 |
|
|
data_i => p_bus.wdata, -- data in
|
1299 |
|
|
data_o => resp_bus(RESP_PWM).rdata, -- data out
|
1300 |
|
|
ack_o => resp_bus(RESP_PWM).ack, -- transfer acknowledge
|
1301 |
2 |
zero_gravi |
-- clock generator --
|
1302 |
60 |
zero_gravi |
clkgen_en_o => pwm_cg_en, -- enable clock generator
|
1303 |
2 |
zero_gravi |
clkgen_i => clk_gen,
|
1304 |
|
|
-- pwm output channels --
|
1305 |
|
|
pwm_o => pwm_o
|
1306 |
|
|
);
|
1307 |
60 |
zero_gravi |
resp_bus(RESP_PWM).err <= '0'; -- no access error possible
|
1308 |
2 |
zero_gravi |
end generate;
|
1309 |
|
|
|
1310 |
|
|
neorv32_pwm_inst_false:
|
1311 |
60 |
zero_gravi |
if (IO_PWM_NUM_CH = 0) generate
|
1312 |
|
|
resp_bus(RESP_PWM) <= resp_bus_entry_terminate_c;
|
1313 |
70 |
zero_gravi |
--
|
1314 |
2 |
zero_gravi |
pwm_cg_en <= '0';
|
1315 |
|
|
pwm_o <= (others => '0');
|
1316 |
|
|
end generate;
|
1317 |
|
|
|
1318 |
|
|
|
1319 |
|
|
-- True Random Number Generator (TRNG) ----------------------------------------------------
|
1320 |
|
|
-- -------------------------------------------------------------------------------------------
|
1321 |
|
|
neorv32_trng_inst_true:
|
1322 |
44 |
zero_gravi |
if (IO_TRNG_EN = true) generate
|
1323 |
2 |
zero_gravi |
neorv32_trng_inst: neorv32_trng
|
1324 |
|
|
port map (
|
1325 |
|
|
-- host access --
|
1326 |
60 |
zero_gravi |
clk_i => clk_i, -- global clock line
|
1327 |
|
|
addr_i => p_bus.addr, -- address
|
1328 |
|
|
rden_i => io_rden, -- read enable
|
1329 |
|
|
wren_i => io_wren, -- write enable
|
1330 |
|
|
data_i => p_bus.wdata, -- data in
|
1331 |
|
|
data_o => resp_bus(RESP_TRNG).rdata, -- data out
|
1332 |
|
|
ack_o => resp_bus(RESP_TRNG).ack -- transfer acknowledge
|
1333 |
2 |
zero_gravi |
);
|
1334 |
60 |
zero_gravi |
resp_bus(RESP_TRNG).err <= '0'; -- no access error possible
|
1335 |
2 |
zero_gravi |
end generate;
|
1336 |
|
|
|
1337 |
|
|
neorv32_trng_inst_false:
|
1338 |
44 |
zero_gravi |
if (IO_TRNG_EN = false) generate
|
1339 |
60 |
zero_gravi |
resp_bus(RESP_TRNG) <= resp_bus_entry_terminate_c;
|
1340 |
2 |
zero_gravi |
end generate;
|
1341 |
|
|
|
1342 |
|
|
|
1343 |
52 |
zero_gravi |
-- Smart LED (WS2811/WS2812) Interface (NEOLED) -------------------------------------------
|
1344 |
|
|
-- -------------------------------------------------------------------------------------------
|
1345 |
|
|
neorv32_neoled_inst_true:
|
1346 |
|
|
if (IO_NEOLED_EN = true) generate
|
1347 |
|
|
neorv32_neoled_inst: neorv32_neoled
|
1348 |
62 |
zero_gravi |
generic map (
|
1349 |
|
|
FIFO_DEPTH => IO_NEOLED_TX_FIFO -- TX FIFO depth (1..32k, power of two)
|
1350 |
|
|
)
|
1351 |
52 |
zero_gravi |
port map (
|
1352 |
|
|
-- host access --
|
1353 |
60 |
zero_gravi |
clk_i => clk_i, -- global clock line
|
1354 |
|
|
addr_i => p_bus.addr, -- address
|
1355 |
|
|
rden_i => io_rden, -- read enable
|
1356 |
|
|
wren_i => io_wren, -- write enable
|
1357 |
|
|
data_i => p_bus.wdata, -- data in
|
1358 |
|
|
data_o => resp_bus(RESP_NEOLED).rdata, -- data out
|
1359 |
|
|
ack_o => resp_bus(RESP_NEOLED).ack, -- transfer acknowledge
|
1360 |
52 |
zero_gravi |
-- clock generator --
|
1361 |
60 |
zero_gravi |
clkgen_en_o => neoled_cg_en, -- enable clock generator
|
1362 |
52 |
zero_gravi |
clkgen_i => clk_gen,
|
1363 |
|
|
-- interrupt --
|
1364 |
60 |
zero_gravi |
irq_o => neoled_irq, -- interrupt request
|
1365 |
52 |
zero_gravi |
-- NEOLED output --
|
1366 |
60 |
zero_gravi |
neoled_o => neoled_o -- serial async data line
|
1367 |
52 |
zero_gravi |
);
|
1368 |
60 |
zero_gravi |
resp_bus(RESP_NEOLED).err <= '0'; -- no access error possible
|
1369 |
52 |
zero_gravi |
end generate;
|
1370 |
|
|
|
1371 |
|
|
neorv32_neoled_inst_false:
|
1372 |
|
|
if (IO_NEOLED_EN = false) generate
|
1373 |
60 |
zero_gravi |
resp_bus(RESP_NEOLED) <= resp_bus_entry_terminate_c;
|
1374 |
70 |
zero_gravi |
--
|
1375 |
52 |
zero_gravi |
neoled_cg_en <= '0';
|
1376 |
|
|
neoled_irq <= '0';
|
1377 |
|
|
neoled_o <= '0';
|
1378 |
|
|
end generate;
|
1379 |
|
|
|
1380 |
|
|
|
1381 |
61 |
zero_gravi |
-- Stream Link Interface (SLINK) ----------------------------------------------------------
|
1382 |
|
|
-- -------------------------------------------------------------------------------------------
|
1383 |
|
|
neorv32_slink_inst_true:
|
1384 |
|
|
if (io_slink_en_c = true) generate
|
1385 |
|
|
neorv32_slink_inst: neorv32_slink
|
1386 |
|
|
generic map (
|
1387 |
|
|
SLINK_NUM_TX => SLINK_NUM_TX, -- number of TX links (0..8)
|
1388 |
|
|
SLINK_NUM_RX => SLINK_NUM_RX, -- number of TX links (0..8)
|
1389 |
|
|
SLINK_TX_FIFO => SLINK_TX_FIFO, -- TX fifo depth, has to be a power of two
|
1390 |
|
|
SLINK_RX_FIFO => SLINK_RX_FIFO -- RX fifo depth, has to be a power of two
|
1391 |
|
|
)
|
1392 |
|
|
port map (
|
1393 |
|
|
-- host access --
|
1394 |
|
|
clk_i => clk_i, -- global clock line
|
1395 |
|
|
addr_i => p_bus.addr, -- address
|
1396 |
|
|
rden_i => io_rden, -- read enable
|
1397 |
|
|
wren_i => io_wren, -- write enable
|
1398 |
|
|
data_i => p_bus.wdata, -- data in
|
1399 |
|
|
data_o => resp_bus(RESP_SLINK).rdata, -- data out
|
1400 |
|
|
ack_o => resp_bus(RESP_SLINK).ack, -- transfer acknowledge
|
1401 |
|
|
-- interrupt --
|
1402 |
|
|
irq_tx_o => slink_tx_irq, -- transmission done
|
1403 |
|
|
irq_rx_o => slink_rx_irq, -- data received
|
1404 |
|
|
-- TX stream interfaces --
|
1405 |
|
|
slink_tx_dat_o => slink_tx_dat_o, -- output data
|
1406 |
|
|
slink_tx_val_o => slink_tx_val_o, -- valid output
|
1407 |
|
|
slink_tx_rdy_i => slink_tx_rdy_i, -- ready to send
|
1408 |
|
|
-- RX stream interfaces --
|
1409 |
|
|
slink_rx_dat_i => slink_rx_dat_i, -- input data
|
1410 |
|
|
slink_rx_val_i => slink_rx_val_i, -- valid input
|
1411 |
|
|
slink_rx_rdy_o => slink_rx_rdy_o -- ready to receive
|
1412 |
|
|
);
|
1413 |
|
|
resp_bus(RESP_SLINK).err <= '0'; -- no access error possible
|
1414 |
|
|
end generate;
|
1415 |
|
|
|
1416 |
|
|
neorv32_slink_inst_false:
|
1417 |
|
|
if (io_slink_en_c = false) generate
|
1418 |
|
|
resp_bus(RESP_SLINK) <= resp_bus_entry_terminate_c;
|
1419 |
70 |
zero_gravi |
--
|
1420 |
61 |
zero_gravi |
slink_tx_irq <= '0';
|
1421 |
|
|
slink_rx_irq <= '0';
|
1422 |
|
|
slink_tx_dat_o <= (others => (others => '0'));
|
1423 |
|
|
slink_tx_val_o <= (others => '0');
|
1424 |
|
|
slink_rx_rdy_o <= (others => '0');
|
1425 |
|
|
end generate;
|
1426 |
|
|
|
1427 |
|
|
|
1428 |
|
|
-- External Interrupt Controller (XIRQ) ---------------------------------------------------
|
1429 |
|
|
-- -------------------------------------------------------------------------------------------
|
1430 |
|
|
neorv32_xirq_inst_true:
|
1431 |
|
|
if (XIRQ_NUM_CH > 0) generate
|
1432 |
|
|
neorv32_slink_inst: neorv32_xirq
|
1433 |
|
|
generic map (
|
1434 |
|
|
XIRQ_NUM_CH => XIRQ_NUM_CH, -- number of external IRQ channels (0..32)
|
1435 |
|
|
XIRQ_TRIGGER_TYPE => XIRQ_TRIGGER_TYPE, -- trigger type: 0=level, 1=edge
|
1436 |
|
|
XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
|
1437 |
|
|
)
|
1438 |
|
|
port map (
|
1439 |
|
|
-- host access --
|
1440 |
|
|
clk_i => clk_i, -- global clock line
|
1441 |
|
|
addr_i => p_bus.addr, -- address
|
1442 |
|
|
rden_i => io_rden, -- read enable
|
1443 |
|
|
wren_i => io_wren, -- write enable
|
1444 |
|
|
data_i => p_bus.wdata, -- data in
|
1445 |
|
|
data_o => resp_bus(RESP_XIRQ).rdata, -- data out
|
1446 |
|
|
ack_o => resp_bus(RESP_XIRQ).ack, -- transfer acknowledge
|
1447 |
|
|
-- external interrupt lines --
|
1448 |
|
|
xirq_i => xirq_i,
|
1449 |
|
|
-- CPU interrupt --
|
1450 |
|
|
cpu_irq_o => xirq_irq
|
1451 |
|
|
);
|
1452 |
|
|
resp_bus(RESP_XIRQ).err <= '0'; -- no access error possible
|
1453 |
|
|
end generate;
|
1454 |
|
|
|
1455 |
|
|
neorv32_xirq_inst_false:
|
1456 |
|
|
if (XIRQ_NUM_CH = 0) generate
|
1457 |
|
|
resp_bus(RESP_XIRQ) <= resp_bus_entry_terminate_c;
|
1458 |
70 |
zero_gravi |
--
|
1459 |
61 |
zero_gravi |
xirq_irq <= '0';
|
1460 |
|
|
end generate;
|
1461 |
|
|
|
1462 |
|
|
|
1463 |
67 |
zero_gravi |
-- General Purpose Timer (GPTMR) ----------------------------------------------------------
|
1464 |
|
|
-- -------------------------------------------------------------------------------------------
|
1465 |
|
|
neorv32_gptmr_inst_true:
|
1466 |
|
|
if (IO_GPTMR_EN = true) generate
|
1467 |
|
|
neorv32_gptmr_inst: neorv32_gptmr
|
1468 |
|
|
port map (
|
1469 |
|
|
-- host access --
|
1470 |
|
|
clk_i => clk_i, -- global clock line
|
1471 |
|
|
addr_i => p_bus.addr, -- address
|
1472 |
|
|
rden_i => io_rden, -- read enable
|
1473 |
|
|
wren_i => io_wren, -- write enable
|
1474 |
|
|
data_i => p_bus.wdata, -- data in
|
1475 |
|
|
data_o => resp_bus(RESP_GPTMR).rdata, -- data out
|
1476 |
|
|
ack_o => resp_bus(RESP_GPTMR).ack, -- transfer acknowledge
|
1477 |
|
|
-- clock generator --
|
1478 |
|
|
clkgen_en_o => gptmr_cg_en, -- enable clock generator
|
1479 |
|
|
clkgen_i => clk_gen,
|
1480 |
|
|
-- interrupt --
|
1481 |
|
|
irq_o => gptmr_irq -- transmission done interrupt
|
1482 |
|
|
);
|
1483 |
|
|
resp_bus(RESP_GPTMR).err <= '0'; -- no access error possible
|
1484 |
|
|
end generate;
|
1485 |
|
|
|
1486 |
|
|
neorv32_gptmr_inst_false:
|
1487 |
|
|
if (IO_GPTMR_EN = false) generate
|
1488 |
|
|
resp_bus(RESP_GPTMR) <= resp_bus_entry_terminate_c;
|
1489 |
70 |
zero_gravi |
--
|
1490 |
67 |
zero_gravi |
gptmr_cg_en <= '0';
|
1491 |
|
|
gptmr_irq <= '0';
|
1492 |
|
|
end generate;
|
1493 |
|
|
|
1494 |
|
|
|
1495 |
12 |
zero_gravi |
-- System Configuration Information Memory (SYSINFO) --------------------------------------
|
1496 |
|
|
-- -------------------------------------------------------------------------------------------
|
1497 |
|
|
neorv32_sysinfo_inst: neorv32_sysinfo
|
1498 |
|
|
generic map (
|
1499 |
|
|
-- General --
|
1500 |
72 |
zero_gravi |
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
|
1501 |
|
|
INT_BOOTLOADER_EN => INT_BOOTLOADER_EN, -- implement processor-internal bootloader?
|
1502 |
63 |
zero_gravi |
-- Physical memory protection (PMP) --
|
1503 |
73 |
zero_gravi |
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..16)
|
1504 |
23 |
zero_gravi |
-- internal Instruction memory --
|
1505 |
72 |
zero_gravi |
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
|
1506 |
|
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
1507 |
23 |
zero_gravi |
-- Internal Data memory --
|
1508 |
72 |
zero_gravi |
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
|
1509 |
|
|
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
|
1510 |
41 |
zero_gravi |
-- Internal Cache memory --
|
1511 |
72 |
zero_gravi |
ICACHE_EN => ICACHE_EN, -- implement instruction cache
|
1512 |
|
|
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 2), has to be a power of 2
|
1513 |
|
|
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2
|
1514 |
|
|
ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity (min 1), has to be a power 2
|
1515 |
23 |
zero_gravi |
-- External memory interface --
|
1516 |
72 |
zero_gravi |
MEM_EXT_EN => MEM_EXT_EN, -- implement external memory bus interface?
|
1517 |
|
|
MEM_EXT_BIG_ENDIAN => MEM_EXT_BIG_ENDIAN, -- byte order: true=big-endian, false=little-endian
|
1518 |
59 |
zero_gravi |
-- On-Chip Debugger --
|
1519 |
72 |
zero_gravi |
ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, -- implement OCD?
|
1520 |
12 |
zero_gravi |
-- Processor peripherals --
|
1521 |
72 |
zero_gravi |
IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)?
|
1522 |
|
|
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)?
|
1523 |
|
|
IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
1524 |
|
|
IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
1525 |
|
|
IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)?
|
1526 |
|
|
IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)?
|
1527 |
|
|
IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement
|
1528 |
|
|
IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)?
|
1529 |
|
|
IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)?
|
1530 |
|
|
IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)?
|
1531 |
|
|
IO_SLINK_EN => io_slink_en_c, -- implement stream link interface?
|
1532 |
|
|
IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
|
1533 |
|
|
IO_XIRQ_NUM_CH => XIRQ_NUM_CH, -- number of external interrupt (XIRQ) channels to implement
|
1534 |
|
|
IO_GPTMR_EN => IO_GPTMR_EN, -- implement general purpose timer (GPTMR)?
|
1535 |
|
|
IO_XIP_EN => IO_XIP_EN -- implement execute in place module (XIP)?
|
1536 |
12 |
zero_gravi |
)
|
1537 |
|
|
port map (
|
1538 |
|
|
-- host access --
|
1539 |
60 |
zero_gravi |
clk_i => clk_i, -- global clock line
|
1540 |
|
|
addr_i => p_bus.addr, -- address
|
1541 |
|
|
rden_i => io_rden, -- read enable
|
1542 |
70 |
zero_gravi |
wren_i => io_wren, -- write enable
|
1543 |
60 |
zero_gravi |
data_o => resp_bus(RESP_SYSINFO).rdata, -- data out
|
1544 |
70 |
zero_gravi |
ack_o => resp_bus(RESP_SYSINFO).ack, -- transfer acknowledge
|
1545 |
|
|
err_o => resp_bus(RESP_SYSINFO).err -- transfer error
|
1546 |
12 |
zero_gravi |
);
|
1547 |
|
|
|
1548 |
|
|
|
1549 |
59 |
zero_gravi |
-- **************************************************************************************************************************
|
1550 |
|
|
-- On-Chip Debugger Complex
|
1551 |
|
|
-- **************************************************************************************************************************
|
1552 |
|
|
|
1553 |
|
|
|
1554 |
|
|
-- On-Chip Debugger - Debug Module (DM) ---------------------------------------------------
|
1555 |
|
|
-- -------------------------------------------------------------------------------------------
|
1556 |
|
|
neorv32_neorv32_debug_dm_true:
|
1557 |
|
|
if (ON_CHIP_DEBUGGER_EN = true) generate
|
1558 |
|
|
neorv32_debug_dm_inst: neorv32_debug_dm
|
1559 |
|
|
port map (
|
1560 |
|
|
-- global control --
|
1561 |
60 |
zero_gravi |
clk_i => clk_i, -- global clock line
|
1562 |
|
|
rstn_i => ext_rstn, -- external reset, low-active
|
1563 |
59 |
zero_gravi |
-- debug module interface (DMI) --
|
1564 |
|
|
dmi_rstn_i => dmi.rstn,
|
1565 |
|
|
dmi_req_valid_i => dmi.req_valid,
|
1566 |
|
|
dmi_req_ready_o => dmi.req_ready,
|
1567 |
|
|
dmi_req_addr_i => dmi.req_addr,
|
1568 |
|
|
dmi_req_op_i => dmi.req_op,
|
1569 |
|
|
dmi_req_data_i => dmi.req_data,
|
1570 |
60 |
zero_gravi |
dmi_resp_valid_o => dmi.resp_valid, -- response valid when set
|
1571 |
|
|
dmi_resp_ready_i => dmi.resp_ready, -- ready to receive respond
|
1572 |
59 |
zero_gravi |
dmi_resp_data_o => dmi.resp_data,
|
1573 |
60 |
zero_gravi |
dmi_resp_err_o => dmi.resp_err, -- 0=ok, 1=error
|
1574 |
59 |
zero_gravi |
-- CPU bus access --
|
1575 |
71 |
zero_gravi |
cpu_debug_i => debug_mode, -- CPU is in debug mode
|
1576 |
60 |
zero_gravi |
cpu_addr_i => p_bus.addr, -- address
|
1577 |
|
|
cpu_rden_i => p_bus.re, -- read enable
|
1578 |
|
|
cpu_wren_i => p_bus.we, -- write enable
|
1579 |
|
|
cpu_data_i => p_bus.wdata, -- data in
|
1580 |
|
|
cpu_data_o => resp_bus(RESP_OCD).rdata, -- data out
|
1581 |
|
|
cpu_ack_o => resp_bus(RESP_OCD).ack, -- transfer acknowledge
|
1582 |
59 |
zero_gravi |
-- CPU control --
|
1583 |
60 |
zero_gravi |
cpu_ndmrstn_o => dci_ndmrstn, -- soc reset
|
1584 |
|
|
cpu_halt_req_o => dci_halt_req -- request hart to halt (enter debug mode)
|
1585 |
59 |
zero_gravi |
);
|
1586 |
60 |
zero_gravi |
resp_bus(RESP_OCD).err <= '0'; -- no access error possible
|
1587 |
59 |
zero_gravi |
end generate;
|
1588 |
|
|
|
1589 |
|
|
neorv32_debug_dm_false:
|
1590 |
|
|
if (ON_CHIP_DEBUGGER_EN = false) generate
|
1591 |
70 |
zero_gravi |
--
|
1592 |
59 |
zero_gravi |
dmi.req_ready <= '0';
|
1593 |
|
|
dmi.resp_valid <= '0';
|
1594 |
|
|
dmi.resp_data <= (others => '0');
|
1595 |
|
|
dmi.resp_err <= '0';
|
1596 |
|
|
--
|
1597 |
60 |
zero_gravi |
resp_bus(RESP_OCD) <= resp_bus_entry_terminate_c;
|
1598 |
|
|
dci_ndmrstn <= '1';
|
1599 |
|
|
dci_halt_req <= '0';
|
1600 |
59 |
zero_gravi |
end generate;
|
1601 |
|
|
|
1602 |
|
|
|
1603 |
|
|
-- On-Chip Debugger - Debug Transport Module (DTM) ----------------------------------------
|
1604 |
|
|
-- -------------------------------------------------------------------------------------------
|
1605 |
|
|
neorv32_neorv32_debug_dtm_true:
|
1606 |
|
|
if (ON_CHIP_DEBUGGER_EN = true) generate
|
1607 |
|
|
neorv32_debug_dtm_inst: neorv32_debug_dtm
|
1608 |
|
|
generic map (
|
1609 |
|
|
IDCODE_VERSION => jtag_tap_idcode_version_c, -- version
|
1610 |
|
|
IDCODE_PARTID => jtag_tap_idcode_partid_c, -- part number
|
1611 |
|
|
IDCODE_MANID => jtag_tap_idcode_manid_c -- manufacturer id
|
1612 |
|
|
)
|
1613 |
|
|
port map (
|
1614 |
|
|
-- global control --
|
1615 |
|
|
clk_i => clk_i, -- global clock line
|
1616 |
|
|
rstn_i => ext_rstn, -- external reset, low-active
|
1617 |
|
|
-- jtag connection --
|
1618 |
|
|
jtag_trst_i => jtag_trst_i,
|
1619 |
|
|
jtag_tck_i => jtag_tck_i,
|
1620 |
|
|
jtag_tdi_i => jtag_tdi_i,
|
1621 |
|
|
jtag_tdo_o => jtag_tdo_o,
|
1622 |
|
|
jtag_tms_i => jtag_tms_i,
|
1623 |
|
|
-- debug module interface (DMI) --
|
1624 |
|
|
dmi_rstn_o => dmi.rstn,
|
1625 |
|
|
dmi_req_valid_o => dmi.req_valid,
|
1626 |
|
|
dmi_req_ready_i => dmi.req_ready, -- DMI is allowed to make new requests when set
|
1627 |
|
|
dmi_req_addr_o => dmi.req_addr,
|
1628 |
|
|
dmi_req_op_o => dmi.req_op, -- 0=read, 1=write
|
1629 |
|
|
dmi_req_data_o => dmi.req_data,
|
1630 |
|
|
dmi_resp_valid_i => dmi.resp_valid, -- response valid when set
|
1631 |
|
|
dmi_resp_ready_o => dmi.resp_ready, -- ready to receive respond
|
1632 |
|
|
dmi_resp_data_i => dmi.resp_data,
|
1633 |
|
|
dmi_resp_err_i => dmi.resp_err -- 0=ok, 1=error
|
1634 |
|
|
);
|
1635 |
|
|
end generate;
|
1636 |
|
|
|
1637 |
|
|
neorv32_debug_dtm_false:
|
1638 |
|
|
if (ON_CHIP_DEBUGGER_EN = false) generate
|
1639 |
|
|
jtag_tdo_o <= jtag_tdi_i; -- feed-through
|
1640 |
|
|
--
|
1641 |
|
|
dmi.rstn <= '0';
|
1642 |
|
|
dmi.req_valid <= '0';
|
1643 |
|
|
dmi.req_addr <= (others => '0');
|
1644 |
|
|
dmi.req_op <= '0';
|
1645 |
|
|
dmi.req_data <= (others => '0');
|
1646 |
|
|
dmi.resp_ready <= '0';
|
1647 |
|
|
end generate;
|
1648 |
|
|
|
1649 |
|
|
|
1650 |
2 |
zero_gravi |
end neorv32_top_rtl;
|