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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_uart.vhd] - Blame information for rev 23

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1 2 zero_gravi
-- #################################################################################################
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-- # << NEORV32 - Universal Asynchronous Receiver and Transmitter (UART) >>                        #
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-- # ********************************************************************************************* #
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-- # Fixed frame config: 8-bit, no parity bit, 1 stop bit, programmable BAUD rate (via clock pre-  #
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-- # scaler and BAUD value config register.                                                        #
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-- # Interrupt: UART_RX_available or UART_TX_done                                                  #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
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-- #                                                                                               #
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-- # Redistribution and use in source and binary forms, with or without modification, are          #
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-- # permitted provided that the following conditions are met:                                     #
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-- #                                                                                               #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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-- #    conditions and the following disclaimer.                                                   #
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-- #                                                                                               #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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-- #    conditions and the following disclaimer in the documentation and/or other materials        #
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-- #    provided with the distribution.                                                            #
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-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
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-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_uart is
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  port (
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    -- host access --
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    clk_i       : in  std_ulogic; -- global clock line
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    addr_i      : in  std_ulogic_vector(31 downto 0); -- address
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    rden_i      : in  std_ulogic; -- read enable
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    wren_i      : in  std_ulogic; -- write enable
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    data_i      : in  std_ulogic_vector(31 downto 0); -- data in
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    data_o      : out std_ulogic_vector(31 downto 0); -- data out
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    ack_o       : out std_ulogic; -- transfer acknowledge
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    -- clock generator --
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    clkgen_en_o : out std_ulogic; -- enable clock generator
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    clkgen_i    : in  std_ulogic_vector(07 downto 0);
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    -- com lines --
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    uart_txd_o  : out std_ulogic;
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    uart_rxd_i  : in  std_ulogic;
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    -- interrupts --
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    uart_irq_o  : out std_ulogic  -- uart rx/tx interrupt
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  );
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end neorv32_uart;
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architecture neorv32_uart_rtl of neorv32_uart is
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  -- IO space: module base address --
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  constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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  constant lo_abb_c : natural := index_size_f(uart_size_c); -- low address boundary bit
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  -- accessible regs --
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  signal ctrl : std_ulogic_vector(31 downto 0);
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  -- control reg bits --
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  constant ctrl_uart_baud00_c  : natural :=  0; -- r/w: UART baud config bit 0
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  constant ctrl_uart_baud01_c  : natural :=  1; -- r/w: UART baud config bit 1
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  constant ctrl_uart_baud02_c  : natural :=  2; -- r/w: UART baud config bit 2
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  constant ctrl_uart_baud03_c  : natural :=  3; -- r/w: UART baud config bit 3
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  constant ctrl_uart_baud04_c  : natural :=  4; -- r/w: UART baud config bit 4
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  constant ctrl_uart_baud05_c  : natural :=  5; -- r/w: UART baud config bit 5
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  constant ctrl_uart_baud06_c  : natural :=  6; -- r/w: UART baud config bit 6
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  constant ctrl_uart_baud07_c  : natural :=  7; -- r/w: UART baud config bit 7
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  --
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  constant ctrl_uart_baud08_c  : natural :=  8; -- r/w: UART baud config bit 8
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  constant ctrl_uart_baud09_c  : natural :=  9; -- r/w: UART baud config bit 9
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  constant ctrl_uart_baud10_c  : natural := 10; -- r/w: UART baud config bit 10
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  constant ctrl_uart_baud11_c  : natural := 11; -- r/w: UART baud config bit 11
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  --
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  constant ctrl_uart_prsc0_c   : natural := 24; -- r/w: UART baud prsc bit 0
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  constant ctrl_uart_prsc1_c   : natural := 25; -- r/w: UART baud prsc bit 1
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  constant ctrl_uart_prsc2_c   : natural := 26; -- r/w: UART baud prsc bit 2
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  constant ctrl_uart_rxovr_c   : natural := 27; -- r/-: UART RX overrun
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  constant ctrl_uart_en_c      : natural := 28; -- r/w: UART enable
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  constant ctrl_uart_rx_irq_c  : natural := 29; -- r/w: UART rx done interrupt enable
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  constant ctrl_uart_tx_irq_c  : natural := 30; -- r/w: UART tx done interrupt enable
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  constant ctrl_uart_tx_busy_c : natural := 31; -- r/-: UART transmitter is busy
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  -- data register flags --
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  constant data_rx_avail_c : natural := 31; -- r/-: Rx data available/valid
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103
  -- access control --
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  signal acc_en : std_ulogic; -- module access enable
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  signal addr   : std_ulogic_vector(31 downto 0); -- access address
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  signal wr_en  : std_ulogic; -- word write enable
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  signal rd_en  : std_ulogic; -- read enable
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  -- clock generator --
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  signal uart_clk : std_ulogic;
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112
  -- uart tx unit --
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  signal uart_tx_busy     : std_ulogic;
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  signal uart_tx_done     : std_ulogic;
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  signal uart_tx_bitcnt   : std_ulogic_vector(03 downto 0);
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  signal uart_tx_sreg     : std_ulogic_vector(09 downto 0) := (others => '1'); -- just for simulation
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  signal uart_tx_baud_cnt : std_ulogic_vector(11 downto 0);
118
 
119
  -- uart rx unit --
120
  signal uart_rx_sync     : std_ulogic_vector(04 downto 0);
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  signal uart_rx_avail    : std_ulogic_vector(01 downto 0);
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  signal uart_rx_busy     : std_ulogic;
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  signal uart_rx_busy_ff  : std_ulogic;
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  signal uart_rx_bitcnt   : std_ulogic_vector(03 downto 0);
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  signal uart_rx_sreg     : std_ulogic_vector(08 downto 0);
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  signal uart_rx_reg      : std_ulogic_vector(07 downto 0);
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  signal uart_rx_baud_cnt : std_ulogic_vector(11 downto 0);
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129
begin
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131
  -- Access Control -------------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = uart_base_c(hi_abb_c downto lo_abb_c)) else '0';
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  addr   <= uart_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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  wr_en  <= acc_en and wren_i;
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  rd_en  <= acc_en and rden_i;
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138
 
139
  -- Read/Write Access ----------------------------------------------------------------------
140
  -- -------------------------------------------------------------------------------------------
141
  rw_access: process(clk_i)
142
  begin
143
    if rising_edge(clk_i) then
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      ack_o <= acc_en and (rden_i or wren_i);
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      -- write access --
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      if (wr_en = '1') then
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        if (addr = uart_ctrl_addr_c) then
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          ctrl <= data_i;
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        end if;
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      end if;
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      -- read access --
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      data_o <= (others => '0');
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      if (rd_en = '1') then
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        if (addr = uart_ctrl_addr_c) then
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          data_o <= ctrl; -- default
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          data_o(ctrl_uart_rxovr_c)   <= uart_rx_avail(0) and uart_rx_avail(1);
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          data_o(ctrl_uart_tx_busy_c) <= uart_tx_busy;
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        else -- uart_rtx_addr_c
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          data_o(data_rx_avail_c) <= uart_rx_avail(0);
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          data_o(07 downto 0)     <= uart_rx_reg;
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        end if;
162
      end if;
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    end if;
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  end process rw_access;
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  -- Clock Selection ------------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  -- clock enable --
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  clkgen_en_o <= ctrl(ctrl_uart_en_c);
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  -- uart clock select --
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  uart_clk <= clkgen_i(to_integer(unsigned(ctrl(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c))));
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  -- UART Transmitter -----------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  uart_tx_unit: process(clk_i)
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  begin
180
    if rising_edge(clk_i) then
181
      -- serial engine --
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      uart_tx_done <= '0';
183
      if (uart_tx_busy = '0') or (ctrl(ctrl_uart_en_c) = '0') then -- idle or disabled
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        uart_tx_busy     <= '0';
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        uart_tx_baud_cnt <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
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        uart_tx_bitcnt   <= "1010"; -- 10 bit
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        if (wr_en = '1') and (ctrl(ctrl_uart_en_c) = '1') and (addr = uart_rtx_addr_c) then
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          uart_tx_sreg <= '1' & data_i(7 downto 0) & '0'; -- stopbit & data & startbit
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          uart_tx_busy <= '1';
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        end if;
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      elsif (uart_clk = '1') then
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        if (uart_tx_baud_cnt = x"000") then
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          uart_tx_baud_cnt <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
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          uart_tx_bitcnt   <= std_ulogic_vector(unsigned(uart_tx_bitcnt) - 1);
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          uart_tx_sreg     <= '1' & uart_tx_sreg(9 downto 1);
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          if (uart_tx_bitcnt = "0000") then
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            uart_tx_busy <= '0'; -- done
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            uart_tx_done <= '1';
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          end if;
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        else
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          uart_tx_baud_cnt <= std_ulogic_vector(unsigned(uart_tx_baud_cnt) - 1);
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        end if;
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      end if;
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      -- transmitter output --
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      uart_txd_o <= uart_tx_sreg(0);
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    end if;
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  end process uart_tx_unit;
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  -- UART Receiver --------------------------------------------------------------------------
211
  -- -------------------------------------------------------------------------------------------
212
  uart_rx_unit: process(clk_i)
213
  begin
214
    if rising_edge(clk_i) then
215
      -- input synchronizer --
216
      uart_rx_sync <= uart_rxd_i & uart_rx_sync(4 downto 1);
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      -- serial engine --
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      if (uart_rx_busy = '0') or (ctrl(ctrl_uart_en_c) = '0') then -- idle or disabled
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        uart_rx_busy     <= '0';
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        uart_rx_baud_cnt <= '0' & ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud01_c); -- half baud rate to sample in middle of bit
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        uart_rx_bitcnt   <= "1001"; -- 9 bit (startbit + 8 data bits, ignore stop bit/s)
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        if (ctrl(ctrl_uart_en_c) = '0') then
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          uart_rx_reg <= (others => '0'); -- to ensure defined state when reading
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        elsif (uart_rx_sync(2 downto 0) = "001") then -- start bit? (falling edge)
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          uart_rx_busy <= '1';
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        end if;
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      elsif (uart_clk = '1') then
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        if (uart_rx_baud_cnt = x"000") then
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          uart_rx_baud_cnt <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
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          uart_rx_bitcnt   <= std_ulogic_vector(unsigned(uart_rx_bitcnt) - 1);
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          uart_rx_sreg     <= uart_rx_sync(0) & uart_rx_sreg(8 downto 1);
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          if (uart_rx_bitcnt = "0000") then
234
            uart_rx_busy <= '0'; -- done
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            uart_rx_reg  <= uart_rx_sreg(8 downto 1);
236
          end if;
237
        else
238
          uart_rx_baud_cnt <= std_ulogic_vector(unsigned(uart_rx_baud_cnt) - 1);
239
        end if;
240
      end if;
241
 
242
      -- RX available flag --
243
      uart_rx_busy_ff <= uart_rx_busy;
244
      if (ctrl(ctrl_uart_en_c) = '0') or (((uart_rx_avail(0) = '1') or (uart_rx_avail(1) = '1')) and (rd_en = '1') and (addr = uart_rtx_addr_c)) then
245
        uart_rx_avail <= "00";
246
      elsif (uart_rx_busy_ff = '1') and (uart_rx_busy = '0') then
247
        uart_rx_avail <= uart_rx_avail(0) & '1';
248
      end if;
249
    end if;
250
  end process uart_rx_unit;
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252
 
253
  -- Interrupt ------------------------------------------------------------------------------
254
  -- -------------------------------------------------------------------------------------------
255
  -- UART Rx data available [OR] UART Tx complete
256
  uart_irq_o <= (uart_rx_busy_ff and (not uart_rx_busy) and ctrl(ctrl_uart_rx_irq_c)) or (uart_tx_done and ctrl(ctrl_uart_tx_irq_c));
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end neorv32_uart_rtl;

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