1 |
2 |
zero_gravi |
-- #################################################################################################
|
2 |
50 |
zero_gravi |
-- # << NEORV32 - Universal Asynchronous Receiver and Transmitter (UART0/1) >> #
|
3 |
2 |
zero_gravi |
-- # ********************************************************************************************* #
|
4 |
51 |
zero_gravi |
-- # Frame configuration: 1 start bit, 8 bit data, parity bit (none/even/odd), 1 stop bit, #
|
5 |
65 |
zero_gravi |
-- # programmable BAUD rate via clock pre-scaler and 12-bit BAUD value configuration register, #
|
6 |
|
|
-- # optional configurable RX and TX FIFOs. #
|
7 |
30 |
zero_gravi |
-- # #
|
8 |
65 |
zero_gravi |
-- # Interrupts: Configurable RX and TX interrupt (both triggered by specific FIFO fill-levels) #
|
9 |
|
|
-- # #
|
10 |
51 |
zero_gravi |
-- # Support for RTS("RTR")/CTS hardware flow control: #
|
11 |
65 |
zero_gravi |
-- # * uart_rts_o = 0: RX is ready to receive a new char, enabled via CTRL.ctrl_rts_en_c #
|
12 |
|
|
-- # * uart_cts_i = 0: TX is allowed to send a new char, enabled via CTRL.ctrl_cts_en_c #
|
13 |
51 |
zero_gravi |
-- # #
|
14 |
50 |
zero_gravi |
-- # UART0 / UART1: #
|
15 |
|
|
-- # This module is used for implementing UART0 and UART1. The UART_PRIMARY generic configures the #
|
16 |
65 |
zero_gravi |
-- # interface register addresses and simulation outputs for UART0 (UART_PRIMARY = true) or UART1 #
|
17 |
|
|
-- # (UART_PRIMARY = false). #
|
18 |
50 |
zero_gravi |
-- # #
|
19 |
51 |
zero_gravi |
-- # SIMULATION MODE: #
|
20 |
65 |
zero_gravi |
-- # When the simulation mode is enabled (setting the ctrl.ctrl_sim_en_c bit) any write #
|
21 |
30 |
zero_gravi |
-- # access to the TX register will not trigger any UART activity. Instead, the written data is #
|
22 |
|
|
-- # output to the simulation environment. The lowest 8 bits of the written data are printed as #
|
23 |
50 |
zero_gravi |
-- # ASCII char to the simulator console. #
|
24 |
|
|
-- # This char is also stored to the file "neorv32.uartX.sim_mode.text.out" (where X = 0 for UART0 #
|
25 |
|
|
-- # and X = 1 for UART1). The full 32-bit write data is also stored as 8-digit hexadecimal value #
|
26 |
|
|
-- # to the file "neorv32.uartX.sim_mode.data.out" (where X = 0 for UART0 and X = 1 for UART1). #
|
27 |
51 |
zero_gravi |
-- # No interrupts are triggered when in SIMULATION MODE. #
|
28 |
2 |
zero_gravi |
-- # ********************************************************************************************* #
|
29 |
|
|
-- # BSD 3-Clause License #
|
30 |
|
|
-- # #
|
31 |
48 |
zero_gravi |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
32 |
2 |
zero_gravi |
-- # #
|
33 |
|
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
34 |
|
|
-- # permitted provided that the following conditions are met: #
|
35 |
|
|
-- # #
|
36 |
|
|
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
37 |
|
|
-- # conditions and the following disclaimer. #
|
38 |
|
|
-- # #
|
39 |
|
|
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
40 |
|
|
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
41 |
|
|
-- # provided with the distribution. #
|
42 |
|
|
-- # #
|
43 |
|
|
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
44 |
|
|
-- # endorse or promote products derived from this software without specific prior written #
|
45 |
|
|
-- # permission. #
|
46 |
|
|
-- # #
|
47 |
|
|
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
48 |
|
|
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
49 |
|
|
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
50 |
|
|
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
51 |
|
|
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
52 |
|
|
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
53 |
|
|
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
54 |
|
|
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
55 |
|
|
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
56 |
|
|
-- # ********************************************************************************************* #
|
57 |
|
|
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
58 |
|
|
-- #################################################################################################
|
59 |
|
|
|
60 |
|
|
library ieee;
|
61 |
|
|
use ieee.std_logic_1164.all;
|
62 |
|
|
use ieee.numeric_std.all;
|
63 |
|
|
|
64 |
|
|
library neorv32;
|
65 |
|
|
use neorv32.neorv32_package.all;
|
66 |
65 |
zero_gravi |
use std.textio.all;
|
67 |
2 |
zero_gravi |
|
68 |
|
|
entity neorv32_uart is
|
69 |
50 |
zero_gravi |
generic (
|
70 |
65 |
zero_gravi |
UART_PRIMARY : boolean; -- true = primary UART (UART0), false = secondary UART (UART1)
|
71 |
|
|
UART_RX_FIFO : natural; -- RX fifo depth, has to be a power of two, min 1
|
72 |
|
|
UART_TX_FIFO : natural -- TX fifo depth, has to be a power of two, min 1
|
73 |
50 |
zero_gravi |
);
|
74 |
2 |
zero_gravi |
port (
|
75 |
|
|
-- host access --
|
76 |
|
|
clk_i : in std_ulogic; -- global clock line
|
77 |
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
78 |
|
|
rden_i : in std_ulogic; -- read enable
|
79 |
|
|
wren_i : in std_ulogic; -- write enable
|
80 |
|
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
81 |
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
82 |
|
|
ack_o : out std_ulogic; -- transfer acknowledge
|
83 |
|
|
-- clock generator --
|
84 |
|
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
85 |
|
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
86 |
|
|
-- com lines --
|
87 |
|
|
uart_txd_o : out std_ulogic;
|
88 |
|
|
uart_rxd_i : in std_ulogic;
|
89 |
51 |
zero_gravi |
-- hardware flow control --
|
90 |
|
|
uart_rts_o : out std_ulogic; -- UART.RX ready to receive ("RTR"), low-active, optional
|
91 |
|
|
uart_cts_i : in std_ulogic; -- UART.TX allowed to transmit, low-active, optional
|
92 |
2 |
zero_gravi |
-- interrupts --
|
93 |
48 |
zero_gravi |
irq_rxd_o : out std_ulogic; -- uart data received interrupt
|
94 |
|
|
irq_txd_o : out std_ulogic -- uart transmission done interrupt
|
95 |
2 |
zero_gravi |
);
|
96 |
|
|
end neorv32_uart;
|
97 |
|
|
|
98 |
|
|
architecture neorv32_uart_rtl of neorv32_uart is
|
99 |
|
|
|
100 |
50 |
zero_gravi |
-- interface configuration for UART0 / UART1 --
|
101 |
|
|
constant uart_id_base_c : std_ulogic_vector(data_width_c-1 downto 0) := cond_sel_stdulogicvector_f(UART_PRIMARY, uart0_base_c, uart1_base_c);
|
102 |
|
|
constant uart_id_size_c : natural := cond_sel_natural_f( UART_PRIMARY, uart0_size_c, uart1_size_c);
|
103 |
|
|
constant uart_id_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := cond_sel_stdulogicvector_f(UART_PRIMARY, uart0_ctrl_addr_c, uart1_ctrl_addr_c);
|
104 |
|
|
constant uart_id_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := cond_sel_stdulogicvector_f(UART_PRIMARY, uart0_rtx_addr_c, uart1_rtx_addr_c);
|
105 |
|
|
|
106 |
|
|
-- IO space: module base address --
|
107 |
|
|
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
|
108 |
|
|
constant lo_abb_c : natural := index_size_f(uart_id_size_c); -- low address boundary bit
|
109 |
|
|
|
110 |
30 |
zero_gravi |
-- simulation output configuration --
|
111 |
|
|
constant sim_screen_output_en_c : boolean := true; -- output lowest byte as char to simulator console when enabled
|
112 |
|
|
constant sim_text_output_en_c : boolean := true; -- output lowest byte as char to text file when enabled
|
113 |
66 |
zero_gravi |
constant sim_data_output_en_c : boolean := true; -- dump 32-bit TX word to file when enabled
|
114 |
65 |
zero_gravi |
constant sim_uart_text_file_c : string := cond_sel_string_f(UART_PRIMARY, "neorv32.uart0.sim_mode.text.out", "neorv32.uart1.sim_mode.text.out");
|
115 |
|
|
constant sim_uart_data_file_c : string := cond_sel_string_f(UART_PRIMARY, "neorv32.uart0.sim_mode.data.out", "neorv32.uart1.sim_mode.data.out");
|
116 |
30 |
zero_gravi |
|
117 |
51 |
zero_gravi |
-- control register --
|
118 |
2 |
zero_gravi |
signal ctrl : std_ulogic_vector(31 downto 0);
|
119 |
|
|
|
120 |
51 |
zero_gravi |
-- control register bits --
|
121 |
65 |
zero_gravi |
constant ctrl_baud00_c : natural := 0; -- r/w: baud config bit 0
|
122 |
|
|
constant ctrl_baud01_c : natural := 1; -- r/w: baud config bit 1
|
123 |
|
|
constant ctrl_baud02_c : natural := 2; -- r/w: baud config bit 2
|
124 |
|
|
constant ctrl_baud03_c : natural := 3; -- r/w: baud config bit 3
|
125 |
|
|
constant ctrl_baud04_c : natural := 4; -- r/w: baud config bit 4
|
126 |
|
|
constant ctrl_baud05_c : natural := 5; -- r/w: baud config bit 5
|
127 |
|
|
constant ctrl_baud06_c : natural := 6; -- r/w: baud config bit 6
|
128 |
|
|
constant ctrl_baud07_c : natural := 7; -- r/w: baud config bit 7
|
129 |
|
|
constant ctrl_baud08_c : natural := 8; -- r/w: baud config bit 8
|
130 |
|
|
constant ctrl_baud09_c : natural := 9; -- r/w: baud config bit 9
|
131 |
|
|
constant ctrl_baud10_c : natural := 10; -- r/w: baud config bit 10
|
132 |
|
|
constant ctrl_baud11_c : natural := 11; -- r/w: baud config bit 11
|
133 |
|
|
constant ctrl_sim_en_c : natural := 12; -- r/w: UART <<SIMULATION MODE>> enable
|
134 |
|
|
constant ctrl_rx_empty_c : natural := 13; -- r/-: RX FIFO is empty
|
135 |
|
|
constant ctrl_rx_half_c : natural := 14; -- r/-: RX FIFO is at least half-full
|
136 |
|
|
constant ctrl_rx_full_c : natural := 15; -- r/-: RX FIFO is full
|
137 |
|
|
constant ctrl_tx_empty_c : natural := 16; -- r/-: TX FIFO is empty
|
138 |
|
|
constant ctrl_tx_half_c : natural := 17; -- r/-: TX FIFO is at least half-full
|
139 |
|
|
constant ctrl_tx_full_c : natural := 18; -- r/-: TX FIFO is full
|
140 |
51 |
zero_gravi |
-- ...
|
141 |
65 |
zero_gravi |
constant ctrl_rts_en_c : natural := 20; -- r/w: enable hardware flow control: assert rts_o if ready to receive
|
142 |
|
|
constant ctrl_cts_en_c : natural := 21; -- r/w: enable hardware flow control: send only if cts_i is asserted
|
143 |
|
|
constant ctrl_pmode0_c : natural := 22; -- r/w: Parity config (0=even; 1=odd)
|
144 |
|
|
constant ctrl_pmode1_c : natural := 23; -- r/w: Enable parity bit
|
145 |
|
|
constant ctrl_prsc0_c : natural := 24; -- r/w: baud prsc bit 0
|
146 |
|
|
constant ctrl_prsc1_c : natural := 25; -- r/w: baud prsc bit 1
|
147 |
|
|
constant ctrl_prsc2_c : natural := 26; -- r/w: baud prsc bit 2
|
148 |
|
|
constant ctrl_cts_c : natural := 27; -- r/-: current state of CTS input
|
149 |
|
|
constant ctrl_en_c : natural := 28; -- r/w: UART enable
|
150 |
|
|
constant ctrl_rx_irq_c : natural := 29; -- r/w: RX IRQ mode: 1=FIFO at least half-full; 0=FIFO not empty
|
151 |
|
|
constant ctrl_tx_irq_c : natural := 30; -- r/w: TX IRQ mode: 1=FIFO less than half-full; 0=FIFO not full
|
152 |
|
|
constant ctrl_tx_busy_c : natural := 31; -- r/-: UART transmitter is busy
|
153 |
2 |
zero_gravi |
|
154 |
|
|
-- data register flags --
|
155 |
65 |
zero_gravi |
constant data_lsb_c : natural := 0; -- r/-: received char LSB
|
156 |
|
|
constant data_msb_c : natural := 7; -- r/-: received char MSB
|
157 |
|
|
-- ...
|
158 |
|
|
constant data_rx_perr_c : natural := 28; -- r/-: RX parity error
|
159 |
|
|
constant data_rx_ferr_c : natural := 29; -- r/-: RX frame error
|
160 |
|
|
constant data_rx_overr_c : natural := 30; -- r/-: RX data overrun
|
161 |
|
|
constant data_rx_avail_c : natural := 31; -- r/-: RX data available
|
162 |
2 |
zero_gravi |
|
163 |
|
|
-- access control --
|
164 |
|
|
signal acc_en : std_ulogic; -- module access enable
|
165 |
|
|
signal addr : std_ulogic_vector(31 downto 0); -- access address
|
166 |
68 |
zero_gravi |
signal wren : std_ulogic; -- word write enable
|
167 |
|
|
signal rden : std_ulogic; -- read enable
|
168 |
2 |
zero_gravi |
|
169 |
|
|
-- clock generator --
|
170 |
|
|
signal uart_clk : std_ulogic;
|
171 |
|
|
|
172 |
42 |
zero_gravi |
-- numbers of bits in transmission frame --
|
173 |
66 |
zero_gravi |
signal num_bits : std_ulogic_vector(3 downto 0);
|
174 |
42 |
zero_gravi |
|
175 |
51 |
zero_gravi |
-- hardware flow-control IO buffer --
|
176 |
|
|
signal uart_cts_ff : std_ulogic_vector(1 downto 0);
|
177 |
|
|
signal uart_rts : std_ulogic;
|
178 |
|
|
|
179 |
65 |
zero_gravi |
-- UART transmitter --
|
180 |
|
|
type tx_state_t is (S_TX_IDLE, S_TX_GET, S_TX_CHECK, S_TX_TRANSMIT, S_TX_SIM);
|
181 |
|
|
type tx_engine_t is record
|
182 |
|
|
state : tx_state_t;
|
183 |
|
|
busy : std_ulogic;
|
184 |
68 |
zero_gravi |
done : std_ulogic;
|
185 |
65 |
zero_gravi |
bitcnt : std_ulogic_vector(03 downto 0);
|
186 |
|
|
sreg : std_ulogic_vector(10 downto 0);
|
187 |
|
|
baud_cnt : std_ulogic_vector(11 downto 0);
|
188 |
|
|
cts : std_ulogic; -- allow new transmission when 1
|
189 |
42 |
zero_gravi |
end record;
|
190 |
65 |
zero_gravi |
signal tx_engine : tx_engine_t;
|
191 |
2 |
zero_gravi |
|
192 |
65 |
zero_gravi |
-- UART receiver --
|
193 |
|
|
type rx_state_t is (S_RX_IDLE, S_RX_RECEIVE);
|
194 |
|
|
type rx_engine_t is record
|
195 |
|
|
state : rx_state_t;
|
196 |
68 |
zero_gravi |
done : std_ulogic;
|
197 |
42 |
zero_gravi |
sync : std_ulogic_vector(04 downto 0);
|
198 |
|
|
bitcnt : std_ulogic_vector(03 downto 0);
|
199 |
|
|
sreg : std_ulogic_vector(09 downto 0);
|
200 |
|
|
baud_cnt : std_ulogic_vector(11 downto 0);
|
201 |
65 |
zero_gravi |
overr : std_ulogic;
|
202 |
51 |
zero_gravi |
rtr : std_ulogic; -- ready to receive when 1
|
203 |
42 |
zero_gravi |
end record;
|
204 |
65 |
zero_gravi |
signal rx_engine : rx_engine_t;
|
205 |
2 |
zero_gravi |
|
206 |
65 |
zero_gravi |
-- TX FIFO --
|
207 |
|
|
type tx_buffer_t is record
|
208 |
|
|
we : std_ulogic; -- write enable
|
209 |
|
|
re : std_ulogic; -- read enable
|
210 |
|
|
clear : std_ulogic; -- sync reset, high-active
|
211 |
|
|
wdata : std_ulogic_vector(31 downto 0); -- write data
|
212 |
|
|
rdata : std_ulogic_vector(31 downto 0); -- read data
|
213 |
|
|
avail : std_ulogic; -- data available?
|
214 |
|
|
free : std_ulogic; -- free entry available?
|
215 |
|
|
half : std_ulogic; -- half full
|
216 |
|
|
end record;
|
217 |
|
|
signal tx_buffer : tx_buffer_t;
|
218 |
|
|
|
219 |
|
|
-- RX FIFO --
|
220 |
|
|
type rx_buffer_t is record
|
221 |
|
|
we : std_ulogic; -- write enable
|
222 |
|
|
re : std_ulogic; -- read enable
|
223 |
|
|
clear : std_ulogic; -- sync reset, high-active
|
224 |
|
|
wdata : std_ulogic_vector(9 downto 0); -- write data
|
225 |
|
|
rdata : std_ulogic_vector(9 downto 0); -- read data
|
226 |
|
|
avail : std_ulogic; -- data available?
|
227 |
|
|
free : std_ulogic; -- free entry available?
|
228 |
|
|
half : std_ulogic; -- half full
|
229 |
|
|
end record;
|
230 |
|
|
signal rx_buffer : rx_buffer_t;
|
231 |
|
|
|
232 |
68 |
zero_gravi |
-- interrupt generator --
|
233 |
|
|
type irq_t is record
|
234 |
69 |
zero_gravi |
set : std_ulogic;
|
235 |
|
|
buf : std_ulogic_vector(1 downto 0);
|
236 |
68 |
zero_gravi |
end record;
|
237 |
|
|
signal rx_irq, tx_irq : irq_t;
|
238 |
|
|
|
239 |
2 |
zero_gravi |
begin
|
240 |
|
|
|
241 |
65 |
zero_gravi |
-- Sanity Checks --------------------------------------------------------------------------
|
242 |
|
|
-- -------------------------------------------------------------------------------------------
|
243 |
|
|
assert not (is_power_of_two_f(UART_RX_FIFO) = false) report "NEORV32 PROCESSOR CONFIG ERROR: UART" &
|
244 |
|
|
cond_sel_string_f(UART_PRIMARY, "0", "1") & " <UART_RX_FIFO> has to be a power of two." severity error;
|
245 |
|
|
assert not (is_power_of_two_f(UART_TX_FIFO) = false) report "NEORV32 PROCESSOR CONFIG ERROR: UART" &
|
246 |
|
|
cond_sel_string_f(UART_PRIMARY, "0", "1") & " <UART_TX_FIFO> has to be a power of two." severity error;
|
247 |
|
|
|
248 |
|
|
|
249 |
2 |
zero_gravi |
-- Access Control -------------------------------------------------------------------------
|
250 |
|
|
-- -------------------------------------------------------------------------------------------
|
251 |
50 |
zero_gravi |
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = uart_id_base_c(hi_abb_c downto lo_abb_c)) else '0';
|
252 |
|
|
addr <= uart_id_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
|
253 |
68 |
zero_gravi |
wren <= acc_en and wren_i;
|
254 |
|
|
rden <= acc_en and rden_i;
|
255 |
2 |
zero_gravi |
|
256 |
|
|
|
257 |
|
|
-- Read/Write Access ----------------------------------------------------------------------
|
258 |
|
|
-- -------------------------------------------------------------------------------------------
|
259 |
|
|
rw_access: process(clk_i)
|
260 |
|
|
begin
|
261 |
|
|
if rising_edge(clk_i) then
|
262 |
65 |
zero_gravi |
-- bus access acknowledge --
|
263 |
68 |
zero_gravi |
ack_o <= wren or rden;
|
264 |
65 |
zero_gravi |
|
265 |
2 |
zero_gravi |
-- write access --
|
266 |
68 |
zero_gravi |
if (wren = '1') then
|
267 |
50 |
zero_gravi |
if (addr = uart_id_ctrl_addr_c) then
|
268 |
42 |
zero_gravi |
ctrl <= (others => '0');
|
269 |
65 |
zero_gravi |
ctrl(ctrl_baud11_c downto ctrl_baud00_c) <= data_i(ctrl_baud11_c downto ctrl_baud00_c);
|
270 |
|
|
ctrl(ctrl_sim_en_c) <= data_i(ctrl_sim_en_c);
|
271 |
|
|
ctrl(ctrl_pmode1_c downto ctrl_pmode0_c) <= data_i(ctrl_pmode1_c downto ctrl_pmode0_c);
|
272 |
|
|
ctrl(ctrl_prsc2_c downto ctrl_prsc0_c) <= data_i(ctrl_prsc2_c downto ctrl_prsc0_c);
|
273 |
|
|
ctrl(ctrl_rts_en_c) <= data_i(ctrl_rts_en_c);
|
274 |
|
|
ctrl(ctrl_cts_en_c) <= data_i(ctrl_cts_en_c);
|
275 |
|
|
ctrl(ctrl_rx_irq_c) <= data_i(ctrl_rx_irq_c);
|
276 |
|
|
ctrl(ctrl_tx_irq_c) <= data_i(ctrl_tx_irq_c);
|
277 |
|
|
ctrl(ctrl_en_c) <= data_i(ctrl_en_c);
|
278 |
2 |
zero_gravi |
end if;
|
279 |
|
|
end if;
|
280 |
65 |
zero_gravi |
|
281 |
2 |
zero_gravi |
-- read access --
|
282 |
|
|
data_o <= (others => '0');
|
283 |
68 |
zero_gravi |
if (rden = '1') then
|
284 |
50 |
zero_gravi |
if (addr = uart_id_ctrl_addr_c) then
|
285 |
65 |
zero_gravi |
data_o(ctrl_baud11_c downto ctrl_baud00_c) <= ctrl(ctrl_baud11_c downto ctrl_baud00_c);
|
286 |
|
|
data_o(ctrl_sim_en_c) <= ctrl(ctrl_sim_en_c);
|
287 |
|
|
data_o(ctrl_pmode1_c downto ctrl_pmode0_c) <= ctrl(ctrl_pmode1_c downto ctrl_pmode0_c);
|
288 |
|
|
data_o(ctrl_prsc2_c downto ctrl_prsc0_c) <= ctrl(ctrl_prsc2_c downto ctrl_prsc0_c);
|
289 |
|
|
data_o(ctrl_rts_en_c) <= ctrl(ctrl_rts_en_c);
|
290 |
|
|
data_o(ctrl_cts_en_c) <= ctrl(ctrl_cts_en_c);
|
291 |
|
|
data_o(ctrl_rx_empty_c) <= not rx_buffer.avail;
|
292 |
|
|
data_o(ctrl_rx_half_c) <= rx_buffer.half;
|
293 |
|
|
data_o(ctrl_rx_full_c) <= not rx_buffer.free;
|
294 |
|
|
data_o(ctrl_tx_empty_c) <= not tx_buffer.avail;
|
295 |
|
|
data_o(ctrl_tx_half_c) <= tx_buffer.half;
|
296 |
|
|
data_o(ctrl_tx_full_c) <= not tx_buffer.free;
|
297 |
|
|
data_o(ctrl_en_c) <= ctrl(ctrl_en_c);
|
298 |
|
|
data_o(ctrl_rx_irq_c) <= ctrl(ctrl_rx_irq_c) and bool_to_ulogic_f(boolean(UART_RX_FIFO > 1)); -- tie to zero if UART_RX_FIFO = 1
|
299 |
|
|
data_o(ctrl_tx_irq_c) <= ctrl(ctrl_tx_irq_c) and bool_to_ulogic_f(boolean(UART_TX_FIFO > 1)); -- tie to zero if UART_TX_FIFO = 1
|
300 |
|
|
data_o(ctrl_tx_busy_c) <= tx_engine.busy;
|
301 |
|
|
data_o(ctrl_cts_c) <= uart_cts_ff(1);
|
302 |
50 |
zero_gravi |
else -- uart_id_rtx_addr_c
|
303 |
65 |
zero_gravi |
data_o(data_msb_c downto data_lsb_c) <= rx_buffer.rdata(7 downto 0);
|
304 |
|
|
data_o(data_rx_perr_c) <= rx_buffer.rdata(8);
|
305 |
|
|
data_o(data_rx_ferr_c) <= rx_buffer.rdata(9);
|
306 |
|
|
data_o(data_rx_overr_c) <= rx_engine.overr;
|
307 |
|
|
data_o(data_rx_avail_c) <= rx_buffer.avail; -- data available (valid?)
|
308 |
2 |
zero_gravi |
end if;
|
309 |
|
|
end if;
|
310 |
|
|
end if;
|
311 |
|
|
end process rw_access;
|
312 |
|
|
|
313 |
42 |
zero_gravi |
-- number of bits to be sampled --
|
314 |
51 |
zero_gravi |
-- if parity flag is ENABLED: 11 bit -> "1011" (1 start bit + 8 data bits + 1 parity bit + 1 stop bit)
|
315 |
|
|
-- if parity flag is DISABLED: 10 bit -> "1010" (1 start bit + 8 data bits + 1 stop bit)
|
316 |
65 |
zero_gravi |
num_bits <= "1011" when (ctrl(ctrl_pmode1_c) = '1') else "1010";
|
317 |
2 |
zero_gravi |
|
318 |
42 |
zero_gravi |
|
319 |
2 |
zero_gravi |
-- Clock Selection ------------------------------------------------------------------------
|
320 |
|
|
-- -------------------------------------------------------------------------------------------
|
321 |
|
|
-- clock enable --
|
322 |
65 |
zero_gravi |
clkgen_en_o <= ctrl(ctrl_en_c);
|
323 |
2 |
zero_gravi |
|
324 |
|
|
-- uart clock select --
|
325 |
65 |
zero_gravi |
uart_clk <= clkgen_i(to_integer(unsigned(ctrl(ctrl_prsc2_c downto ctrl_prsc0_c))));
|
326 |
2 |
zero_gravi |
|
327 |
|
|
|
328 |
65 |
zero_gravi |
-- TX FIFO --------------------------------------------------------------------------------
|
329 |
2 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
330 |
65 |
zero_gravi |
tx_engine_fifo_inst: neorv32_fifo
|
331 |
|
|
generic map (
|
332 |
|
|
FIFO_DEPTH => UART_TX_FIFO, -- number of fifo entries; has to be a power of two; min 1
|
333 |
|
|
FIFO_WIDTH => 32, -- size of data elements in fifo (32-bit only for simulation)
|
334 |
|
|
FIFO_RSYNC => false, -- async read
|
335 |
|
|
FIFO_SAFE => true -- safe access
|
336 |
|
|
)
|
337 |
|
|
port map (
|
338 |
|
|
-- control --
|
339 |
|
|
clk_i => clk_i, -- clock, rising edge
|
340 |
|
|
rstn_i => '1', -- async reset, low-active
|
341 |
|
|
clear_i => tx_buffer.clear, -- sync reset, high-active
|
342 |
|
|
level_o => open,
|
343 |
|
|
half_o => tx_buffer.half, -- FIFO at least half-full
|
344 |
|
|
-- write port --
|
345 |
|
|
wdata_i => tx_buffer.wdata, -- write data
|
346 |
|
|
we_i => tx_buffer.we, -- write enable
|
347 |
|
|
free_o => tx_buffer.free, -- at least one entry is free when set
|
348 |
|
|
-- read port --
|
349 |
|
|
re_i => tx_buffer.re, -- read enable
|
350 |
|
|
rdata_o => tx_buffer.rdata, -- read data
|
351 |
|
|
avail_o => tx_buffer.avail -- data available when set
|
352 |
|
|
);
|
353 |
|
|
|
354 |
|
|
-- control --
|
355 |
|
|
tx_buffer.clear <= not ctrl(ctrl_en_c);
|
356 |
|
|
|
357 |
|
|
-- write access --
|
358 |
68 |
zero_gravi |
tx_buffer.we <= '1' when (wren = '1') and (addr = uart_id_rtx_addr_c) else '0';
|
359 |
65 |
zero_gravi |
tx_buffer.wdata <= data_i;
|
360 |
|
|
|
361 |
|
|
|
362 |
|
|
-- UART Transmitter Engine ----------------------------------------------------------------
|
363 |
|
|
-- -------------------------------------------------------------------------------------------
|
364 |
|
|
uart_tx_engine: process(clk_i)
|
365 |
2 |
zero_gravi |
begin
|
366 |
|
|
if rising_edge(clk_i) then
|
367 |
65 |
zero_gravi |
-- defaults --
|
368 |
68 |
zero_gravi |
uart_txd_o <= '1'; -- keep TX line idle (=high) if waiting for permission to start sending (->CTS)
|
369 |
|
|
tx_buffer.re <= '0';
|
370 |
|
|
tx_engine.done <= '0';
|
371 |
65 |
zero_gravi |
|
372 |
|
|
-- FSM --
|
373 |
|
|
if (ctrl(ctrl_en_c) = '0') then -- disabled
|
374 |
|
|
tx_engine.state <= S_TX_IDLE;
|
375 |
|
|
else
|
376 |
|
|
case tx_engine.state is
|
377 |
|
|
|
378 |
|
|
when S_TX_IDLE => -- wait for new data to send
|
379 |
|
|
-- ------------------------------------------------------------
|
380 |
|
|
if (tx_buffer.avail = '1') then -- new data available
|
381 |
|
|
if (ctrl(ctrl_sim_en_c) = '0') then -- normal mode
|
382 |
|
|
tx_engine.state <= S_TX_GET;
|
383 |
|
|
else -- simulation mode
|
384 |
|
|
tx_engine.state <= S_TX_SIM;
|
385 |
|
|
end if;
|
386 |
|
|
tx_buffer.re <= '1';
|
387 |
|
|
end if;
|
388 |
|
|
|
389 |
|
|
when S_TX_GET => -- get new data from buffer and prepare transmission
|
390 |
|
|
-- ------------------------------------------------------------
|
391 |
|
|
tx_engine.baud_cnt <= ctrl(ctrl_baud11_c downto ctrl_baud00_c);
|
392 |
|
|
tx_engine.bitcnt <= num_bits;
|
393 |
|
|
if (ctrl(ctrl_pmode1_c) = '1') then -- add parity flag
|
394 |
|
|
-- stop bit & parity bit & data (8-bit) & start bit
|
395 |
|
|
tx_engine.sreg <= '1' & (xor_reduce_f(tx_buffer.rdata(7 downto 0)) xor ctrl(ctrl_pmode0_c)) & tx_buffer.rdata(7 downto 0) & '0';
|
396 |
|
|
else
|
397 |
|
|
-- (dummy fill-bit &) stop bit & data (8-bit) & start bit
|
398 |
|
|
tx_engine.sreg <= '1' & '1' & tx_buffer.rdata(7 downto 0) & '0';
|
399 |
|
|
end if;
|
400 |
|
|
tx_engine.state <= S_TX_CHECK;
|
401 |
|
|
|
402 |
|
|
when S_TX_CHECK => -- check if allowed to send
|
403 |
|
|
-- ------------------------------------------------------------
|
404 |
|
|
if (tx_engine.cts = '1') then -- clear to send
|
405 |
|
|
tx_engine.state <= S_TX_TRANSMIT;
|
406 |
|
|
end if;
|
407 |
|
|
|
408 |
|
|
when S_TX_TRANSMIT => -- transmit data
|
409 |
|
|
-- ------------------------------------------------------------
|
410 |
|
|
if (uart_clk = '1') then
|
411 |
66 |
zero_gravi |
if (or_reduce_f(tx_engine.baud_cnt) = '0') then -- bit done?
|
412 |
65 |
zero_gravi |
tx_engine.baud_cnt <= ctrl(ctrl_baud11_c downto ctrl_baud00_c);
|
413 |
|
|
tx_engine.bitcnt <= std_ulogic_vector(unsigned(tx_engine.bitcnt) - 1);
|
414 |
|
|
tx_engine.sreg <= '1' & tx_engine.sreg(tx_engine.sreg'left downto 1);
|
415 |
|
|
else
|
416 |
|
|
tx_engine.baud_cnt <= std_ulogic_vector(unsigned(tx_engine.baud_cnt) - 1);
|
417 |
|
|
end if;
|
418 |
|
|
end if;
|
419 |
|
|
uart_txd_o <= tx_engine.sreg(0);
|
420 |
66 |
zero_gravi |
if (or_reduce_f(tx_engine.bitcnt) = '0') then -- all bits send?
|
421 |
68 |
zero_gravi |
tx_engine.done <= '1'; -- sending done
|
422 |
65 |
zero_gravi |
tx_engine.state <= S_TX_IDLE;
|
423 |
|
|
end if;
|
424 |
|
|
|
425 |
|
|
when S_TX_SIM => -- simulation mode output
|
426 |
|
|
-- ------------------------------------------------------------
|
427 |
|
|
tx_engine.state <= S_TX_IDLE;
|
428 |
|
|
|
429 |
|
|
when others => -- undefined
|
430 |
|
|
-- ------------------------------------------------------------
|
431 |
|
|
tx_engine.state <= S_TX_IDLE;
|
432 |
|
|
|
433 |
|
|
end case;
|
434 |
2 |
zero_gravi |
end if;
|
435 |
|
|
end if;
|
436 |
65 |
zero_gravi |
end process uart_tx_engine;
|
437 |
2 |
zero_gravi |
|
438 |
65 |
zero_gravi |
-- transmitter busy --
|
439 |
|
|
tx_engine.busy <= '0' when (tx_engine.state = S_TX_IDLE) else '1';
|
440 |
2 |
zero_gravi |
|
441 |
65 |
zero_gravi |
|
442 |
|
|
-- UART Receiver Engine -------------------------------------------------------------------
|
443 |
2 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
444 |
65 |
zero_gravi |
uart_rx_engine: process(clk_i)
|
445 |
2 |
zero_gravi |
begin
|
446 |
|
|
if rising_edge(clk_i) then
|
447 |
|
|
-- input synchronizer --
|
448 |
66 |
zero_gravi |
rx_engine.sync <= uart_rxd_i & rx_engine.sync(rx_engine.sync'left downto 1);
|
449 |
2 |
zero_gravi |
|
450 |
68 |
zero_gravi |
-- default --
|
451 |
|
|
rx_engine.done <= '0';
|
452 |
|
|
|
453 |
65 |
zero_gravi |
-- FSM --
|
454 |
|
|
if (ctrl(ctrl_en_c) = '0') then -- disabled
|
455 |
|
|
rx_engine.overr <= '0';
|
456 |
|
|
rx_engine.state <= S_RX_IDLE;
|
457 |
|
|
else
|
458 |
|
|
case rx_engine.state is
|
459 |
|
|
|
460 |
|
|
when S_RX_IDLE => -- idle; prepare receive
|
461 |
|
|
-- ------------------------------------------------------------
|
462 |
|
|
rx_engine.baud_cnt <= '0' & ctrl(ctrl_baud11_c downto ctrl_baud01_c); -- half baud delay at the beginning to sample in the middle of each bit
|
463 |
|
|
rx_engine.bitcnt <= num_bits;
|
464 |
66 |
zero_gravi |
if (rx_engine.sync(3 downto 0) = "0011") then -- start bit? (falling edge)
|
465 |
65 |
zero_gravi |
rx_engine.state <= S_RX_RECEIVE;
|
466 |
|
|
end if;
|
467 |
|
|
|
468 |
|
|
when S_RX_RECEIVE => -- receive data
|
469 |
|
|
-- ------------------------------------------------------------
|
470 |
|
|
if (uart_clk = '1') then
|
471 |
66 |
zero_gravi |
if (or_reduce_f(rx_engine.baud_cnt) = '0') then -- bit done
|
472 |
65 |
zero_gravi |
rx_engine.baud_cnt <= ctrl(ctrl_baud11_c downto ctrl_baud00_c);
|
473 |
|
|
rx_engine.bitcnt <= std_ulogic_vector(unsigned(rx_engine.bitcnt) - 1);
|
474 |
66 |
zero_gravi |
rx_engine.sreg <= rx_engine.sync(2) & rx_engine.sreg(rx_engine.sreg'left downto 1);
|
475 |
65 |
zero_gravi |
else
|
476 |
|
|
rx_engine.baud_cnt <= std_ulogic_vector(unsigned(rx_engine.baud_cnt) - 1);
|
477 |
|
|
end if;
|
478 |
|
|
end if;
|
479 |
66 |
zero_gravi |
if (or_reduce_f(rx_engine.bitcnt) = '0') then -- all bits received?
|
480 |
68 |
zero_gravi |
rx_engine.done <= '1'; -- receiving done
|
481 |
65 |
zero_gravi |
rx_engine.state <= S_RX_IDLE;
|
482 |
|
|
end if;
|
483 |
|
|
|
484 |
|
|
when others => -- undefined
|
485 |
|
|
-- ------------------------------------------------------------
|
486 |
|
|
rx_engine.state <= S_RX_IDLE;
|
487 |
|
|
|
488 |
|
|
end case;
|
489 |
|
|
|
490 |
|
|
-- overrun flag --
|
491 |
68 |
zero_gravi |
if (rden = '1') and (addr = uart_id_rtx_addr_c) then -- clear when reading data register
|
492 |
69 |
zero_gravi |
rx_engine.overr <= '0';
|
493 |
|
|
elsif (rx_buffer.we = '1') and (rx_buffer.free = '0') then -- write to full FIFO
|
494 |
65 |
zero_gravi |
rx_engine.overr <= '1';
|
495 |
2 |
zero_gravi |
end if;
|
496 |
|
|
end if;
|
497 |
|
|
end if;
|
498 |
65 |
zero_gravi |
end process uart_rx_engine;
|
499 |
2 |
zero_gravi |
|
500 |
51 |
zero_gravi |
-- RX engine ready for a new char? --
|
501 |
65 |
zero_gravi |
rx_engine.rtr <= '1' when (rx_engine.state = S_RX_IDLE) and (ctrl(ctrl_en_c) = '1') else '0';
|
502 |
51 |
zero_gravi |
|
503 |
|
|
|
504 |
65 |
zero_gravi |
-- RX FIFO --------------------------------------------------------------------------------
|
505 |
|
|
-- -------------------------------------------------------------------------------------------
|
506 |
|
|
rx_engine_fifo_inst: neorv32_fifo
|
507 |
|
|
generic map (
|
508 |
|
|
FIFO_DEPTH => UART_RX_FIFO, -- number of fifo entries; has to be a power of two; min 1
|
509 |
|
|
FIFO_WIDTH => 10, -- size of data elements in fifo
|
510 |
|
|
FIFO_RSYNC => false, -- async read
|
511 |
|
|
FIFO_SAFE => true -- safe access
|
512 |
|
|
)
|
513 |
|
|
port map (
|
514 |
|
|
-- control --
|
515 |
|
|
clk_i => clk_i, -- clock, rising edge
|
516 |
|
|
rstn_i => '1', -- async reset, low-active
|
517 |
|
|
clear_i => rx_buffer.clear, -- sync reset, high-active
|
518 |
|
|
level_o => open,
|
519 |
|
|
half_o => rx_buffer.half, -- FIFO at least half-full
|
520 |
|
|
-- write port --
|
521 |
|
|
wdata_i => rx_buffer.wdata, -- write data
|
522 |
|
|
we_i => rx_buffer.we, -- write enable
|
523 |
|
|
free_o => rx_buffer.free, -- at least one entry is free when set
|
524 |
|
|
-- read port --
|
525 |
|
|
re_i => rx_buffer.re, -- read enable
|
526 |
|
|
rdata_o => rx_buffer.rdata, -- read data
|
527 |
|
|
avail_o => rx_buffer.avail -- data available when set
|
528 |
|
|
);
|
529 |
|
|
|
530 |
|
|
-- control --
|
531 |
|
|
rx_buffer.clear <= not ctrl(ctrl_en_c);
|
532 |
|
|
|
533 |
|
|
-- read/write access --
|
534 |
|
|
rx_buffer.wdata(7 downto 0) <= rx_engine.sreg(7 downto 0) when (ctrl(ctrl_pmode1_c) = '1') else rx_engine.sreg(8 downto 1); -- RX data
|
535 |
|
|
rx_buffer.wdata(8) <= ctrl(ctrl_pmode1_c) and (xor_reduce_f(rx_engine.sreg(8 downto 0)) xor ctrl(ctrl_pmode0_c)); -- parity error flag
|
536 |
|
|
rx_buffer.wdata(9) <= not rx_engine.sreg(9); -- frame error flag: check stop bit (error if not set)
|
537 |
|
|
rx_buffer.we <= '1' when (rx_engine.bitcnt = "0000") and (rx_engine.state = S_RX_RECEIVE) else '0'; -- RX complete
|
538 |
68 |
zero_gravi |
rx_buffer.re <= '1' when (rden = '1') and (addr = uart_id_rtx_addr_c) else '0';
|
539 |
65 |
zero_gravi |
|
540 |
|
|
|
541 |
51 |
zero_gravi |
-- Hardware Flow Control ------------------------------------------------------------------
|
542 |
2 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
543 |
65 |
zero_gravi |
tx_engine.cts <= (not uart_cts_ff(1)) when (ctrl(ctrl_cts_en_c) = '1') else '1'; -- input is low-active, internal signal is high-active
|
544 |
|
|
uart_rts <= (not rx_engine.rtr) when (ctrl(ctrl_rts_en_c) = '1') else '0'; -- output is low-active
|
545 |
51 |
zero_gravi |
|
546 |
|
|
-- flow-control input/output synchronizer --
|
547 |
|
|
flow_control_buffer: process(clk_i)
|
548 |
|
|
begin
|
549 |
|
|
if rising_edge(clk_i) then -- should be mapped to IOBs
|
550 |
|
|
uart_cts_ff <= uart_cts_ff(0) & uart_cts_i;
|
551 |
|
|
uart_rts_o <= uart_rts;
|
552 |
|
|
end if;
|
553 |
|
|
end process flow_control_buffer;
|
554 |
|
|
|
555 |
|
|
|
556 |
68 |
zero_gravi |
-- Interrupt Generator --------------------------------------------------------------------
|
557 |
51 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
558 |
69 |
zero_gravi |
irq_type: process(ctrl, tx_buffer, rx_buffer, tx_engine.done)
|
559 |
68 |
zero_gravi |
begin
|
560 |
|
|
-- TX interrupt --
|
561 |
69 |
zero_gravi |
if (UART_TX_FIFO = 1) or (ctrl(ctrl_tx_irq_c) = '0') then
|
562 |
|
|
tx_irq.set <= tx_buffer.free and tx_engine.done; -- fire IRQ if FIFO is not full
|
563 |
68 |
zero_gravi |
else
|
564 |
69 |
zero_gravi |
tx_irq.set <= (not tx_buffer.half) and tx_engine.done; -- fire IRQ if FIFO is less than half-full
|
565 |
68 |
zero_gravi |
end if;
|
566 |
|
|
-- RX interrupt --
|
567 |
69 |
zero_gravi |
if (UART_RX_FIFO = 1) or (ctrl(ctrl_rx_irq_c) = '0') then
|
568 |
68 |
zero_gravi |
rx_irq.set <= rx_buffer.avail; -- fire IRQ if FIFO is not empty
|
569 |
|
|
else
|
570 |
69 |
zero_gravi |
rx_irq.set <= rx_buffer.half; -- fire IRQ if FIFO is at least half-full
|
571 |
68 |
zero_gravi |
end if;
|
572 |
|
|
end process irq_type;
|
573 |
|
|
|
574 |
69 |
zero_gravi |
-- interrupt edge detector --
|
575 |
|
|
irq_detect: process(clk_i)
|
576 |
65 |
zero_gravi |
begin
|
577 |
|
|
if rising_edge(clk_i) then
|
578 |
68 |
zero_gravi |
if (ctrl(ctrl_en_c) = '0') then
|
579 |
69 |
zero_gravi |
tx_irq.buf <= "00";
|
580 |
|
|
rx_irq.buf <= "00";
|
581 |
65 |
zero_gravi |
else
|
582 |
69 |
zero_gravi |
tx_irq.buf <= tx_irq.buf(0) & tx_irq.set;
|
583 |
|
|
rx_irq.buf <= rx_irq.buf(0) & rx_irq.set;
|
584 |
65 |
zero_gravi |
end if;
|
585 |
|
|
end if;
|
586 |
69 |
zero_gravi |
end process irq_detect;
|
587 |
2 |
zero_gravi |
|
588 |
68 |
zero_gravi |
-- IRQ requests to CPU --
|
589 |
69 |
zero_gravi |
irq_txd_o <= '1' when (tx_irq.buf = "01") else '0';
|
590 |
|
|
irq_rxd_o <= '1' when (rx_irq.buf = "01") else '0';
|
591 |
65 |
zero_gravi |
|
592 |
68 |
zero_gravi |
|
593 |
65 |
zero_gravi |
-- SIMULATION Transmitter -----------------------------------------------------------------
|
594 |
30 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
595 |
56 |
zero_gravi |
-- pragma translate_off
|
596 |
|
|
-- synthesis translate_off
|
597 |
|
|
-- RTL_SYNTHESIS OFF
|
598 |
30 |
zero_gravi |
sim_output: process(clk_i) -- for SIMULATION ONLY!
|
599 |
50 |
zero_gravi |
file file_uart_text_out : text open write_mode is sim_uart_text_file_c;
|
600 |
|
|
file file_uart_data_out : text open write_mode is sim_uart_data_file_c;
|
601 |
|
|
variable char_v : integer;
|
602 |
|
|
variable line_screen_v : line; -- we need several line variables here since "writeline" seems to flush the source variable
|
603 |
|
|
variable line_text_v : line;
|
604 |
|
|
variable line_data_v : line;
|
605 |
30 |
zero_gravi |
begin
|
606 |
|
|
if rising_edge(clk_i) then
|
607 |
65 |
zero_gravi |
if (tx_engine.state = S_TX_SIM) then -- UART simulation mode
|
608 |
30 |
zero_gravi |
|
609 |
65 |
zero_gravi |
-- print lowest byte as ASCII char --
|
610 |
|
|
char_v := to_integer(unsigned(tx_buffer.rdata(7 downto 0)));
|
611 |
|
|
if (char_v >= 128) then -- out of range?
|
612 |
|
|
char_v := 0;
|
613 |
|
|
end if;
|
614 |
30 |
zero_gravi |
|
615 |
65 |
zero_gravi |
if (char_v /= 10) and (char_v /= 13) then -- skip line breaks - they are issued via "writeline"
|
616 |
|
|
if (sim_screen_output_en_c = true) then
|
617 |
|
|
write(line_screen_v, character'val(char_v));
|
618 |
30 |
zero_gravi |
end if;
|
619 |
65 |
zero_gravi |
if (sim_text_output_en_c = true) then
|
620 |
|
|
write(line_text_v, character'val(char_v));
|
621 |
30 |
zero_gravi |
end if;
|
622 |
65 |
zero_gravi |
end if;
|
623 |
30 |
zero_gravi |
|
624 |
65 |
zero_gravi |
if (char_v = 10) then -- line break: write to screen and text file
|
625 |
|
|
if (sim_screen_output_en_c = true) then
|
626 |
|
|
writeline(output, line_screen_v);
|
627 |
30 |
zero_gravi |
end if;
|
628 |
65 |
zero_gravi |
if (sim_text_output_en_c = true) then
|
629 |
|
|
writeline(file_uart_text_out, line_text_v);
|
630 |
|
|
end if;
|
631 |
|
|
end if;
|
632 |
30 |
zero_gravi |
|
633 |
65 |
zero_gravi |
-- dump raw data as 8 hex chars to file --
|
634 |
|
|
if (sim_data_output_en_c = true) then
|
635 |
|
|
for x in 7 downto 0 loop
|
636 |
|
|
write(line_data_v, to_hexchar_f(tx_buffer.rdata(3+x*4 downto 0+x*4))); -- write in hex form
|
637 |
|
|
end loop; -- x
|
638 |
|
|
writeline(file_uart_data_out, line_data_v);
|
639 |
30 |
zero_gravi |
end if;
|
640 |
65 |
zero_gravi |
|
641 |
30 |
zero_gravi |
end if;
|
642 |
|
|
end if;
|
643 |
|
|
end process sim_output;
|
644 |
56 |
zero_gravi |
-- RTL_SYNTHESIS ON
|
645 |
|
|
-- synthesis translate_on
|
646 |
|
|
-- pragma translate_on
|
647 |
30 |
zero_gravi |
|
648 |
2 |
zero_gravi |
end neorv32_uart_rtl;
|