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zero_gravi |
-- #################################################################################################
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-- # << NEORV32 - Watch Dog Timer (WDT) >> #
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-- # ********************************************************************************************* #
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zero_gravi |
-- # Watchdog counter to trigger an action if the CPU gets stuck. #
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-- # The internal counter is 20-bit wide. If this counter overflows one of two possible actions is #
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-- # triggered: Generate an IRQ or force a hardware reset of the system. #
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-- # A WDT action can also be triggered manually at any time by setting the FORCE bit. #
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-- # #
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-- # Access to the control register can be permanently locked by setting the lock bit. This bit #
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-- # can only be cleared by a hardware reset (external or caused by the watchdog itself). #
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zero_gravi |
-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_wdt is
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port (
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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-- clock generator --
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_i : in std_ulogic_vector(07 downto 0);
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-- timeout event --
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irq_o : out std_ulogic; -- timeout IRQ
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rstn_o : out std_ulogic -- timeout reset, low_active, use as async
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);
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end neorv32_wdt;
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architecture neorv32_wdt_rtl of neorv32_wdt is
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-- IO space: module base address --
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant lo_abb_c : natural := index_size_f(wdt_size_c); -- low address boundary bit
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-- Control register bits --
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zero_gravi |
constant ctrl_enable_c : natural := 0; -- r/w: WDT enable
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constant ctrl_clksel0_c : natural := 1; -- r/w: prescaler select bit 0
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constant ctrl_clksel1_c : natural := 2; -- r/w: prescaler select bit 1
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constant ctrl_clksel2_c : natural := 3; -- r/w: prescaler select bit 2
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constant ctrl_mode_c : natural := 4; -- r/w: 0: WDT timeout triggers interrupt, 1: WDT timeout triggers hard reset
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constant ctrl_rcause_c : natural := 5; -- r/-: cause of last action (reset/IRQ): 0=external reset, 1=watchdog overflow
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constant ctrl_reset_c : natural := 6; -- -/w: reset WDT if set
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constant ctrl_force_c : natural := 7; -- -/w: force WDT action
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constant ctrl_lock_c : natural := 8; -- r/w: lock access to control register when set
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2 |
zero_gravi |
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-- access control --
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zero_gravi |
signal acc_en : std_ulogic; -- module access enable
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signal wren : std_ulogic;
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signal rden : std_ulogic;
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zero_gravi |
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zero_gravi |
-- control register --
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type ctrl_reg_t is record
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enable : std_ulogic; -- 1=WDT enabled
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clk_sel : std_ulogic_vector(2 downto 0);
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mode : std_ulogic; -- 0=trigger IRQ on overflow; 1=trigger hard reset on overflow
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rcause : std_ulogic; -- cause of last system reset: '0' = external, '1' = watchdog
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reset : std_ulogic; -- reset WDT
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force : std_ulogic; -- force action
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lock : std_ulogic; -- lock control register
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end record;
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signal ctrl_reg : ctrl_reg_t;
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zero_gravi |
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-- prescaler clock generator --
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signal prsc_tick : std_ulogic;
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zero_gravi |
-- WDT core --
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signal wdt_cnt : std_ulogic_vector(20 downto 0);
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signal hw_rst : std_ulogic;
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signal rst_gen : std_ulogic_vector(03 downto 0);
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-- internal reset (sync, low-active) --
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signal rstn_sync : std_ulogic;
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zero_gravi |
begin
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = wdt_base_c(hi_abb_c downto lo_abb_c)) else '0';
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zero_gravi |
wren <= acc_en and wren_i;
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rden <= acc_en and rden_i;
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2 |
zero_gravi |
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zero_gravi |
-- Write Access ---------------------------------------------------------------------------
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2 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
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zero_gravi |
write_access: process(rstn_i, clk_i)
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2 |
zero_gravi |
begin
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zero_gravi |
if (rstn_i = '0') then
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ctrl_reg.reset <= '0';
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ctrl_reg.force <= '0';
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ctrl_reg.enable <= '0'; -- disable WDT
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ctrl_reg.mode <= '0'; -- trigger interrupt on WDT overflow
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ctrl_reg.clk_sel <= (others => '1'); -- slowest clock source
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ctrl_reg.lock <= '0';
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elsif rising_edge(clk_i) then
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if (rstn_sync = '0') then -- internal reset
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ctrl_reg.reset <= '0';
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ctrl_reg.force <= '0';
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ctrl_reg.enable <= '0'; -- disable WDT
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ctrl_reg.mode <= '0'; -- trigger interrupt on WDT overflow
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ctrl_reg.clk_sel <= (others => '1'); -- slowest clock source
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ctrl_reg.lock <= '0';
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zero_gravi |
else
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zero_gravi |
-- auto-clear WDT reset and WDT force flags --
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ctrl_reg.reset <= '0';
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ctrl_reg.force <= '0';
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-- actual write access --
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if (wren = '1') then
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ctrl_reg.reset <= data_i(ctrl_reset_c);
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ctrl_reg.force <= data_i(ctrl_force_c);
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if (ctrl_reg.lock = '0') then -- update configuration only if unlocked
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ctrl_reg.enable <= data_i(ctrl_enable_c);
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ctrl_reg.mode <= data_i(ctrl_mode_c);
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ctrl_reg.clk_sel <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c);
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ctrl_reg.lock <= data_i(ctrl_lock_c);
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end if;
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2 |
zero_gravi |
end if;
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end if;
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end if;
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zero_gravi |
end process write_access;
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2 |
zero_gravi |
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47 |
zero_gravi |
-- clock generator --
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clkgen_en_o <= ctrl_reg.enable; -- enable clock generator
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prsc_tick <= clkgen_i(to_integer(unsigned(ctrl_reg.clk_sel))); -- clock enable tick
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2 |
zero_gravi |
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47 |
zero_gravi |
-- Watchdog Counter -----------------------------------------------------------------------
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2 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
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zero_gravi |
wdt_counter: process(clk_i)
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2 |
zero_gravi |
begin
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171 |
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if rising_edge(clk_i) then
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47 |
zero_gravi |
if (ctrl_reg.reset = '1') then -- watchdog reset
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173 |
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wdt_cnt <= (others => '0');
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elsif (ctrl_reg.enable = '1') and (prsc_tick = '1') then
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wdt_cnt <= std_ulogic_vector(unsigned(wdt_cnt) + 1);
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2 |
zero_gravi |
end if;
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end if;
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47 |
zero_gravi |
end process wdt_counter;
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2 |
zero_gravi |
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180 |
47 |
zero_gravi |
-- action trigger --
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irq_o <= ctrl_reg.enable and (wdt_cnt(wdt_cnt'left) or ctrl_reg.force) and (not ctrl_reg.mode); -- mode 0: IRQ
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hw_rst <= ctrl_reg.enable and (wdt_cnt(wdt_cnt'left) or ctrl_reg.force) and ( ctrl_reg.mode); -- mode 1: RESET
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2 |
zero_gravi |
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184 |
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185 |
47 |
zero_gravi |
-- Reset Generator & Action Cause Indicator -----------------------------------------------
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186 |
2 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
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187 |
47 |
zero_gravi |
reset_generator: process(rstn_i, clk_i)
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188 |
2 |
zero_gravi |
begin
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189 |
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if (rstn_i = '0') then
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190 |
47 |
zero_gravi |
ctrl_reg.rcause <= '0';
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rst_gen <= (others => '1'); -- do NOT fire on reset!
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192 |
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rstn_sync <= '1';
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2 |
zero_gravi |
elsif rising_edge(clk_i) then
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194 |
47 |
zero_gravi |
ctrl_reg.rcause <= ctrl_reg.rcause or hw_rst; -- sticky-set on WDT timeout/force
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195 |
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if (hw_rst = '1') then
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rst_gen <= (others => '0');
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197 |
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else
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198 |
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rst_gen <= rst_gen(rst_gen'left-1 downto 0) & '1';
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199 |
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end if;
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200 |
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rstn_sync <= rst_gen(rst_gen'left);
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201 |
2 |
zero_gravi |
end if;
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202 |
47 |
zero_gravi |
end process reset_generator;
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203 |
2 |
zero_gravi |
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204 |
47 |
zero_gravi |
-- system reset --
|
205 |
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rstn_o <= rst_gen(rst_gen'left);
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2 |
zero_gravi |
|
207 |
47 |
zero_gravi |
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208 |
2 |
zero_gravi |
-- Read Access ----------------------------------------------------------------------------
|
209 |
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-- -------------------------------------------------------------------------------------------
|
210 |
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read_access: process(clk_i)
|
211 |
|
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begin
|
212 |
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if rising_edge(clk_i) then
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213 |
47 |
zero_gravi |
ack_o <= rden or wren;
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214 |
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if (rden = '1') then
|
215 |
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data_o(ctrl_enable_c) <= ctrl_reg.enable;
|
216 |
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data_o(ctrl_mode_c) <= ctrl_reg.mode;
|
217 |
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data_o(ctrl_rcause_c) <= ctrl_reg.rcause;
|
218 |
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data_o(ctrl_clksel2_c downto ctrl_clksel0_c) <= ctrl_reg.clk_sel;
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219 |
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data_o(ctrl_lock_c) <= ctrl_reg.lock;
|
220 |
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else
|
221 |
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data_o <= (others => '0');
|
222 |
2 |
zero_gravi |
end if;
|
223 |
|
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end if;
|
224 |
|
|
end process read_access;
|
225 |
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|
226 |
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|
227 |
|
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end neorv32_wdt_rtl;
|